HI5812KIBZ - Intersil - Datasheet.Live

FN3214.6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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HI5812

CMOS 20 Microsecond, 12-Bit, Sampling

A/D Converter with Internal Track and

Hold

The HI5812 is a fast, low power, 12 -bit, successive

approximation analog-to-digi tal converter. It can operate

from a single 3V to 6V supply and typically draws just 1.9mA

when operating at 5V. The HI5812 features a built-i n track

and hold. The conversion time is as low as 20µs with a 5V

supply.

The twelve data outputs feature full high speed CMOS

three-state bus driver capability, and are latched and held

through a full conversion cycle. The output is user

selectable, i.e., 12-bit, 8-bit (MSBs), and/or 4-bit (LSBs). A

data ready flag, and conversion-start input complete the

digital interface.

An internal clock is provided and is available as an output.

The clock may also be over-driven by an external source.

Features

• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µs

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 50 kSPS

• Built-In Track and Hold

• Guaranteed No Missing Codes Over Te mperature

• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V

• Maximum Power Consumption . . . . . . . . . . . . . . . 25mW

• Internal or External Clock

• Pb-Free Available (RoHS Compliant)

Applications

• Remote Low Power Data Acquisition Systems

• Digital Audio

• DSP Modems

• General Purpose DSP Front End

•µP Controlled Measurement System

• Professional Audio Positione r/Fader

Pinout HI5812

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART

NUMBER

INL (LSB)

(MAX OVER

TEMP.)

TEMP.

RANGE

(oC) PACKAGE PKG.

DWG. #

HI5812JIP ±1.5 -40 to 85 24 Ld PDIP E24.3

HI5812JIPZ

(See Note) ±1.5 -40 to 85 24 Ld PDIP*

(Pb-free) E24.3

HI5812JIB ±1.5 -40 to 85 24 Ld SOIC M24.3

HI5812JIBZ

(See Note) ±1.5 -40 to 85 24 Ld SOIC

(Pb-free) M24.3

HI5812KIB ±1.0 -40 to 85 24 Ld SOIC M24.3

HI5812KIBZ

(See Note) ±1.0 -40 to 85 24 Ld SOIC

(Pb-free) M24.3

*Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder

processing applications.

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

DRDY

(LSB) D0

VSS

VDD

CLK

STRT

VREF-

VREF+

VAA+

OEM

D11 (MSB)

D10

OEL

VIN

VAA-

Data Sheet March 31, 2005

Functional Block Diagram

12-BIT

SUCCESSIVE

APPROXIMATION

CLOCK

TO INTERNAL LOGIC

VDD

VSS

VIN

VREF+

VAA+

VAA-

VREF-

64C

50Ω

SUBSTRATE

16C

32C

16C

32C

CLK

DRDY

OEM

D11 (MSB)

D10

D0 (LSB)

OEL

STRT

12-BIT EDGE

TRIGGERED

“D” LATCHES

CONTROL

TIMING

HI5812

Absolute Maximum Ratings Thermal Information

Supply Voltage

VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V

VAA+ to VAA- . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V)

VAA+ to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V

Analog and Reference Inputs

VIN , VREF+ , VREF- . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V)

Digital I/O Pins. . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V)

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Maximum Junction Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . -65οC to 150oC

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing

applications.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 750kHz,

Unless Otherwise Specified

PARAMETER TEST CONDITIONS

25oC-40oC TO 85oC

UNITSMIN TYP MAX MIN MAX

ACCURACY

Resolution 12 - - 12 -Bits

Integral Linearity Error, INL

(End Point) J - - ±1.5 -±1.5 LSB

K - - ±1.0 -±1.0 LSB

Differential Linearity Error, DNL J - - ±2.0 -±2.0 LSB

K - - ±1.0 -±1.0 LSB

Gain Error, FSE

(Adjustable to Zero) J - - ±3.0 -±3.0 LSB

K - - ±2.5 -±2.5 LSB

Offset Error, VOS

(Adjustable to Zero) J - - ±2.0 -±2.0 LSB

K - - ±1.0 -±1.0 LSB

Power Supply Rejection, PSRR

Offset Error PSRR

Gain Error PSRR

VREF = 4V

VDD = VAA+ = 5V ±5%

-±0.1

±0.1 ±0.5

±0.5

±0.5 LSB

LSB

DYNAMIC CHARACTERISTICS

Signal to Noise Ratio, SINAD

RMS Signal

RMS Noise + Distortion

J fS = Internal Clock, fIN = 1kHz

fS = 750kHz, fIN = 1kHz -68.8

69.2 - - - dB

K fS = Internal Clock, fIN = 1kHz

fS = 750kHz, fIN = 1kHz -71.0

71.5 - - - dB

Signal to Noise Ratio, SNR

RMS Signal

RMS Noise

J fS = Internal Clock, fIN = 1kHz

fS = 750kHz, fIN = 1kHz -70.5

71.1 - - - dB

K fS = Internal Clock, fIN = 1kHz

fS = 750kHz, fIN = 1kHz -71.5

72.1 - - - dB

Total Harmonic Distortion, THD J fS = Internal Clock, fIN = 1kHz

fS = 750kHz, fIN = 1kHz --73.9

-73.8 - - - dBc

dBc

K fS = Internal Clock, fIN = 1kHz

fS = 750kHz, fIN = 1kHz --80.3

-79.0 - - - dBc

dBc

HI5812

Spurious Free Dynamic Range,

SFDR J fS =Internal Clock, fIN = 1kHz

fS = 750kHz, fIN = 1kHz --75.4

-75.1 - - - dB

K fS = Internal Clock, fIN = 1kHz

fS = 750kHz, fIN = 1kHz --80.9

-79.6 - - - dB

ANALOG INPUT

Input Current, Dynamic At VIN = VREF+, 0V -±50 ±100 -±100 µA

Input Current, Static Conversion Stopped -±0.4 ±10 -±10 µA

Input Bandwidth -3dB - 1 - - - MHz

Reference Input Current -160 - - - µA

Input Series Resistance, RSIn Series with Input CSAMPLE -420 - - - W

Input Capacitance, CSAMPLE During Sample State -380 - - - pF

Input Capacitance, CHOLD During Hold State -20 - - - pF

DIGITAL INPUTS OEL, OEM, STRT

High-Level Input Voltage, VIH 2.4 - - 2.4 - V

Low-Level Input Voltage, VIL - - 0.8 -0.8 V

Input Leakage Current, IIL Except CLK, VIN = 0V, 5V - - ±10 -±10 µA

Input Capacitance, CIN -10 - - - pF

DIGITAL OUTPUTS

High-Level Output Voltage, VOH ISOURCE = -400µA4.6 - - 4.6 - V

Low-Level Output Voltage, VOL ISINK = 1.6mA - - 0.4 -0.4 V

Three-State Leakage, IOZ Except DRDY, VOUT = 0V, 5V - - ±10 -±10 µA

Output Capacitance, COUT Except DRDY -20 - - - pF

CLOCK

High-Level Output Voltage, VOH ISOURCE = -100µA (Note 2) 4 - - 4 - V

Low-Level Output Voltage, VOL ISINK = 100µA (Note 2) - - 1 - 1 V

Input Current CLK Only, VIN = 0V, 5V - - ±5 - ±5mA

TIMING

Conversion Time (tCONV + tACQ)

(Includes Acquisition Time) 20 - - 20 -µs

Clock Frequency Internal Clock, (CLK = Open) 200 300 400 150 500 kHz

External CLK (Note 2) 0.05 21.5 0.05 1.5 MHz

Clock Pulse Width, tLOW, tHIGH External C LK (Note 2) 100 - - 100 -ns

Aperture Delay, tDAPR (Note 2) -35 50 -70 ns

Clock to Data Ready Delay, tD1DRDY (Note 2) -105 150 -180 ns

Clock to Data Ready Delay, tD2DRDY (Note 2) -100 160 -195 ns

Start Removal Time, tRSTRT (Note 2) 75 30 -75 -ns

Start Setup Time, tSUSTRT (Note 2) 85 60 -100 -ns

Start Pulse Width, tWSTRT (Note 2) 10 4 - 15 -ns

Start to Data Ready Delay, tD3 DRDY (Note 2) -65 105 -120 ns

Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 750kHz,

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS

25oC-40oC TO 85oC

UNITSMIN TYP MAX MIN MAX

HI5812

Clock Delay from Start, tDSTRT (Note 2) -60 - - - ns

Output Enable Delay, tEN (Note 2) -20 30 -50 ns

Output Disabled Delay, tDIS (Note 2) -80 95 -120 ns

POWER SUPPLY CHARACTERISTICS

Supply Current, IDD + IAA -1.9 5 - 8 mA

NOTE:

2. Parameter guaranteed by design or characterization, not production tested.

Timing Diagrams

FIGURE 1. CONTINUOUS CONVERSION MODE

Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 750kHz,

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS

25oC-40oC TO 85oC

UNITSMIN TYP MAX MIN MAX

D0 - D11

CLK

(EXTERNAL

tD2DRDY

tLOW

tHIGH

12345 - 14 15 123

STRT

OR INTERNAL)

HOLD N

TRACK N TRACK N + 1

VIN

OEL = OEM = VSS

DRDY

tD1DRDY

DATA N - 1 DATA N

HI5812

FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK

FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK

Timing Diagrams (Continued)

STRT

HOLD TRACK HOLD

CLK

(EXTERNAL)

DRDY

VIN

tRSTRT tSUSTRT

tWSTRT

15 1222345

tD3DRDY

HOLD TRACK HOLD

tRSTRT tDSTRT

tWSTRT

15 1 2 3 4 5

tD3DRDY

DON’T CARE

DRDY

CLK

(INTERNAL)

VIN

STRT

HI5812

FIGURE 4A. FIGURE 4B.

FIGURE 4. OUTPUT ENABLE/DISABLE TIMIN G DIAGRAM

FIGURE 5. GENERAL TIMING LOAD CIRCUIT

Timing Diagrams (Continued)

OEL OR OEM

D0 - D3 OR D4 - D11

HIGH

tDIS

tEN

50%

10%

90%

TO LOW

OUTPUT

IMPEDANCE

HIGH IMPEDANCE

TO HIGH

-1.6mA

1.6mA

50pF +2.1V

-400µA

1.6mA

50pF +2.1V

HI5812

Typical Performance Curves

FIGURE 6. INL vs TEMPERATURE FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE

FIGURE 8. DNL vs TEMPERATURE FIGURE 9. ACCURACY vs REFERENCE VOLTAGE

FIGURE 10. FULL SCALE ERROR vs TEMPERATURE FIGURE 11. POWER SUPPLY REJECTION vs TEMPERATURE

-60 -40 -20 0 20 40 60 80 100 120 140

1.0

0.75

0.5

0.25

INL ERROR (LSBs)

TEMPERATURE (oC)

VDD = VAA+ = 5V, VREF+ = 4.608V

A. CLK = INTERNAL

B. CLK = 750kHz

C. CLK = 1MHz

-60 -40 -20 0 20 40 60 80 100 120 140

1.5

0.5

TEMPERATURE (oC)

VDD = VAA+ = 5V

VOS ERROR (LSBs)

A. CLK = INTERNAL

B. CLK = 750kHz

C. CLK = 1MHz

VREF+ = 4.608V

-60 -40 -20 0 20 40 60 80 100 120 140

1.0

0.75

0.5

0.25

TEMPERATURE (oC)

VDD = VAA+ = 5V, VREF+ = 4.608V C

A. CLK = INTERNAL

B. CLK = 750kHz

C. CLK = 1MHz

DNL ERROR (LSBs)

3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6

1.5

0.5

REFERENCE VOLTAGE, VREF (V)

VDD = VAA+ = 5V, TA = 25oC

FSE

DNL

INL

CLK = 750kHz

ERROR (LSBs)

VOS

-60 -40 -20 0 20 40 60 80 100 120 140

1.5

0.5

TEMPERATURE (oC)

VDD = VAA+ = 5V,

A. CLK = INTERNAL

B. CLK = 750kHz

C. CLK = 1MHz

FS ERROR (LSBs)

VREF+ = 4.608V

-60 -40 -20 0 20 40 60 80 100 120 140

0.5

0.375

0.25

0.125

TEMPERATURE (oC)

VDD = VAA+ = 5V ±5%

PSRR FSE

CLK = 750kHz

PSRR VOS

VREF+ = 4.0V

PSRR (LSBs)

HI5812

FIGURE 12. SUPPLY CURRENT vs TEMPERATURE FIGURE 13. FFT SPECTRUM

FIGURE 14. INTERNAL CLOCK FREQUENCY vs TEMPERATURE FIGURE 15. EFFECTIVE BITS vs INPUT FREQUENCY

FIGURE 16. TOTAL HARMONIC D ISTORTION vs IN PUT

FREQUENCY FIGURE 17. SIGNAL NOISE RATIO vs INPUT FREQUENCY

Typical Performance Curves (Continued)

-60 -40 -20 0 20 40 60 80 100 120 140

TEMPERATURE (oC)

SUPPLY CURRENT, IDD (mA)

VDD = VAA+ = 5V, VREF+ = 4.608V

INTERNAL CLOCK

0 500 1000 1500

AMPLITUDE (dB)

0.0

-20.0

-30.0

-40.0

-50.0

-60.0

-70.0

-80.0

-90.0

-100.0

-110.0

-120.0

-130.0

FREQUENCY BINS

-10.0

2000

INPUT FREQUENCY = 1kHz

SAMPLING RATE = 50kHz

SNR = 72.1dB

THD = -79.1dBc

PEAK NOISE = -80.9dB

SFDR = -80.9dB

SINAD = 71.4dB

EFFECTIVE BITS = 11.5

-140.0

-60 -40 -20 0 20 40 60 80 100 120 140

500

400

250

TEMPERATURE (oC)

450

350

300

200

150

VDD = VAA+ = 5V, VREF+ = 4.608V

INTERNAL CLOCK FREQUENCY (kHz)

INPUT FREQUENCY (kHz)

0.1 1 10 100

A. CLK = INTERNAL

B. CLK = 750kHz

C. CLK = 1MHz

VDD = VAA+ = 5V

VREF+ = 4.608V

TA = 25oC

ENOB (BITS)

INPUT FREQUENCY (kHz)

0.1 1 10 100

-80

-50

-70

-60 B

A. CLK =INTERNAL

B. CLK = 750kHz

C. CLK = 1MHz

VDD = VAA+ = 5V

VREF+ = 4.608V

TA = 25oC

THD (dBc)

INPUT FREQUENCY (kHz)

0.1 1 10 100

A. CLK = INTERNAL

B. CLK = 750kHz

C. CLK = 1MHz

VDD = VAA+ = 5V

VREF+ = 4.608V

TA = 25oC

SNR (dBc)

HI5812

Theory of Operation

HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that

uses capacitor-charge balancing to successive ly approximate

the analog input. A binarily weighted capacitor network forms

the A/D heart of the device. See the block diagram for the

HI5812.

The capacitor network has a common node which is

connected to a comparator . The second terminal of each

capacitor is individuall y switchable to the input, VREF+ or

VREF - .

During the first three clock periods of a conversion cycle, the

switchable end of every capacitor is connected to the input

and the comparator is being auto-balanced at the capacitor

common node.

During the fourth period, all capacitors are disconnected

from the input; the one representing the MSB (D11) is

connected to the VREF+ terminal; and the remaining

capacitors to VREF -. The capacitor-common node, after the

charges balance out, will indicate whether the input was

above 1/2 of (VREF+ - VREF -). At the end of the fourth

period, the comparator output is stored and the MSB

capacitor is either left connected to VREF+ (if the compar ator

was high) or returned to VREF -. This allows the next

comparison to be at either 3/4 or 1/4 of (VREF+ - VREF -).

At the end of periods 5 through 14, capacitors representing

D10 through D1 are tested, the result stored, and each

capacitor either left at VREF+ or at VREF -.

At the end of the 15th period, when the LSB (D0) capacitor is

tested, (D0) and all the previous results are shifted to the

output registers and drivers. The capacitors are reconnected

to the input, the comparator returns to the balance state, and

the data-ready output goes active. The conversion cycle is

now complete.

Analog Input

The analog input pin is a predomi nately capacitive load that

changes between the track and hold periods of the

conversion cycle. During hold, clock period 4 through 15, the

input loading is leakage and stray capacitance, typically less

than 5µA and 20pF.

At the start of input tracking, clock period 1, some charge is

dumped back to the input pin. The input source must have

low enough impedance to dissipate the current spike by the

end of the tracking period as shown in Figure 18. The

amount of charge is dependent on supply and input

voltages. The average current is also proportional to clock

frequency.

As long as these current spikes settle completely by end of

the signal acquisition period, co nverter accuracy will be

preserved. The analog input is tracked for 3 clock cycles.

With an external clock of 750kHz the track period is 4µs.

TABLE 1. PIN DESCRIPTIONS

PIN NO. NAME DESCRIPTION

1DRDY Output flag signifying new data is available.

Goes high at end of clock period 15. Goes low

when new conversion is started.

2D0 Bit 0 (Least Significant Bit, LSB).

3D1 Bit 1.

4D2 Bit 2.

5D3 Bit 3.

6D4 Bit 4.

7D5 Bit 5.

8D6 Bit 6.

9D7 Bit 7.

10 D8 Bit 8.

11 D9 Bit 9.

12 VSS Digital Ground (0V).

13 D10 Bit 10.

14 D11 Bit 11 (Most Significant Bit, MSB).

15 OEM Three-State Enable for D4-D11. Active low input.

16 VAA-Analog Ground, (0V).

17 VAA+Analog Positive Supply. (+5V) (See text.)

18 VIN Analog Input.

19 VREF+Reference Voltage Positive Input, sets 4095

code end of input range.

20 VREF-Reference Voltage Negative Input, sets 0 code

end of input range.

21 STRT Start Conversion Input Active Low, recognized

after end of clock period 15.

22 CLK CLK Input or Output. Conversion functions are

synchronized to positive going edge. (See

text.)

23 OEL Three-State Enable for D0 D3. Active Low Input.

24 VDD Digital Positive Supply (+5V). 20mA

10mA

0mA

IIN

CLK

DRDY

200ns/DIV.

CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V,

VIN = 4.608V, CLK = 750kHz, TA = 25oC

FIGURE 18. TYPICAL ANALOG INPUT CURRENT

HI5812

A simplified analog input model is presented in Figure 19.

During tracking, the A/D input (V IN) typically appears as a

380pF capacitor being charged th rough a 420 Ω internal

switch resistance. The time constant is 160ns. To charge this

capacitor from an external “zero Ω” source to 0.5 LSB

(1/8192), the charging time must be at least 9 time constants

or 1.4µs. The maximum source impedan ce (RSOURCE Max )

for a 4µs acquisition time settling to within 0.5LSB is 750Ω.

If the clock frequency was slower, or the converter was not

restarted immediately (causing a longer sample time), a

higher source impedance could be tolera ted.

Reference Input

The reference input VREF+ should be driven from a low

impedance source and be well decoupled.

As shown in Figure 20, current spikes are generated on the

reference pin during each bit test of the succe s sive

approximation part of the conversion cycle as the charge-

balancing capacitors are switched between VREF - and

VREF+ (clock periods 5 - 14). These current spikes must

settle completely during each bit test of the conversion to not

degrade the accuracy of the converter. Therefore VREF+

and VREF - should be well bypassed. Reference input VREF -

is normally connected directly to the analog ground plane. If

VREF - is biased for nulling the conve rters offset it must be

stable during the conversion cycle.

The HI5812 is specified with a 4.608V reference, however, it

will operate with a reference down to 3V having a slight

degradation in performance. A typical graph of accuracy vs

reference voltage is presented.

Full Scale and Offset Adjustment

In many applications the accuracy of the HI5812 would be

sufficient without any adjustments. In applications where

accuracy is of utmost importance full scale and offset errors

may be adjusted to zero.

The VREF+ and VREF - pins reference the two ends of the

analog input range and may be used for offset and full scale

adjustments. In a typical system the VREF - might be

returned to a clean ground, and the offset adjustmen t done

on an input amplifier. VREF+ would then be adjusted to null

out the full scale error. When this is not possib le, the VREF -

input can be adjusted to null the offset error, however,

VREF - must be well decoupled.

Full scale and offset error can also be adjusted to zero in the

signal conditioning amplifi er driving the analog input (VIN).

Control Signal

The HI5812 may be synchronized from an external source

by using the STRT (Start Conversion) input to initiate

conversion, or if STRT is tied low, may be allowed to free

run. Each conversion cycle takes 15 clock periods.

The input is tracked from clock period 1 through period 3,

then disconnected as the successive approximation takes

place. After the start of the next period 1 (specified by tD

data), the output is updated.

The DRDY (Data Ready) status output goes high (specified

by tD1DRDY) after the start of clock period 1, and returns

low (specified by tD2DRDY) after the start of clock period 2.

The 12 data bits are available in parallel on three-state bus

driver outputs. When low, the OEM input enables the most

significant byte (D4 through D11) while the OEL input

enables the four least significant bits (D0 - D3). tEN and tDIS

specify the output enable and disab le times.

If the output data is to be latched externally, either the

trailing edge of data ready or the next falling edge of the

clock after data ready goes high can be used.

When STRT input is used to initiate conversions, operation

is slightly different depending on whether an internal or

external clock is used.

Figure 3 illustrates operation with an interna l clock. If the

STRT signal is removed (at least tRSTRT) before clock

period 1, and is not reapplied during that period, the clock

will shut off after entering period 2. The input will continue to

track and the DRDY output will remain high during this time.

A low signal applied to STRT (at least tWSTRT wide) can

now initiate a new conversion. The STRT signal (after a

delay of (tDSTRT)) causes the clock to restart.

RSOURCE

VIN RSW ≈ 420Ω

CSAMPLE ≈ 380pF

RSOURCE(MAX) tACQ

–

CSAMPLEIn 2 N1+()–

[]

--------------------------------------------------------------RSW

–=

FIGURE 19. ANALOG INPUT MODEL IN TRACK MODE

20mA

10mA

0mA

IREF+

CLK

DRDY

2µs/DIV.

CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V,

VIN = 2.3V, CLK = 750kHz, TA = 25oC

FIGURE 20. TYPICAL REFERENCE INPUT CURRENT

HI5812

Depending on how long the clock was shut off, the low

portion of clock period 2 may be longer than during the

remaining cycles.

The input will continue to track until the end of period 3, the

same as when free running.

Figure 2 illustrates the same operation as above but with an

external clock. If STRT is removed (at least tRSTRT) before

clock period 2, a low signal applied to STRT will drop the

DRDY flag as before, and with the first positive-going clock

edge that meets the (tSUSTRT) setup time, the converter will

continue with clock period 3.

Clock

The HI5812 can operate either from its internal clock or from

one externally supplied. The CLK pin functions either as the

clock output or input. All converter functions are

synchronized with the rising edge of the clock signal.

Figure 21 shows the configuration of the internal clock. The

clock output drive is low power: if used as an output, it

should not have more than 1 CMOS gate load applie d, and

stray wiring capacitance should be kept to a minimum.

The internal clock will shut down if the A/D is not restarted

after a conversion. The clock could also be shut down with

an open collector driver applied to the CLK pin. This should

only be done during the sample portion (th e first three clock

periods) of a conversion cycle, and might be useful for using

the device as a digital sample and hold.

If an external clock is supplied to the CLK pin, it must have

sufficient drive to overcome the internal clock source. The

external clock can be shut off, but again, only during the

sample portion of a conversion cycle. At other times, it must

be above the minimum frequency shown in the

specifications. In the above two cases, a further restriction

applies in that the clock should not be shut off during the

third sample period for more than 1ms. This might cause an

internal charge-pump voltage to decay.

If the internal or external clock was shut off during the

conversion time (clock cycles 4 through 15) of the A/D, the

output might be invalid due to balancing capacitor droop.

An external clock must also meet the minimum tLOW and

tHIGH times shown in the specifications. A violation may

cause an internal miscount and invalidate the results.

Power Supplies and Grounding

VDD and VSS are the digital supply pins: they power all

internal logic and the output drivers. Because the output

drivers can cause fast current spikes in the VDD and VSS

lines, VSS should have a low impedance path to digital

ground and VDD should be well bypassed.

Except for VAA+, which is a substrate connection to VDD , all

pins have protection diodes connected to VDD and VSS .

Input transients above VDD or below VSS will get steered to

the digital supplies.

The VAA+ and VAA- terminals supply the charg e-balancing

comparator only. Because the comparator is autoba lanced

between conversions, it has good low-frequency supply

rejection. It does not reject well at high frequencies however;

VAA- should be returned to a clean analog ground and VAA+

should be RC decoupled from the digital supply as shown in

Figure 22.

There is approximately 50Ω of substrate impedance

between VDD and VAA+. This can be used, for example , as

part of a low-pass RC filter to attenuate switching supply

noise. A 10µF capacitor from VAA+ to ground would

attenuate 30kHz noise by approximately 40dB. Note that

back-to-back diodes should be placed from VDD to VAA+ to

handle supply to capacitor turn-on or turn-off current spikes.

Dynamic Performance

Fast Fourier Transform (FFT) techniques are used to

evaluate the dynamic performance of the A/D. A low

distortion sine wave is applied to the input of the A/D

converter. The input is sampled by the A/D and its output

stored in RAM. The data is than transformed into the

frequency domain with a 4096 point FFT and analyzed to

evaluate the converters dynamic performance such as SNR

and THD. See typical performance characteristics.

Signal-To-Noise Ratio

The signal to noise ratio (SNR) is the measured RMS signal

to RMS sum of noise at a specified input and sampling

frequency. The noise is the RMS sum of all except the

fundamental and the first five harmonic signals. The SNR is

dependent on the number of quantization levels used in the

converter. The theoretical SNR for an N-bit converter with no

differential or integral linearity error is: SNR = (6.02N + 1.76)

dB. For an ideal 12-bit converter the SNR is 74dB.

Differential and integral linearity errors will deg rade SNR.

Signal-To-Noise + Distortion Ratio

SINAD is the measured RMS signal to RMS sum of noise

plus harmonic power and is expressed by the following:

OPTIONAL

CLK

INTERNAL

100kΩ18pF

CLOCK

ENABLE

EXTERNAL

CLOCK

FIGURE 21. INTERNAL CLOCK CIRCUITRY

SNR = 10 Log Sinewave Signal Power

Total Noise Power

SINAD = 10 Log Sinewave Signal Power

Noise + Harmonic Power (2nd - 6th)

HI5812

Effective Number of Bits

The effective number of bits (ENOB) is derived from the

SINAD data;

Total Harmonic Distortion

The total harmonic distortion (THD) is the ratio of the RMS

sum of the second through sixth harmonic components to

the fundamental RMS signal for a sp ecified input and

sampling frequency.

Spurious-Free Dynamic Range

The spurious-free dynamic range (SFDR) is the ratio of the

fundamental RMS amplitude to the RMS amplitude of the

next largest spur or spectral component. If the harmonics

are buried in the noise floor it is the largest peak.

ENOB = SINAD - 1.76

6.02

THD = 10 Log Total Harmonic Power (2nd - 6th Harmonic)

Sinewave Signal Power

SFDR = 10 Log Sinewave Signal Power

Highest Spurious Signal Power

TABLE 2. CODE TABLE

CODE

DESCRIPTION

INPUT VOLTAGE†

VREF+ = 4.608V

VREF- = 0.0V

(V) DECIMAL

COUNT

BINARY OUTPUT CODE

MSB LSB

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Full Scale (FS) 4.6069 4095 1 1 1 1 1 1 1 1 1 1 1 1

FS - 1 LSB 4.6058 4094 1 1 1 1 1 1 1 1 1 1 1 0

3/4 FS 3.4560 3072 1 1 0 0 0 0 0 0 0 0 0 0

1/2 FS 2.3040 2048 1 0 0 0 0 0 0 0 0 0 0 0

1/4 FS 1.1520 1024 0 1 0 0 0 0 0 0 0 0 0 0

1 LSB 0.001125 1 0 0 0 0 0 0 0 0 0 0 0 1

Zero 0 0 0 0 0 0 0 0 0 0 0 0 0 0

† The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.

0.01µF0.1µF10µF

4.7µF

VREF+

VIN

VAA+V

D11

DRDY

OEM

OEL

STRT

CLK

0.1µF

VREF- VAA- VSS

+5V

OUTPUT

DATA

750kHz CLOCK

0.001µF

0.1µF4.7µF

VREF

ANALOG

INPUT

FIGURE 22. GROUND AND SUPPLY DECOUPLING

HI5812

Die Characteristics

DIE DIMENSIONS:

3200µm x 3940µm

METALLIZATION:

Type: AlSi

Thickness: 11kÅ ±1kÅ

PASSIVATION:

Type: PSG

Thickness: 13kÅ ±2.5kÅ

WORST CASE CURRENT DENSITY:

1.84 x 105 A/cm2

Metallization Mask Layout HI5812

D1 D0

(LSB) DRDY VDD OEL

CLK

STRT

VREF-

VREF+

VIN

VAA+

VAA-

OEM

VSS (MSB)

D11D10

HI5812

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and

Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in

JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

ular to datum .

7. eB and eC are measured at the lead tips with the leads unconstrained.

eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

eA-C-

-B-

INDEX 12 3 N/2

AREA

SEATING

BASE

PLANE

-C-

B1 Be

-A-

0.010 (0.25) C AMBS

E24.3 (JEDEC MS-001-AF ISSUE D)

24 LEAD NARROW BODY DUAL-IN-LINE PLASTIC

PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.210 - 5.33 4

A1 0.015 - 0.39 - 4

A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8

C 0.008 0.014 0.204 0.355 -

D 1.230 1.280 31.24 32.51 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

eA0.300 BSC 7.62 BSC 6

eB- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N24 249

Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

HI5812

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45o

0.25(0.010) BM M

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9

C 0.0091 0.0125 0.23 0.32 -

D 0.5985 0.6141 15.20 15.60 3

E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6

N24 247

α0o8o0o8o-

Rev. 0 12/93