LMP7701,LMP7702,LMP7704
LMP7701/LMP7702/LMP7704 Precision, CMOS Input, RRIO, Wide Supply Range
Amplifiers
Literature Number: SNOSAI9G
June 23, 2008
LMP7701/LMP7702/LMP7704
Precision, CMOS Input, RRIO, Wide Supply Range
Amplifiers
General Description
The LMP7701/LMP7702/LMP7704 are single, dual, and quad
low offset voltage, rail-to-rail input and output precision am-
plifiers each with a CMOS input stage and a wide supply
voltage range. The LMP7701/LMP7702/LMP7704 are part of
the LMP® precision amplifier family and are ideal for sensor
interface and other instrumentation applications.
The guaranteed low offset voltage of less than ±200 µV along
with the guaranteed low input bias current of less than ±1 pA
make the LMP7701 ideal for precision applications. The
LMP7701/LMP7702/LMP7704 are built utilizing VIP50 tech-
nology, which allows the combination of a CMOS input stage
and a 12V common mode and supply voltage range. This
makes the LMP7701/LMP7702/LMP7704 great choices in
many applications where conventional CMOS parts cannot
operate under the desired voltage conditions.
The LMP7701/LMP7702/LMP7704 each have a rail-to-rail in-
put stage that significantly reduces the CMRR glitch com-
monly associated with rail-to-rail input amplifiers. This is
achieved by trimming both sides of the complimentary input
stage, thereby reducing the difference between the NMOS
and PMOS offsets. The output of the LMP7701/LMP7702/
LMP7704 swings within 40 mV of either rail to maximize the
signal dynamic range in applications requiring low supply
voltage.
The LMP7701 is offered in the space saving 5-Pin SOT23 and
8-Pin SOIC package. The LMP7702 is offered in the 8-Pin
SOIC and 8-Pin MSOP package. The quad LMP7704 is of-
fered in the 14-Pin SOIC and 14-Pin TSSOP package. These
small packages are ideal solutions for area constrained PC
boards and portable electronics.
Features
Unless otherwise noted, typical values at VS = 5V
Input offset voltage (LMP7701) ±200 µV (max)
Input offset voltage (LMP7702/LMP7704) ±220 µV (max)
Input bias current ±200 fA
Input voltage noise 9 nV/Hz
CMRR 130 dB
Open loop gain 130 dB
Temperature range −40°C to 125°C
Unity gain bandwidth 2.5 MHz
Supply current (LMP7701) 715 µA
Supply current (LMP7702) 1.5 mA
Supply current (LMP7704) 2.9 mA
Supply voltage range 2.7V to 12V
Rail-to-rail input and output
Applications
High impedance sensor interface
Battery powered instrumentation
High gain amplifiers
DAC buffer
Instrumentation amplifier
Active filters
Typical Application
20127305
Precision Current Source
LMP® is a registered trademark of National Semiconductor Corporation.
© 2008 National Semiconductor Corporation 201273 www.national.com
LMP7701/LMP7702/LMP7704 Precision, CMOS Input, RRIO, Wide Supply Range Amplifiers
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Human Body Model 2000V
Machine Model 200V
Charge-Device Model 1000V
VIN Differential ±300 mV
Supply Voltage (VS = V+ – V)13.2V
Voltage at Input/Output Pins V++ 0.3V, V − 0.3V
Input Current 10 mA
Storage Temperature Range −65°C to +150°C
Junction Temperature (Note 3) +150°C
Soldering Information
Infrared or Convection (20 sec) 235°C
Wave Soldering Lead Temp. (10
sec) 260°C
Operating Ratings (Note 1)
Temperature Range (Note 3) −40°C to +125°C
Supply Voltage (VS = V+ – V)2.7V to 12V
Package Thermal Resistance (θJA (Note 3))
5-Pin SOT23 265°C/W
8-Pin SOIC 190°C/W
8-Pin MSOP 235°C/W
14-Pin SOIC 145°C/W
14-Pin TSSOP 122°C/W
3V Electrical Characteristics (Note 4)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 3V, V = 0V, VCM = V+/2, and RL > 10 k to V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
VOS Input Offset Voltage LMP7701 ±37 ±200
±500 μV
LMP7702/LMP7704 ±56 ±220
±520
TCVOS Input Offset Voltage Temperature Drift (Note 7) ±1 ±5 μV/°C
IBInput Bias Current (Notes 7, 8)
−40°C TA 85°C
±0.2 ±1
±50
pA
(Notes 7, 8)
−40°C TA 125°C
±0.2 ±1
±400
IOS Input Offset Current 40 fA
CMRR Common Mode Rejection Ratio 0V VCM 3V
LMP7701
86
80
130
dB
0V VCM 3V
LMP7702/LMP7704
84
78
130
PSRR Power Supply Rejection Ratio 2.7V V+ 12V, Vo = V+/2 86
82
98 dB
CMVR Common Mode Voltage Range CMRR 80 dB
CMRR 77 dB
–0.2
–0.2
3.2
3.2 V
AVOL Open Loop Voltage Gain RL = 2 kΩ (LMP7701)
VO = 0.3V to 2.7V
100
96
114
dB
RL = 2 kΩ (LMP7702/LMP7704)
VO = 0.3V to 2.7V
100
94
114
RL = 10 k
VO = 0.2V to 2.8V
100
96
124
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LMP7701/LMP7702/LMP7704
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
VOUT Output Voltage Swing High RL = 2 k to V+/2
LMP7701
40 80
120
mV
from V+
RL = 2 k to V+/2
LMP7702/LMP7704
40 80
150
RL = 10 k to V+/2
LMP7701
30 40
60
RL = 10 k to V+/2
LMP7702/LMP7704
35 50
100
Output Voltage Swing Low RL = 2 k to V+/2
LMP7701
40 60
80
mV
RL = 2 k to V+/2
LMP7702/LMP7704
45 100
170
RL = 10 k to V+/2
LMP7701
20 40
50
RL = 10 k to V+/2
LMP7702/LMP7704
20 50
90
IOUT Output Current
(Notes 3, 9)
Sourcing VO = V+/2
VIN = 100 mV
25
15
42
mA
Sinking VO = V+/2
VIN = −100 mV (LMP7701)
25
20
42
Sinking VO = V+/2
VIN = −100 mV (LMP7702/
LMP7704)
25
15
42
ISSupply Current LMP7701 0.670 1.0
1.2
mA
LMP7702 1.4 1.8
2.1
LMP7704 2.9 3.5
4.5
SR Slew Rate (Note 10) AV = +1, VO = 2 VPP
10% to 90%
0.9 V/μs
GBW Gain Bandwidth 2.5 MHz
THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, R.L = 10 k 0.02 %
enInput Referred Voltage Noise Density f = 1 kHz 9 nV/
inInput Referred Current Noise Density f = 100 kHz 1 fA/
5V Electrical Characteristics (Note 4)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5V, V = 0V, VCM = V+/2, and RL > 10 k to V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
VOS Input Offset Voltage LMP7701 ±37 ±200
±500 μV
LMP7702/LMP7704 ±32 ±220
±520
TCVOS Input Offset Voltage Temperature Drift (Note 7) ±1 ±5 μV/°C
IBInput Bias Current (Notes 7, 8)
−40°C TA 85°C
±0.2 ±1
±50
pA
(Notes 7, 8)
−40°C TA 125°C
±0.2 ±1
±400
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LMP7701/LMP7702/LMP7704
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
IOS Input Offset Current 40 fA
CMRR Common Mode Rejection Ratio 0V VCM 5V
LMP7701
88
83
130
dB
0V VCM 5V
LMP7702/LMP7704
86
81
130
PSRR Power Supply Rejection Ratio 2.7V V+ 12V, VO = V+/2 86
82
100 dB
CMVR Common Mode Voltage Range CMRR 80 dB
CMRR 78 dB
–0.2
–0.2
5.2
5.2 V
AVOL Open Loop Voltage Gain RL = 2 kΩ (LMP7701)
VO = 0.3V to 4.7V
100
96
119
dB
RL = 2 kΩ (LMP7702/LMP7704)
VO = 0.3V to 4.7V
100
94
119
RL = 10 k
VO = 0.2V to 4.8V
100
96
130
VOUT Output Voltage Swing High RL = 2 k to V+/2
LMP7701
60 110
130
mV
from V+
RL = 2 k to V+/2
LMP7702/LMP7704
60 120
200
RL = 10 k to V+/2
LMP7701
40 50
70
RL = 10 k to V+/2
LMP7702/LMP7704
40 60
120
Output Voltage Swing Low RL = 2 k to V+/2
LMP7701
50 80
90
mV
RL = 2 k to V+/2
LMP7702/LMP7704
50 120
190
RL = 10 k to V+/2
LMP7701
30 40
50
RL = 10 k to V+/2
LMP7702/LMP7704
30 50
100
IOUT Output Current
(Notes 3, 9)
Sourcing VO = V+/2
VIN = 100 mV (LMP7701)
40
28
66
mA
Sourcing VO = V+/2
VIN = 100 mV (LMP7702/LMP7704)
38
25
66
Sinking VO = V+/2
VIN = −100 mV (LMP7701)
40
28
76
Sinking VO = V+/2
VIN = −100 mV (LMP7702/LMP7704)
40
23
76
ISSupply Current LMP7701 0.715 1.0
1.2
mA
LMP7702 1.5 1.9
2.2
LMP7704 2.9 3.7
4.6
SR Slew Rate (Note 10) AV = +1, VO = 4 VPP
10% to 90%
1.0 V/μs
GBW Gain Bandwidth 2.5 MHz
THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, RL = 10 k 0.02 %
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LMP7701/LMP7702/LMP7704
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
enInput Referred Voltage Noise Density f = 1 kHz 9 nV/
inInput Referred Current Noise Density f = 100 kHz 1 fA/
±5V Electrical Characteristics (Note 4)
Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5V, V = −5V, VCM = 0V, and RL > 10 k to 0V. Bold-
face limits apply at the temperature extremes.
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
VOS Input Offset Voltage LMP7701 ±37 ±200
±500 μV
LMP7702/LMP7704 ±37 ±220
±520
TCVOS Input Offset Voltage Temperature Drift (Note 7) ±1 ±5 μV/°C
IBInput Bias Current (Notes 7, 8)
−40°C TA 85°C
±0.2 1
±50
pA
(Notes 7, 8)
−40°C TA 125°C
±0.2 1
±400
IOS Input Offset Current 40 fA
CMRR Common Mode Rejection Ratio −5V VCM 5V
LMP7701
92
88
138
dB
−5V VCM 5V
LMP7702/LMP7704
90
86
138
PSRR Power Supply Rejection Ratio 2.7V V+ 12V, VO = 0V 86
82
98 dB
CMVR Common Mode Voltage Range CMRR 80 dB
CMRR 78 dB
−5.2
−5.2
5.2
5.2 V
AVOL Open Loop Voltage Gain RL = 2 kΩ (LMP7701)
VO = −4.7V to 4.7V
100
98
121
dB
RL = 2 kΩ (LMP7702/LMP7704)
VO = −4.7V to 4.7V
100
94
121
RL = 10 kΩ (LMP7701)
VO = −4.8V to 4.8V
100
98
134
RL = 10 kΩ (LMP7702/LMP7704)
VO = −4.8V to 4.8V
100
97
134
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LMP7701/LMP7702/LMP7704
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
VOUT Output Voltage Swing High RL = 2 k to 0V
LMP7701
90 150
170
mV
from V+
RL = 2 k to 0V
LMP7702/LMP7704
90 180
290
RL = 10 k to 0V
LMP7701
40 80
100
RL = 10 k to 0V
LMP7702/LMP7704
40 80
150
Output Voltage Swing Low RL = 2 k to 0V
LMP7701
90 130
150
mV
from V
RL = 2 k to 0V
LMP7702/LMP7704
90 180
290
RL = 10 k to 0V
LMP7701
40 50
60
RL = 10 k to 0V
LMP7702/LMP7704
40 60
110
IOUT Output Current
(Notes 3, 9)
Sourcing VO = 0V
VIN = 100 mV (LMP7701)
50
35
86
mA
Sourcing VO = 0V
VIN = 100 mV (LMP7702/LMP7704)
48
33
86
Sinking VO = 0V
VIN = −100 mV
50
35
84
ISSupply Current LMP7701 0.790 1.1
1.3
mA
LMP7702 1.7 2.1
2.5
LMP7704 3.2 4.2
5.0
SR Slew Rate (Note 10) AV = +1, VO = 9 VPP
10% to 90%
1.1 V/μs
GBW Gain Bandwidth 2.5 MHz
THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, RL = 10 k 0.02 %
enInput Referred Voltage Noise Density f = 1 kHz 9 nV/
inInput Referred Current Noise Density f = 100 kHz 1 fA/
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics
Tables.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-
Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >
TA.
Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 6: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using the Statistical Quality
Control (SQC) method.
Note 7: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 8: Positive current corresponds to current flowing into the device.
Note 9: The short circuit test is a momentary test.
Note 10: The number specified is the slower of positive and negative slew rates.
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LMP7701/LMP7702/LMP7704
Connection Diagrams
5-Pin SOT23 (LMP7701)
20127302
Top View
8-Pin SOIC (LMP7701)
20127364
Top View
8-Pin SOIC/MSOP (LMP7702)
20127303
Top View
14-Pin SOIC/TSSOP (LMP7704)
20127304
Top View
Ordering Information
Package Part Number Package Marking Transport Media NSC Drawing
5-Pin SOT23 LMP7701MF AC2A 1k Units Tape and Reel MF05A
LMP7701MFX 3k Units Tape and Reel
8-Pin SOIC LMP7701MA LMP7701MA 95 Units/Rail M08A
LMP7701MAX 2.5k Units Tape and Reel
8-Pin SOIC LMP7702MA LMP7702MA 95 Units/Rail M08A
LMP7702MAX 2.5k Units Tape and Reel
8-Pin MSOP LMP7702MM AA3A 1k Units Tape and Reel MUA08A
LMP7702MMX 3.5k Units Tape and Reel
14-Pin SOIC LMP7704MA LMP7704MA 55 Units/Rail M14A
LMP7704MAX 2.5k Units Tape and Reel
14-Pin TSSOP LMP7704MT LMP7704MT 94 Units/Rail MTC14
LMP7704MTX 2.5k Units Tape and Reel
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LMP7701/LMP7702/LMP7704
Typical Performance Characteristics Unless otherwise noted: TA = 25°C, VCM = VS/2, RL > 10 kΩ.
Offset Voltage Distribution
20127336
TCVOS Distribution
20127341
Offset Voltage Distribution
20127337
TCVOS Distribution
20127342
Offset Voltage Distribution
20127338
TCVOS Distribution
20127343
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LMP7701/LMP7702/LMP7704
Offset Voltage vs. Temperature
20127306
CMRR vs. Frequency
20127350
Offset Voltage vs. Supply Voltage
20127310
Offset Voltage vs. VCM
20127307
Offset Voltage vs. VCM
20127308
Offset Voltage vs. VCM
20127309
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LMP7701/LMP7702/LMP7704
Input Bias Current vs. VCM
20127346
Input Bias Current vs. VCM
20127330
Input Bias Current vs. VCM
20127347
Input Bias Current vs. VCM
20127331
Input Bias Current vs. VCM
20127348
Input Bias Current vs. VCM
20127349
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LMP7701/LMP7702/LMP7704
PSRR vs. Frequency
20127345
Supply Current vs. Supply Voltage (Per Channel)
20127311
Sinking Current vs. Supply Voltage
20127313
Sourcing Current vs. Supply Voltage
20127312
Output Voltage vs. Output Current
20127316
Slew Rate vs. Supply Voltage
20127317
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LMP7701/LMP7702/LMP7704
Open Loop Frequency Response
20127315
Open Loop Frequency Response
20127314
Large Signal Step Response
20127318
Small Signal Step Response
20127320
Large Signal Step Response
20127319
Small Signal Step Response
20127326
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LMP7701/LMP7702/LMP7704
Input Voltage Noise vs. Frequency
20127327
Open Loop Gain vs. Output Voltage Swing
20127352
Output Swing High vs. Supply Voltage
20127333
Output Swing Low vs. Supply Voltage
20127335
Output Swing High vs. Supply Voltage
20127332
Output Swing Low vs. Supply Voltage
20127334
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LMP7701/LMP7702/LMP7704
THD+N vs. Frequency
20127328
THD+N vs. Output Voltage
20127329
Crosstalk Rejection Ratio vs. Frequency (LMP7702/
LMP7704)
20127353
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LMP7701/LMP7702/LMP7704
Application Information
LMP7701/LMP7702/LMP7704
The LMP7701/LMP7702/LMP7704 are single, dual, and quad
low offset voltage, rail-to-rail input and output precision am-
plifiers each with a CMOS input stage and wide supply voltage
range of 2.7V to 12V. The LMP7701/LMP7702/LMP7704
have a very low input bias current of only ±200 fA at room
temperature.
The wide supply voltage range of 2.7V to 12V over the ex-
tensive temperature range of −40°C to 125°C makes the
LMP7701/LMP7702/LMP7704 excellent choices for low volt-
age precision applications with extensive temperature re-
quirements.
The LMP7701/LMP7702/LMP7704 have only ±37 μV of typ-
ical input referred offset voltage and this offset is guaranteed
to be less than ±500 μV for the single and ±520 μV for the
dual and quad, over temperature. This minimal offset voltage
allows more accurate signal detection and amplification in
precision applications.
The low input bias current of only ±200 fA along with the low
input referred voltage noise of 9 nV/ gives the LMP7701/
LMP7702/LMP7704 superiority for use in sensor applications.
Lower levels of noise from the LMP7701/LMP7702/LMP7704
mean of better signal fidelity and a higher signal-to-noise ra-
tio.
National Semiconductor is heavily committed to precision
amplifiers and the market segment they serve. Technical sup-
port and extensive characterization data is available for sen-
sitive applications or applications with a constrained error
budget.
The LMP7701 is offered in the space saving 5-Pin SOT23 and
8-Pin SOIC package. The LMP7702 comes in the 8-Pin SOIC
and 8-Pin MSOP package. The LMP7704 is offered in the 14-
Pin SOIC and 14-Pin TSSOP package. These small pack-
ages are ideal solutions for area constrained PC boards and
portable electronics.
CAPACITIVE LOAD
The LMP7701/LMP7702/LMP7704 can each be connected
as a non-inverting unity gain follower. This configuration is the
most sensitive to capacitive loading.
The combination of a capacitive load placed on the output of
an amplifier along with the amplifier's output impedance cre-
ates a phase lag which in turn reduces the phase margin of
the amplifier. If the phase margin is significantly reduced, the
response will be either underdamped or it will oscillate.
In order to drive heavier capacitive loads, an isolation resistor,
RISO, in Figure 1 should be used. By using this isolation re-
sistor, the capacitive load is isolated from the amplifier's
output, and hence, the pole caused by CL is no longer in the
feedback loop. The larger the value of RISO, the more stable
the output voltage will be. If values of RISO are sufficiently
large, the feedback loop will be stable, independent of the
value of CL. However, larger values of RISO result in reduced
output swing and reduced output current drive.
20127321
FIGURE 1. Isolating Capacitive Load
INPUT CAPACITANCE
CMOS input stages inherently have low input bias current and
higher input referred voltage noise. The LMP7701/LMP7702/
LMP7704 enhance this performance by having the low input
bias current of only ±200 fA, as well as, a very low input re-
ferred voltage noise of 9 nV/ . In order to achieve this a
larger input stage has been used. This larger input stage in-
creases the input capacitance of the LMP7701/LMP7702/
LMP7704. The typical value of this input capacitance, CIN, for
the LMP7701/LMP7702/LMP7704 is 25 pF. The input capac-
itance will interact with other impedances such as gain and
feedback resistors, which are seen on the inputs of the am-
plifier, to form a pole. This pole will have little or no effect on
the output of the amplifier at low frequencies and DC condi-
tions, but will play a bigger role as the frequency increases.
At higher frequencies, the presence of this pole will decrease
phase margin and will also cause gain peaking. In order to
compensate for the input capacitance, care must be taken in
choosing the feedback resistors. In addition to being selective
in picking values for the feedback resistor, a capacitor can be
added to the feedback path to increase stability.
The DC gain of the circuit shown in Figure 2 is simply –R2/
R1.
20127344
FIGURE 2. Compensating for Input Capacitance
For the time being, ignore CF. The AC gain of the circuit in
Figure 2 can be calculated as follows:
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LMP7701/LMP7702/LMP7704
This equation is rearranged to find the location of the two
poles:
(1)
As shown in Equation 1, as values of R1 and R2 are increased,
the magnitude of the poles is reduced, which in turn decreas-
es the bandwidth of the amplifier. Whenever possible, it is
best to choose smaller feedback resistors. Figure 3 shows the
effect of the feedback resistor on the bandwidth of the
LMP7701/LMP7702/LMP7704.
20127354
FIGURE 3. Closed Loop Gain vs. Frequency
Equation 1 has two poles. In most cases, it is the presence of
pairs of poles that causes gain peaking. In order to eliminate
this effect, the poles should be placed in Butterworth position,
since poles in Butterworth position do not cause gain peaking.
To achieve a Butterworth pair, the quantity under the square
root in Equation 1 should be set to equal −1. Using this fact
and the relation between R1 and R2, R2 = −AV R1, the optimum
value for R1 can be found. This is shown in Equation 2. If R1
is chosen to be larger than this optimum value, gain peaking
will occur.
(2)
In Figure 2, CF is added to compensate for input capacitance
and to increase stability. Additionally, CF reduces or elimi-
nates the gain peaking that can be caused by having a larger
feedback resistor. Figure 4 shows how CF reduces gain peak-
ing.
20127355
FIGURE 4. Closed Loop Gain vs. Frequency with
Compensation
DIODES BETWEEN THE INPUTS
The LMP7701/LMP7702/LMP7704 have a set of anti-parallel
diodes between the input pins, as shown in Figure 5. These
diodes are present to protect the input stage of the amplifier.
At the same time, they limit the amount of differential input
voltage that is allowed on the input pins. A differential signal
larger than one diode voltage drop might damage the diodes.
The differential signal between the inputs needs to be limited
to ±300 mV or the input current needs to be limited to ±10 mA.
20127325
FIGURE 5. Input of LMP7701
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LMP7701/LMP7702/LMP7704