AF82801JIR S LB8S AF82801JIR SLB8S - INTEL

Notice: The Intel

I/O Controll er Hu b 10 (ICH 10) may contain des ig n defe ct s or error s known as errata which

may cause the product to deviate from published specifications. Current characterized errata are documented in

this spe cific a ti on upd a te.

Document Number: 319974-016

Intel® I/O Controller Hub 10

(ICH10) Family

Specification Update

May 2012

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

2Document Number: 319974-016

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The Intel

I/O Controller Hub 10 (ICH10) F amily chipset component may contain design defects or errors known as errata which may cause the prod uct

to deviate from published specifications. Current characterized errata are available on requ est.

Contact your local Intel sales office or your dist ributor to obtain the latest specifications and before placing your product order.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of t he I

C bus/protocol and was developed by Intel.

Implementations of the I

C bus/proto col ma y re qu ir e lice n se s fro m v a r io us e nti ties , including Philips Electr o nic s N. V. and North A mer ica n P hil ip s

Corporation.

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Active Management Technology requires activation and a system with a corpo rate network connection, an Intel® AMT-enabled chipset, n etwork

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power, sl eepi n g, hibe rnating or powered of f. Resu lts de pe nden t upon hard ware, se tup and config uration. For more info rm ation , see

www.intel.com/technology/platform-technology/intel-amt/

Intel

Virtualization Technology requires a computer system with an enabled Intel

processor, BIOS, virtual machine monitor (VMM). Functionality,

performance or other benefits will vary depending on hardware and so ftware configurations. Software applications may not be compatible with all

operating systems. Consult your PC manufacturer. For more information, visit http://www.intel.com/go/virtualization

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Trusted Execu tio n Technology (Intel

TXT) requires a computer system

with Intel Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible meas u red

launch ed en vironment (MLE). The MLE coul d c o ns ist of a virtua l m a chine monitor, an OS o r an application. In addition, I nte l TXT requires the system to

contain a TPM v1.s . For more in formation, see http://www.intel.com/technology/security

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High Definition Audio requires an Intel

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Intel, Intel logo, Intel SpeedStep, and Intel vPro are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

Contents—ICH10

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 3

Contents

Preface......................................................................................................................7

Summary Tables of Changes......................................................................................8

Identification Information....................................................................................... 11

Intel® ICH10 Device and Revis ion Identificati on..................................................... 12

Errata...................................................................................................................... 14

Specification Cha n g e s.............................................................................................. 21

Spec if ic a t io n C la r if ic a t io ns ...................................................................................... 22

Document Chan ges.................................................................................................. 23

ICH10—Revision History

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

4Document Number: 319974-016

Revision History

Revision Description Date

-016 A dde d It e m :

- Errata: 19- Incorrect IRQ(x) Vector Returned for 8259 Interrupts With RAEOI Enabled

- Specification Change: 1- ROAEI options removal for OCW2 May 2012

-015 A dde d It e m s:

- Docume n t Ch ang es : 2 0- Co r rect OUTSTRMPAY Register informati on

- Document Changes: 21 - Correct INSTRMPA Y Register information December 2011

-014 A dde d It e m s:

- Errata: 18 Intel

ICH10 SATA GEN3 Device Detection

- Errata: 16 Intel

I/O Controller Hub 10 (ICH10) Fam ily HPET Write Timing February 2011

-013 A dde d It e m s:

- Document Changes: 19-Update Section 8.2 in the Datasheet

- Errata: 18 Intel

ICH10 SATA GEN3 Device Detection December 2010

-012 A dde d It e m s:

- Errata: 17 Intel

ICH10 Corporate May Not Detect Unsolicited SATA COMINITs

- Document Changes: 18 - Correct A20M# Signal Description November 2010

-011 A dde d It e m s:

- Document Changes: 17-Correct Section 13.1.23 Bits 15:2 definition May 2010

-010 A dde d It e m s:

- Errata: 16 Intel

I/O Controller Hub 10 (ICH10) Fam ily HPET Write Timing

- Document Changes: 16- Correct Section 10.1.45 Bit 0 definition February 2010

-009 A dde d It e m s:

- Errata 15 Intel

I/O Controller Hub 10 (ICH10) Family SATA SYNC Escape December 2009

-008

Added Ite m s:

- Errata: 14- Intel

I/O Controller Hub 10 (ICH10) Family PCI Express Function Disable

-Document Changes: 15- Correct Section 5.13.6.5 Sx-G3-Sx, Handling Po wer Failures

regardin g wake events following a powe r fa ilure

August 2009

-007

Added Ite m s:

- Errata: 13- Intel

I/O Controller Hub 10 (ICH10) Family SATA Low Power Device Detection

-Document Changes: 13 -Correct SMBCLK_CTL bit default v alue 14 - C orrect Table 2-24 Strap

selection for Boot BIOS Destinatio n

July 2009

-006

Added Ite m s:

Corrected Device ID fo r D30:F0 in Table 2-27 ICH10 Consumer Device and Rev ID Table

Document Changes:

9- Remove GPIO58 from Figure 2-1 Intel

ICH10 Interface Signals Block Diagram. 10- Add

1.1v for VccDMI in Table 2-24.

11-Correct Bit Ty pes for PCI Express UnCorrectable Error Severity register (UEV) Corporate

ICH10. 12- Correct PCI Expre ss DSTS register definition for bit 1 (NFED)

April 2009

-005 A dde d It e m s:

Document Change: 8- Add foot note for all references to SPI Flash descriptors ICHSTRP0 and

MCHSTRP0 February 2009

-004 A dde d It e m s:

Document Changes: 6- Make correction to Table 5-40 Causes of Hos t and Global Resets 7-

Update bit definition for SECOND_TO_STS January 2009

Revision History—ICH10

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 5

-003

Added Ite ms :

Document Changes: 1-Add G PIO Reset Notes, 2- Correct EOIFD bit definition, 3- Correct

GPI_I N V -G PIO Sign a l In ver t re gi s ter definition 4- Update TBD defaults. 5 Update GPIO Note

#4 in Section 3.2 Output and I/O Signals Planes and States

December 2008

-002

Added Int e l ICH1 0 Co rp orat e compone nts

- Intel 82801JD ICH10 Corporate Base (ICH10D)

- Intel 82801JDO ICH10 Digital Office (ICH10DO)

Added Errata 7-12.

September 2008

-001 Initial Release. June 2008

Revision Description Date

ICH10—Revision History

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

6Document Number: 319974-016

Preface

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 7

Preface

This document is an update to the specifications contained in the Affected

Documents/Related Documents table below.

This document is a compilation of device

and do c um enta ti on er rata, spe c ification cl a r ificat ions and chang es .

It is intended for

hardware system manufacturers and software developers of applications, operating

systems, or tools.

Infor m a tion types defined in No m enclature are consolidated into the specification

update and are no longer published in other documen ts.

This document may also contain information that was not previously published.

Affected Documents/Related Documents

Nomenclature

Errata are design defects or errors. Errata may cause the ICH10's behavior to deviate

from publ ish ed specifications. Hardware and software de sign ed to be used with an y

given stepping must assume that all errata documented for that stepping are present in

all devices.

Speci fication Cha n ges are modifications to the current published specifications.

These chan ges w il l be incorporated in any new release of the specific ation.

Specifica tio n Cla rificat ions describe a specification in greater detai l or further

highlight a specification’ s impact to a complex design situation.

These clarifications will

be incorporated in any new release of the specification.

Documentation Chan ges include typos, errors, or omi ssions from the current

publis hed specifica tions. These will be incorpora ted in any new release of th e

specification.

Title Document

Number

Intel

I/O Controller Hub 10 (ICH10) Family Datasheet 319973

Summary Tables of Changes

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

8Document Number: 319974-016

Summary Tables of Changes

The follo wi ng tables in dicate the erra ta, s pec ification changes, s pec ification

clarifications, or documentation changes which apply to the ICH10 product family. Intel

may fix some of the errata in a future stepping of the component, and account for the

other outstanding issues through documentation or specification changes as noted.

These tables uses the following notations:

Codes Used in Summary Tables

Stepping

X: Errata exists in the stepping indicated. Sp ecification Change or

Clarification that applies to this stepping.

(No mark)

or (Bla nk box): This erratum is fixed in listed stepping or s pecification change

does not apply to listed steppin g.

Page

(Page): Page location of item in this document.

Status

Doc: Document change or update will be implemented.

Plan Fix: This erratum may be fixed in a future stepping of the product.

Fixed: This err a tu m has been previously fixed.

No Fix: There are no plans to fix this erratum.

Row

Chang e ba r to left of ta ble row indic a tes this erratum is either

new or modified from the previous version of the document.

Summary Tables of Changes

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 9

Errata

Erratum

Number

Stepping

Status ERRATA

Consumer B0

Corporate

1X No Fix

Intel

I/O Contro ll er Hub 10 (ICH10) Consu mer Family UHCI Hang wit h

USB Reset

2X No Fix

Intel

I/O Controller Hub 10 (ICH10) Consumer F amily THRM Polarity on

SMBus

3X No Fix

Intel

I/O Controller Hub 10 (ICH10) Consumer Family High Speed (HS)

USB 2.0 D+ and D- Maximum Driven Signal Level

4X No Fix

Intel

I/O Controller Hub 10 (ICH10) Consumer Family PET Alerts on

SMBus

5X No Fix

Intel

I/O Controller Hub 10 (ICH10) C onsumer Family SMBus Host

Controller May Hang

No Fix

(Consumer)

Fixed

(Corporate)

Intel

I/O Controller Hub 10 (ICH10) Family LAN_PHY_PWR_CTRL

Functionality

7X No FixIntel

I/O Controller Hub 10 (ICH10) Family High-speed USB 2.0 V

HSOH

8X No Fix

Intel

I/O Controller Hub 10 (ICH10) F am ily 1.5 Gb/s SATA Signal

Voltage Level

9XNo Fix

Intel

I/O Controller Hub 10 (ICH10) Corporate Fam ily System Re s et

with Intel

Anti-Theft Technology

10 X No Fix Intel

I/O Controller Hub 10 (ICH10) Corporate Family LAN_RST#

Asse rtion on Sx/ M of f En tr y

11 X No Fix Intel

I/O Controller Hub 10 (ICH10) Corporate Fam ily Power Button

Override Behavio r

12 X No Fi x ICH10 C or porat e ME SM B u s/S MLink Clock Frequ e n cy

13 X X No Fix Intel

I/O Controller Hub 10 (ICH10) Family SATA Low Power De v ice

Detection

14 X X No Fix Intel

I/O Controller Hub 10 (ICH10) Family PCI Express Function

Disable

15 X X No Fix Intel

I/O Controller Hub 10 (ICH10) Family SAT A SYNC Escape

16 X X No Fix Intel

I/O Controller Hub 10 (ICH10) Family HPET Write Timing

17 X No Fix Intel

ICH10 Corporate May Not Detect Unsolicited SATA COMINITs

18 X X No Fix Intel

ICH10 SAT A GEN3 Dev ice Detection

19 X X No Fix Incorrect IRQ(x) Vector Returned for 8259 Interrupts With RAEOI

Enabled

Specification Changes

Spec

Change

Number SPECIFICATION CHANGES

1 ROAEI options removal for OCW2

Summary Tables of Changes

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

10 Document Number: 319974-016

Specification Clarifications

No. SPECIFICATION CLARIFICAT IONS

There are no Specification Clarifications in the revision of the Specification Update

Documentation Changes

No. DOCUMENTATION CHANGES

1 Add GPIO Reset Notes

2 Correct EOIFD bit Definition

3 Correct GPI_INV -GPIO Signal Invert regis ter definitio n

4 Update TBD defaults

5 Update GPIO Note #4 in Section 3.2, Output and I/O Signals Planes and States

6 Make corre ct ion to Table 5- 40, Causes of Hos t and Global Resets

7 Update bit definition for SECOND_TO_STS

8 Add foot note for all references to SPI Flash descriptors ICHSTRP0 and MCHSTRP0

9 Remove GPIO58 from Figure 2-1 Intel

ICH10 Interface Signals Block Diagram

10 Add 1.1v for VccDMI in Table 2-24

11 Correct Bit Types for PCI Express UnCorrect ab le Erro r Sev erity register (UEV) Corporate ICH 10

12 Correct PCI Express DSTS regi s ter de finition for bit 1 (NFED)

13 Correct SMBCLK_CTL bit default value

14 Correct Table 2-24, Strap selection for Boot BIOS Destination

15 Correct Section 5.13.6.5, Sx-G3-Sx, regarding possible wake events following a power failure

16 Correct Secti on 10. 1.45, Bit 0 definition

17 Correct Section 13.1.23, Bits 15:2 definition

18 Correct A20M# signal description

19 Update Section 8.2 in the Datasheet

20 Correct OUTSTRMPAY Register information

21 Correct INSTRMP AY Register information

Identification Information

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 11

Identification Information

Markings

ICH10

Stepping S-Spec Top Mar k i n g Note s

Consumer

A0 SLB8R AF82801JIB 82801JIB ICH10 (Base)

A0 SLB8S AF82801JIR 82801JIR ICH10R

Corporate

B0 SLG8T AF82801JD 82801JD ICH10D

B0 SLG8U AF82801JDO 82801JDO ICH10DO

Intel® ICH10 Device and Revision Identification

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

12 Document Number: 319974-016

Intel

ICH10 Device and Revision Identification

Intel

ICH10 Corporate Device and Revi sion ID Table

Device

Function Description Intel

ICH10 Dev

ICH10

B0 Rev

ID Comments

D31:F0 LPC 3A14h 02h ICH10DO

3A1Ah 02h ICH10D

D31:F21 SATA

3A00h 02h Non-AHCI and Non-RAID Mode (Po rts 0,1, 2

and 3)

3A02h 02h AHCI Mode (Ports 0-5)

3A05h

02h RAID 0/1/5/10 Mode

D31:F51 SATA 3A06h 02h Non-AHCI and Non-RAID Mode (Ports 4 and

D31:F3 SMBus 3A60h 02h

D31:F6 Thermal 3A62h 02h

D30:F0 DMI to PCI Bridge 244Eh A2h

D29:F0 USB UHCI #1 3A64h 02h

D29:F1 USB UHCI #2 3A65h 02h

D29:F2 USB UHCI #3 3A66h 02h

D29:F3 USB UHCI #6 3A69h 02h Note: Device and Revision ID is always the

same as D26:F2.

D29:F7 USB EHC I #1 3A6Ah 02h

D26:F0 USB UHCI #4 3A67h 02h

D26:F1 USB UHCI #5 3A68h 02h

D26:F2 USB UHCI #6 3A69h 02h

D26:F7 USB EHC I #2 3A6Ch 02h

D27:F0 Intel

High

Definition Audio 3A6Eh 02h

D28:F0 PCI Express* Port 1 3A70h 02h

D28:F1 PCI Express Port 2 3A72h 02h

D28:F2 PCI Express Port 3 3A74h 02h

D28:F3 PCI Express Port 4 3A76h 02h

D28:F4 PCI Express Port 5 3A78h 02h

D28:F5 PCI Express Port 6 3A7Ah 02h

D25:F0 LAN 3A7Ch

02h

D23:F0 VECI 3A51h 02h ICH10DO Only

D22:F01 SATA 3A55h 02h Virtualized S AT A contro ller for use by Intel

Anti-Theft Technology

Intel® ICH10 Device and Revision Identification

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 13

Notes:

1. ICH10 con ta i n s mu l ti pl e SATA devices. The SATA Device ID is dep en da n t u pon wh i ch SATA mode is

selected by BIOS and what RAID capabilities exist in the SKU.

2. LAN Device ID is loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the Device ID

location, then 3A7Ch is used. Refer to the 82567 GbE Physical Layer Transceiver (PHY) Datasheet for

LAN Device IDs.

3. The SATA RAID Controller Device ID may reflect a different value based on Bit 7 of D31:F2:Offset 9Ch

NOTES:

1. ICH10 contains two SATA devices. The SATA Device ID is dependant upon which SATA mode is selected

by BIOS and what RAID capabilities exist in the SK U.

2. LAN Device ID is loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the Device ID

location, then 3A4Ch is used. Refer to the 82567 GbE Physical Layer Transceiver (PHY) Datasheet for

LAN Device IDs.

3. The SATA RAID Controller Device ID may re f lect a different value based on Bit 7 of D31:F 2:Of fset 9Ch.

Intel

ICH10 Consumer Device and Revision ID Table

Device

Function Description Intel

ICH10 Dev

ICH10

A0 Rev

ID Comments

D31:F0 LPC 3A16h 00h ICH10R

3A18h 00h ICH10 (Consumer Base)

D31:F21 SATA

3A20h 00h Non-AHCI and Non-RAID Mode (Ports 0,1, 2

and 3)

3A22h 00h AHCI Mode (Ports 0-5)

3A25h3 00h RAID 0/1/5/10 mode

D31:F51 SATA 3A26h 00h Non-AHC I and Non-RAID Mode (Ports 4 and 5)

D31:F3 SMBus 3A30h 00h

D31:F6 Thermal 3A32h 00h

D30:F0 DMI to PCI Bridge 244Eh 90h

D29:F0 USB UHCI #1 3A34h 00h

D29:F1 USB UHCI #2 3A35h 00h

D29:F2 USB UHCI #3 3A36h 00h

D29:F3 USB UHCI #6 3A39h 00h Note : Device and Revi sion ID is al way s t he

same as D26:F2.

D29:F7 USB EHCI #1 3A3Ah 00h

D26:F0 USB UHCI #4 3A37h 00h

D26:F1 USB UHCI #5 3A38h 00h

D26:F2 USB UHCI #6 3A39h 00h

D26:F7 USB EHCI #2 3 A3Ch 00h

D27:F0 Intel

High

Definition Audio 3A3Eh 00h

D28:F0 PCI Express* Port

13A40h 00h

D28:F1 PCI Express Port 2 3A42h 00h

D28:F2 PCI Express Port 3 3A44h 00h

D28:F3 PCI Express Port 4 3A46h 00h

D28:F4 PCI Express Port 5 3A48h 00h

D28:F5 PCI Express Port 6 3A4Ah 00h

D25:F0 LAN 3A4Ch2 00h

Errata

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

14 Document Number: 319974-016

Errata

1. Intel® I/O Controller Hub 10 (ICH10) Consumer Family UHCI Hang

with USB Re set

Problem: When SW initiates a Host Controller Reset or a USB Global Reset while concurrent

traffic occurs on at least three UHCI controllers, the UHCI controller(s) may hang.

Note: The issue has only been replicated in a synthetic rese t test environment.

Impl ic a tion: System may han g.

Workaround: BIOS wo rkaround availabl e. C ontact your Inte l field repre sentative for the lat est BIOS

information.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

2. Intel® I/O Controller Hub 10 (ICH10) Consumer Family THRM Polarity

on SMBus

Pro blem : When THRM #_ POL (PM B AS E+ 42 h:b it 0) is s et t o h igh, th e TH RM# pin s t ate as re po rted

to the SMBus TCO unit is logic a lly invert ed .

Implication: If the THRM#_POL bit is set to high, an external SMBus master reading the BTI

Temperature Event status will not receive the correct state of the THRM# pin. The value

will b e logically inverted. If THRM#_P O L is set to low, value is correct.

Workaround: None.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

3. Intel® I/O Controller Hub 10 (ICH10) Co nsumer Family High Speed

(HS) USB 2.0 D+ and D- Maximum Driven Signal Level

Problem: During Start-of-Packet (SOP)/End-of -Packet (EOP), the ICH10 Consumer may drive D+

and D- lines to a level greater than USB 2.0 spec +/-200mV max.

Implication: May cause High Speed (HS) USB 2.0 devices to be unrecognized by OS or may not be

readable/writable if the foll owing two conditions are met:

•

The receiver is pseudo differential design

•

The receiver is not able to ign ore SE1 (single-ended) state

Note: Intel has only observed this issue with a motherboa r d down HS USB 2 . 0 device using

pseudo differential design. This issue will not affect HS USB 2.0 devices with

complementary differential design or Low Spee d (LS ) and Ful l Speed (FS) devices

Workaround: None.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

Errata

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 15

4. Intel® I/O Controller Hub 10 (ICH10) Consumer Family PET Alerts on

SMBus

Problem: When using the ICH Consumer SMBus for Platform Event Trap (PET) alerts on a system

with the Intel

Management Engine (ME) enabled, the SMBus packet headers may be

corr upted if al l of the following co nd itions a r e met:

•

SMBus sl ave is the target of an ext ern al PET generating master on SMBus/SMLink

•

The ME is in the middle of M0-M1 transitions

•

SMBus slave receives ba c k-to-back PET alerts of which some PET alerts are

inco mp l ete (i. e. the packe t is tr uncate d to less tha n 6 bytes)

Note: This issue has only been observed under a synthetic test environment.

Implication: ME firmware may stop functioning, which could cause a system hang.

Workaround: None

Status: No Fix. For steppings affected, see the Summary Table of Changes.

5. Intel® I/O Cont r o ll er Hub 10 (ICH10) Consumer Fami ly SMBus Host

Contro ll er May Hang

Problem: During heavy SMBus traffic utilization, the ICH10 Consumer SMBus host controller may

attempt to start a transaction while the bus is busy.

Note: This issue has only been observed under a synthetic test environment.

Implication: May cause the SMBus host controller to hang.

•After boot:

— SMBus host controller transaction may not complete.

— External master transaction in progress targeting ICH10 Consumer SMBus

slave may get NACK or timeout.

— There is no impact to any other transaction that was in progress by an external

master.

• This issue has not been o bserved d uring boot as SMBus utilization tend s to be light.

Work around: BIOS workaround available. Cont act your Intel field represen tative for the late st BIOS

information.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

Errata

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

16 Document Number: 319974-016

6. Intel® I/O Controller Hub 10 (ICH10) Family LAN_PHY_PWR_CTRL

Functionality

Problem: LAN_PHY_PWR_CTRL output is driven low by the ICH10 during a host reset with or

without power cycle for up to 3 RTC clock cycles due to the pin momentarily being

configured as an output GPIO.

• LAN_PHY_PWR_CTRL functionality requires a soft strap setting in the SPI descriptor

and use of the integrated LAN controll er in ICH1 0 with the Intel

82567 PHY.

Implication: Functional failures such as sy stem hangs or link loss with dropped packets have been

observed when LAN_PHY_PWR_CTRL is tied to the LAN_DISABLE_N pin on the Intel

82567.

Note: There are no functional implications if the pin is configured as GPIO12.

For ICH10 Consumer based platforms:

• Intel ME-Enabled Platforms: An Intel ME FW workaround will be provided in the PC

FW releas e.

— Both the Intel ME Disab le bits i n the SPI flash descriptor (ICHSTRP0

bit 0 &

MCHSTRP0

bit 0) must be set to 0 to enable the ME FW workaround.

— MCHSTRP0

bit 7 in the SPI flash descriptor can be set to disable all other ME

FW based fe atures while ke eping the Intel ME F W wo rkaround enabled.

• Non Intel ME-Enabled Platfo rms: Remove LAN_PHY_PWR_CTRL Supp ort on the

Platform.

— Isolate the LAN_PHY_PWR_CTRL signal from the LAN_DISABLE_N pin.

— LAN_DISABLE_N has a weak integrated pull-u p resist or and th e Inte l 82567

PHY will always rem a i n e d enabled with this imp lemen ta t ion.

Note: ICHSTRP0

and MCHSTRP0

are in the SPI fl ash descriptor and programmed by

Original Equipment M anufactures.

For ICH1 0 Corpo rate based platforms:

—None.

Status: ICH10 Corporate: Fixed. For steppings affected, see the Summary Table of Changes.

ICH10 Consumer: No Fix. One of the proposed workarounds must be implemented. For

steppings affected, see the Summary Table of Changes.

7. Intel® I/O Controller Hub 10 (ICH10) Family High-speed USB 2.0

VHSOH

Problem: ICH10 High-speed USB 2.0 VHSOH may not meet the USB 2.0 specification

• The maximum expected VHSOH is 460 mV.

Implication: N one known. No Fix

Workaround: None.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

Errata

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 17

8. Intel® I/O Controller Hub 10 (ICH10) Family 1.5 Gb/s SATA Signal

Volt ag e L evel

Problem: The ICH10 1.5 Gb/s SATA transmit buffers have been designed to maximize

performance and robustness over a varie ty of routing scenarios. As a result, the ICH10

SATA 1.5 Gb/s (Gen1i and Gen1m) transmit signaling voltage levels may exceed the

maximum motherboard TX connector and device RX connector voltage specifications

(Section 7. 2. 1 of Serial ATA Specificat ion, rev 2.5).

Implication: None Known.

Workaround: None.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

9. Intel® I/O Contr o ll er Hub 10 (IC H 10) Corporate Fa mil y System Reset

with Intel® Anti-Theft Technology

Problem: If Intel Anti-Theft Technology is enabled on a platform, a CF9h write of 06h or 0Eh

when the CF9h Global Reset bit is clear (D31:F0:ACh:bit 20) will cause the ICH10 to

not complete the reset seque nce properly.

Implication: The ICH10 will complete a global reset after 4 seconds instead of an immediate host

partition reset.

Workaround: For ICH10 Corporate A0/A1 silicon none. For ICH10 Corporate B0 silicon a BIOS

workaround must be im plemented. S e e the ICH 10 BIOS specification for details.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

10. Intel® I/O Controller Hub 10 (IC H 10) Cor porate Famil y LA N _ RST#

Assertion on Sx/MOff Entry

Problem: If the integrated LAN controller is powered down (LAN_RST# is asserted) in Sx/Moff,

the SP I c ontroller ma y not reset completely.

— Platforms that do not support the integrated LAN controller (LAN_RST# is

always asserted) are not impacted.

— Platforms that always power VccLAN3_3 in S0-S5 are also not impacted.

Implication: Upon platform wake, the integrated LAN Cont roller a nd Inte l Manage ment Eng ine may

be unable to in itialize or respond to PCI co nfiguration space accesses which can cause

the plat form to hang with IERR# asserted by th e CPU.

Workaround: For platforms without Intel ME FW, one of the following options maybe be

implemented:

1. Motherboard design must ensure LAN_RST# asserts within 500 nanoseconds of

SLP_M# as ser t ing on Sx/ Moff entry or

2. VccLAN3_3 must always be powered in S0-S5

Note: ICHSTRP0

Bits 29 : 27 m ust be set to 000b if usin g one of the hardware based

workarounds above.

For platforms with Intel ME FW:

This iss u e is re solved wit h Intel ME FW 10 7 9 or later and require s ICHSTRP0* bits

29:27 to be set correctly. See table below for platform configuration specific settings.

Errata

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

18 Document Number: 319974-016

Note: ICHSTRP0

is in the SPI flash descri pt or and prog rammed by Original Equipment

Manufactures.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

11. Intel® I/O Controller Hub 10 (ICH10) Corporate Family Power Button

Override

Problem: When in S0/1 after waking from a sleep state (S3-S5), triggering a power button

override event will require the ICH10 PWRBTN# pin to be driven low for up to 9-10

seconds.

Note: ICH10 Corporate based platforms alw ay s require PWRBTN# to assert for

9-10 seconds to trigger a power button override event when the platform is in S3

or S4. This desired beh avior ensures a wake event that is del ayed by SLP_S3#

and/or SLP_S4# str etching can be observed before unintentionally triggerin g a

powe r b utton overri de event.

Implication: Instead of taking 4-5 seconds to initiate a power button override event from S0/1,

ICH10 corporate based platforms may require PWRBTN# to assert for up to 9-10

seconds.

Wor karou nd: T he In tel

Management Engine’s capability allows fo r a FW workaround which ensures

a power button override event is triggered when PWRBTN# is asserted fo r 4-5 seconds

in S0/1. This workaround has been included in the Intel

Management Engine

Firmware 5.0 McCreary Prod uction Candidate release.

Note: As long as ME FW (PC or later release) is included in the ME region on the SPI

device the FW workaround will always be enabled, even if ME is disabled in the

flash descript or.

A workaround is not available for pl atf orms that do not support ME F W.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

12. Intel® I/O Controller Hub 10 (ICH10) Corporate Family ME

SMBus/SMLink Clock Frequency

Problem: When ICHSTRP0

bits 15:14 for ME SMBus Controller 2 and/or 13:12 for ME SMBus

Controller 1 are set to 01 (EDS recommended value), the ME SMBus Controllers will

drive the bus at 125 kHz instead of the expect ed 100 kHz.

— The host SMBus controller is not impacted by this issue. The host SMBus

controll er whe n ac ting as th e bus m aster will driv e the S MBus cl ock at 100 kHz .

Impli ca tion: No kno wn functi on a l fa il ur es have been ob s erved or repor ted to In te l.

Motherboard designers should evaluate the ability of all slave devices on the same

interface as the ME SMBus controller to reliable recei ved a 125 kHz clock input to

determine impact to their platform.

Table 1. ICHST RP0 Bits 29:27 Setting Recommendations

Motherboard LAN Power Configuration ICHSTRP0* Bits 29:27 Settings

VccLAN3_3 is tie d to VccSus3_3 000b

Design ensures LAN_RST# asserts within 500

nanoseconds of SLP_ M# assert ion on Sx /MO ff ent ry

VccLAN3_3 is tied to Vcc3_3 001b

VccLAN3_3 is powered of VccSus3_3 using WOL_EN and

SLP_M# Or gate 010b

Reserved 011b-111b

Errata

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 19

Workaround: Configure the ME SMBus Controllers to run at 80 kHz by setting ICHSTRP0

bits 15:14

and/or 13 :12 to 00 in the flash descriptor.

Note: ICHSTRP0* is in the SPI flash descriptor and programmed by Original Equipment

Manufactures.

Status: No Plan Fix. For steppings affected, see the Summary Table of Changes.

13. Intel® I/O Controller Hub 10 (IC H 10) Fam il y SATA Low Power Device

Detection

Problem: Intel

ICH10 Family SATA Low Power Device Detection (SLPD) may not recognize, or

may falsely detect, a SATA hot-plug event during a Partial or Slumber Link Power

Management (LPM) state.

Impli c ati on: Th is issu e affe cts ICH10, ICH10R, IC H1 0D, and ICH10 DO

On systems which enable LPM, when a SA T A device attached to the ICH10 is configured

as External or Hot P lug capable, one of the following sympt om s m ay occur:

• Symptom #1: A Hot-Plug or External SATA device removal which is not detected

results in the OS and Intel

Matrix St orage Manager c onsole falsely reporting the

device present, or incorrectly ident ifying an eSATA device.

• Symptom #2: A fa ls e hot-p lug removal detection may occur r esulting in OS boot

hang or OD D me dia play ba c k hang.

Workaround: A driver workaround is available.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

14. Intel® I/O Controller Hub 10 (IC H 10) Fam il y PCI Expr ess Function

Disable

Problem: Intel

ICH10 Family PCI Express [1:16] Disable bit in Function Disable Register may

not put the PCI Express Port into a link down state if a PCI Express Device is attached.

Implication: ICH10, ICH10R, ICH10D and ICH10D0:

PCI Express Port [1:6] with a PCI Express device attached may remain in L0 State and

DMI may not be able to go into L1 State.

Workaround: A BIOS workaround has been identified

Status: No Fix. For steppings affected, see the Summary Table of Changes.

15. Intel® I/O Controller Hub 10 (ICH10) Family SATA SYNC Escape

Problem: When a SYNC Escape by a SATA device occurs on a D2H FIS, the ICH10 does not set

the PxIS.IFS bit to ‘1.’ This deviates from Section 6.1.9 of the Rev 1.3 Serial ATA

Advanced Host Con troller Interface (AHCI)

Implication: There is no known observable impact. Instead of detecting the IFS bit, software will

detect a timeout error caused by the SYNC escape and then re spond

Workaround: None

Status: No Fix. For steppings affected, see the Summary Table of Changes.§

16. Intel® I/O Controll er Hub 10 (ICH10) Family HPE T Writ e T imi ng

Problem: A read transaction that immediately follows a write transaction to the HPET space may

return an incorrect value

Imp lication: Impleme ntati on is depe ndent on the usag e m odel as no ted bel ow:

F or th e H PE T TIM n_ COMP Timer 0 Comparator Value Register and HPET

MAIN_CNT—Main Counter Value Re gister the issue could result in the software

receiving stale data. This may result in undetermined system behavior.

Errata

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

20 Document Number: 319974-016

Note: Timers [1:7] are not affected by this issue

For TIMERn_VAL_SET_CNF bit 6 in the TIMn_CONF—Timer n Configuration th ere is no

known usage mod el for readi ng t his bit and there are no known functional implications.

A writ e to a Hig h P r ec ision Timer Configur a tion (HPTC) regis ter followed by a read to

HPET register space may ret urn all 0xFFFF_FFFFh

Workaround: A workaround is available.

Status: No Fix. For steppings affected, see the Summary Table of Changes.

17. Intel® ICH10 Corporate May Not Detect Unsolicited SATA COMINITs

Problem: Intel

ICH10 Corporate (ICH10D and ICH10DO) may not detect an unsolicited

COM INIT from a SATA device.

Implication: The SATA device may not be properly detected and configured resulting in the device

not functioning as expected

Workaround: A BIOS code change has been id entified and may be implement ed as a workaround for

this er ratum.

Status: No Plan to Fix.

18. Intel® ICH10 SATA 6.0 Gb ps Device Detection

Problem: Intel

ICH10 may not be able to complete SATA Out Of Band (OOB) Signaling with

SATA 6.0 Gbps Devices and down shift to SATA 3.0 Gbps speed.

Implication: ICH10 may not detect SA TA 6.0 Gbps Devices upon power up or resume from S3, S4 or

S5 State.

Workaround: None.

Status: No Plan to Fix.

19. Incorrect IRQ(x) Vector Returned for 8259 Interrupts With RAEOI

Enabled

Problem: If multiple interrupts are active prior to an interrupt acknowledge cycle with Rotating

Automatic End of Interrupt (RAEOI) mode of operation enabled for 8259 interrupts

(0-7), an incorrect IRQ(x) vector may be returned to the CPU.

Implication: Implications of an incorrect IRQ(x) vector being returned to the CPU are SW

implementation dependent.

Note: This issue has only been observed in a synthetic test environment.

Workaround: None.

Status: No Plan to Fix.

Specification Changes

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 21

Specification Changes

1. ROAEI options remova l for O CW 2

R emo v e bit setting “000” and “100” for Operational Control Word 2 Register bits [7:5 ]

in section 13. 4. 8.

13.4.8 OC W2—O perational Control Word 2 Regi st er (L PC I/F-D3 1:F0)

Offset Address: Master Controller

–

020h Attribute:W O

Slav e C on troller

–

0A0h Size : 8 bits

Default Value: Bit[4:0]=un defined, Bit[7:5 ] = 001

Following a part reset or ICW initialization, the controller enters the fully nested mode

of operation. N on-specif ic EOI without rotation is the default. Both rotation mo de a nd

spec ific EOI mode are disabled fo llowing init ia lization.

Bit Description

7:5

Rotate and EOI Codes (R, SL, EOI) —WO. These three bits control the Rotate and End of

Interrupt modes and combinations of the two.

000 = R o tate in Auto EOI Mode (Clear) Reserv e d

001 = Non-specific EOI command

010 = No Operation

011 = *Specific EOI Command

100 = R o tate in Auto EOI Mode (Set) Reserved

101 = Rotate on Non-Sp ecific EOI Command

110 = *Set Priority Co mmand

111 = *Rotate on Specific EOI Command

*L0 – L2 Are Used

Specification Clarifications

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

22 Document Number: 319974-016

Specification Clarifications

There are no Specification Clarifications in the revision of the Specification Update.

Document Changes

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 23

Document Changes

1. Add GPIO Signal Res et Notes

Add the f ollowing notes a bove Table 2-23 in Section 2.23 of the Datasheet.

Note:

1. GPIO Configurations registers within the Core Well are reset whenever PWROK is

de-asserted.

2. GPIO Configuration re gisters within the Suspend Well are reset when RSMRST# is

asserted, CF9 reset (06h or 0Eh) event occurs, or SYS_RST# is asserted.

3. GPIO24 is an exception to the other GPIO Signal s in t he S uspend Well and is not

reset by CF9 reset (06h or 0Eh).

2. Corrected EOIFD Bi t Defini tion

Update the EO I F D bit defi nition in Sect ion 20.1 .48 of the Datasheet a s foll ows:

3. Correct GPI_INV - GPIO Signal Invert Register Definition

Secti on 13.10.8 of the Da ta s heet is updated as follows :

GPI_INV—GPIO Signal Invert Register

Offset Address: GPIOBASE +2Ch Attribute: R/W

Default Value: 00000000h Size: 32-bit

Lock a bl e: No Power Well : Cor e for

17, 16, 7:0

Bit Description

EOI Forwa rdi ng Disable (EOIFD) — R/W. When set, EOI messages are not claim ed

on the backbone by this port and will not be forwarded across the PCIe link.

0 = Broadcast EOI messages that are sent on the backbone are claimed by this port

and fowarded across the PCIe link.

1 = Broadcast EOI messages are not claimed on the backbone by this port and will not

be forwa r de d a c ros s the PCIe Link.

Document Chang es

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

24 Document Number: 319974-016

4. Update TBD defaults

Update the TBD defaults in Sectio n 23, Therma l Sensor Regis te r s

Tabl e 23-1

Section 23.1.2

DID —Device Identification

Offset Address: 02 h

–

03h Attribute: RO

Default Value: 3A62h Size: 16 bit

Section 23.1.18

INTPN— Interrupt Pin

Address Offset: 3Dh Attribute: RO

Default Value: 03h Size: 8 bits

5. Upd ate GPIO Note #4 in Section 3.2, Output and I/ O Sig na ls and

States

Mak e the following upd a te to Section 3. 2, Note #4 for Table 3- 2 of the Datasheet

Notes:(Update for Table 3-3)

4. The states of Core and processor signals are evalua ted at the times Du ring

PLTRST# and Immediately after PLTRST#. The states of the LAN and GLAN

signals is are evaluated at the times During LAN_RST# and Immediat el y after

LAN_RST#. Th e states of the Controll er Lin k signals are evaluated at the times

During CL_RST# and Immedi ately after CL_RST#. The states of the Suspend

Bit Description

31:16 0000h - Reserved

15:0

Input Inversion (GP_INV[n]) — R/W. This bit only has effect if the corresponding

GPIO is used a s an input a nd us ed by the GPE log ic , whe re the polar ity matte r s. Whe n

set to ‘1’, then the GPI is inverted as it is sent to the GPE logic that is using it. This bit

has no effect on the val ue that is reported in the GP_LVL register.

These bits are used to allow both active-low and active-high inputs to cause SMI# or

SCI. Note that in the S0 or S1 state, the input sig nal must be active for at least two PCI

clock s to ens ure de te ct ion by th e ICH1 0. In the S3, S4 or S5 states the inp ut si gnal

must be active for at least 2 RTC clocks to ensure detection. The setting of these bi ts

has no effec t if th e cor re s po n di n g GP I O is pr ogrammed a s an output. These bit s

correspond to GPI that are in the resume well, and will be reset to their default values

by RSMRST# or by a wri te to the CF 9h re gi ster.

0 = The corresponding GPI_STS bit is set when the ICH10 detects the state of the input

pin to be high.

1 = The corresponding GPI_STS bit is set when the ICH10 detects the state of the input

pin to be low.

Offset Mnemonic Register Name Default Type

02h-03 h DID Devi ce Ide nti fic atio n 3A62h RO

3Dh INTPN Interrupt Pin 03h RO

Document Changes

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 25

signals are evaluated at the times During RSMRST# and Immediately after

RSMRST#, with an exception to GPIO signals; refer to Section 2.22, General

Purpose I/O Signals, for more details on GPIO state after reset. The states of the

HDA signals are ev aluated at the times During HDA_RST# and Immediately after

HDA_RST#.

6. Make Correction to Table 5-40

Make the following correction to Table 5-40 in Section 5.13.13, Reset Behavior, in the

Datasheet.

Table 5-40. Cause s of Ho st and Global Resets

7. Update bit defini tion for Second_T O_ STS

Update the following bit definition for Second_TO_STS in Section 13.9.5, TCO2_STS -

TCO2 Status Register, in the Datasheet.

8. Add Foot Note s For A ll References to SPI Flash Descriptor s ICH S TR P0

and MCHSTRP0

Add the below note to all ref er ences to SPI Flash desc r iptor MCHS TRP0 in Sections

5.27.2, Enabling Integrated TPM, and 22.2.5.1, FLUMAP1 - Flash Upper MAP 1 (Flash

Descriptor)

Note: MCHSTRP0 is in the SPI flash descriptor and programmed by Original

Equip m ent Manuf a cturers.

Add the below note to all references to SPI Flash descriptor ICHSTRP0 in Sections 2.20

Contr o l ler Li nk Signal s , 3.3 Power Planes fo r In p ut S i gnals, 5.14. 2 . 1 , TCO

Legacy/Co mpatible Mode, 5.14.2.2, A dvanced TC O M ode, and 5.14.2 .2 . 1, Advanced

TC O Intel Manageabi li ty Engine Mode.

Note: ICHSTR P0 is in the S PI flash descriptor and pro grammed by Original Equipment

Manufactures.

9. Remove GPIO58 from Figure 2-1, Intel® ICH10 Inte rface Si gnals Blo ck

Diagram

Upda te the fol lowing block d ia gram in Sec tion 2, Signal Descr iption, in th e Da tasheet.

Trigger

Host Reset

without

Power

Cycle

Host Reset

with Power

Cycle

Global

Reset with

Power C y cle

Power Failure: PWROK signal or VRMPWRGD signal

goes inactive or RSMRST# asserts No Yes Yes (Note 2)

Bit Description

SECOND_TO_STS — R/W C .

0 = Software clear s this bi t by wr iting a 1 to it, or by a RSMR ST#.

1 = ICH10 sets this bit to 1 to indicate that the TIMEOUT bit is set and a second

timeo ut occ urre d. If th is bit is se t and th e NO_RE BOO T confi g bit is 0, t hen the

ICH10 will reboot the system after the second timeout. The reboot is done by

asse rti n g PLTRST#.

Document Chang es

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

26 Document Number: 319974-016

Figure 2-1. Intel

ICH10 Interface Signals Block Diagram

10. Add 1.1v for VccDMI in Table 2-24

Add 1.1v support for VccDMI in Section 2.4 in Table 2-4, Power and Ground Signals, in

the Datas heet.

THRM#

THRMTRIP#

SYS_RESET#

RSMRST#

MCH_SYNC#

SLP_S3#

SLP_S4#

SLP_S5#/GPIO63

†

SLP_M#

S4_STATE#/GPIO26

PWROK

CLPWROK

PWRBTN#

RI#

WAKE#

SUS_STAT#/LPCPD/GPIO61

†

SUSCLK/GPIO62

†

LAN_RST#

VRMPWRGD

PLTRST#

CK_PWRGD

BMBUSY#/GPIO0

STP_PCI#/GPIO15

STP_CPU#/GPIO25

†

DRAMPWROK

†

/GPIO8

DPRSTP#

DPR SLPVR / GPIO 1 6

AD[31:0]

C/BE[3:0]#

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

PAR

PERR#

REQ0#

REQ1#/GPIO50

REQ2#/GPIO52

REQ3#/GPIO54

GNT0#

GNT1#/GPIO51

GNT2#/GPIO53

GNT3#/GPIO55

SERR#

PME#

PCICLK

PCIRST#

PLOCK#

PCI

Interface

LAN_RSTSYNC

GLAN_CLK

GLAN_TXP/PETp6; GLAN_TXN/PETn6

GLAN_RXP/PER p6; GLAN_RXN /PER n6

GLAN_COMPO

GLAN_COMPI

Gigabit LAN

Connect

Interface

Power

Mgnt.

In terrupt

Interface

A20M#

FERR#

IGNNE#

INIT#

INIT3_3V#

INTR

NMI

SMI#

STPCLK#

RCIN#

A20GATE

CPUPWRGD

DPSLP#

Processor

Interface

USB

SERIRQ

PIRQ[D:A]#

PIRQ[H:E]#/GPIO[5:2]

USB[1 1:0 ]P; U SB[11:0 ]N

OC0#/GPIO59; OC1#/GPIO40

OC2#/GPIO41; OC3#/GPIO42

OC4#/GPIO43; OC5#/GPIO29

OC6#/GPIO30; OC7#/GPIO31

OC8#/GPIO44; OC9#/GPIO45

OC10#/GPIO46; OC11#/GPIO47

USBRBIAS

USBRBIAS#

RTCX1

RTCX2

CLK14

CLK48

SATA_CLKP, SATA_CLKN

DMI_CLKP, DMI_CLKN

RTC

Clocks

Misc.

Signals

INTVRMEN

SPKR

SRTCRST #; RT CRST #

TP[5:4]

TP7

TP6

GPIO72

†

/ TP 0

LAN100_SLP

General

Purpose

I/O

GPIO[72,49,34,33,32,28,

27,20,18,16,13,12,0]

PWM[2:0]

TACH0/GPIO17; TACH1/GPIO1

TACH2/GPIO6; TACH3/GPIO7

SST

PECI

INT RUDE R#; S MLIN K[1:0]

LINKALERT#/GPIO60

GPIO24/MEM_LED;

GPIO10/CPU_MISSING/JTAGTMS

†

GPIO14/JTAGTDI

†

GPIO57/TPM_PP/JTAGTCK

†

SPI_CS1#/GPIO58

;

WOL_EN/GPIO9

DMI[3 :0] T X P , DM I[3:0]T X N

DMI[3:0]RXP, DMI[3:0]RXN

DMI_ZCOMP

DMI_IRCOMP

Direct

Media

Interface

LPC

Interface

SMBus

Interface

HDA_RST#

HDA_SYNC

HDA_BIT_CLK

HDA_SDOUT

HDA_SDIN[3:0]

Intel

High

Definition

Audio

Firmware

Hub

System

Mgnt.

FWH[3:0]/LAD[3:0]

FWH4/LFRAME#

LAD[3:0]/FWH[3:0]

LFRAME#/FWH4

LDRQ0#

LDRQ1#/GPIO23

SMBDATA

SMBCLK

GPIO11/SMBALERT#/JTAGTDO

†

GLAN_CLK

LAN_RXD[2:0]

LAN_TXD[2:0]

LAN_RSTSYNC

LAN

Connect

Interface

SATA[5:0]TXP, SATA[5:0] TXN

SATA[5:0]RXP, SATA[5:0]RXN

SATARBIAS

SATARBIAS#

SATALED#

SATACLKREQ#/GPIO35

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA2GP/GPIO36

SATA3GP/GPIO37

SATA4GP

SATA5GP

SCLOCK/GPIO22

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

Serial ATA

Interface

PCI

Express*

Interface

PETp[5:1], PETn[5:1]

PERp[5:1], PERn[5:1]

GLAN_TXP/PETp6; GLAN_TX N/PETn6

GLAN_RXP/PER p6; GLAN_RXN/PERn6

SPI

SPI_CS0#

SPI_CS1#/GPIO58

SPI_MISO

SPI_MOSI

SPI_CLK

JTAG

(Corporate

Only)

CL_CLK0 ; CL_DATA0

CL_VREF0

CL_RST0#

Controller

Link

Fan Speed

Control

GPIO57/TPM_PP/JTAGTCK

†

GPIO10/CPU_MISSING/JTAGTMS

†

GPIO14/JTAGTDI

†

GPIO11/SMBALERT#/JTAGTDO

†

GPIO60/LINKALERT#/JTAGRST#

†

Document Changes

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 27

Tabl e 2- 2 4. Pow er an d Gr ou nd Signals

11. Correct Bit Types for PCI Express* UnCorrectable Error Severity

Update the bit types for as follows in Section 20.1.62, UEV - UnCorrectable Error

Severi ty Regis ter Des cr iption, in the Da t a s heet.

20.1.62 UEV — Uncorrectable Error Severity

(PCI Express—D28:F0/F1/F2/F3/F4/F5)

Address Offset: 14Ch

–

14Fh Attribute: RO (Consumer), RW (Corporate)

Default Value: 00060011h Size: 32 bits

Name Description

VccDMI Power supply for DMI. 1.05V, 1.1v, 1.25V or 1.5V depending on (G)MCH’s DMI

voltage.

Bit Description

31:21 Reserved

20 Unsupported Request Erro r Severity (URE) — RO (Consumer), RW (Corporate).

Error considered non- fatal . (Defaul t)

1 = Error is fatal.

19 ECRC Error Severity (EE) — RO. ECRC is not supported.

18 Malforme d TLP Seve ri ty (MT) — RO (Cons u m e r), RW (C orp orate ).

Error considered non- fatal .

1 = Error is fatal. (Default)

17 Receiver Overflow Severity (RO) — RO (Consume r), R W (Corporate).

Error considered non- fatal .

1 = Error is fatal. (Default)

16 Unexpected Completion Severity (UC) — RO (Consumer), RW (Corporate).

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

15 Completion Abort Severity (CA) — RO (Consumer), RW (Corporate).

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

14 Comple tion Timeout Severity (CT) — RO (Consumer), RW (Corporate).

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

13 Flow Control Protocol Error Severity (FCPE) — RO. Flow Control Protocol Errors not

supported.

12 Poisoned TLP Severity (PT) — RO (Cons um e r), RW (Co rp orate ).

0 = Error considered non-fatal. (Default)

1 = Error is fatal.

11:5 Reserved

4Data Link Protoco l Erro r Severity (DL PE ) — RO (Cons um e r), RW (Co rp orate).

0 = Error considered non-fatal.

1 = Error is fatal. (Default)

3:1 Reserved

Document Chang es

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

28 Document Number: 319974-016

12. Correct PCI Exp res s* DSTS register definition for bit 1 (NFED)

Update the bit defini tion for bit 2( NFED) in Secti on 20.1.27 , DTST- Device Status

Revision 1.1.

Section 20.1.27 DSTS—Device Status Register

(PCI Expr es s—D28:F0/F1/F2/F3/F4/ F5 )

Address Offset: 4Ah–4Bh Attribute: R/WC, RO

Default Value: 0010h Siz e: 16 bits

13. Correct SMBCLK_CTL bit default value

Correct SMBC LK_CTL bit 2 de fau lt value defined in Sectio n 19 .2 .14,

SMBus_PIN_CTL—SMBus Pin Control Register (SMBus—D31:F3), in the Datasheet.

14. Correct Ta bl e 2-24, Strap selectio n for Boot BIOS Desti na tion

Correct Boot BIOS Destination strap selection definition in Table 2-24, Functional Strap

Definitions (Sheet 2 of 3), in the Datasheet.

0 Training Error Severity (TE) — RO. TE is not supported.

Bit Description

1Non-Fatal Error Detected (NFED) — R/WC. Indicates a non-fatal error was detected.

0 = Non-fatal has not occurred.

1 = A non-fatal error occurred.

Bit Description

SMBCLK_CTL — R/W.

1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of

the pin. (Default)

0 = ICH10 drives the SMB CLK pi n low, independent of wha t the othe r SMB lo gic wo uld

otherwise indi cate for the SMB CLK pin.

Document Changes

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 29

Signal Usage When

Sampled Comment

GNT0# Boot BIOS

Destination

Selection 1

Rising Edge of

PWROK

This field determines the destination of accesses to

the BIOS memory range. Signals have weak internal

pull-ups. Also controllable via Boot BIOS Destination

bit (Ch ipse t Config Registe r s: Of fs et 3410 h:bit 11) .

This strap is used in conjun ction with Bo ot BIOS

Destination Selection 1strap.

NOTE: If option 11 LPC is selected, BIOS may still be

placed on LPC, but all platforms with ICH10

(Corporate Only) require SPI flash connected

directly to the ICH's SPI bus with a valid

descriptor in ord e r to boot.

NOTE: Booting to PCI is intended for debut/testing

only. Boot BIOS Dest ination S elect to LPC/PCI

by fun ctional strap or via Boo t BIOS

Destination Bit will not affect SPI accesses

initiat ed by Intel Ma nag em e nt Engi ne or

Integrated GbE LAN.

SPI_CS 1# Boot BIOS

Destination

Selection 0

Rising Edge of

CLPWROK

This field determines the destination of accesses to

the BIOS memory range. Signals have weak internal

pull-ups. Also controllable via Boot BIOS Destination

bit (Ch ipse t Config Registe r s: Of fs et 3410 h:bit 10) .

This strap is used in conjun ction with Bo ot BIOS

Desti n at io n Se le ction 0 strap.

NOTE: If option 11 LPC is selected, BIOS may still be

placed on LPC, but all platforms with ICH10

(Corporate Only) require SPI flash connected

directly to the ICH's SPI bus with a valid

descriptor in ord e r to boot.

NOTE: Booting to PCI is intended for debut/testing

only. Boot BIOS Dest ination S elect to LPC/PCI

by fun ctional strap or via Boo t BIOS

Destination Bit will not affect SPI accesses

initiat ed by Intel Ma nag em e nt Engi ne or

Integrated GbE LAN.

Bit11

(GNT0#) Bit 10

(SPI_CS1#) Boot BIOS

Destination

0X SPI

10 PCI

11 LPC

Bit11

(GNT0#) B i t 10

(SPI_CS1#) Boot BIOS

Destination

0X SPI

10 PCI

11 LPC

Document Chang es

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

30 Document Number: 319974-016

15. Correct Section 5.13.6.5, Sx-G3-Sx, Handling Power Failures,

regarding possible wake events following a power failure

Correct selection 5.13.6.5, Sx-G3-Sx, Handling Power Failures, in the Datasheet

Sectio n 5.13.6.5, Sx-G3-Sx, Handlin g Powe r Failures

Dependin g on when the powe r failure occu rs and how the syst em is designed , differ ent

transitions could occur due to a power failure.

The AFTER_ G3 bi t pr ovides th e a bility to pr og ram wh ether or no t th e s ys tem should

boot once power returns after a power loss event. If the policy is to not boot, the

system remains in an S5 state (unless previously in S4). The following wake events can

wake the system following a power loss by either RSMRST# going low and enabling by

default, the enable bits reside in the RTC well or the wake event is always enabled.

1. PWRBTN#: P WRBTN# is always enabled as a wake event. When RSMRST# is low

(G3 s tate), th e PWRBTN_STS bit is r eset. When the ICH10 exi ts G3 after power

returns (RSMRST# goes high), the PWRBTN# signal is already high (because

-standby goes high befo re R S M R ST# goes high) and the PWRBTN_STS bi t is 0.

2. RI#: RI# do es not ha ve an internal pul l-up. Therefore, if this si gnal is enabled as a

wake event, it is important to keep this signal powered during the power loss

event. If this signal goes low (active), when power returns the RI_S TS bit is set and

the system interprets that as a wake event.

3. RTC Al a rm: The R T C _EN bi t is i n the RTC we ll and is pre ser ve d af ter a p ow er l oss.

Like P WRBTN_STS the RTC_STS bit is cleared when RSMR ST# goes low.

4. PCI Express Wake# S ign al: T he PCIEXPWAK_DIS bit is cleared by RSMRST # going

low enabling PCI Express Ports to wak e the platform after a power loss. The

PCIEXPWAK_STS bit is also cleared when RSMRST# goes low.

5. PME_B0: PME_ B0_EN is in the RTC Well and is preserved after a power loss. The

PME_B0_STS bit is also cleared when RSMRST# goes low.

6. PME: PME_EN: is in the RT C W ell and is preserved after a power loss. The PME_STS

bit is also cleared when RSMRST# goes low.

7. Host SMBUS: SMBUSALER T# or Slave Wake message is always enabled as Wake

Event

8. ME Non-Maskable Wake: Always enabled as Wake Event.

9. WOL Ena ble Ov er ride (Corporate only): is in the RTC Well and is pr eserved after a

power loss. The WOL_OVR_WK_STS bit is cleared by software.

The ICH10 monitors b oth PWROK and RSMRST# to detect for power failures. If PWROK

goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.

16. Correct Section 10.1.45, Bit 0 definition

Correct selection 10 .1.45 CIR5—Chipset Initialization Register 5 in the Datasheet

10.1. 45 CIR5—Chips et Initialization Reg ister 5

Offset Address: 1D40h–1D47h Attribute: R/W

Default Value: 0 000000000000000h Size: 64-bit

Bit Description

63:0 Reserved

Document Changes

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 31

17. Correct Section 13.1.23, Bits 15:2 definition

Correct Section 13.1.23, GEN1_DEC-LPC I/F Generic Decode Range 1 Register, in the

Datasheet.

13.1.23 GEN1_DEC-LPC I/F Generic Decode Ran ge 1 Register

(LPC I/F-D31:F0)

Offset Address: 84h–87h Attribute: R/W

Default Value: 00000000h Size: 32 bit

Power Well: Core

18. Correct A20M# Signal Des cription

Correct A20M# signal description in Table 2-12, Processor Interface Signals, in the

ICH10 D a ta s heet.

19. Update Section 8.2 in the Datasheet

The title of Section 8.2 of the ICH10 Data s heet is c ha ng ed as follows .

8.2 Absolute Maximum and Minimum Ra tings

The follow ing paragraphs are added to Section 8.2:

Table 8-1 specifies absolute maximum and minimum ratings. At conditions outside

functional operation condition limits, but within absolu te maximum and minimum

ratings, neither functionality nor long-term reliability can be expected. If a device is

returned to conditions within functional operation limits after having been subjected to

conditions outside these limits (but within the absolute maximum and minimum

rat ings) the device may be f un c tional, but with its lifetime degraded depending on

exposure to conditions exceeding the functional operation condition limits.

Bit Description

31:24 Reserved

23:18

Generic I/O D ecode Range Address[7:2] Mask — R/W. A 1 in any bit position

indicates that any value in the corresponding address bit in a rec eived cycle will be

treated as a match . T he corr e sponding bit in the Addr e ss fie ld, be low, is ignored. The

mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up

to 256 bytes in size.

17:16 Reserved

15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W.

NOTE: The ICH Does not provide decode down to the word or byte level.

1Reserved

0Generic Decode Range 1 Enable (GEN1_EN) — R/W.

0 = Disable.

1 = Enable the GEN1 I/ O range to be forwarded to the LPC I/F.

Name Type Description

A20M# OMask A20: A20M# will go active inactive based on either setting the

appropriate bi t in the Port 92h register, or based on the A20GATE input

being active.

Document Chang es

Intel

I/O Controller Hub 10 (ICH10) Family

Specification Update May 2012

32 Document Number: 319974-016

At conditions exceeding absolute maximum and minimum r atings, neither functionality

nor long-term reliability can be ex pec ted. Moreover, if a device is subjected to these

conditions for an y length of ti m e, it will eith er not functio n or its reliabi lity will be

severely degraded when returned to conditions within the functional operating

condition limits.

Although the ICH10 c ontains protective ci r c uitry to resis t damage from Electro-Static

Discharge (ESD), precautions sho uld always be taken t o avoid high static voltages or

elec tric fields .

20. Correct OUTSTRMPAY Registe r inf ormation

Section 18.2.10 of the Datasheet is updated as follows:

OUTSTRMPAY—Output Stream Payload Capability

(Intel

High Definition Audio Controller—D27:F0)

Memory Addre ss: HDBAR + 18h Attribute: RO

Default Value: 0030h Size: 16 bits

Bit Description

15:8

15:14

Reserved

Output FIFO Padding Type (OPA DT YPE) — RO. This field indicates how the

controller pads the samples in the controller's buffer (FIFO). Controllers may not pad

at all or may pad to byte or memory container sizes.

0h = Controller pads all samples to bytes

1h = Reserved

2h = Controller pads to memo ry containe r size

3h = Contr oller does not pa d and uses samples directly

7:0

13:0

Output Stream Payload Capability (OUTSTRMPAY) — RO. This field indicates

maxim um number of word s per frame fo r any single ou tput stream. This

measurement is in 16 bit word quantities per 48 kHz frame. The maximum supported

is 48 Words (96B); therefore, a value of 30h is reported in this register.

The value does not specify the number of words actually transmitted in the frame,

but is the size of the data in the controller buffer (FIFO) after the samples are padded

as specif ie d by OPADTYPE. Thus, to co m put e the sup po rte d str eam s, eac h sam p le is

padded according to OPADTYPE and then multiplied by the number of channels and

sampl es pe r fram e . If this com pute d value is larg e r than OU TS TRMPA Y , the n tha t

stream is not supported. The value specified is not affected by striping.

Software must ensure that a format that wou ld cause more Words per frame than

indicated is not programmed into the Output Stream Descriptor Register.

00h = 0 words

01h = 1 word paylo ad

…

FFh = 255h word payload

The value may be larger than the OUTPAY register valu e in some cases.

Document Changes

Intel

I/O Controller Hub 10 (ICH10) Family

May 2012 Specification Update

Document Number: 319974-016 33

21. Correct INSTRMPA Y Register information

Section 18.2.11 of the Datasheet is updated as follows:

INSTRMPAY—Input Stream Payload Capability

(Intel

High Definition Audio Controller—D27:F0)

Memory Address: HDBAR + 1Ah Attribute: RO

Default Value: 0018h Size: 16 bits

Bit Description

15:8

15:14

Reserved

Input FIFO Pa dding Type (IPADTYPE) — RO. This field indicates how the

controller pads the samples in the controller's buffer (FIFO). Controllers may not pad

at all or ma y pad to byte or me m ory conta ine r siz e s.

0h = Controller pa ds all sample s to by te s

1h = Reserve d

2h = Controll er pads to mem ory co ntai ner size

3h = Controller does not pad and uses samples directly

7:0

13:0

Input Stream Payload Capability (INSTRMPAY) — RO. Th is field indic a te s the

maximu m num be r of Wo rd s per fram e for any s ing le inpu t s tre am . T his

measure ment is in 16-bit Word quan tities per 48-kHz fr ame. The maximum

supported is 24 Words (48B); therefore, a value of 18h is reported in this register.

The valu e does not specify the number of words actually transmitted in the frame,

but is the size of the data as it will be placed into the controller's buffer (FIFO). Thus,

samples will be padded according to IPADTYPE before being stored into controller

buffer. To compute the suppo rted streams, each sample is padded ac cording to

IPADTYPE a nd then m ulti plied by the number of c hanne ls an d sa m p le s pe r fr a m e. If

this computed value is larger than INSTRMPAY, then that stream is not supported. As

the inbound stream tag is not stored with the samples it is not included in the word

count.

The value may be larger than INPAY register value in some cases, although values

less than IN PAY m ay a ls o be inva li d du e to ov er h e ad.

Software must ens ure that a format that would cause more W ords per fr ame than indicated is not

programm ed int o th e In put Str eam De sc r i pt or Regist e r.

00h = 0 words

01h = 1 word payload

…

FFh = 255h word payload