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Rev.2.0, Sep.18.2003, page 1 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Switching Regulator for Chopper Type DC/DC Converter
REJ03F0055-0200Z
(Previous: ADE-204-020A)
Rev.2.0
Sep.18.2003
Description
The HA16114P/FP/FPJ and HA16120FP/FPJ are single-channel PWM switching regulator controller ICs
suitable for chopper-type DC/DC converters. Integrated totem-pole output circuits enable these ICs to
drive the gate of a power MOSFET directly. The output logic of the HA16120 is designed to control a
DC/DC step-up (boost) converter using an N-channel power MOS FET. The output logic of the HA16114
is designed to control a DC/DC step-down (buck) converter or inverting converter using a P-channel power
MOS FET.
These ICs can operate synchronously with external pulse, a feature that makes them ideal for power
supplies that use a primary-control AC/DC converter to convert commercial AC power to DC, then use one
or more DC/DC converters on the secondary side to obtain multiple DC outputs. Synchronization is with
the falling edge of the ‘sync’ pulse, which can be the secondary output pulse from a flyback transformer.
Synchronization eliminates the beat interference that can arise from different operating frequencies of the
AC/DC and DC/DC converters, and reduces harmonic noise. Synchronization with an AC/DC converter
using a forward transformer is also possible, by inverting the ‘sync’ pulse.
Overcurrent protection features include a pulse-by-pulse current limiter that can reduce the width of
individual PWM pulses, and an intermittent operating mode controlled by an on-off timer. Unlike the
conventional latched shutdown function, the intermittent operating function turns the IC on and off at
controlled intervals when pulse-by-pulse current limiting continues for a programmable time. This results
in sharp vertical settling characteristics. Output recovers automatically when the overcurrent condition
subsides.
Using these ICs, a compact, highly efficient DC/DC converter can be designed easily, with a reduced
number of external components.
Functions
• 2.5 V voltage reference
• Sawtooth oscillator (Triangle wave)
• Overcurrent detection
• External synchronous input
• Totem-pole output
• Undervoltage lockout (UVL)
• Error amplifier
• Vref overvoltage protection (OVP)
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 2 of 37
Features
• Wide supply voltage range: 3.9 V to 40 V*
• Maximum operating frequency: 600 kHz
• Able to drive a power MOS FET (±1 A maximum peak current) by the built-in totem-pole gate pre-
driver circuit
• Can operate in synchronization with an external pulse signal, or with another controller IC
• Pulse-by-pulse overcurrent limiting (OCL)
• Intermittent operation under continuous overcurrent
• Low quiescent current drain when shut off by grounding the ON/OFF pin
HA16114: IOFF = 10 µA (max)
HA16120: IOFF = 150 µA (max)
• Externally trimmable reference voltage (Vref): ±0.2 V
• Externally adjustable undervoltage lockout points (with respect to VIN)
• Stable oscillator frequency
• Soft start and quick shut function
Note: The reference voltage 2.5 V is under the condition of VIN ≥ 4.5 V.
Ordering Information
Hitachi Control ICs for Chopper-Type DC/DC Converters
Control Functions
Channels
Product
Number
Channel
No. Step-Up Step-Down Inverting Output Circuits
Overcurrent
Protection
Ch 1 ❍❍ ❍Dual HA17451
Ch 2 ❍❍ ❍
Open collector SCP with timer (latch)
HA16114 —— ❍❍Single
HA16120 —❍——
Ch 1 — ❍❍HA16116
Ch 2 — ❍—
Ch 1 — ❍❍
Dual
HA16121
Ch 2 ❍——
Totem pole
power MOS FET
driver
Pulse-by-pulse
current limiter and
intermittent operation
by on/off timer
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 3 of 37
Pin Arrangement
(Top view)
116
Note: 1. Pin 1 (GND) and Pin 8 (P.GND) must be connected each other with external wire.
215
314
413
512
611
710
8
Vref
ADJ
DB
ON/
OFF
TM
CL(−)
V
IN
OUT9
GND*
1
SYNC
R
T
C
T
IN(−)
E/O
IN(+)
P.GND*
1
Pin Description
Pin No. Symbol Function
1 GND Signal ground
2SYNC External sync signal input (synchronized with falling edge)
3R
TOscillator timing resistor connection (bias current control)
4C
TOscillator timing capacitor connection (sawtooth voltage output)
5 IN(–) Inverting input to error amplifier
6 E/O Error amplifier output
7 IN(+) Non-inverting input to error amplifier
8 P.GND Power ground
9 OUT Output (pulse output to gate of power MOS FET)
10 VIN Power supply input
11 CL(–) Inverting input to current limiter
12 TM Timer setting for intermittent shutdown when overcurrent is detected
(sinks timer transistor current)
13 ON/OFF IC on/off control (off below approximately 0.7 V)
14 DB Dead-band duty cycle control input
15 ADJ Reference voltage (Vref) adjustment input
16 Vref 2.5 V reference voltage output
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 4 of 37
Block Diagram
UVL
H
LV
L
V
H
16 15 14 13 12 11 10 9
12345678
Vref ADJ DB ON/
OFF
TM CL(−)V
IN
OUT
SYNC
R C IN(−) E/O IN(+) P.GND
TT
1.1 V
R
T
+
−
+
NAND (HA16114)
−+
0.2 V
from
UVL 1k
1k
0.3V
ON/
OFF
ADJ V
IN
Vref
PWM COMP
from
UVL
V
IN
1.6 V
1.0 V
from
UVL
OUT
Latch
S
R
Q
OVP
+
−
*1
2.5V
bandgap
reference
voltage
generator
UVL
output
Triangle waveform
generator
Latch reset pulses
Bias
current
EA
CL
0.3 V
GND
Note: 1. The HA16120 has an AND gate.
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 5 of 37
Timing Waveforms
T = 1
f
OSC
1.6 V typ
1.0 V
typ
V
0 V
IN
V
0 V
IN
Off Off Off
Off
On On On OnOn
Off Off Off OffOff
On On On OnOn
Dead-band
voltage (at DB)
Sawtooth wave
(at C
T
)
Off
Error amplifier
output (at E/O)
HA16114 PWM
pulse output
(drives gate of
P-channel
power MOS FET)
HA16120 PWM
pulse output
(drives gate of
N-channel
power MOS FET)
Time t
Note: On duty = t
ON
T
Generation of PWM pulse output from sawtooth wave (during steady-state operation)
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 6 of 37
Guide to the Functional Description
The description covers the topics indicated below.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND*
1
SYNC
R
T
C
T
IN(−)
E/O
IN(+)
P.GND*
1
Vref
ADJ
DB
ON/
OFF
TM
CL(−)
V
IN
OUT
1.
2.
3.
4.
5.
6.
7.
8.
Oscillator
frequency
(f ) control and
synchronization
OSC
DC/DC output
voltage setting
and error
amplifier usage
Dead-band and
soft-start settings
Output stage and
power MOS FET
driving method
Vref adjustment,
undervoltage
lockout, and
overcurrent
protection
Intermittent
mode timing
during
overcurrent
Setting of
current limit
(Top view)
Note: 1.
ON/
OFF
pin
usage
P.GND is a high-current (±1 A maximum peak) ground pin connected to the totem-pole output circuit.
GND is a low-current ground pin connected to the Vref voltage reference. Both pins must be grounded.
1. Sawtooth Oscillator (Triangle Wave)
1.1 Operation and Frequency Control
The sawtooth wave is a voltage waveform from which the PWM pulses are created (See figure 1). The
sawtooth oscillator operates as follows. A constant current IO determined by an external timing resistor RT
is fed continuously to an external timing capacitor CT. When the CT pin voltage exceeds a comparator
threshold voltage VTH, the comparator output opens a switching transistor, allowing a 3IO discharge current
to flow from CT. When the CT pin voltage drops below a threshold voltage VTL, the comparator output
closes the switching transistor, stopping the 3IO discharge. Repetition of these operations generates a
sawtooth wave.
The value of IO is 1.1 V/RT Ω. The IO current mirror has a limited current capacity, so RT should be at least
5 kΩ (IO ≤ 220 µA).
Internal resistances RA, RB, and RC set the peak and valley voltages VTH and VTL of the sawtooth waveform at
approximately 1.6 V and 1.0 V.
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 7 of 37
The oscillator frequency fOSC can be calculated as follows.
1
t
1
+ t
2
+ t
3
f
OSC
=
t
1
= C
T
× (V
H
− V
L
)
1.1 V/R
T
t2 = C
T
× (V
H
− V
L
)
3 × 1.1 V/R
T
V
H
− V
L
= 0.6 V
f
OSC
≈1
0.73 × C
T
× R
T
+ 0.8 (µs) (Hz)
t3 ≈ 0.8 µs (comparator delay time)
Here,
Since
At high frequencies the comparator delay causes the sawtooth wave to overshoot the 1.6 V threshold and
undershoot the 1.0 V threshold, and changes the dead-band thresholds accordingly. Select constants by
testing under implementation conditions.
R
T
1 : 4
C
T
Vref
V
H
= 1.6 V typ
V
L
= 1.0 V typ
t
1
t
2
t
1
: t
2
= 3 : 1
External circuit
3.2 V
(Internal voltage)
2.5 V
SYNC
R
B
R
C
R
A
1.1 V
Current
mirror C
T
charging
I
O
Discharg
-ing 3I
O
Oscillator
comparator
Sync
circuit
I
O
Figure 1.1 Equivalent Circuit of Oscillator
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 8 of 37
1.2 External Synchronization
These ICs have a sync input pin so that they can be synchronized to a primary-control AC/DC converter.
Pulses from the secondary winding of the switching transformer should be dropped through a resistor
voltage divider to the sync input pin. Synchronization takes place at the falling edge, which is optimal for
multiple-output power supplies that synchronize with a flyback AC/DC converter.
The sync input pin (SYNC) is connected internally through a synchronizing circuit to the sawtooth
oscillator to synchronize the sawtooth waveform (see figure 1.2).
• Synchronization is with the falling edge of the external sync signal.
• The frequency of the external sync signal must be in the range fOSC < fSYNC < fOSC × 2.
• The duty cycle of the external sync signal must be in the range 5% < t1/t2 < 50% (t1 = 300 ns Min).
• With external synchronization, VTH' can be calculated as follows.
f
OSC
f
SYNC
V
TH
' = (V
TH
− V
TL
) ×+ V
TL
Note: When not using external synchronization, connect the SYNC pin to the Vref pin.
Sawtooth wave
(fOSC)
SYNC
pin
(f
SYNC
)
Synchronized
at falling edge
VTH (1.6 V typ)
VTL
(1.0 V typ)
VTH'
Vref
1 V
t1
t2
Figure 1.2 External Synchronization
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 9 of 37
2. DC/DC Output Voltage Setting and Error Amplifier Usage
2.1 DC/DC Output Voltage Setting
1. Positive Output Voltage (VO > Vref)
V
IN
IN(−)
IN(+)
EA
GND
Vref
C
L
OUT
V
O
+
−
R
2
R
1
V
IN
IN(−)
IN(+)
EA
GND
Vref
C
L
OUT
V
O
R
2
R
1
+
−
+
−
V
O
= Vref ×R
1
+ R
2
R
2
HA16114 with step-down topology HA16120 with step-down (boost) topology
+
−
Figure 2.1 Output Voltage Setting (1)
2. Negative Output Voltage (VO < 0 V)
VIN
IN(−)
IN(+)
EA
CL
OUT
+
−
R2R1
R3
Vref
R4
+
−
VO = −Vref ×R1 + R2
R2
R3
R3 + R4
×− 1
HA16114 with inverting topology
Figure 2.2 Output Voltage Setting (2)
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 10 of 37
2.2 Error Amplifier Usage
Figure 2.3 shows an equivalent circuit of the error amplifier. The error amplifier in these ICs is a simple
NPN-transistor differential amplifier with a constant-current-driven output circuit.
The amplifier combines a wide bandwidth (fT = 4 MHz) with a low open-loop gain (50 dB Typ), allowing
stable feedback to be applied when the power supply is designed. Phase compensation is also easy.
IN(−)
IN(+)
E/O
40 µA80 µA
IC internal V
IN
To internal PWM
comparator
Figure 2.3 Error Amplifier Equivalent Circuit
3. Dead-Band Duty Cycle and Soft-Start Settings
3.1 Dead-Band Duty Cycle Setting
The dead-band duty cycle (the maximum duty cycle of the PWM pulse output) can be programmed by the
voltage VDB at the DB pin. A convenient way to obtain VDB is to divide the IC’s Vref output by two external
resistors. The dead-band duty cycle (DB) and VDB can be calculated as follows.
V
DB
= Vref ×R
2
R
1
+ R
2
DB = ⋅ ⋅ ⋅ ⋅ This applies when V
DB
> V
TL
.
If V
DB
< V
TL
, there is no PWM output.
V
TH
− V
DB
V
TH
− V
TL
× 100 (%)
Note: VDB is the voltage at the DB pin.
VTH: 1.6 V (Typ)
VTL: 1.0 V (Typ)
Vref is typically 2.5 V. Select R1 and R2 so that 1.0 V ≤ VDB ≤ 1.6 V.
−
+
+
Sawtooth
wave Sawtooth wave Voltage at DB pin
V
TH
V
DB
V
TL
To Vref
R
1
R
2
V
DB
DB E/O
PWM
COMP
from
UVL Dead band
V
TH
and V
TL
vary depending on the oscillator.
Select constants by testing under implementation
conditions.
Note:
Figure 3.1 Dead-Band Duty Cycle Setting
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 11 of 37
3.2 Soft-Start Setting
Soft-start avoids overshoot at power-up by widening the PWM output pulses gradually, so that the
converted DC output rises slowly. Soft-start is programmed by connecting a capacitor between the DB pin
and ground. The soft-start time is determined by the time constant of this capacitor and the resistors that set
the voltage at the DB pin.
VDB = Vref ×
VX
VDB
R2
R1 + R2
R = R1 × R2
R1 + R2
tsoft = −C1 × R × ln (1 −)
Note: VX is the voltage at the DB pin after time t (VX < VDB).
−
+
+
To Vref
R
1
R
2
V
X
DB
E/O
PWM
COMP
from
UVL
V
TH
V
TL
1.6 V
1.0 V
t
C
1
Soft-start time
t
soft
Undervoltage
lockout released
V
DB
V
X
UVL sink
transistor
Sawtooth
wave
Sawtooth wave
Figure 3.2 Soft-Start Setting
3.3 Quick Shutdown
The quick shutdown function resets the voltages at all pins when the IC is turned off, to assure that PWM
pulse output stops quickly. Since the UVL pull-down resistor in the IC remains on even when the IC is
turned off, the sawtooth wave output, error amplifier output, and DB pin are all reset to low voltage.
This feature helps in particular to discharge capacitor C1 in figure 3.2, which has a comparatively large
capacitance. In intermittent mode (explained on a separate page), this feature enables the IC to soft-start in
each on-off cycle.
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 12 of 37
4. PWM Output Circuit and Power MOSFET Driving Method
These ICs have built-in totem-pole push-pull drive circuits that can drive a power MOS FET as shown in
figure 4.1. The power MOS FET can be driven directly through a gate protection resistor.
If VIN exceeds the gate breakdown voltage of the power MOS FET additional protective measures should be
taken, e.g. by adding Zener diodes as shown in figure 4.2.
To drive a bipolar power transistor, the base should be protected by voltage and current dividing resistors as
shown in figure 4.3.
P.GND
To C
L
OUT R
G
V
IN
Bias
circuit V
O
Gate protection
resistor
Totem-pole output circuit
Example:
P-channel power MOSFET
Figure 4.1 Connection of Output Stage to Power MOS FET
OUT
GND
VIN
RG
DZ
VO
Example: N-channel power MOSFET
Figure 4.2 Gate Protection by Zener Diodes
OUT
GND
VIN
VO
Base discharging resistor
Base current
limiting resistor
Example: NPN power transistor
Figure 4.3 Driving a Bipolar Power Transistor
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 13 of 37
5. Voltage Reference (Vref = 2.5 V)
5.1 Voltage Reference
A bandgap reference built into the IC (see figure 5.1) outputs 2.5 V ± 50 mV. The sawtooth oscillator,
PWM comparator, latch, and other internal circuits are powered by this 2.5 V and an internally-generated
voltage of approximately 3.2 V.
The voltage reference section shut downs when the IC is turned off at the ON/OFF pin as described later,
saving current when the IC is not used and when it operates in intermittent mode during overcurrent.
ON/
OFF
+
−
1.25 V
1.25 V 25 kΩ
25 kΩ
VIN
Vref
2.5 V
3.2 V
ADJ
Sub bandgap circuit
Main bandgap circuit
Figure 5.1 Vref Reference Circuit
5.2 Trimming the Reference Voltage (Vref and ADJ pins)
Figure 5.2 shows a simplified circuit equivalent to figure 5.1. The ADJ pin in this circuit is provided for
trimming the reference voltage (Vref). The output at the ADJ pin is a voltage VADJ of 1.25 V (Typ)
generated by the bandgap circuit. Vref is determined by VADJ and the ratio of internal resistors R1 and R2 as
follows:
Vref = VADJ ×R1 + R2
R2
The design values of R1 and R2 are 25 kΩ with a tolerance of ±25%.
If trimming is not performed, the ADJ pin open can be left open.
−
+
V
IN
Vref
ADJ
R
1
R
2
25 kΩ
(typ)
25 kΩ
(typ) V
BG
(bandgap voltage)
1.25 V (typ)
Figure 5.2 Simplified Diagram of Voltage Reference Circuit
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 14 of 37
The relation between Vref and the ADJ pin enables Vref to be trimmed by inserting one external resistor
(R3) between the Vref and ADJ pins and another (R4) between the ADJ pin and ground, to change the
resistance ratio. Vref is then determined by the combined resistance ratio of the internal R1 and R2 and
external R3 and R4.
Vref = VADJ ×RA + RB
RB
Where, RA: parallel resistance of R1 and R3
RB: parallel resistance of R2 and R4
Although Vref can be trimmed by R3 or R4 alone, to decrease the temperature dependence of Vref it is
better to use two resistors having identical temperature coefficients. Vref can be trimmed in the range of
2.5 V ± 0.2 V. Outside this range, the bandgap circuit will not operate and the IC may shut down.
Vref
ADJ R
1
R
2
Internal
resistors
R
3
R
4
External
resistors
R
A
= R
1
R
3
R
1
+ R
3
R
B
= R
2
R
4
R
2
+ R
4
Figure 5.3 Trimming of Reference Voltage
5.3 Vref Undervoltage Lockout and Overvoltage Protection
The undervoltage lockout (UVL) function turns off PWM pulse output when the input voltage (VIN) is low.
In these ICs, this is done by monitoring the Vref voltage, which normally stays constant at approximately
2.5 V. The UVL circuit operates with hysteresis: it shuts PWM output off when Vref falls below 1.7 V,
and turns PWM output back on when Vref rises above 2.0 V. Undervoltage lockout also provides
protection in the event that Vref is shorted to ground.
The overvoltage protection circuit shuts PWM output off when Vref goes above 6.8 V. This provides
protection in case the Vref pin is shorted to VIN or another high-voltage source.
PWM
output
off
PWM output on
PWM output off
1.7 2.0 2.5 5.0 6.8 Vref
PWM
output
(V)
10
Figure 5.4 Vref Undervoltage Lockout and Overvoltage Protection
UVL Voltage Vref (V typ) VIN (V typ) Description
VH2.0 V 3.6 V VIN increasing: UVL releases; PWM output starts
VL1.7 V 3.3 V VIN decreasing: undervoltage lockout; PWM output stops
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 15 of 37
6. Usage of ON/OFF
OFFOFF
OFF Pin
This pin is used for the following purposes:
• To shut down the IC while its input power remains on (power management)
• To externally alter the UVL release voltage
• With the timer (TM) pin, to operate in intermittent mode during overcurrent (see next section)
6.1 Shutdown by ON/OFF
OFFOFF
OFF Pin Control
The IC can be shut down safely by bringing the voltage at the ON/OFF pin below about 0.7 V (the internal
VBE value). This feature can be used in power supply systems to save power. When shut down, the
HA16114 draws a maximum current (IOFF) of 10 µA, while the HA16120 draws a maximum 150 µA. The
ON/OFF pin sinks 290 µA (Typ) at 5 V, so it can be driven by TTL and other logic ICs. If intermittent
mode will also be employed, use a logic IC with an open-collector or open-drain output.
HA16114,
HA16120
GND
VIN
IIN
TM
ON/
OFF
VIN
Vref
output
To other circuitry
Vref
reference
To latch
RB
RA
CON/
OFF
+
−
Switch 10 kΩ
3VBE
Q1
Q3
Off On
External logic IC
On/off hysteresis circuit
Q2
Figure 6.1 Shutdown by ON/OFF
OFFOFF
OFF Pin Control
6.2 Adjustment of UVL Voltages (when not using intermittent mode)
These ICs permit external adjustment of the undervoltage lockout voltages. The adjustment is made by
changing the undervoltage lockout thresholds VTH and VTL relative to VIN, using the relationships shown in
the accompanying diagrams.
When the IC is powered up, transistor Q3 is off, so VON is 2VBE, or about 1.4 V. Connection of resistors RC
and RD in the diagram makes undervoltage lockout release at:
V
IN
= 1.4 V ×R
C
+ R
D
R
D
This VIN is the supply voltage at which undervoltage lockout is released. At the release point Vref is still
below 2.5 V. To obtain Vref = 2.5 V, VIN must be at least about 4.3 V.
Since VON/OFF operates in relation to the base-emitter voltage of internal transistors, VON has a temperature
coefficient of approximately –4 mV/°C. Keep this in mind when designing the power supply unit.
When undervoltage lockout and intermittent mode are both used, the intermittent-mode time constant is
shortened, so the constants of external components may have to be altered.
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 16 of 37
R
C
R
D
TM
(open)
ON/
OFF
GND
10 kΩ
V
IN
V
IN
Q
1
Q
2
Q
3
Vref output
Vref
generation
circuit
To other circuitry
To latch
Vref
3
2
1
0012345
V
ON
1.4 V
V
ON/
OFF
2.5 V
V
IN
4.5 V≥
On/off hysteresis circuit
V
OFF
0.7 V
3V
BE
I
IN
Figure 6.2 Adjustment of UVL Voltages
7. Timing of Intermittent Mode during Overcurrent
7.1 Principle of Operation
These ICs provide pulse-by-pulse overcurrent protection by sensing the current during each pulse and
shutting off the pulse if overcurrent is detected. In addition, the TM and ON/OFF pins can be used to
operate the IC in intermittent mode if the overcurrent state continues. A power supply with sharp settling
characteristics can be designed in this way.
Intermittent mode operates by making use of the hysteresis of the ON/OFF pin threshold voltages VON and
VOFF (VON – VOFF = VBE). The timing can be programmed as explained below.
When not using intermittent mode, leave the TM pin open, and pull the ON/OFF pin up to VON or higher.
The VBE is base emitter voltage of internal transistors.
390 kΩ
2.2 kΩ
2.2 µF+
−
RA
RB
CON/
OFF
ON/OFF
TM
Latch
QR
S
Vref
reference
VIN Current
limiter
CL
Figure 7.1 Connection Diagram (example)
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 17 of 37
7.2 Intermittent Mode Timing Diagram (VON/OFF
OFFOFF
OFF only)
V
BE
2V
BE
3V
BE*1
V
ON/
OFF
b
Off
On On
c
0 V
2T
ON
T
OFF
T
ON
t
a
a.
b.
c.
Note: 1.
Continuous overcurrent is detected
Intermittent operation starts (IC is off)
Voltage if overcurrent ends (thick dotted line)
V
BE
is the base-emitter voltage of internal transistors, and is approximately 0.7 V.
(See the figure 6.1.)
IC is on
c
IC is off
For details, see the overall waveform timing diagram.
Figure 7.2 Intermittent Mode Timing Diagram (VON/OFF
OFFOFF
OFF only)
7.3 Calculation of Intermittent Mode Timing
Intermittent mode timing is calculated as follows.
(1) TON (time until the IC shuts off when continuous overcurrent occurs)
2VBE
VBE ×1
1 − On duty*
TON = CON/
OFF
× RB × ln
= CON/
OFF
× RB × ln2 ×
≈ 0.69 × CON/
OFF
× RB ×
1
1 − On duty*
1
1 − On duty*
(2) TOFF (time from when the IC shuts off until it next turns on)
V
IN
− V
BE
V
IN
− 2V
BE
T
OFF
= C
ON/
OFF
× (R
A
+ R
B
) × ln
Where V
BE
≈ 0.7 V
The greater the overload, the sooner the pulse-by-pulse current limiter operates, the smaller tON becomes,
and from the first equation (1) above, the smaller TON becomes. From the second equation (2), TOFF depends
on VIN. Note that with the connections shown in the diagram, when VIN is switched on the IC does not turn
on until TOFF has elapsed.
Sawtooth wave
Point at which the current
limiter operates
PWM output
(In case of HA16114)
T
t
ON
Dead-band voltage
Note: On duty is the percent of time the IC output is on during one PWM cycle
when the pulse-by-pulse current limiter is operating.
On duty = × 100 (%)
t
ON
T
Where T = t/f
OSC
Figure 7.3
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 18 of 37
7.4 Examples of Intermittent Mode Timing (calculated values)
T
ON
= T
1
× C
ON/
OFF
× R
B
T
1
= 0.69 ×1
1 − On duty
Here, coefficient
Example: If C
ON/
OFF
= 2.2 µF,
R
B
= 2.2 kΩ, and the on duty
of the current limiter is 75%,
then T
ON
= 13 ms.
from section 7.3 (1) previously.
(1) T
ON
0 20406080100
0
2
4
6
8
T
1
(PWM) On duty (%)
Figure 7.4 Examples of Intermittent Mode Timing (1)
If C
ON/
OFF
= 2.2 µF, R
B
= 2.2 kΩ,
R
A
= 390 kΩ, V
IN
= 12 V,
(2) T
OFF
T
OFF
= T
2
× C
ON/
OFF
× (R
A
+ R
B
)
T
2
= ln V
IN
− V
BE
V
IN
− 2V
BE
Here, coefficient
from section 7.3 (2) previously.
then T
OFF
= 55 ms.
Example:
02040
0
0.05
0.1
T
2
V
IN
(V)
10 30
Figure 7.5 Examples of Intermittent Mode Timing (2)
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 19 of 37
VIN
CF
RF
CL
IC
RCS
OUT VOUT
F. B .
VTH (CL)
VIN − 0.2 V
VIN
Sawtooth wave VCT
Dead band VDB
Error output VE/O
PWM pulse output
(In case of HA16120)
Power MOS FET
drain current (ID)
(dotted line shows
inductor current)
Current limiter
pin (CL)
Inductor
L
Example of step-up circuit
ID
Determined by L and VIN
Determined by RCS and RF
Figure 7.6
8. Setting the Overcurrent Detection Threshold
The voltage drop VTH at which overcurrent is detected in these ICs is typically 0.2 V. The bias current is
typically 200 µA. The power MOS FET peak current value before the current limiter goes into operation is
given as follows.
I
D
= V
TH
− (R
F
+ R
CS
) × I
BCL
R
CS
Where, VTH = VIN – VCL = 0.2 V, VCL is a voltage refered on GND.
Note that RF and CF form a low-pass filter with a cutoff frequency determined by their RC time constant.
This filter prevents incorrect operation due to current spikes when the power MOS FET is switched on or
off.
R
CS
V
IN
R
F
C
F
I
BCL
G
S
DV
O
1 k
200 µA
+−
Detector
output
(internal)
OUT
CL
V
IN
IN(−)
To other
circuitry
1800 pF
+
−
240 Ω
0.05 Ω
Note: This circuit is an example for step-down use.
Figure 8.1 Example for Step-Down Use
With the values shown in the diagram, the peak current is:
ID = 0.2 V − (240 Ω + 0.05 Ω) × 200 µA
0.05 Ω= 3.04 A
The filter cutoff frequency is calculated as follows:
f
C
==
1
2π C
F
R
F
1
6.28 × 1800 pF × 240 Ω= 370 kHz
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 20 of 37
Absolute Maximum Ratings
(Ta = 25°C)
Rating
Item Symbol HA16114P/FP,
HA16120FP
HA16114PJ/FPJ,
HA16120FPJ Unit
Supply voltage VIN 40 40 V
Output current (DC) IO±0.1 ±0.1 A
Output current (peak) IO peak ±1.0 ±1.0 A
Current limiter input voltage VCL VIN VIN V
Error amplifier input voltage VIEA VIN VIN V
E/O input voltage VIE/O Vref Vref V
RT source current IRT 500 500 µA
TM sink current ITM 33mA
SYNC voltage VSYNC Vref Vref V
SYNC current ISYNC ±250 ±250 µA
Power dissipation PT680*1, *2680*1, *2mW
Operating temperature Topr –40 to +85 –40 to +85 °C
Junction temperature TjMax 125 125 °C
Storage temperature Tstg –55 to +125 –55 to +125 °C
Notes: 1. This value is for an SOP package (FP) and is based on actual measurements on a 40 × 40 × 1.6
mm glass epoxy circuit board. With a 10% wiring density, this value is permissible up to Ta =
45°C and should be derated by 8.3 mW/°C at higher temperatures. With a 30% wiring density,
this value is permissible up to Ta = 64°C and should be derated by 11.1 mW/°C at higher
temperatures.
2. For the DIP package. (P)
This value applies up to Ta = 45°C; at temperatures above this, 8.3 mW/°C derating should be
applied.
800
600
400
200
0
680 mW
447 mW
348 mW
45°C 85°C 125°C64°C
Permissible dissipation P
T
(mW)
20 40 60 80 100 120 1400−40 −20
Operating ambient temperature Ta (°C)
10% wiring density
30% wiring density
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 21 of 37
Electrical Characteristics
(Ta = 25°C, VIN = 12 V, fOSC = 100 kHz)
Item Symbol Min Typ Max Unit Test Conditions Notes
Output voltage Vref 2.45 2.50 2.55 V IO = 1 mA
Line regulation Line — 2 60 mV 4.5 V ≤ VIN ≤ 40V 1
Load regulation Load — 30 60 mV 0 ≤ IO ≤ 10 mA
Short-circuit output
current
IOS 10 24 — mA Vref = 0 V
Vref overvoltage
protection threshold
Vrovp 6.2 6.8 7.4 V
Temperature stability
of output voltage
∆Vref/∆Ta — 100 — ppm/°C
Voltage
reference
section
Vref adjustment
voltage
VADJ 1.225 1.25 1.275 V
Maximum frequency fmax 600 — — kHz
Minimum frequency fmin — — 1 Hz
Frequency stability
with input voltage
∆f/f01 — ±1 ±3 % 4.5 V ≤ VIN ≤ 40 V
(f01 = (fmax + fmin)/2)
Frequency stability
with temperature
∆f/f02 — ±5 — % –20°C ≤ Ta ≤ 85°C
(f02 = (fmax + fmin)/2)
Sawtooth
oscillator
section
Oscillator frequency fOSC 90 100 110 kHz RT = 10 kΩ
CT = 1300 pF
Low level threshold
voltage
VTL 0.9 1.0 1.1 V Output duty cycle:
0% on
High level threshold
voltage
VTH 1.5 1.6 1.7 V Output duty cycle:
100% on
Threshold difference ∆VTH 0.5 0.6 0.7 V ∆VTH = VTH – VTL
Dead-band
adjustment
section
Output source current Isource 170 250 330 µA DB pin: 0 V
Low level threshold
voltage
VTL 0.9 1.0 1.1 V Output duty cycle:
0% on
High level threshold
voltage
VTH 1.5 1.6 1.7 V Output duty cycle:
100% on
PWM
comparator
section
Threshold difference ∆VTH 0.5 0.6 0.7 V ∆VTH = VTH – VTL
Note: 1. Resistors connected to ON/OFF pin:
TM pin
ON/
OFF
pin
V pin
IN
12
13
10
390 kΩ
2 kΩ
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 22 of 37
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 12 V, fOSC = 100 kHz)
Item Symbol Min Typ Max Unit Test Conditions Notes
Input offset voltage VIO —2 10mV
Input bias current IB—0.52.0µA
Output sink current IOsink 28 40 52 µAV
O = 2.5 V
Output source
current
IOsource 28 40 52 µAV
O = 1.0 V
Common-mode
input voltage range
VCM 1.1 — 3.7 V
Voltage gain AV40 50 — dB f = 10 kHz
Unity gain
bandwidth
BW—4 —MHz
High level output
voltage
VOH 3.5 4.0 — V IO = 10 µA
Error
amplifier
section
Low level output
voltage
VOL —0.20.5VI
O = 10 µA
Threshold voltage VTH VIN–0.22 VIN–0.2 VIN–0.18 V
CL(–) bias current IBCL(–) 140 200 260 µA CL(–) = VIN
— 200 300 ns 1
Overcurrent
detection
section Turn-off time tOFF
— 500 600 ns 2
Vref high level
threshold voltage
VTH 1.7 2.0 2.3 V
Vref low level
threshold voltage
VTL 1.4 1.7 2.0 V
Threshold
difference
∆VTH 0.1 0.3 0.5 V ∆VTH = VTH – VTL
VIN high level
threshold voltage
VINH 3.3 3.6 3.9 V
UVL section
VIN low level
threshold voltage
VINL 3.0 3.3 3.6 V
Notes: 1. HA16114 only.
2. HA16120 only.
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 23 of 37
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 12 V, fOSC = 100 kHz)
Item Symbol Min Typ Max Unit Test Conditions Notes
Output low voltage VOL —0.91.5VI
Osink = 10 mA
Output high voltage VOH1 VIN–2.2 VIN–1.6 — V IOsource = 10 mA
High voltage when off VOH2 VIN–2.2 VIN–1.6 — V IOsource = 1 mA
ON/OFF pin: 0 V
1
Low voltage when off VOL2 —0.91.5VI
Osink = 1 mA
ON/OFF pin: 0 V
2
Rise time tr— 50 200 ns CL = 1000 pF
Output
stage
Fall time tf— 50 200 ns CL = 1000 pF
SYNC source current ISYNC 120 180 240 µASYNC pin: 0 V
Sync input
frequency range
fSYNC fOSC —f
OSC × 2kHz
External sync
initiation voltage
VSYNC Vref–1.0 — Vref–0.5 V
Minimum pulse width
of sync input
PWmin 300 — — ns
External
sync
section
Input sync pulse
duty cycle
PW 5 — 50 % 3
ON/OFF sink current 1 ION/ OFF 1 60 90 120 µAON/OFF pin: 3 V
ON/OFF sink current 2 ION/ OFF 2 220 290 380 µAON/OFF pin: 5 V
IC on threshold VON 1.1 1.4 1.7 V
IC off threshold VOFF 0.4 0.7 1.0 V
On/off
section
ON/OFF threshold
difference
∆VON/OFF 0.5 0.7 0.9 V
Operating current IIN 6.0 8.5 11.0 mA CL = 1000 pF
0—10µAON/OFF pin: 0 V 1
Total
device Quiescent current IOFF
— 120 150 µAON/OFF pin: 0 V 2
Notes: 1. HA16114 only.
2. HA16120 only.
3. PW = t1 / t2 × 100
External
sync pulse
t2
t1
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 24 of 37
Characteristic Curves
4.0
3.0
2.0
1.0
0.001234
4.3V
2.5V
540
Reference voltage (V)
Reference voltage (V)
Supply voltage (V)
Reference Voltage vs. Supply Voltage Reference Voltage vs. Ambient Temperature
Ta = 25°C2.54
2.52
2.50
2.48
2.46
−20 0 20406080
2.55 max
2.45 min
SPEC
VIN = 12 V
Ambient temperature (°C)
2.5
2.0
1.5
1.0
0.5
0.0
100 200 300 400 500 600
Ta = 25°C
VIN = 12 V
RT = 10 kΩ
Low level threshold voltage of
sawtooth wave (V)
Frequency (kHz)
2.5
2.0
1.5
1.0
0.5
0.0
100 200 300 400 500 600
Ta = 25°C
VIN = 12 V
RT = 10 kΩ
High level threshold voltage of
sawtooth wave (V)
Frequency (kHz)
Low Level Threshold Voltage of Sawtooth Wave vs.
Frequency High Level Threshold Voltage of Sawtooth Wave vs.
Frequency
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 25 of 37
Oscillator Frequency Change
with Ambient Temperature (1) Oscillator Frequency Change
with Ambient Temperature (2)
Error Amplifier Gain, Error Amplifier Phase vs. Error Amplifier Input Frequency
10
5
0
−5
−10
−20 0 20406080
V
IN
= 12 V
f
OSC
= 100 kHz
SPEC
Ambient temperature (°C)
A
VO
BW
φ
Oscillator frequency change (%)
10
5
0
−5
−10
−20 0 20406080
V
IN
= 12 V
f
OSC
= 350 kHz
Ambient temperature (°C)
Oscillator frequency change (%)
60
40
20
0
1 k 3 k 10 k 30 k 100 k
Error amplifier gain A
VO
(dB)
Error amplifier phase φ (deg.)
Error amplifier input frequency f
IN
(Hz)
300 k 1 M 3 M 10 M
180
90
0
135
45
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 26 of 37
Error Amplifier Voltage Gain vs. Ambient Temperature Current Limiter Turn-Off Time vs.
Current Limiter Threshold Voltage Note
Current Limiter Turn-Off Time vs.
Ambient Temperature Note
Current Limiter Threshold Voltage vs.
Ambient Temperature
60
55
50
45
40
−20 0 20406080
40 dB min
VIN = 12 V
f = 10 kHz
50 dB typ
Error amplifier voltage gain (dB)
Ambient temperature (°C)
500
400
300
200
100
Ta = 25°C
VIN = 12 V
CL = 1000 pF
• HA16114
0.1 0.2 0.3 0.4 0.5
300 ns max
Current limiter turn-off time (ns)
CL voltage VIN−VCL (V)
0.22
0.21
0.20
0.19
0.18
−20 0 20406080
0.18 min
VIN = 12 V 0.22 max
Ambient temperature (°C)
Current limiter threshold voltage (V)
300
250
200
150
100
−20 0 20406080
VIN = 12 V
VCL = VTH − 0.3 V
CL = 1000 pF
300 ns max
Ambient temperature (°C)
Current limiter turn-off time (ns)
200 ns typ
Note: Approximatery 300 ns greater than this
in the case of the HA16120.
Note: Approximatery 300 ns greater than this
in the case of the HA16120.
• HA16114
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 27 of 37
Reference Voltage vs. IC On/Off Voltages IC On/Off Voltages vs. Ambient Temperature
Operating Current vs. Supply Voltage
Peak Output Current vs. Load Capacitance
5.0
4.0
3.0
2.0
1.0
0.0
Ta = 25°C
V
IN
= 12 V
0 0.5 1.0 1.5 2.0 2.5
Reference voltage (V)
IC on/off voltage (V)
SPEC SPEC
2.0
1.5
1.0
0.5
0.0
−20 0 20406080
SPEC
V
IN
= 12 V
f
OSC
= 100 kHz
SPEC
IC on/off voltage (V)
Ambient temperature (°C)
IC off voltage
IC off voltage
IC on voltage IC on voltage
600
500
400
300
200
100
00 1000 2000 3000 4000 5000
Ta = 25°C
V
IN
= 12 V
f
OSC
= 100 kHz
Peak output current (mA)
Load capacitance (pF)
20
15
10
5
0
Ta = 25°C
f
OSC
= 100 kHz
On duty = 50%
C
L
= 1000 pF
010203040
SPEC
Operating current (mA)
Supply voltage (V)
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 28 of 37
Operating Current vs. Output Duty Cycle
20
15
10
5
0
SPEC
0 20 40 80 10060
Operating current (mA)
Output duty cycle (%)
Ta = 25°C
V
IN
= 12 V
f
OSC
= 100 kHz
C
L
= 1000 pF
PWM Comparator Input vs. Output Duty Cycle (1)
100
0
20
40
60
80
0.6 1.61.41.21.00.8 1.8
ON duty (%)
V
DB
or V
E/O
(V)
• HA16114
300 kHz
50 kHz
600 kHz
f
OSC
Note: The on-duty of the HA16114 is the proportion
of one cycle during which output is low. Note: The on-duty of the HA16120 is the proportion
of one cycle during which output is high.
300 kHz
50 kHz
100
0
20
40
60
80
0.6 1.61.41.21.00.8 1.8
ON duty (%)
V
DB
or V
E/O
(V)
• HA16120
PWM Comparator Input vs. Output Duty Cycle (2)
600 kHz
f
OSC
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 29 of 37
024 8106
12
1
2
3
9
10
11
0
Output voltage VO (VDC)
Io sink or Io source (mA)
• HA16114 Output high voltage
when on
Output low voltage
when on
• HA16120
Output pin (Output Resistor) Characteristics
Output high voltage
when off
Output low voltage
when off
VGS
(P-channel
Power MOS FET)
VGS
(N-channel
Power MOS FET)
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 30 of 37
15
10
5
0
400
200
0
−200
−400
VOUT
(V)
IO
(mA)
VOUT
(V)
IO
(mA)
200 ns/div
Vref DB CL(−)V
IN
IN(+) CT
RT
IO
CL
1000 pF
Test Circuit
OUT
Output Waveforms: Rise of Output Voltage VOUT
Output Waveforms: Fall of Output Voltage VOUT
1300 pF
10 kΩ
Vref DB CL(−)
IN(+) CT
RT
IO
CL
1000 pF
Test Circuit
OUT
1300 pF
10 kΩ
15
10
5
0
400
200
0
−200
−400 200 ns/div
VIN
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 31 of 37
1000
100
10
1
0.1
10
1
10
2
10
3
10
4
10
5
10
6
R
T
= 3kΩ
R
T
= 10kΩ
R
T
= 30kΩ
Oscillator frequency f
OSC
(kHz)
Timing capacitance C
T
(pF)
R
T
= 100kΩ
R
T
= 300kΩ
R
T
= 1MΩ
Oscillator Frequency vs. Timing Capacitance
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 32 of 37
Application Examples (1)
+
12 V
DC
input
−
GND
SYNC
RTIN(−) E/O IN(+) P.GND
Vref ADJ DB
HA16114FP
ON/
OFF
TM CL(−)V
IN OUT
CT
390 k
2 k
2µ
−+
4.7µ
15 k 10 k
−
+
−
+
0.1µ
10k
560p 130k
470p
(gate protection resistor)
50m
220
1800p
47µH
SBD
HRP24
+
−
560µ
12V
+
−
5k 5k
Units: C : F
R : Ω
• 12 V
DC
to 5 V
DC
Step-Down Converter Using HA16114FP
Noise countermeasures:
1
34
GDS
2
16 13 12 11 10 915 14
1 4567823
5C
5B
5D
5.6
5A
5A
2
3
4
155A
5B
5C
5D
Timing circuit for
intermittent mode
during overcurrent
Specific tips for high efficiency (see the numbers in the diagram)
Use a switching element (power MOS FET) with low on-resistance.
Use an inductor with low DC resistance.
Use a Schottky barrier diode (SBD) with low V
F
.
Use a low-ESR capacitor designed for switching power supplies.
Separate the power ground from the small-signal ground,
and connect both at one point.
Add noise-absorbing capacitors.
Ground the bottom of the package with a ground strip.
Make the output-to-gate wiring as short as possible.
Dead-band and
soft-start circuit
470 µ
35 V
(noise-
absorbing
capacitor)
Small-signal ground
Ground strip
Low on-resistance
P-channel power MOSFET
Example: 2SJ214, 2SJ296
Overcurrent sense resistor
High-saturation-current choke coil
Example: Toko 8R-HB Series
Low-ESR
capacitor 5 V DC
stepped-
down
output
0.22 µ
(noise-
absorbing
capacitor)
Feedback
Power ground
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 33 of 37
Application Examples (2)
HRA83
• External Synchronization with Primary-Control AC/DC Converter
(1) Combination with a flyback AC/DC converter (simplified schematic)
Commer-
cial AC
Error amp.
−
+
VIN
OUT
CL(CS)
Transformer
Main DC
output
+
−
SBD
HRP24
1S2076A
D
R1
R2
1S2076A
+
+
−
+
−
VIN
CL
P.GNDOUTGND
SYNC
HA16114,
HA16120
10
11
891
2
Primary AC/DC converter IC
(HA16107, HA17384, etc.) 2SJ296
+
−
+
−
Sub DC
output
SBD
HRP24
Step-down
output
(HA16114) A
K
To A of SBD
This is one example of a circuit that uses the features of the HA16114/120 by operating in
synchronization with a flyback AC/DC converter. Note the following design points concerning the
circuit from the secondary side of the transformer to the
SYNC
pin of the HA16114/120.
• Diode D prevents reverse current. Always insert a diode here. Use a general-purpose switching
diode.
• Resistors R1 and R2 form a voltage divider to ensure that the input voltage swing at the
SYNC
pin
does not exceed Vref (2.5 V). To maintain operating speed, R1 + R2 should not exceed 10 kΩ.
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 34 of 37
Application Examples (3)
Input
DFG1C8
HA16107,
HA16666 etc.
Switching transformer
Coil
Coil
Coil
Coil
HRW26F
SBD
module
HA17431 and optocoupler
Feedback
section
Main DC
output
+
−
FB
2SC458
R
1
R
2
R
3
6.2kΩ
510Ω
390Ω
Q
ZD
SYNC V
IN
GND
HA16114,
HA16120
Other parts as
on previous page
1
210
OUT
Primary, for main
Secondary, for output
Tertiary, for IC
For reset
V
IN
9
C
D
AB
C
D
A
B
• External Synchronization with Primary-Control AC/DC Converter (cont.)
(2) Combination with a forward AC/DC converter (simplified schematic)
This circuit illustrates the combination of the HA16114/120 with a forward AC/DC converter. The
HA16114/120 synchronizes with the falling edge of the external sync signal, so with a forward
transformer, the sync pulses must be inverted. In the diagram, this is done by an external circuit
consisting of the following components:
• Q:
• R
1
and R
2
:
• R
3
:
• ZD:
Transistor for inverting the pulses. Use a small-signal transistor.
These resistors form a voltage divider for driving the base of transistor Q. R
2
also provides
a path for base discharge, so that the transistor can turn off quickly.
Load resistor for transistor Q.
Zener diode for protecting the
SYNC
pin.
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 35 of 37
Overall Waveform Timing Diagram (for Application Example (1))
V
IN
V
TM
,
V
ON/
OFF
V
TM
,
V
ON/
OFF
12 V
0 V
1.4 V
2.1 V
1.4 V 0.7 V
On
On On
On
OffOffOffOff
On
Pulse-by-pulse
current limiting
3.0
2.0
1.0
0.0
V
CT
sawtooth wave
V
E/O
V
E/O
,
V
CT
,
V
DB
12 V
11.8 V
0 V
V
OUT
*1
PWM
pulse
12 V
0 V
DC/DC output
(example for
positive
voltage)
IC operation
status
V
DB
Power-up IC on
Soft start Steady state Overcurrent
detected;
intermittent
operation
Overcurrent
subsides;
steady-state
operation
Quick
shutdown
Power supply off,
IC off
Note: 1. This PWM pulse is on the step-down/inverting control channel (HA16114).
The booster control channel (HA16120) output consists of alternating L and H of the IC on cycle.
Off
(V)
V
CL
0.0 V
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 36 of 37
Application Examples (4) (Some Pointers on Use)
1. Inductor, Power MOS FET, and Diode Connections
V
IN
C
F
R
F
R
CS
V
IN
CL
OUT
GND
V
O
V
IN
C
F
R
F
R
CS
V
IN
CL
OUT
GND
V
O
FB
FB
FB
C
F
R
F
R
CS
V
IN
CL
OUT
GND
FB
C
F
R
F
R
CS
V
IN
CL
OUT
GND
V
O
Vref
1. Step-up topology 2. Step-down topology
4. Step-down/step-up (buck-boost) topology3. Inverting topology
Applicable only
to HA16120 Applicable only
to HA16114
Applicable only
to HA16114 Applicable only
to HA16114
2. Turning Output On and Off while the IC is On
DB
E/O
OFF
To turn only one channel off, ground the DB pin or the E/O pin.
In the case of E/O, however, there will be no soft start
when the output is turned back on.
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Rev.2.0, Sep.18.2003, page 37 of 37
Package Dimensions
Package Code
JEDEC
JEITA
Mass
(reference value)
DP-16
Conforms
Conforms
1.07 g
6.30
19.20
16 9
81
1.3
20.00 Max
7.40 Max
7.62
0.25+ 0.13
– 0.05
2.54 ± 0.25 0.48 ± 0.10
0.51 Min
2.54 Min 5.06 Max
0˚ – 15˚
1.11 Max
As of January, 2003
Unit: mm
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-16DA
—
Conforms
0.24 g
*Dimension including the plating thickness
Base material dimension
*0.22 ± 0.05
*0.42 ± 0.08
0.12
0.15
M
2.20 Max 5.5
10.06
0.80 Max
16 9
18
10.5 Max
+ 0.20
– 0.30
7.80
0.70 ± 0.20
0˚ – 8˚
0.10 ± 0.10
1.15
1.27
0.40 ± 0.06
0.20 ± 0.04
As of January, 2003
Unit: mm
©
2003. Renesas Technolo
gy
Corp., All ri
g
hts reserved. Printed in Japan
.
Colo
p
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first in
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our circuit desi
g
ns
!
1. Renesas Technolo
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Corp. puts the maximum effort into makin
g
semiconductor products better and more reliable, but there is alwa
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m
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occur with them. Trouble with semiconductors ma
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lead to personal in
j
ur
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g
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
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2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
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