TinyRISC(R) BDMR4103 Evaluation Board User's Guide July 2000 Order Number C14071 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. Document DB15-000161-00, First Edition (July 2000). This document describes revision A of the LSI Logic Corporation TinyRISC(R) BDMR4103 Evaluation Board User's Guide and will remain the official reference source for all revisions/releases of this product until rescinded by an update. To receive product literature, visit us at http://www.lsilogic.com. LSI Logic Corporation reserves the right to make changes to any products described herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. Copyright (c) 2000 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT The LSI Logic logo design, TinyRISC, and MiniRISC are registered trademarks and SerialICE is a trademark of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies. ii Preface This book is the primary reference and user's guide for the TinyRISC(R) BDMR4103 Evaluation Board. This guide describes the basic features of the evaluation board, including hookup procedures and system configuration. For additional information that relates to the board and its components, refer to "Related Publications," on page iv. Audience This document assumes that you are familiar with microprocessors and related support devices. The people who benefit from this book are: * Engineers and managers who are evaluating the LR4103 microprocessor for possible use in a system * Engineers who are designing the microprocessor into a system Organization This document has the following chapters: * Chapter 1, Introduction, gives an overview of the BDMR4103 Evaluation Board and describes its features. * Chapter 2, Installation Procedures, explains how to connect power to the BDMR4103 Evaluation Board, go through a quick board check procedure, and install jumpers. * Chapter 3, Board Design and Layout, describes the design and layout of the BDMR4103 Evaluation Board. * Chapter 4, PAL Equations, provides the PAL equations for the BDMR4103 Evaluation Board. * Chapter 5, Schematics, contains the schematics for the BDMR4103 Evaluation Board. * Chapter 6, Bill of Materials, lists the bill of materials for the BDMR4103 Evaluation Board. Preface iii Related Publications TinyRISC(R) EZ4103 EasyMACRO Microprocessor and FBusMacro Technical Manual, LSI Logic Corporation, Order Number C14068. TinyRISC(R) LR4103 Microprocessor Technical Manual, LSI Logic Corporation, Document Number DB14-000081-00. TinyRISC(R) BDMR4103 Evaluation Kit Getting Started, LSI Logic Corporation, Document Number DB15-000095-00. MIPS PROM Monitor and C Run-Time Library User's Guide, LSI Logic Corporation, Order Number C14017.A. The C Programming Language, 2nd edition 1988, by B Kerringhan and D. Ritchie, Prentice Hall. PC16550D Universal Asynchronous Receiver Transmitter with FIFOs, National Semiconductor Corp. Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product, Advanced Micro Devices. DS1307/DS1308 64 X 8 Serial Real Time Clock, DALLAS Semiconductor. Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix "0x"--for example, 0x32CF. Binary numbers are indicated by the prefix "0b"--for example, 0b0011.0010.1100.1111. All signals with names ending in "N" are active LOW; otherwise, signals are active HIGH. iv Preface Abbreviations The following abbreviations are used in this manual. Note that abbreviated signal names are not listed: ASE Application Specific Extension CPLD Complex Programmable Logic Device DIMM Dual Inline Memory Module DIN Deutsches Institut fur Normung DIP Dual In-line Package DMA Direct Memory Access DRAM Dynamic Random Access Memory EDO Extended Data Output EEPROM Electronically Erasable Programmable Read Only Memory EJTAG Enhanced Joint Test Action Group EPROM Erasable Programmable Read Only Memory FAPI FBus Advanced Peripheral Interface FBM FBusMACRO FET Field Effect Transistor ICE In-Circuit Emulation ISA Instruction Set Architecture ISP In-System Programmable JEDEC Joint Electrical Device Engineering Committee JTAG Joint Test Action Group k Kilo-ohm Kbyte Kilobyte LED Light Emitting Diode M Megaohm Mbyte Megabyte Preface v vi PAL Programmable Array Logic PBGA Plastic Ball Grid Array PCI Peripheral Component Interface PLCC Plastic Leaded Chip Carrier PLD Programmable Logic Device PLL Phase-Locked Loop PROM Programmable Read Only Memory QSOP Quarter Size Outline Package R/A Right Angle RTC Real Time Clock SDRAM Synchronous DRAM SOIC Small Outline Integrated Circuit SOJ Small Outline J-bend SPST Single-Pole Single-throw SRAM Static RAM SSOP Shrink Small Outline Package TAP Test Access Port TP Test Point TQFP Thin Quad Flat Package TSOP Thin Small Outline Package TSSOP Thin Shrink Small Outline Package UART Universal Asynchronous Receiver Transmitter UHS Ultra High Speed F Microfarad Ohm Preface Contents Chapter 1 Chapter 2 Introduction 1.1 Product Summary 1.2 Product Features 1.3 Debug Environment Overview 1.3.1 PROM-Based Debug Environments 1.3.2 EJTAG Debug Environment 1.4 Block Diagram Installation Procedures 2.1 Quick Check 2.1.1 Checking the Board 2.1.2 Resolving Problems 2.2 Jumper Settings 2.2.1 Select PLLN (JP1) 2.2.2 Divide C1 (JP2) and Divide C0 (JP3) 2.2.3 Divide A1 (JP4) and Divide A0 (JP5) 2.2.4 Endian Selection (JP6) 2.2.5 PLL Range Select (JP7) 2.2.6 Alternate Boot Program Selection (JP8) 2.2.7 Boot Device Selection (JP9) 2.2.8 Connect 3.3 V Power (JP10) 2.2.9 Connect CPU I/O Ring Power (JP11) 2.2.10 Connect VDD Core Power (JP12) 2.2.11 Clock Source Selection (JP14) 2.2.12 SerialICE-1 Input Data Selection (JP15) 2.2.13 SerialICE-1 Clock Selection (JP16) 2.2.14 EDO/SDRAM Selection (JP17) Contents 1-1 1-2 1-3 1-3 1-3 1-4 2-1 2-2 2-4 2-5 2-9 2-9 2-10 2-11 2-11 2-11 2-11 2-12 2-12 2-12 2-13 2-13 2-13 2-13 vii Chapter 3 Board Design and Layout 3.1 Board Layout 3.2 External Interfaces 3.2.1 Expansion Connector (J2) 3.2.2 DIMM Connector (J3) 3.2.3 Serial Port Connector (J10) 3.2.4 RS-232 Serial Connector for SerialICE-1 Debug Interface(J9) 3.2.5 SerialICE-1 Connector (J8) 3.2.6 Ethernet Connector (J7) 3.2.7 EJTAG Connectors Overview of EJTAG Functions EJTAG Connector (J4) EJTAG Connector (J5) 3.2.8 PAL Programming Connector (J11) 3.2.9 Power Supply Connector (J1) 3.3 Indicators 3.3.1 Power LED 3.3.2 Ethernet LEDs 3.3.3 Debug LED 3.3.4 7-Segment Display 3.4 System Memory 3.4.1 Synchronous DRAM Dual Inline Memory Module (SDRAM DIMM) 3.4.2 Static RAM (SRAM) 3.4.3 Boot EPROMs 3.5 Memory Map 3.6 Two-Wire Serial Bus Peripheral Devices 3.6.1 Real-Time Clock (RTC) 3.6.2 EEPROM 3.6.3 Serial Presence Detect (SPD) 3.6.4 LR4103 Interrupts 3.7 Device Registers 3.7.1 PC16550D UART Registers 3.7.2 Am79C970A Ethernet Controller Chapter 4 PAL Equations viii Contents 3-2 3-3 3-4 3-7 3-9 3-10 3-11 3-12 3-13 3-13 3-13 3-15 3-18 3-19 3-20 3-20 3-21 3-21 3-22 3-23 3-23 3-23 3-23 3-24 3-26 3-26 3-28 3-28 3-29 3-29 3-30 3-31 Chapter 5 Chapter 6 Schematics 5.1 Microprocessor and Clock Circuitry 5.2 ROMs, SRAMs, and Address Latches 5.3 Ethernet and DRAM Circuitry 5.4 Miscellaneous Circuitry and Connectors 5.5 Expansion Connector and Boot Device Selection Circuitry 5.6 Power and Reset Circuitry 5.7 EJTAG Connectors 5-2 5-4 5-6 5-8 5-10 5-12 5-14 Bill of Materials Customer Feedback Figures 1.1 2.1 2.2 2.3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 5.1 5.2 5.3 BDMR4103 Block Diagram View of the BDMR4103 Quick Check Components Jumper Positions Jumper Locations on the BDMR4103 Evaluation Board BDMR4103 Evaluation Board Layout Expansion Connector DIMM Connector Pin Numbers Serial Port Connector RS-232 SerialICE-1 Connector SerialICE-1 Connector Ethernet 10BASE-T Connector EJTAG Connector J4 EJTAG Connector J5 PAL Programming Connector Power Supply Connector Indicator Positions Ethernet Indicator Positions 7-Segment Display Microprocessor and Clock Circuitry ROMs, SRAMs, and Address Latches Ethernet and DRAM Circuitry Contents 1-4 2-2 2-5 2-6 3-2 3-5 3-7 3-9 3-10 3-11 3-12 3-14 3-15 3-18 3-19 3-20 3-21 3-22 5-3 5-5 5-7 ix 5.4 5.5 5.6 5.7 Miscellaneous Circuitry and Connectors Expansion Connector and Boot Device Selection Circuitry Power and Reset Circuitry EJTAG Connectors 5-9 5-11 5-13 5-15 2.1 2.2 2.3 2.4 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 6.1 Default Jumper Settings JP2 and JP3 Jumper Settings JP4 and JP5 Jumper Settings JP9 Jumper Settings Summary of LR4103 Interface Connector Functions Expansion Connector Pin Designations DIMM Connector Pin Assignments Serial Port Connector Pin Assignments RS-232 SerialICE-1 Connector Pin Assignments SerialICE-1 Header Pin Assignments Ethernet Connector Pin Assignments EJTAG Connector J4 Pin Assignment EJTAG Connector J5 Pin Assignments PAL Programming Connector Pin Assignments Ethernet Indicator Functions 7-Segment Display Settings Boot EPROM Addressing Physical Memory Map Real-Time Clock Addressing RTC Registers EEPROM Addressing SPD EEPROM Addressing BDMR4103 Interrupts UART Registers Ethernet Controller User Registers BDMR4103 Bill of Materials 2-7 2-10 2-10 2-12 3-3 3-5 3-8 3-9 3-10 3-11 3-12 3-14 3-15 3-19 3-21 3-22 3-24 3-25 3-27 3-27 3-28 3-28 3-29 3-30 3-31 6-2 Tables x Contents Chapter 1 Introduction This chapter gives an overview of the BDMR4103 Evaluation Board. Topics covered in the chapter include: * Section 1.1, "Product Summary" * Section 1.2, "Product Features" * Section 1.3, "Debug Environment Overview" * Section 1.4, "Block Diagram" 1.1 Product Summary The BDMR4103 Evaluation Board is designed for use with the LSI Logic TinyRISC LR4103 reference device. You can use the evaluation board to * Develop application software before (or in parallel with) designing a system on a chip * Evaluate the memory system design price/performance trade-off by running an actual benchmark program Together with a PC or UNIX host, the evaluation board provides you with a complete environment for hardware and software development and debugging. Access to off-board logic through a 150-pin AMP expansion connector and the capability to download software through communication ports allows you to verify the functionality of your system before protoyping the hardware. TinyRISC(R) BDMR4103 Evaluation Board User's Guide 1-1 1.2 Product Features The features of the BDMR4103 Evaluation Board are: 1-2 * A TinyRISC LR4103 processor that provides a 120 MHz evaluation target * 128 Kbytes of on-board SRAM * A plug-in DRAM DIMM (dual inline memory module); the DIMM connector accepts any standard 100-pin JEDEC (Joint Electrical Device Engineering Committee) DIMM; a 16 Mbyte SDRAM DIMM is supplied with board * 1 Mbyte of FLASH EPROM; the EPROM contains a powerful monitor and debugger for downloading and debugging user programs * A 1 Kbyte EEPROM for the configuration parameters * Real-Time Clock (RTC) * An on-board 16550 UART (universal asynchronous receiver/transmitter) with one RS-232C serial port * SerialICETM-1 on-chip debugging capabilities * EJTAG debugging capabilities * A 7-segment display for status display and debug use * An on-board AM79C970A PCnet Ethernet controller with a 10BASE-T interface * A 150-pin AMP expansion connector that provides easy access to the evaluation board * Support for 3.3 V devices Introduction 1.3 Debug Environment Overview The BDMR4103 evaluation board offers debug support through a PROM monitor-based debug environment (PMON and SerialICE-1 debug interface) and EJTAG, a nonintrusive on-chip MIPS standard debug environment. For more information on setting up the three debug environments, please refer to the TinyRISC BDMR4103 Evaluation Kit Getting Started. 1.3.1 PROM-Based Debug Environments PMON is a conventional assembly-level PROM-based debug monitor. PMON supports stand-alone operation and operation as the backend for a source-level debugger. The principal disadvantage of PMON is memory usage. PMON takes up approximately 300 Kbytes of target memory. The BDMR4103 evaluation board is shipped with PMON stored in the lower 512 Kbyte region of the FLASH memory at U12. Communication is done through the RS-232 serial port and downloaded through the RS-232 connector at J9 or the Ethernet connector at J7. The BDMR4103 evaluation board also offers the SerialICE-1 debug environment. The SerialICE-1 debug interface provides the same debug features as PMON, but does it with less than 1 Kbyte of target memory. Use the SerialICE-1 debug interface with either an assembly-level or a source-level debugger. Communication and download is provided through the SerialICE-1 RS-232 serial port (J9) or the TTL-level 10-pin header (J8). 1.3.2 EJTAG Debug Environment EJTAG (Extended Joint Test Action Group) is a standard on-chip MIPS debugging environment. EJTAG does not require target system memory. To use EJTAG, the user needs to set up the memory map for the BDMR4103 evaluation board since it has a programmable memory controller. The user can either accomplish this in application code or use the sample boot-up code provided in the upper 512 Kbyte region of the FLASH EPROM memory. The user must run this boot-up code before Debug Environment Overview 1-3 downloading application programs to the evaluation board using an assembly-level or source-level debugger. Communication and download occurs through the EJTAG connector at J4. 1.4 Block Diagram Figure 1.1 shows a high level block diagram of the BDMR4103 evaluation board. Figure 1.1 BDMR4103 Block Diagram 1 Mbyte EPROM SerialICE-1 Circuitry 16 Mbytes 128 Kbytes SDRAM SRAM 1 Mbyte FLASH EPROM EJTAG Connectors for Debug LR4103 Microprocessor Address Bus Data Bus EEPROM I2C Devices 16550 UART Ethernet Control 7-Segment Display RTC 150-Pin Expansion Connector Serial Port 1-4 Introduction 10BASE-T Ethernet Connector Chapter 2 Installation Procedures This chapter describes the installation procedure for the BDMR4103 Evaluation Board. Topics covered in the chapter include: * Section 2.1, "Quick Check" * Section 2.2, "Jumper Settings" 2.1 Quick Check Figure 2.1 shows a simplified view of the BDMR4103 board with the components referenced in this section. Figure 3.1, on page 3-2, shows a more detailed view of the board. Major connectors and the LR4103 processor are shown in Figure 2.1 to provide an orientation. TinyRISC(R) BDMR4103 Evaluation Board User's Guide 2-1 Figure 2.1 View of the BDMR4103 Quick Check Components SerialICE-1 Header J8 Reset Button Ethernet (RJ45) Port J7 SerialICE-1 RS232 Port J9 Serial Port J10 U6 SI Oscillator 1 Mbyte 1 Mbyte U12 FLASH EPROM JP9 JP8 JP7 JP6 JP5 JP4 JP3 JP2 JP1 U25 EPROM Microprocessor U5 mproc OSC U1 X1 Power Supply Connector mproc Crystal U16 LR4103 Reference Device U36 D5 Power LED J1 Core Power 3.3 V U13 1 Kbyte EEPROM Pins J3 100-Pin DIMM Connector 50 100 Pins 1 51 C50 B50 A50 C1 B1 A1 J2 150-Pin DIN Connector 2.1.1 Checking the Board You can check the evaluation board by booting the PROM monitor program. The BDMR4103 board is shipped with a monitor program burned into the AM29F080 FLASH EPROM at location U12. Use the following procedure to check the board: 2-2 Installation Procedures 1. Using a standard RS-232C cable, connect the serial port (J10) to one of the following: - A terminal console. - A workstation or PC running a terminal emulator program. Standard VT100-type terminals and PC AT-compatible PCs operating in VT100 emulation mode are suitable. To emulate a VT100 terminal on a PC, use the Hyperterminal application in Microsoft Windows. Set the terminal software for the following: - 9600 baud - 8 data bits - no parity - 1 stop bit Section 3.2.3, "Serial Port Connector (J10)," on page 3-9 describes the serial port connector. 2. Set the following jumpers: (Refer to Figure 2.3) - Remove JP9 to select the FLASH EPROM at location U12 as the boot device. - Remove JP8 to select the correct boot program within the FLASH EPROM. - Remove JP6 to select big-endian addressing mode. 3. LSI Logic provides an AC adapter with the BDMR4103 board. Power from the adapter is supplied to the board by means of the standard DC power connector at location J1. Figure 2.1 shows the position of the DC connector on the evaluation board. Section 3.2.9, "Power Supply Connector (J1)," on page 3-19, describes the connector. To apply power to the board, plug the DC power connector on the AC adapter into the on-board power connector (J1) and plug the three-pin AC connector on the adapter into main building power. The power supply provided with the board will operate with AC power in the range of 100 V-240 V, at 50/60 Hz. When power is applied to the board, the power LED at D5 lights up. Quick Check 2-3 4. The following events then occur: - The terminal screen displays a banner. - The monitor prompt appears on the screen. - The terminal displays the start-up message. 5. After the start-up message, the monitor displays the following prompt: PMON> This prompt may vary slightly depending on the terminal display type and settings. When you see the prompt, the system is ready for use. 2.1.2 Resolving Problems If nothing appears on the screen when you power up the board, check the following: 1. Is the power adapter plugged into the BDMR4103 board and into the AC building supply? 2. Is the LED at D5 lit? 3. Is the RS-232C cable correctly installed at location J10? 4. Are the jumpers set for correct operation, as described in Section 2.1.1, "Checking the Board", step 2.? 5. If you are using a PC, is it operating in standard VT100 terminal emulation mode? If problems persist, contact your LSI Logic sales representative for further assistance. 2-4 Installation Procedures 2.2 Jumper Settings The BDMR4103 board has both 2- and 3-pin jumpers. As shown in Figure 2.2, the 2-pin jumpers are described as being either in (installed) or out (not installed), and the 3-pin jumpers are described as being in positions 1-2, positions 2-3, or out. Figure 2.2 Jumper Positions In Out 1 2 1 2 Two-Pin Jumpers Positions 1-2 1 2 3 Positions 2-3 1 2 3 Three-Pin Jumpers Out 1 2 3 All jumpers are identified by a number of the form JPnn (JP1, JP2, and so forth) on the BDMR4103 board. Figure 2.3 on page 2-6 shows the locations of the jumpers on the evaluation board. Connectors are shown in Figure 2.3 on page 2-6 to provide the proper orientation. Table 2.1 on page 2-7 summarizes the jumper functions and indicates the defaults (factory settings). Sections 2.2.1 through 2.2.14 provide more detailed information about jumper settings. After performing the Quick Check in Section 2.1, disconnect the power connection from the board and set the jumpers. Jumper Settings 2-5 Figure 2.3 Jumper Locations on the BDMR4103 Evaluation Board JP9 Boot Device Selection 3 2 1 JP8 Alternate Boot Program Selection JP16 SerialICE-1 Clock Selection JP7 PLL Range Selector JP15 SerialICE-1 Input Data Selection JP6 Endian Selection J7 J8 J9 JP5 Divide A0 Control PCLK Freq. JP4 Divide A1 JP3 Divide Clock 0 Control PBCLK Freq. J10 JP9 JP8 JP7 JP6 JP5 JP4 JP3 JP2 JP1 JP16 U24 JP15 JP2 Divide Clock 1 JP1 PLLN Selection 3 2 1 JP14 Clock Source Selection LR4103 Microprocessor J1 JP 14 U1 JP13 VDD Core Voltage Selection JP13 JP12 JP12 Connect/ Disconnect LR4103 Core Power JP11 JP10 JP17 JP11 Connect/Disconnect LR4103 I/O Power J3 JP10 Connect/Disconnect +3 V Power J2 3 2 1 2-6 When installed, these jumpers tie the related input to the LR4103 microprocessor low. JP17 Address Line Configuration for SDRAM and EDO DRAM Installation Procedures Table 2.1 Default Jumper Settings Jumper Jumper Name Setting Function Implemented Reference JP1 Select PLLN In (Default) Selects the PLL (phase-locked loop) circuit as the clock source for the LR4103. Out Selects the input clock as the clock source for the LR4103. Section 2.2.1, page 2-9 Default: JP2 In JP3 In See Table 2.2 Control the PBCLK frequency. Default: JP4 In JP5 Out See Table 2.3 Control the PCLK frequency. Out (Default) Selects big endian mode. In Selects little endian mode. In (Default) 100-250 MHz Out 200-500 MHz In Inverts the A19 input to the boot device to allow the selection of an alternate boot program. Out (Default) A19 input to the boot device is not inverted. In Selects the EPROM at U25 as the boot device. Out (Default) Selects the FLASH EPROM at U12 as the boot device. In (Default) Connects 3.3 V power to the onboard devices. Out Disconnects 3.3 V power from the onboard devices for test purposes. JP2 and JP3 Divide C[1:0] JP4 and JP5 Divide A[1:0] JP6 Endian Selection JP7 JP8 JP9 JP10 PLL Range Selector Alternate Boot Program Selection Boot Device Selection Connect 3.3 V The default settings select a PBCLK frequency equal to 1/3 PCLK. The default settings select a PCLK frequency equal to 4 x the input clock. Section 2.2.2, page 2-9 Section 2.2.3, page 2-10 Section 2.2.4, page 2-11 Section 2.2.5, page 2-11 Section 2.2.6, page 2-11 Section 2.2.7, page 2-11 Section 2.2.8, page 2-12 (Sheet 1 of 2) Jumper Settings 2-7 Table 2.1 Default Jumper Settings (Cont.) Jumper Jumper Name Setting Function Implemented Reference JP11 Connect CPU Power In (Default) Connects the 3.3 V power to the LR4103 VDDIO pins. Out Disconnects 3.3 V power from the LR4103 VDDIO pins for test purposes. Section 2.2.9, page 2-12 In (Default) Connects power to the LR4103 VDD_CORE pins. Out Disconnects power from the LR4103 VDD_CORE pins for test purposes. Oscillator/ Crystal Clock Selection Positions 1-2 Enables the oscillator at U5 to provide the clock input to the LR4103 microprocessor. Positions 2-3 (Default) Enables the X1 crystal to provide the clock input to the LR4103 microprocessor. SerialICE-1 Input Data Selection Positions 1-2 (Default) The connector at J9 provides the data. Positions 2-3 The connector at J8 provides the data. Positions 1-2 (Default) The on-board oscillator (U6) supplies the SerialICE-1 clock. Positions 2-3 The connector at J8 provides the SerialICE-1 clock. Positions 1-2 (Default) Address lines are configured for SDRAM. Positions 2-3 Address lines are configured for EDO (extended data output) DRAM. JP12 JP14 JP15 J16 JP17 Connect VDD Core Power SerialICE-1 Clock Selection SDRAM/EDO Selection-- Controls Address Input to DRAM DIMM Module (Sheet 2 of 2) 2-8 Installation Procedures Section 2.2.10, page 2-12 Section 2.2.11, page 2-13 Section 2.2.12, page 2-13 Section 2.2.13, page 2-13 Section 2.2.14, page 2-13 2.2.1 Select PLLN (JP1) This jumper selects the clock source for the LR4103 microprocessor. The default setting is installed. When JP1 is installed, the SELECT_PLLN input to the clock circuitry in the microprocessor is tied low. This means that on reset, the CLKSEL bit of the SCR2 register in the LR4103 is cleared, thus selecting the PLL (phase-locked loop) circuit as the clock source for the LR4103. When JP1 is not installed, the SELECT_PLLN input to the clock circuitry in the microprocessor is tied high. This means that on reset, the CLKSEL bit of the SCR2 register in the LR4103 chip is set, thus selecting the input clock as the clock source for the LR4103. You can use software at any time to overwrite the CLKSEL bit in the SCR2 register originally set by this jumper. 2.2.2 Divide C1 (JP2) and Divide C0 (JP3) These jumpers control the PBCLK frequency. The PBCLK is used as the clock for the PCI devices connected to the LR4103 microprocessor. When the jumpers are installed, they tie the inputs to the clock circuitry in the microprocessor low. When they are not installed, the inputs are high. On reset, the values set by these jumpers are loaded into the CLKDC[1:0] bits in the LR4103 SCR2 register. See the TinyRISC EZ4103 EasyMACRO Microprocessor and FBusMacro Technical Manual for more information. The frequency of PBCLK is derived by dividing PCLK by the value of CLKDC[1:0]. Table 2.2 shows the CLKDC values provided by the jumper settings and the clock frequencies derived from these values. Jumper Settings 2-9 You can use software at any time to overwrite the DIVC[1:0] values set by these jumpers in the SCR2 register. Table 2.2 JP2 and JP3 Jumper Settings JP2 Setting JP3 Setting CLKDC[1:0] Values PBCLK Frequency In (Default) In (Default) 0b00 PCLK divided by 3 In Out 0b01 PCLK divided by 1 Out In 0b10 PCLK divided by 2 Out Out 0b11 PCLK divided by 4 2.2.3 Divide A1 (JP4) and Divide A0 (JP5) These jumpers control the PCLK frequency by setting the multiplication value of the LR4103 PLL circuit. PCLK is the processor core clock, and it is synthesized by multiplying the input clock by the value set on jumpers JP4 and JP5. Table 2.2 shows the DIVA[1:0] inputs provided by the jumpers and lists the PCLK frequencies derived from these inputs. Table 2.3 JP4 and JP5 Jumper Settings JP4 Setting JP5 Setting DIVA[1:0] Inputs Values Max. PCLK Frequency1 In In 0b00 4 Input*21 In (Default) Out (Default) 0b01 8 Input*41 Out In 0b10 16 Input*81 Out Out 0b11 32 Input*161 1. The maximum value is the value derived after reset. The values shown in the right-hand column are the maximum values possible. A lower value for PCLK can be obtained using software to program CLKDB[3:0] in the SCR2 register of the LR4103. You cannot control the DIVA value using software. 2-10 Installation Procedures 2.2.4 Endian Selection (JP6) Jumper JP6 selects between big endian and little-endian addressing mode. When the jumper is installed, the endian input to the board, BIG_ENDIANP, is tied low, meaning the board is in little-endian mode. When the jumper is not installed, BIG_ENDIANP is tied high, causing the board to function in big-endian mode. The default is big-endian mode. 2.2.5 PLL Range Select (JP7) When the JP7 jumper is in, the PLL range is 100-250 MHz. When the JP7 jumper is out, the PLL range is 200-500 MHz. The PLL runs at twice the chip clock. The LR4103 is rated for 120 MHz; thus, since 120 x 2 = 240, when the jumper JP7 is in, all valid input speeds are acceptable. 2.2.6 Alternate Boot Program Selection (JP8) When installed, JP8 inverts the most significant address bit (A19) input to the boot device. When JP8 is not installed, A19 is not inverted. The default is not installed. This jumper is used to select between two boot programs installed in the same 1 Mbyte EPROM. Each boot EPROM can accommodate two boot programs, provided that neither program is larger than 512 Kbytes. The alternate program should be programmed at address 0x80000 in the boot EPROM memory. Setting the most significant address bit to the EPROM HIGH (that is, installing JP8) allows the alternate program to be selected. 2.2.7 Boot Device Selection (JP9) The BDMR4103 Evaluation Board accommodates two boot devices: the EPROM in the DIP socket at location U25, and the onboard FLASH EPROM at location U12. Jumper JP9 selects between the system boot devices. The default setting is not installed, causing the system to boot from the FLASH EPROM at location U12. Jumper Settings 2-11 The PAL at U42 maps the address of the selected boot device to the MIPS boot vector address (0x1FC0 0000). Table 2.4 shows the address spaces for each boot device. Table 2.4 JP9 Jumper Settings JP9 Setting Boot Device (Board Location) Boot Device Address Space Alternate Device (Board Location) Alternate Device Address Space In EPROM (U25) 0x1FC00000- 0x1FCFFFFF FLASH EPROM (U12) 0x1FD00000- 0X1FDFFFFF Out (Default) FLASH EPROM (U12) 0x1FC00000- 0x1FCFFFFF EPROM (U25) 0x1FD00000- 0X1FDFFFFF 2.2.8 Connect 3.3 V Power (JP10) When jumper JP10 is installed, 3.3 V power is supplied to the on-board devices. When the jumper is not installed, there is no 3.3 V power supply to these devices. This jumper allows you to measure the current used by 3.3 V devices. To do this, remove the jumper and connect a current meter between the terminals. The default setting is installed. 2.2.9 Connect CPU I/O Ring Power (JP11) When jumper JP11 is installed, 3.3 V power is supplied to the LR4103 VDDIO pins. When the jumper is not installed, there is no 3.3 V power supply to these pins. This jumper allows you to measure the current used by the LR4103 I/O devices. To do this, remove the jumper and connect a current meter between the terminals. The default setting is installed. 2.2.10 Connect VDD Core Power (JP12) When jumper JP12 is installed, power is supplied to the LR4103 VDD_CORE pins. When the jumper is not installed, no power is supplied to these pins. This jumper allows you to measure the current used by the LR4103 internal logic. To do this, remove the jumper and connect a current meter between the terminals. The default setting is installed. VDD_CORE provides power to everything on the LR4103 but the I/O ring. 2-12 Installation Procedures 2.2.11 Clock Source Selection (JP14) The three-position jumper, JP14, selects the clock input to the LR4103 microprocessor. When this jumper is installed in positions 1-2, the oscillator at location U5 supplies the clock. When it is installed in positions 2-3, the 25 MHz crystal X1 supplies the clock. The default is positions 2-3. 2.2.12 SerialICE-1 Input Data Selection (JP15) The three-position jumper, JP15, selects the source of the SerialICE-1 input data. When this jumper is installed in positions 1-2, the data input comes from connector J9. When the jumper is in positions 2-3, the data comes from connector J8. The default is positions 1-2. 2.2.13 SerialICE-1 Clock Selection (JP16) The three-position jumper, JP16, selects the source of the SerialICE-1 clock. When this jumper is installed in positions 1-2, the on-board oscillator at location U6 supplies the clock. The clock supplied should be 16x the desired baud rate. When the jumper is installed in positions 2-3, the clock signal is supplied from pin 4 of the connector at location J8. The default is positions 1-2. 2.2.14 EDO/SDRAM Selection (JP17) Jumper JP17 enables you to configure the address lines so that you can use either SDRAM or EDO DRAM devices on the DIMM installed in the DIMM slot at location J3. This is accomplished by routing the correct signal to pin 68 of the DIMM. For SDRAM devices, pin 68 is defined as bank address 0 (BA0); for EDO DRAM devices, pin 68 is defined as address 11 (A11). To configure the BDMR4103 board for SDRAM, the jumper is installed in positions 1-2, routing address FADDRP27 to pin 68 of the DIMM socket. To configure the BDMR4103 board for EDO DRAM, the jumper is installed in positions 2-3, routing address FADDRP11 to pin 68. The default is positions 1-2. Jumper Settings 2-13 2-14 Installation Procedures Chapter 3 Board Design and Layout This chapter describes the board design and layout of the BDMR4103 Evaluation Board as well as elements of the design architecture. Topics covered in the chapter include: * Section 3.1, "Board Layout" * Section 3.2, "External Interfaces" * Section 3.3, "Indicators" * Section 3.4, "System Memory" * Section 3.5, "Memory Map" * Section 3.6, "Two-Wire Serial Bus Peripheral Devices" * Section 3.7, "Device Registers" TinyRISC(R) BDMR4103 Evaluation Board User's Guide 3-1 3.1 Board Layout Figure 3.1 shows the placement of the major components on the BDMR4103 Evaluation Board. Note that the board is not drawn to scale and the figure should not be used as a manufacturing aid. Figure 3.1 BDMR4103 Evaluation Board Layout SeriaIICE-1 RS232 Port J9 Ethernet 10BASE-T SerialICE-1 Connector Header J7 J8 Ethernet Status Lights Serial Port J10 S1 B1 J6 Debug Probe Factory Use Only Battery U6 for Real-Time SI Oscillator X3 Clock U10 J11 PAL Prog. U14 U21 U37 U4 J5 Ethernet Transformer Debug LED D6 Real-Time Clock JP16 JP15 U42 PAL 1 Mbyte U12 FLASH EPROM U30 U24 16550 UART U17 U8 U18 U7 Microprocessor U5 mproc OSC OSC U9 U19 AM79C970A PCnet TM EJTAG J4 U3 U35 7-Segment Display JP14 proc Crystal U1 X1 Ethernet Controller U38 LR4103 Reference Device U2 D5 Power Supply Connector JP13 U16 JP12 JP11 I Kbyte EEPROM U13 1 Mbyte U25 EPROM U30 U36 JP10 3.3 V 32 Kbytes x 8 SRAMs U26 U32 32 Kbytes x 8 SRAMs JP17 U27 U22 U29 Voltage Regulators U28 J3 100-pin DIMM Connector 50 1 100 51 C50 B50 A50 C1 B1 A1 J2 150-Pin DIN Connector 3-2 Board Design and Layout JP9 JP8 JP7 JP6 JP5 JP4 JP3 JP2 JP1 Power LED J1 Core Power 3.2 External Interfaces This section describes the external interfaces to the BDMR4103 Evaluation Board. The connectors that implement the interfaces let you connect external logic, download software, connect to the Ethernet, debug the board, program the PAL, and so forth. This section describes the connectors listed in Table 3.1. Figure 3.1 (page 3-2) shows the positions of the connectors on the board. Table 3.1 Summary of LR4103 Interface Connector Functions Board Location Connector Name Description Application Main Ref. J1 Power Supply Standard 5 V, 4.0 A, DC power connector Connects board to AC power supply. Page 3-19 J2 Expansion 150-pin DIN connector Connects external modules to board; expands design and debug capabilities. Page 3-4 J3 DIMM 100-pin DIMM connector Allows a DIMM module to be installed on the board, either SDRAM (Synchronous DRAM) or EDO (Extended Data Output). Page 3-7 J4 EJTAG 16-pin connector Provides basic break and run control. Allows you to download programs and data to memory. You can use this connector or connector J5 to debug the board. Page 3-13 J5 EJTAG 52-pin connector Provides the same debugging capabilities as J4, plus PC trace capability. Page 3-15 J6 Debug Probe 20-pin connector Used only for factory testing. Do not use this connector. - External Interfaces 3-3 Table 3.1 Summary of LR4103 Interface Connector Functions (Cont.) Board Location Connector Name Description Application Main Ref. J7 Ethernet 10BASE-T RJ45 connector Connects the board to the Ethernet using a standard 10BASE-T plug. Page 3-12 J8 SerialICE-1 Interface 10-pin header Provides a logic level SerialICE-1 interface. You need special equipment to use this interface. Page 3-11 J9 SerialICE-1 RS232 DB-9 connector Provides a standard RS232 serial connector for SerialICE-1 Debug Interface. Page 3-10 J10 Serial Port DB-9 connector Allows you to connect a standard terminal for RS232 serial I/O communication. Page 3-9 J11 PAL Programming Port 8-pin header Allows you to program the PAL (U42). Page 3-18 3.2.1 Expansion Connector (J2) A 150-pin DIN connector (J2) lets you expand your design and debugging capability to include external logic. Figure 3.2 on page 3-5 shows the pin numbers for the expansion connector and Table 3.2 on page 3-5 lists the pin assignments. Note that the expansion connector signals are not buffered on the BDMR4103 Evaluation Board. You should buffer these signals when using them off the evaluation board. 3-4 Board Design and Layout Figure 3.2 Expansion Connector Position #50 Position #1 Row C Row B Row A A1 Indicator Table 3.2 Expansion Connector Pin Designations Pin Signal Name Pin Signal Name Pin Signal Name A1 +5 V B1 Ground C1 Ground A2 +5 V B2 Ground C2 Ground A3 +5 V B3 FADDR12 C3 FADP00 A4 Ground B4 FADDR13 C4 FADP01 A5 Ground B5 FADDR14 C5 FADP02 A6 Ground B6 FADDR15 C6 FADP03 A7 INTP0 B7 FADDR16 C7 FADP04 A8 INTP1 B8 FADDR17 C8 FADP05 A9 INTP2 B9 FADDR18 C9 FADP06 A10 INTP3 B10 FADDR19 C10 FADP07 A11 INTP4 B11 Ground C11 FADP08 A12 INTP5 B12 FADDR20 C12 FADP09 A13 T0_OUTN B13 FADDR21 C13 FADP10 A14 T1_OUTN B14 FADDR22 C14 FADP11 A15 Ground B15 FADDR23 C15 FADP12 A16 NC1 B16 AFADDR24 C16 FADP13 A17 BOOTCFG0 B17 FADDR25 C17 FADP14 A18 BOOTCFG1 B18 FADDR26 C18 FADP15 External Interfaces 3-5 Table 3.2 3-6 Expansion Connector Pin Designations (Cont.) Pin Signal Name Pin Signal Name Pin Signal Name A19 BOOTCFG2 B19 Ground C19 Ground A20 NC1 B20 SDCASN C20 SDWEN A21 NC1 B21 SDDDMP0 C21 SDDMP1 A22 CWAITP B22 SDCSN0 C22 SDRASN A23 RSTOUTN B23 FADDR01 C23 FADDRP00 A24 RESETN B24 FADDR03 C24 FADDRP02 A25 Ground B25 FADDR05 C25 FADDRP04 A26 NC1 B26 FADDR07 C26 FADDRP06 A27 GP0 B27 FADDR09 C27 FADDRP08 A28 GP1 B28 FADDR11 C28 FADDRP10 A29 GP2 B29 FADDR28 C29 FADDRP27 A30 GP3 B30 SDCSN1 C30 SDCLK0 A31 GP4 B31 SDDMP2 C31 Ground A32 GP5 B32 SDDMP3 C32 FADP16 A33 Ground B33 Ground C33 FADP17 A34 GPWEN0 B34 FRAMEN C34 FADP18 A35 GPWEN1 B35 IRDYN C35 FADP19 A36 GPWEN2 B36 TRDYN C36 FADP20 A37 GPWEN3 B37 STOPN C37 FADP21 A38 GPRDN B38 DEVSELN C38 FADP22 A39 Ground B39 PBCLK C39 FADP23 A40 GPI00 B40 Ground C40 Ground A41 GPI01 B41 CEBEN0 C41 FADP24 A42 GPI02 B42 CEBEN1 C42 FADP25 A43 GPI03 B43 CEBEN2 C43 FADP26 Board Design and Layout Table 3.2 Expansion Connector Pin Designations (Cont.) Pin Signal Name Pin Signal Name Pin Signal Name A44 NC1 B44 CEBEN3 C44 FADP27 A45 Ground B45 SDONEP C45 FADP28 A46 Ground B46 FALEP C46 FADP29 A47 Ground B47 EXP_GNTN C47 FADP30 A48 +3.3 V B48 EXP_REQN C48 FADP31 A49 +3.3 V B49 Ground C49 Ground A50 +3.3 V B50 Ground C50 Ground 1. Not connected. 3.2.2 DIMM Connector (J3) A 100-pin DIMM connector (J3), allows you to install a DIMM (Dual Inline Memory Module) on the board. The connector accommodates DIMMs populated with SDRAM or EDO devices. Figure 3.3 shows the pin numbers for this connector and Table 3.3 lists the pin assignments. In Table 3.3 on page 3-8, "NC" in the Signal Name column signifies No Connection on the listed pin. Figure 3.3 DIMM Connector Pin Numbers Pins Pins 50 1 100 51 Keys 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 08 06 04 02 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 09 07 05 03 01 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 99 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 97 External Interfaces 3-7 Table 3.3 DIMM Connector Pin Assignments Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name 1 Ground 26 Ground 51 Ground 76 Ground 2 FADP00 27 +3.3 V 52 FADP08 77 +3.3 V 3 FADP01 28 SDWEN 53 FADP09 78 SDCASN 4 FADP02 29 SDCSN0 54 FADP10 79 SDCSN1 5 FADP03 30 SDCSN0 55 FADP11 80 SDCSN1 6 +3.3 V 31 +3.3 V 56 +3.3 V 81 +3.3 V 7 FADP04 32 NC2 57 FADP12 82 NC2 8 FADP05 33 NC2 58 FADP13 83 NC2 9 FADP06 34 NC2 59 FADP14 84 NC2 10 FADP07 35 NC2 60 FADP15 85 NC2 11 SDDMP0 36 Ground 61 SDDMP1 86 Ground 12 Ground 37 SDDMP2 62 Ground 87 SDDMP3 13 FADDRP00 38 FADP16 63 FADDRP01 88 FADP24 14 FADDRP02 39 FADP17 64 FADDRP03 89 FADP25 15 FADDRP04 40 FADP18 65 FADDRP05 90 FADP26 16 FADDRP06 41 FADP19 66 FADDRP07 91 FADP27 17 FADDRP08 42 +3.3 V 67 FADDRP09 92 +3.3 V 1 18 FADDRP10 43 FADP20 68 FADDRP27 (BA0) FADDRP11 (A11) 93 FADP28 19 FADDRP28 44 FADP21 69 FADDRP11 94 FADP29 95 FADP30 20 NC 2 45 FADP22 70 NC2 21 +3.3 V 46 FADP23 71 +3.3 V 96 FADP31 22 NC 2 47 Ground 72 SDRASN 97 Ground NC 2 48 GPI01 73 SDCASN 98 Ground 24 NC 2 99 Ground 25 SDCLK0 100 Ground 23 49 GPI00 74 NC2 50 +3.3 V 75 SDCLK0 1. The signal on pin 68 depends upon the setting of JP17. Refer to Section 2.2.14, "EDO/SDRAM Selection (JP17)," page 2-13. 2. Not connected. 3-8 Board Design and Layout 3.2.3 Serial Port Connector (J10) A 9-pin serial port connector (J10) provides connections for serial port devices. Figure 3.4 shows the pin numbers for this connector and Table 3.4 lists the pin assignments. The PROM Monitor initializes the serial port to operate at 9600 baud with eight bits of data, no parity bit, and one stop bit. Figure 3.4 Serial Port Connector TX Transmitted Data DTR Data Terminal Ready Ground RX Received Data DCD Data Carrier Detect 1 2 6 3 7 4 8 5 9 DSR Data Set Ready Request to Send RTS Not connected CTS Clear to Send Table 3.4 Serial Port Connector Pin Assignments Pin Signal Name Description 1 DCD Data Carrier Detect (Not Connected) 2 RX Received Data 3 TX Transmitted Data 4 DTR Data Terminal Ready (Not Connected) 5 GND Ground 6 DSR Data Set Ready (Not Connected) 7 RTS Request to Send 8 CTS Clear to Send 9 -- Not Connected External Interfaces 3-9 3.2.4 RS-232 Serial Connector for SerialICE-1 Debug Interface(J9) A DB-9 connector (J9) allows you to debug the board using the SerialICE-1 debug Interface through an RS-232 cable. Pins 1 and 2 of jumper JP15 need to be shorted to route the RS-232 TX signal to the ICERXP pin of the LR4103 ICEport. Figure 3.5 shows the pin numbers for this connector and Table 3.5 lists the signal assignments. Figure 3.5 RS-232 SerialICE-1 Connector TX Transmitted Data DTR Data Terminal Ready Ground RX Received Data DCD Data Carrier Detect 1 2 6 3 7 4 8 5 9 DSR Data Set Ready RTS Request to Send Not connected CTS Clear to Send Table 3.5 RS-232 SerialICE-1 Connector Pin Assignments Pin 3-10 Signal Name Description 1 DCD Data Carrier Detect (Not Connected) 2 RX Received Data 3 TX Transmitted Data 4 DTR Data Terminal Ready (Not Connected) 5 GND Ground 6 DSR Data Set Ready (Not Connected) 7 RTS Request to Send (Not Connected) 8 CTS Clear to Send (Not Connected) 9 -- Not Connected Board Design and Layout 3.2.5 SerialICE-1 Connector (J8) A 10-pin header (J8) allows you to debug the board using SerialICE-1. Pins 2 and 3 of jumper JP15 need to be shorted to route the CONN_RXP signal to the ICERXP pin of the LR4103 ICEport. Figure 3.6 shows the pin numbers for this connector and Table 3.6 lists the signal assignments. Figure 3.6 SerialICE-1 Connector Ground ICECLKP CONN_RXP Ground ICE_TXP Input 2 4 6 8 10 1 3 5 7 9 Input from Oscillator +5 V Ground SI_RESET Ground Table 3.6 SerialICE-1 Header Pin Assignments Pin Signal Name Description 1 CLK_OUT Supplies clock output from the oscillator (U6). 2 -- Ground. 3 -- Ground. 4 CLK_IN Provides clock source for the LR4103 ICEport 5 -- Ground 6 -- Ground 7 SI_RESET System Reset 8 CONN_RXP Received Serial Data 9 +5 V +5V 10 ICE_TXP Transmitted Serial Data External Interfaces 3-11 3.2.6 Ethernet Connector (J7) The Ethernet 10BASE-T connector (J7) is a standard RJ45 connector that allows you to connect the board to Ethernet. Figure 3.7 shows the pin numbers for this connector and Table 3.7 lists the pin assignments. Figure 3.7 Ethernet 10BASE-T Connector Not connected RD+ Received Data TD- Transmitted Data Return Not connected TD+ Transmitted Data Not connected RD- Received Data Return Not connected 1 2 3 4 5 6 7 8 RJ45 Table 3.7 Ethernet Connector Pin Assignments 3-12 Pin Name Description 1 TD+ Transmitted Data 2 TD- Transmitted Data Return 3 RD+ Received Data 4 NC Not Connected 5 NC Not Connected 6 RD- Received Data Return 7 NC Not Connected 8 NC Not Connected Board Design and Layout 3.2.7 EJTAG Connectors The BDMR4103 has two EJTAG connectors used to debug the board. The connectors are at locations J4 and J5. This section provides an overview of EJTAG functions and describes the two EJTAG connectors. 3.2.7.1 Overview of EJTAG Functions EJTAG is an on-chip debug solution from the MIPS licensees/partners. EJTAG provides a nonintrusive leading-edge debug tool for the LSI Logic MiniRISC(R) and TinyRISC microprocessors in PC and workstation environments. EJTAG is intended to establish a debug standard among MIPS partners and simplify the development of systems based on MIPS microprocessors. EJTAG allows you to debug user code for the MIPS16 ASE (application specific extension) and MIPS I/II/III ISA (instruction set architecture). The revision of the EJTAG specification implemented by LSI Logic is EJTAG Revision 1.5.3. The EJTAG functions associated with the BDMR4103 evaluation board are implemented as hardware. These functions include: * EJTAG interface and memory * Software breakpoints * Single stepping * DMA support * Instruction, data, and processor breakpoints * PC trace (J5) * Profiling 3.2.7.2 EJTAG Connector (J4) The 16-pin EJTAG connector (J4) allows you to use a subset of the EJTAG functions, including downloading data and programs to memory and run control. The connector does not support PC trace. Figure 3.8 shows the pin numbers for this EJTAG connector and Table 3.8 lists the pin assignments. External Interfaces 3-13 Figure 3.8 EJTAG Connector J4 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 Table 3.8 EJTAG Connector J4 Pin Assignment Pin Signal Name Input/Output Description 1 TDO O TDO (test data output) performs different functions, depending on whether or not PC trace mode is turned on. Connector J4 does not support PC trace, so the functions of this signal are the same as those when PC trace mode is turned off. That is, serial output data is shifted from the JTAG instruction of the data register to pin 1 (TDO) on the falling edge of the test clock, TCK. When no data is shifted out, this pin is in a 3-state (high impedance) condition. 2, 5, 8, 10, 11, 14, 15 - - Not connected. 3 TDI/DINT I TDI (test data input)/DINT(debug interrupt). 4 TRST I TRST (test reset) is an active-low, asynchronous, reset signal that resets the EJTAG module independently of the processor logic. 6 3.3 V I 3.3 V power. 7 TCK I TCK (test clock) is the input clock used to shift data into or out of the instruction register or data register. 9 TMS I TMS (test mode select) is decoded by the TAP controller to control test operation. The signal is sampled on the rising edge of TCK. 12, 16 - - Ground 13 EJTAG_RESET I This signal is a board level reset signal. 3-14 Board Design and Layout 3.2.7.3 EJTAG Connector (J5) The 52-pin EJTAG connector (J5) supports the same EJTAG functions as the connector at J4. In addition, it supports PC trace. Figure 3.9 shows the pin numbers for the connector and Table 3.9 lists the pin assignments. Figure 3.9 EJTAG Connector J5 2 4 6 8 10 12 14 16 18 20 44 46 48 50 52 1 3 5 7 9 11 13 15 17 19 43 45 47 49 51 Table 3.9 Pin # EJTAG Connector J5 Pin Assignments Signal Name Input/Output Description 1 TRST I TRST (test reset) is an active-low, asynchronous, reset signal that resets the EJTAG module independently of the processor logic. 3 TDI/DINT I PC trace mode off: Serial input data (TDI, test data input) is shifted into the JTAG Instruction register or Data register on the rising edge of the TCK clock, depending on the TAP (test access port) controller state. PC trace mode on: An active-LOW level on this pin (DINT, debug interrupt) is used as an interrupt to switch off PC trace mode. This signal is sampled at the TCK positive edge or asynchronous to TCK. 5 TDO/TPC O PC trace mode off: Serial output data (TDO) is shifted from the JTAG instruction of the data register to this pin on the falling edge of the test clock, TCK. When no data is shifted out, this pin is in a 3-state (off) condition. PC trace mode on: This pin provides a nonsequential program counter (TPC) on each DCLK clock. 7 TMS I TMS (test mode select) is decoded by the TAP controller to control test operation. The signal is sampled on the rising edge of TCK. 9 TCK I TCK (test clock) is the input clock used to shift data into or out of the instruction register or data register. External Interfaces 3-15 Table 3.9 Pin # EJTAG Connector J5 Pin Assignments (Cont.) Signal Name Input/Output Description 11 EJTAG_RESET I This signal is a board level reset signal. - PCST1_[2:0] During PC trace mode, the status of the CPU is encoded for every CPU cycle, using this group of three status bits. PCST1_[2:0] contains the most recent status bits. 13 PCST1_ 0 PC status trace set 1, bit 0. 15 PCST1_1 PC status trace set 1, bit 1. 17 PCST1_2 PC status trace set 1, bit 2. 19 DCLK O PC trace clock output. This clock qualifies the address and status information contained on the TPC and PCST pins. 21 TPC2 O PC trace out 2. This pin provides a nonsequential program counter (TPC) bit on each DCLK when M (where M is the number of address bits output for each DCLK) is greater than one. - PCST2_[2:0] O During PC trace mode, the status of the CPU is encoded for every CPU cycle, using this group of three status bits. When N (as in DCLK is 1/N processor clock) is greater than 1, PCST2_[2:0] contains the second most recent status bits. 23 PCST2_ 0 PC status trace set 2, bit 0. 25 PCST2_1 PC status trace set 2, bit 1. 27 PCST2_2 PC status trace set 2, bit 2. 29 TPC3 3-16 O O PC trace out 3. This pin provides a nonsequential program counter (TPC) bit on each DCLK, when M (where M is the number of address bits output for each DCLK) is greater than 2. Board Design and Layout Table 3.9 Pin # EJTAG Connector J5 Pin Assignments (Cont.) Signal Name Input/Output Description O During PC trace mode, the status of the CPU is encoded for every CPU cycle using this group of three status bits. When N (as in DCLK is 1/N processor clock) is greater than 2, PCST3_[2:0] contains the third most recent status bits. - PCST3_[2:0] 31 PCST3_ 0 PC status trace set 3, bit 0. 33 PCST3_1 PC status trace set 3, bit 1. 35 PCST3_2 PC status trace set 3, bit 2. 37 TPC4 O PC trace out 4. This pin provides a nonsequential program counter (TPC) on each DCLK, when M (where M is the number of address bits output for each DCLK) is greater than 2. - PCST4_[2:0] O During PC trace mode, the status of the CPU is encoded for every CPU cycle using this group of three status bits. When N (as in DCLK is 1/N processor clock) equals 4, PCST4_[2:0] contains the fourth most recent status bits. 39 PCST4_ 0 PC status trace set 4, bit 0. 41 PCST4_1 PC status trace set 4, bit 1. 43 PCST4_2 PC status trace set 4, bit 2. 45 TPC5 O PC trace out 5. This pin provides a nonsequential program counter (TPC) on each DCLK, when M (where M is the number of address bits output for each DCLK) equals 8. 47 TPC6 O PC trace out 6. This pin provides a nonsequential program counter (TPC) on each DCLK, when M (where M is the number of address bits output for each DCLK) equals 8. 49 TPC7 O PC trace out 7. This pin provides a nonsequential program counter (TPC) on each DCLK, when M (where M is the number of address bits output for each DCLK) equals 8. External Interfaces 3-17 Table 3.9 Pin # 51 EJTAG Connector J5 Pin Assignments (Cont.) Signal Name TPC8 Input/Output Description O PC trace out 8. This pin provides a nonsequential program counter (TPC) on each DCLK, when M (where M is the number of address bits output for each DCLK) equals 8. The following pins are ground: 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 3.2.8 PAL Programming Connector (J11) An 8-pin connector (J11) allows you to program the PAL (U42). Figure 3.10 shows the pin numbers for this connector and Table 3.10 lists the pin assignments. Figure 3.10 PAL Programming Connector Edge of Board 8 7 6 5 4 3 2 1 3-18 Board Design and Layout Table 3.10 PAL Programming Connector Pin Assignments Pins Signal Name Description 1 3.3 V 3.3 V Power Input 2 SDO Serial Data Out 3 SDI Serial Data In 4 ISP_EN Program Enable 5 Not Connected - 6 ISP_MODE In-System Programmable Mode 7 Ground Ground 8 ISP_SCLK PAL Program Clock Input 3.2.9 Power Supply Connector (J1) The BDMR4103 Evaluation Board has a standard 5 V, 4.0 A DC power supply connector (Figure 3.11), at location J1. Figure 3.11 Power Supply Connector Ground 5V LSI Logic supplies a switching AC adapter with a standard power inlet that lets you connect the board to AC power. The adapter takes inputs from 100-240 V AC, 50-60 Hz, and outputs +5 V DC at 4.0 amps. The red LED (D5) comes on when power is applied to the board. External Interfaces 3-19 3.3 Indicators This section describes the following indicators on the BDMR4103 board: * Power LED * Ethernet LEDs * Debug LED * 7-segment display Figure 3.12 shows the positions of these indicators on the board. Figure 3.12 Indicator Positions Ethernet LEDs (D1-D4) Yellow Debug LED (D6) 7-Segment Display (U35) Red Power LED (D5) U1 3.3.1 Power LED The red power LED (D5) comes on when power is applied to the board and stays on as long as power is being applied. 3-20 Board Design and Layout 3.3.2 Ethernet LEDs There are four LEDs on the edge of the evaluation board, to the left of the Ethernet connector, as shown in Figure 3.13. These indicators come on during Ethernet activity. Table 3.11 summarizes the Ethernet indicator functions Figure 3.13 Ethernet Indicator Positions Ethernet Indicators D1 D2 TX Green RX D3 D4 Ethernet 10BASE-T Connector LNK COL Yellow Green Edge of Evaluation Board Red Table 3.11 Ethernet Indicator Functions Indicator Location Function TX D1 Activated to indicate data is being transmitted. RX D2 Activated to indicate data is being received. LNK D3 Activated when Ethernet link integrity is good. COL D4 Activated when a collision occurs; that is, when two Ethernet devices are trying to transmit at the same time. (This is not the default function of this LED2 output from the AM79C970. The Ethernet controller initialization code should enable this function.) 3.3.3 Debug LED The yellow LED (D6) indicates the board is in debug mode. The LED lights when the DM bit in the CP0 debug register of the LR4103 is set. The DM bit is part of the EJTAG debugging system. Refer to Section 3.2.7.1, "Overview of EJTAG Functions," on page 3-13. Indicators 3-21 3.3.4 7-Segment Display The 7-segment display (U35) shown in Figure 3.14 is attached to a memory-mapped latch (register), at location U34. A read operation to the register returns the current value stored in the register and displayed on the segment display. A write operation to the register changes the value shown on the segment display. Table 3.12 lists the data bit assignments for each segment. When the related bit is cleared to `0,' the segment turns on, when the related bit is set to `1,' the segment turns off. The 7-segment display is at address 0x1E00 0020 in the system memory map and must be accessed with byte operations. Figure 3.14 7-Segment Display Example a f b g e c d Decimal Point a (D0) D0 = 1 D1 = 1 D2 = 0 D3 = 0 D4 = 0 D5 = 0 D6 = 0 D7 = 1 No decimal f (D5) e (D4) Segment off Segment on Table 3.12 3-22 7-Segment Display Settings Data Bit Segment D0 a D1 b D2 c D3 d D4 e D5 f D6 g D7 Decimal point Board Design and Layout b (D1) g (D6) c (D2) d (D3) (D7) Decimal Point 3.4 System Memory The BDMR4103 Evaluation Board accommodates a variety of memory devices, including SDRAM DIMM, SRAM (static RAM), and boot PROM. This section describes the different memory types and usage. Figure 3.1 on page 3-2 shows the position of the different memory modules on the board. 3.4.1 Synchronous DRAM Dual Inline Memory Module (SDRAM DIMM) The BDMR4103 Evaluation Board uses the 16 Mbyte SDRAM DIMM installed in the DIMM socket as the main system memory. The software LSI Logic provides initializes the FBM (FbusMACRO) to address the SDRAM DIMM at memory location 0x0000 0000. The FBM provides a glueless interface to the SDRAM DIMM. The LR4103 microprocessor supports other SDRAM DIMM configurations, as well as EDO DRAM. If you use DRAM other than the 16 Mbyte SDRAM DIMM, you must modify the FBM configuration code. If an external PCI master needs access to the SDRAM, the SDRAM clock must be set to 33 MHz. CPU to SDRAM accesses also occur at 33 MHz in this case. 3.4.2 Static RAM (SRAM) The evaluation board also contains 128 Kbytes of SRAM. The software LSI Logic provides initializes the FBM to address the SRAM at memory location 0x0E00 0000. The Ethernet controller uses the SRAM devices to hold its transmit and receive buffers. This memory is used by an external PCI interface to store temporary values without constraining the SDRAM clock to 33 MHz. You can also use the SRAM to store programs or data. 3.4.3 Boot EPROMs The BDMR4103 board is shipped with an AM29F080, 1 Mbyte, FLASH EPROM installed at location U12. The board also contains a DIP socket, at location U25, in which an optional 32-pin UV EPROM may be installed. The socket accommodates EPROMs up to 1 Mbyte, and the EPROM installed in this socket sits over the top of the FLASH EPROM at location U12. System Memory 3-23 The boot EPROMs are addressed at the MIPS boot vector address, which is 0x1FC0 0000. The order in which the boot EPROMs are addressed decides which EPROM acts as the boot EPROM. This is determined by jumper JP9. If JP9 is not installed, the AM29F080 at U12 is selected as the boot device. If JP9 is installed, the UV EPROM at U25 is selected as the boot device. The PAL at U42 maps the addresses of the EPROMs to select the boot and alternate device. Installing jumper JP8 inverts address bit 19 (A19), the most significant address bit, to the boot EPROM. This allows you to install two boot programs in the same 1 Mbyte boot EPROM. Each boot program must be less than 512 Kbytes. The addressing of the nonboot EPROM is not affected by jumper JP8. Table 3.13 lists boot EPROM addresses with JP8 installed and JP8 not installed. Table 3.13 Boot EPROM Addressing LR4103 Address Boot EPROM Address with JP8 Installed Boot EPROM Address with JP8 Not Installed 0x1FC0 0000 0x80000 0x00000 0x1FC0 8000 0x00000 0x80000 3.5 Memory Map Table 3.14 shows the BDMR4103 memory map. Note that the LR4103 microprocessor contains a programmable memory controller, known as the FBusMACRO, and that all address mappings shown in Table 3.14 can be altered by software. However, the addresses shown in Table 3.14 are those that LSI Logic uses for any software delivered with the BDMR4103 Evaluation Board. All memory and peripheral devices on the BDMR4103 board can be accessed in either user or kernel mode. In user mode, addresses in programs (virtual addresses) must be in kuseg, that is, in the range 0x0000 0000 to 0x7FFF FFFF. Kernel-mode programs typically use virtual addresses in kseg0 (0x8000 0000 to 0x9FFF FFFF) for cacheable locations, and kseg1 (0xA000 0000 to 0xBFFF FFFF) for noncacheable locations. 3-24 Board Design and Layout Some device selects are partially decoded off chip, using a general purpose chip select, gp[5:0], and an address offset. These selects are noted as gpx + offset. This method of decoding chip selects was used to leave some gp[x] selects free for expansion. Table 3.14 Physical Memory Map Controlling Chip Select Device Name 0x1FE0 0020 0x1FE0 0000 FAPI AM79C970A Ethernet Controller 0x1FD0 0000 0x1FDF FFFF gp0 + 0x10 0000 1 Mbyte EPROM (U25) or FLASH EPROM (U12) (EPROM type depends on setting of jumper JP9) 0x1FC0 0000 0x1FCF FFFF gp0 1 Mbyte EPROM (U25) or FLASH EPROM (U12) (EPROM type depends on setting of jumper JP9) Address Range Unused 0x1E00 003F 0x1E00 0030 gp4 + 0x30 RTC Interrupt Clear 0x1E00 002F 0x1E00 0020 gp4 + 0x20 7-Segment Display 0x1E00 001F 0x1E00 0000 gp4 + 0x0 16550 UART Unused 0x0E01 FFFF 0x0E00 0000 gp3 128 Kbyte SRAM Unused 0x00FF FFFF 0x0000 0000 gp2 Memory Map 16 Mbyte SDRAM 3-25 3.6 Two-Wire Serial Bus Peripheral Devices The BDMR4103 board contains three peripheral devices that use a standard two-wire serial bus. They are * A real-time clock (U37) * A 1 Kbyte EEPROM (U13) * A serial presence detect (SPD), which is on the DRAM DIMM The LR4103 microprocessor does not contain any dedicated two-wire serial bus support hardware, but instead communicates with the two-wire serial bus peripheral devices using the general purpose I/O pins, gpIO[1:0], which are driven by software. This section describes each of the peripheral devices. The supported devices use a bidirectional two-wire bus and data transmission protocol. Devices sending data onto the bus are described as transmitters and the devices receiving data are the receivers. The device that controls the message is the master and the devices controlled by the master are slaves. The slave devices must be controlled by a master device that generates a serial clock (SCL), controls bus access, and generates start and stop conditions. 3.6.1 Real-Time Clock (RTC) The BDMR4103 board is equipped with a DALLAS Semiconductor DS 1307 real-time clock at U37. This RTC provides a battery-backed clock and date function for the evaluation board. You can also program the RTC to supply a periodic interrupt to the LR4103. The falling edge of the SQW (Square Wave) output from the RTC is used to set a latch in the PLD (programmable logic device), which then asserts an interrupt (int5) to the LR4103 microprocessor. The interrupt is cleared by writing to location gp4 + 0x30 (0x1E00 0030). 3-26 Board Design and Layout Table 3.15 shows the address space for the RTC. Table 3.15 Real-Time Clock Addressing Device ID Address Read/Write 1101 0b000 1 = Read 0 = Write Table 3.16 shows the RTC registers. Table 3.16 Register Name RTC Registers Register Bits Address Range 7 6 5 4 3 2 1 0 Seconds 0x00 CH1 10 Seconds Seconds 00-59 Minutes 0x01 - 10 Minutes Minutes 00-59 Hours 0x02 - 12/24 10/AM or PM 10 Hour Hour Day 0x03 - - - - Date 0x04 - - 10 Date Month 0x05 - - - Year 0x06 10 Year Control 0x07 OUT2 RAM 0x08- 0x3F 56 8-bit registers - - 10 Month - 01-12 + AM/PM 00-23 Day 1-7 Date 01-28/29 01-30 01-31 Month 01-12 Year 00-99 SQWE3 - - RS1 RS0 - - 1. Clock Halt. When HIGH, the oscillator is disabled. When LOW, the oscillator is enabled. 2. Output control. This bit controls the output level of the SQW/OUT pin when the oscillator is disabled. If SQWE is LOW, the level on the SQW/OUT pin is HIGH if OUT is HIGH and LOW if OUT is LOW. 3. Square Wave Enable. When HIGH, enables oscillator output. Frequency is controlled by the Rate Select bits of the Control register (RS[1:0]). Available frequencies are 1 Hz (RS[1:0] = 00), 4.096 KHz (RS[1:0] = 01), 8.192 KHz (RS[1:0] = 10), and 32.768 KHz (RS[1:0] = 11). Two-Wire Serial Bus Peripheral Devices 3-27 For detailed information about the RTC, refer to the DALLAS Semiconductor datasheet for the DS1307/DS1308 64 X 8 Serial Real Time Clock. 3.6.2 EEPROM The BDMR4103 Evaluation Board is equipped with an NM24C08 1 Kbyte EEPROM that provides nonvolatile storage for board identification and configuration information. Table 3.17 shows the address of the EEPROM. Table 3.17 EEPROM Addressing Device ID Address Read/Write 1010 0b1xx 1 = Read 0 = Write 3.6.3 Serial Presence Detect (SPD) The 100-pin DIMM installed in the DIMM socket (J3) is equipped with an SPD EEPROM. The SPD EEPROM contains information about the types and configuration of the memory devices installed on the DIMM. You can use the information in the SPD EEPROM to configure the BDMR4103 board to operate with different types of DIMMs. Table 3.18 shows the address of the SPD EEPROM. 0 Table 3.18 3-28 SPD EEPROM Addressing Device ID Address Read/Write 1010 0b000 1 = Read 0 = Write Board Design and Layout 3.6.4 LR4103 Interrupts Table 3.19 shows how the interrupts from the evaluation board are connected to the LR4103 microprocessor. Table 3.19 BDMR4103 Interrupts Interrupt Number Source Cleared By 0 LR4103 DBE/FBDSTOP Writing to the DBE bit in SCR1 or the FBDSTOP bit in SCR2 of the LR4103. 1 LR4103 Timer 0 Writing to the bit in Timer 0. 2 SerialICE-1 Debugger Writing to the bit in S1. 3 16550 UART or LR4103 Timer 1 Clearing the source in the UART or writing to the bit in Timer 1 4 Ethernet Controller Clearing the source in the Ethernet Controller 5 Real-Time Clock Writing to gp4 + 0x30 (0x1E000030) 3.7 Device Registers This section describes the BDMR4103 Evaluation Board devices that have registers. They are: * PC16550D UART (U24) * Am79C970A Ethernet Controller (U19) The real-time clock (U37) also has registers, which are described in Table 3.16, on page 3-27. Device Registers 3-29 3.7.1 PC16550D UART Registers Table 3.20 lists the registers in the National Semiconductor UART at location U24. For detailed information about the UART, refer to the PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet from National Semiconductor Corporation. Table 3.20 UART Registers Address Register Name Access1 0x1E00 0000 gp4 + 0 Receiver Buffer Register RO 0x1E00 0000 gp4 + 0 Transmitter Holding Register WO 0x1E00 0001 gp4 + 1 Interrupt Enable Register R/W 0x1E00 0002 gp4 + 2 Interrupt Identification Register R/W 0x1E00 0002 gp4 + 2 FIFO Control Register WO 0x1E00 0003 gp4 + 3 Line Control Register R/W 0x1E00 0004 gp4 + 4 Modem Control Register R/W 0x1E00 0005 gp4 + 5 Line Status Register R/W 0x1E00 0006 gp4 + 6 Modem Status Register R/W 0x1E00 0007 gp4 + 7 Scratchpad Register R/W 0x1E00 0000 gp4 + 0 Divisor Latch Register (LS) R/W 0x1E00 0001 gp4 + 1 Divisor Latch Register (MS) R/W 1. RO = Read Only, R/W = Read/Write, WO = Write Only 3-30 Board Design and Layout 3.7.2 Am79C970A Ethernet Controller Table 3.21 describes the user registers in the Am79C970A Ethernet Controller. The PCI configuration registers are accessed with PCI configuration cycles. The Am79C970A Ethernet Controller responds to a configuration cycle with A16 = 1. Table 3.21 Ethernet Controller User Registers Access1 Register Name 0x1FE9 0000 RO PCI Vendor ID 0x1FE9 0002 RO PCI Device ID 0x1FE9 0004 R/W PCI Command 0x1FE9 0006 R/W PCI Status 0x1FE9 0008 RO PCI Revision ID 0x1FE9 0009 RO PCI Programming Interface 0x1FE9 000A RO PCI Subclass 0x1FE9 000B RO PCI Base-Class 0x1FE9 000C RO PCI Latency Timer 0x1FE9 000E RO PCI Header Type 0x1FE9 0010 R/W PCI I/O Base Address 0x1FE9 0014 R/W PCI Memory Mapped I/O Base Address 0x1FE9 0030 RO PCI Expansion ROM Base Address 0x1FE9 003C R/W PCI Interrupt Line 0x1FE9 003D RO PCI Interrupt Pin 0x1FE9 003E RO PCI MIN_GNT 0x1FE9 003F RO PCI MAX_LAT Address A[31:0] PCI Configuration Registers Device Registers 3-31 Table 3.21 Ethernet Controller User Registers (Cont.) Access1 Register Name 0x1FE0 0010 R/W Register Data Port 0x1FE0 0014 R/W Register Address Port 0x1FE0 0018 R/W Reset 0x1FE0 001C R/W BCR Data Port Address A[31:0] I/O Registers2 1. RO = Read Only, R/W = Read/Write 2. You should use PCI memory access from the FBM (FBusMACRO) to access the I/O registers. I/O device addresses are determined by the values programmed in the PCI configuration registers. Refer to the AM79C970A PCnet-PCI II Single-Chip Full Duplex Ethernet Control for PCI Local Bus Product datasheet from Advanced Micro Devices Inc., for more information about the Ethernet Controller registers. 3-32 Board Design and Layout Chapter 4 PAL Equations This chapter provides the code listing for the Programmable Array Logic (PAL) at location U42 on the BDMR4103 Evaluation Board. The pin numbers in the equations refer to the pins on the PAL package shipped on the BDMR4103 Evaluation Board. The PAL performs the following tasks: * Decodes and controls external addresses for ROM devices Both EPROMs on the evaluation board (the EPROM at U25 and the Flash EPROM at U12) connect to chip select GP0 and are selected by signal A20. Jumper JP9 selects the boot device and the addressing order of each EPROM. Additionally, jumper JP8 sets which boot program (regular or alternate) the selected EPROM uses. If JP8 is installed, A19 is inverted and the alternate boot program is selected. The setting of JP8 does not affect the nonboot ROM. Refer to Section 2.2, "Jumper Settings," for more information. * Decodes external addresses for devices connected to chip select GP4 Devices connected to GP4 include the UART, seven-segment display, and the real-time clock interrupt register. An address offset is required for these devices. Refer to Section 3.5, "Memory Map," for each device's offset value. * Combines reset signals The PAL gathers reset signals from other sources and combines them into a single board-level reset request. TinyRISC(R) BDMR4103 Evaluation Board User's Guide 4-1 * Sets interrupts from RTC The PAL sets a latch using the falling edge of the RTC's square ware output. The latch is used as an interrupt for the LR4103. Write to the latch to clear it. * Arbitrates the PCI bus The PAL allows multiple PCI bus masters to connect to the LR4103. You can only connect one PCI bus master to the LR4103. The code in this chapter was up to date at the time of publication. To verify that you have the latest code, you should contact LSI Logic Corporation. module core_logic title 'lr4103 core logic' U42 device 'ispLSI'; PLSI PROPERTY 'PART ispLSI2032v-100LT44'; "define pins and nodes pbclk pin 5; jmp0 jmp1 addr20 addr19 pin pin pin pin 2; 3; 37; 36; addr05 addr04 gp4 gp0 rdn we0 resetn pin pin pin pin pin pin pin 35; 31; 32; 33; 42; 44; 4; flash_sel dip_sel rom_a19 bd_sel uart_sel pin pin pin pin pin 23; 22; 21; 20; 26; read_display write_display 4-2 pin 12; pin 13; PAL Equations "CLK" "used to select between eprom/flash" "invert a19 to allow 2 boot "programs in 1 rom" "used to select between uart/display" "used to select between rtc_int/display" "uart/display select" "eprom/flash select" "buffered data select" "7-seg display rd "7-seg display wr "*** Arbiter signals ***" enet_req enet_gnt pin 14 ; pin 15 istype 'reg_D'; exp_req exp_gnt pin 9 ; pin 10 istype 'reg_D'; req gnt pin 25 istype 'reg_D';"system req" pin 24; "system gnt" sqw_out intp5 pin 16; pin 34; arb0 arb1 arb2 node node node si_reset ejtag_reset pb_reset pin 41; pin 38; pin 43; rtc_sync1 rtc_sync2 rtc_sync3 rtc_intff node node node node "square wave out from RTC "interrupt to uP istype 'buffer, reg_D'; istype 'buffer, reg_D'; istype 'buffer, reg_D'; istype istype istype istype 'reg_D'; 'reg_D'; 'reg_D'; 'reg_SR'; 4-3 PLSI PROPERTY 'OPENDRAIN pb_reset'; "************************************************************************** **" "constants and state definitions h,l,x,ck,z = 1,0,.X.,.C.,.Z.; ARBITER = [arb2,arb1,arb0]; IDLE_ENET IDLE_EXP REQ_ENET REQ_EXP GNT_ENET GNT_EXP = = = = = = [0,0,0]; [0,0,1]; [1,0,0]; [1,0,1]; [0,1,0]; [0,1,1]; RESET = !resetn; equations ARBITER.clk = pbclk; req.clk = pbclk; enet_gnt.clk= pbclk; exp_gnt.clk= pbclk; rtc_sync1.clk= pbclk; rtc_sync2.clk= pbclk; rtc_sync3.clk= pbclk; rtc_intff.clk= pbclk; !flash_sel = !gp0 & (( jp9 & !addr20 ) # (!jp9 & addr20)); !dip_sel = !gp0 & (( jp9 & addr20 ) # (!jp9 & !addr20)); rom_a19 = ((jp8 # addr20) & addr19) # ((!jp8 & !addr20) & !addr19); !bd_sel = ( !gp0 # !gp4); !uart_sel = (!gp4 & !addr05); !read_display = (!gp4 & addr05 & !addr04 & !rdn ); !write_display = (!gp4 & addr05 & !addr04 & !we0) # (RESET); 4-4 PAL Equations !pb_reset = !si_reset # !ejtag_reset; pb_reset.en = !si_reset # !ejtag_reset; rtc_sync1 := sqw_out; rtc_sync2 := rtc_sync1; rtc_sync3 := rtc_sync2; rtc_intff.s = ( !rtc_sync2 & rtc_sync3);"set ff on falling edge rtc_intff.r = ( !gp4 & addr05 & addr04 ) # (RESET); intp5 = rtc_intff; STATE_DIAGRAM ARBITER state IDLE_ENET: if (!enet_req) then REQ_ENET with req := 0; enet_gnt :=1; exp_gnt :=1; endwith; else if (!exp_req) then REQ_EXP with req := 0; enet_gnt :=1; exp_gnt :=1; endwith; else IDLE_ENET with req := 1; enet_gnt :=1; exp_gnt :=1; endwith; state IDLE_EXP: if (!exp_req) then REQ_EXP with req := 0; enet_gnt :=1; exp_gnt :=1; endwith; else if (!enet_req) then REQ_ENET with req := 0; enet_gnt :=1; exp_gnt :=1; endwith; 4-5 else IDLE_EXP with req := 1; enet_gnt :=1; exp_gnt :=1; endwith; state REQ_ENET: if ( !gnt & !enet_req) then GNT_ENET with req := 0; enet_gnt :=0; exp_gnt :=1; endwith; else if ( !enet_req )then REQ_ENET with req := 0; enet_gnt :=1; exp_gnt :=1; endwith; else IDLE_EXP with req := 1; enet_gnt :=1; exp_gnt :=1; endwith; state REQ_EXP: if ( !gnt & !exp_req) then GNT_EXP with req := 0; enet_gnt :=1; exp_gnt :=0; endwith; else if ( !exp_req )then REQ_ENET with req := 0; enet_gnt :=1; exp_gnt :=1; endwith; else IDLE_ENET with req := 1; enet_gnt :=1; exp_gnt :=1; endwith; 4-6 PAL Equations else if ( !exp_req )then REQ_ENET with req := 0; enet_gnt :=1; exp_gnt :=1; endwith; else IDLE_ENET with req := 1; enet_gnt :=1; exp_gnt :=1; endwith; state GNT_ENET: if (!gnt & !enet_req) then GNT_ENET with req := 0; enet_gnt :=0; exp_gnt :=1; endwith; else IDLE_EXP with req := 1; enet_gnt :=1; exp_gnt :=1; endwith; state GNT_EXP: if (!gnt & !exp_req) then GNT_EXP with req := 0; enet_gnt :=1; exp_gnt :=0; endwith; else IDLE_EXP with req := 1; enet_gnt :=1; exp_gnt :=1; endwith; end 4-7 4-8 PAL Equations Chapter 5 Schematics This section contains the following schematics for the BDMR4103 Evaluation Board: * Section 5.1, "Microprocessor and Clock Circuitry" * Section 5.2, "ROMs, SRAMs, and Address Latches" * Section Figure 5.3, "Ethernet and DRAM Circuitry" * Section 5.4, "Miscellaneous Circuitry and Connectors" * Expansion Connector and Boot Device Selection Circuitry * Section 5.6, "Power and Reset Circuitry" * Section 5.7, "EJTAG Connectors" The section also provides brief functional descriptions of key components. Designations in parentheses (J9, U6, and so on) refer to the location of the components on the board. TinyRISC(R) BDMR4103 Evaluation Board User's Guide 5-1 5.1 Microprocessor and Clock Circuitry The microprocessor and clock circuitry shown in Figure 5.1 performs the following functions: 5-2 * The LR4103 microprocessor (U1) provides a full-speed evaluation target. * A crystal (X1) provides the main clock for the LR4103 microprocessor. * The oscillator (U5) provides an alternate clock for the microprocessor. This clock is used when an input frequency other than 25 MHz is needed. * Jumpers JP1-6, and JP14 control various LR4103 functions. Refer to Section 2.2, "Jumper Settings" for further information about these jumpers. Schematics 1&6= ; 0+= & 3) &38B9''&25( 5 5 . 0 5 & 3) 5 . -3 -3 -3 -3 -3 -3 -3 % & (1* '$7( 5 . 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This device is shipped with the board. Jumper J9 determines whether this device or the EPROM at location U25 is the boot device. When JP9 is not installed, U12 is the boot PROM. You can store two boot programs in this EPROM, provided that neither program is larger than 512 Kbytes. Jumper J8 selects between any two programs installed. Refer to Section 2.2.7, "Boot Device Selection (JP9)," for more information about JP9, and to Section 2.2.6, "Alternate Boot Program Selection (JP8)," for more information about JP8. Refer to Section 3.4.3, "Boot EPROMs," for more information on this subject. * A socket (U25) houses an optional 1 Mbyte of EPROM. When installed, the EPROM sits over the top of Flash EPROM (U12). You can use U25 as an alternate boot device for the board by installing jumper JP9. You can store two boot programs in this EPROM, provided that neither program is larger than 512 Kbytes. Jumper J8 selects between any two programs installed. 5-4 * The SN74LCX16244 buffer (U22) buffers the lower order address bits FADDRP[11:0] for all devices except the DRAM DIMM. This buffering is provided to reduce the loading and trace length of these high-speed signals. * The LCX245 buffer (U30) buffers the data to and from the EPROMs, the 7-segment display, and the UART. This buffering is provided to reduce the loading and trace length of these high-speed signals. Schematics Figure 5.2 ROMs, SRAMs, and Address Latches $ % & ' )$''53>@ %$''53>@ 8 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 *3:(1 *35'1 2 , 2 , 2 , 2 , 2 , 2 , , , , , , 2 2 2 2 2 , 2 , 2 , 2 , 2 , 2 2( 2( 2( 2( %$''53 )$''53 %$''53 )$''53 %$''53 )$''53 %$''53 )$''53 %$''53 )$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %B:(1 %$''53 %B5'1 %$''53 %$''53 $ 5<%< )$''53 )$''53 $ )$''53 $ )$''53 $ $ '4 $ $ $ '4 '4 '4 $ '4 $ $ $ '4 '4 '4 %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ $ %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 $ $ 2( $ :( $ &( $ 5(6(7 %B5'1 %B:(1 *3:(1 *35'1 *3 5(6(71 8 )$''53 $ )$''53 $ )$''53 $ $ ' $ ' $ $ $ $ ' ' ' ' $ $ )$''53 $ ' ' )$'3 )$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 %$''53 $ %$''53 $ %$''53 $ *3:(1 :( *35'1 2( *3 &6 $ $ $ $ $ ' $ ' $ $ $ .[ )$''53 )$''53 $ .[ )$''53 8 $ 7623 )$''53 61/&; )$''53 )$''53 $ ' ' ' $ $ ' ' ' )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 $ $ $ :( 2( &6 )/$6+B6(/1 8 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$''53 % $ % $ % $ $ $ % % % $ $ % $ % * %'$7$ )$''53 %'$7$ )$''53 %'$7$ %$''53 %'$7$ %'$7$ %'$7$ %$''53 %$''53 %'$7$ %$''53 %'$7$ %$''53 ',5 %$''53 %$''53 %$''53 %$''53 %B5'1 %$''53 %$''53 %$''53 $ )$''53 $ )$''53 $ )$''53 $ $ '4 $ $ $ $ $ $ $ '4 '4 '4 '4 '4 '4 '4 %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ $ %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 %$''53 $ $ &( *3:(1 *35'1 $ $ 2( %B5'1 *3 8 )$''53 $ )$''53 $ )$''53 $ $ ' $ ' $ $ $ $ $ $ $ ' ' ' ' $ $ )$''53 $ ' ' )$'3 )$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 )$'3 %$''53 %$''53 %$''53 %$''53 *3:(1 :( *35'1 2( *3 &6 $ $ $ $ $ ' $ ' $ $ $ .[ )$''53 )$''53 .[ )$'3 )$''53 $ 65$0 )$''53 8 )$'3 $ & ',3 )$''53 $ $ ' ' ' ' $ 65$0 8 0[ (3520 520B$ )$''53 /&; ROMs, SRAMs, and Address Latches )$''53 8 ) 520B$ 65$0 0[ )ODVK 65$0 520B$ ' ' )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 $ $ $ :( 2( &6 $ %'B6(/1 ',3B6(/1 %'$7$>@ )$'3>@ *3>@*3,2>@*35'1*3:(1>@)$/(35(6(71 352-(&7 7,7/( 5206 65$0 (1* 6,=( -2+1 .$/'816., '$7( $ % & 3$*( ' RI & 5(9 & 5-5 5.3 Ethernet and DRAM Circuitry The Ethernet and DRAM circuitry shown in Figure 5.3 performs the following functions: * * Ethernet circuitry: - The Ethernet transformer (U10), in conjunction with the Ethernet controller, connects the evaluation board to an Ethernet LAN (local area network). - The AM79C970A Ethernet Controller (U19). The controller, in conjunction with the transformer, connects the evaluation board to an Ethernet LAN. - Refer to Section 3.7.2, "Am79C970A Ethernet Controller," for more information about the controller. - The RJ45 connector (J7) provides the Ethernet hardware connection. The 100-pin socket (J3) accommodates any standard 100-pin JEDEC DIMM. A 16 Mbytes SDRAM DIMM is supplied with the board. However, the socket will also accommodate EDO DRAM. Jumper JP17 is used to select between SDRAM and EDO devices. The memory installed in the socket at J3 provides the main system memory for the board. Refer to Section 3.2.2, "DIMM Connector (J3)," for further information about the connector, and to Section 3.4.1, "Synchronous DRAM Dual Inline Memory Module (SDRAM DIMM)," for further information about the DIMM. Refer to Section 2.2.14, "EDO/SDRAM Selection (JP17)," for information about the jumper settings. 5-6 Schematics Figure 5.3 Ethernet and DRAM Circuitry $ % & ' 3%&/.)5$0(1,5'<175'<167231'(96(/15(41*1716'21(3&%(1>@)$/(3 8 6'&61>@6''03>@6'&/.6':(16'5$616'&$61 8 - )$''53>@ 3,1 ',00 )$''53 -3 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 %$ %$$('2 $6'5 $ $ $ $ $ $ $ $ $ $ $ '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 ,173 (1(7B/2&. (1(7B3$5 (1(7B3(55 6$ 6$ 6$ &.( &.( &. &. (1(7B6(55 9 6'&/. :( 6':(1 6'5$61 6'&$61 5$6&6 5$6&6 5$6&6 5$6&6 6'&61 6'&61 &$6'40% &$6'40% &$6'40% &$6'40% 6''03 6''03 6''03 6''03 ,5'<1 '(96(/1 75'<1 67231 &%(1 &%(1 &%(1 &%(1 )5$0(1 5$6 &$6 2( '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 3%&/. )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 0+= 26& 287 /2&. 3$5 3(55 6(55 ;7$/ ;7$/ 7;3 7;' 8 &/. )5$0( ,5'< '(96(/ 75'< 6723 &%( &%( &%( &%( 7;' 7;3 5;' 5;' $' $' $' $' $' $' $' $' $' $' $' $' $' $' $' $' 7' 7' 5' 1& 1& 5' 1& 1& 38/6( 3( 9 9''% 9''% 9''% 9''% 3&QHW $0&$ 9'' 9'' 9'' 9'' 9'' 9'' $' $' $' $' $' $' $' $' $' $' $' $' $' $' $' $' &; 966 966 966 966 966 966 966 966 966 966 966 966 966% 966% 966% 966% 966% 966% 966% 966% 9 5 $966 $966 &; 8) $9'' $9'' $9'' $9'' *5((1 <(//2: & 9 8) ' /(' /(' /(' ' 9 ' ' 5 5 5 5 (WKHUQHW 6WDWXV 352-(&7 /1. 5; &2/ 7; 7,7/( '5$0(7+(51(7 (1* )$'3>@ '$7( $ % 5- - 8) 706 7'2 7', 7&. 6/((3 ,'6(/ /1.67 )$'3 1& /3) (1(7B5(41 567 *17 5(4 ,17$ /3) )$''53 6&/ 6'$ N Ethernet and DRAM Circuitry *3,2>@ (1(7B*171 5(' *3,2 5672871 *5((1 *3,2 & 6,=( -2+1 .$/'816., 3$*( ' RI & 5(9 & 5-7 5.4 Miscellaneous Circuitry and Connectors Figure 5.4 shows the following miscellaneous circuitry and connectors: 5-8 * Lattice ISPLSI2032 PLD (U42) (programmable logic device). * DS1307 real-time clock (U37). Refer to Section 3.6.1, "Real-Time Clock (RTC)," for further information. * An NM24C08 1 Kbyte EEPROM (U13). Refer to Section 3.6.2, "EEPROM," for further information. * 7-segment display (U35) and the associated data buffer (U34). Refer to Section 3.3.4, "7-Segment Display," for further information. * The PC16550 UART (universal asynchronous receiver transmitter) (U24) performs serial-to-parallel and parallel-to-serial data conversions on data received by and transferred from the board. For additional information about the UART, refer to the National Semiconductor datasheet, PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs. * The MAX3245 (U14) RS232 transceiver provides signal voltage level translation. * The SerialICE-1 header (J8) allows you to debug the board using SerialICE-1 inputs. Refer to Section 3.2.5, "SerialICE-1 Connector (J8)," for further information. * The RS232 SerialICE-1 port (J9) allows you to debug the board using SerialICE-1 inputs. Refer to Section 3.2.4, "RS-232 Serial Connector for SerialICE-1 Debug Interface(J9)," for further information. * The RS232 serial port (J10) allows you to connect serial devices to the board. Refer to Section 3.2.3, "Serial Port Connector (J10)," for further information. * The header (J11) is used to program the PAL (U42). Refer to Section 3.2.8, "PAL Programming Connector (J11)," for further information. * Jumpers JP8 (boot program selection), JP9 (boot device selection), JP15 (SerialICE-1 input data selection), and JP16 (SerialICE-1 clock selection). Refer to Section 2.2, "Jumper Settings," for further information about these jumpers. * The 1.8432 MHz oscillator (U6), provides an alternate clock source for the SerialICE-1 debugger. Schematics Figure 5.4 Miscellaneous Circuitry and Connectors $ % & ' %$''53>@ *3,2>@ 8 *3,2 *3,2 % - 9B/,7+,80 $ 6'$ $ 9 6&/ 6'$ ; 9%$7 64:287 ; .+= -03 -3 -03 -3 3%&/. )$''53 )$''53 %$''53 %$''53 *3 *3 %B5'1 %B:(1 5672871 *171 (1(7B5(41 (;3B5(41 6,B5(6(7 (-7$*B5(6(7 %$''53 &/. -3 ,QYHUW 520 $ -3 %227 )520 ',3 64:287 520B$ )/$6+B6(/1 ',3B6(/1 %'B6(/1 5(41 (1(7B*171 (;3B*171 3%B5(6(7 ,173 :5,7(B',631 5($'B',631 8$57B6(/1 ,173 %B:(1 %B5'1 5(6(73 8$57B6(/1 %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ &6 ,17537 :5 5' 05 ' ' ' ' ' ' ' ' ;287 6', ,63B(1 7'2 7', ,63(1 ,63B02'( 706 ,63B6&/. 7&. &; 8) '75 '65 '&' 5, 287 287 '',6 5;5'< 7;5'< 7,1 7,1 5287 5287 7287 7287 5,1 5,1 5,1 5,1 5287 5287 7287 5,1 & & & & & 8) & 9 %$8'287 5&/. &6 &6 5' :5 $'6 9 9 ,19$/,' )25&(21 )25&(2)) 6HULDO 3RUW 6HULDO ,FH 5$B0$/( 7,1 5287 9 & 5, &76 576 '65 9&& *1' '&' 5; 7; '75 6* & 8) & 8) ; 8) 5 & & 0 3) 3) -3 8 %'$7$ %'$7$ %'$7$ %'$7$ %'$7$ /&; ,&(&/.3 2(%$ $ $ $ $ $ $ $ $ /($% % % % % % % % % /(%$ &(%$ 2($% &($% 8 * D ) E ( I ' J & H F % G $ '3 $1 $1 . 8 &211B5;3 /&; 5 9 8 . /&; 5 . )&7 %'$7$ 6,B5(6(7 8 - /&; 8 9 8 0+= %'$7$ ,&(5;3 -3 1& %'$7$ 8 287 - 5, &76 576 '65 '&' 5; 7; '75 6* 5$B0$/( 8) 0+= 26& ;,1 5 9 6'2 576 6287 6,1 &76 3& . - 0$; 8 $ $ $ ; 8 /$77,&( LVS/6,Y Miscellaneous Circuitry and Connectors '6 10& 6&/ $ %$''53 8 8 %$''53 5 . 5 . /&; ,&(7;3 ,&(7;3 8 9 352-(&7 %'$7$>@ 7,7/( 6(5,$/ 32576(5,$/ ,&(',63/$< (1* '$7( $ % & 6,=( -2+1 .$/'816., 3$*( ' RI & 5(9 & 5-9 5.5 Expansion Connector and Boot Device Selection Circuitry The circuitry shown in Figure 5.5 performs the following functions: 5-10 * A 150-pin expansion connector (J2) allows you to expand design and debugging capabilities to include external logic. Refer to Section 3.2.1, "Expansion Connector (J2)," for further information. * At reset, the 74LCX541 (U32) provides the boot device chip select number and the boot device width to the LR4103. The buffer is enabled with RSTOUTN. Schematics Figure 5.5 Expansion Connector and Boot Device Selection Circuitry $ % & ' 6'&61>@6''03>@6'&/.6':(16'5$616'&$61 3%&/.)5$0(1,5'<175'<167231'(96(/15(41*1716'21(3&%(1>@)$/(3 )$''53>@ )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 6':(1 6''03 6'5$61 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 6'&/. )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$'3 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 6'&$61 6''03 6'&61 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 )$''53 6'&61 6''03 6''03 )5$0(1 ,5'<1 75'<1 67231 '(96(/1 3%&/. &%(1 &%(1 &%(1 &%(1 6'21(3 )$/(3 (;3B*171 (;3B5(41 B',1 9 ,173 ,173 ,173 ,173 ,173 ,173 7B2871 7B2871 %227&)* %227&)* %227&)* &:$,73 5672871 5(6(71 *3 *3 *3 *3 *3 *3 *3:(1 *3:(1 *3:(1 *3:(1 *35'1 *3,2 *3,2 *3,2 *3,2 9 B',1 - 8 %227&)* $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ %227&)* %227&)* $ < $ < $ < $ $ $ < < < < $ < $ * &%(1 &%(1 &%(1 * 5672871 9 8 8 *3 *3 *3 *3 *3 *3 *3,2 *3,2 *3,2 *3,2 *3:(1 *3:(1 *3:(1 *3:(1 *35'1 )5$0(1 ,5'<1 75'<1 67231 '(96(/1 (1(7B/2&. (1(7B3$5 (1(7B3(55 (1(7B6(55 (1(7B5(41 (;3B5(41 64:287 8 ,173 ,173 ,173 ,173 ,173 ,173 %227&)* %227&)* %227&)* . )$'3 % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % . )$''53 - & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & B',1 %227&)*>@ *3>@*3,2>@*35'1*3:(1>@5(6(715672871&:$,73 ,173>@7>@B2871 352-(&7 *3,2 Expansion Connector and Boot Device Selection Circuitry )$'3 - . )$'3>@ /&; -3 7,7/( (;3$16,21 &211(&725 (1* 6,=( -2+1 .$/'816., '$7( $ % & 3$*( ' RI & 5(9 & 5-11 5.6 Power and Reset Circuitry The power and reset circuitry shown in Figure 5.6 performs the following functions: 5-12 * The power connector (J1) supplies the board with DC power by means of the switching AC adapter. Refer to Section 3.2.9, "Power Supply Connector (J1)," for further information. * The red Power LED (D5) comes on when power is applied to the board, and it stays on while power is being applied. * The MAX708 device (U33) generates the reset signal for the board. * The voltage regulator (U16) provides the VDD core voltage. The voltage regulator (U36) provides the 3.3 V power supply for the board. * Heatsink HS1 provides the heatsink for the regulator at U36, and HS2 provides the heatsink for the regulator at U16. * Test points TP1, TP2, TP3, TP4, TP5, and TP6 provide grounding for an oscilloscope during testing. * 0.1 F decoupling capacitors. Schematics Figure 5.6 Power and Reset Circuitry $ % & ' +6 +($76,1. 8 /7&7DGM ,1 287 $'- & B -3 '2B127B/2$' 5 8) 5 &; 23(1 8) & & 8) 8) +6 +($76,1. /7&7 8) 8) ,1 *1' 287 & &; 8) 8) ' 32:(5 /(' 3%B5(6(7 8) 5 & & &; 9 &38B9'',2 -3 & 8) & & &; 8) 8) 8) & 8) 8 0$; 9&& 3), 05 6 -3 - 9 8 9 5(' Power and Reset Circuitry 5 B &38B9''&25( -3 *1' 3)2 5(6(7 5(6(71 8 $ 5(6(7 5(6(73 % 9B5(6(71 &%7' 8 $ 9 *HQHUDWLRQ FLUFXLW % &%7' 73 73 73 73 73 73 9 &; &; &; &; &; &; &; &; 8) 8) 8) 8) 8) 8) 8) 8) 9 &; &; &; 8) 8) 8) &; 8) &; &; &; &; &; &; &; &; &; &; &; &; &; &; &; &; &; &; &; 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) 8) &38B9'',2 &38B9''&25( &; &; &; &; &; &; &; &; 8) 8) 8) 8) 8) 8) 8) 8) 352-(&7 &; &; &; &; &; &; &; &; 8) 8) 8) 8) 8) 8) 8) 8) 7,7/( 32:(55(6(7 (1* '$7( $ % & 6,=( -2+1 .$/'816., 3$*( ' RI & 5(9 & 5-13 5.7 EJTAG Connectors The EJTAG connectors shown in Figure 5.7 performs the following functions: * EJTAG connectors and debug indicator: - EJTAG connector (J4) provides basic EJTAG debugging capabilities, including break and run control. Refer to Section 3.2.7.2, "EJTAG Connector (J4)," for additional information. - EJTAG connector (J5) provides the same EJTAG debugging capabilities as J4. In addition, it supports PC trace. Refer to Section 3.2.7.3, "EJTAG Connector (J5)," for further information. - The EJTAG connector (J6) is used only for factory testing. - The yellow LED (D6) comes on when the LR4103 is in debug mode. Refer to Section 3.2.7.1, "Overview of EJTAG Functions," for additional information about EJTAG functions. For detailed EJTAG information, refer to the EJTAG specification published by Philips Semiconductors and MIPS licensees. 5-14 Schematics Figure 5.7 EJTAG Connectors $ % & ' 3,75673,7&.3,7063,7',B',173,7'2B73&3,5673,%5($.37'&/.3775,*,13775,*287 5B%8)B7'2 7',',17 (-7$*B5(6(7 8 9&& *1' 1&6= 8 73& 3&67B 3&67B 3&67B 73& 3&67B 3&67B 3&67B 5B7'273& 5B3&67B 5B3&67B 5B3&67B 5B'&/. 5B73& 5B3&67B 5B3&67B 5B3&67B 5B73& 5B3&67B 5B3&67B 5B3&67B 5B73& 5B3&67B 5B3&67B 5B3&67B 5B73& 5B73& 5B73& 5B73& 8 73& 3&67B 3&67B 3&67B 73& 73& 73& 73& 7',',17 7567 7',',17 5B7'273& 706 7&. (-7$*B5(6(7 5B3&67B 5B3&67B 5B3&67B 5B'&/. 5B73& 5B3&67B 5B3&67B 5B3&67B 5B73& 5B3&67B 5B3&67B 5B3&67B 5B73& 5B3&67B 5B3&67B 5B3&67B 5B73& 5B73& 5B73& 5B73& - 23(1 5 23(1 5 23(1 8 23(1 3,7'2B73& 3,%5($. 3775,*,1 3775,*287 ' 8 3,7567 37'&/. /&; 7567 5 . 352-(&7 7,7/( (1* '$7( $ 9 3,7',B',17 3,706 3,7&. 3,567 5 '(%8*03 '2B127B/2$' - 5B3,7567 5B3,7',B',17 3,7'2B73& 5B3,706 5B3,7&. 5B3,567 3,%5($. 3775,*,1 3775,*287 37'&/. 9 . -03 -03 3,7567 3,7',B',17 3,706 3,7&. 3,567 <(//2: 706 7&. 8 9 8 (-7$*B5(6(7 9 7567 7'273& 3&67B 3&67B 3&67B '&/. 8 '(%8* $&7,9( 7'273& '&/.7'273&3&67>@B>@73&>@7567 7',',17 7067&.(-7$*B5(6(7'(%8*03 EJTAG Connectors 7&. 706 9 - % & (-7$* 6,=( -2+1 .$/'816., 3$*( ' RI & 5(9 & 5-15 5-16 Schematics Chapter 6 Bill of Materials Table 6.1 lists the bill of materials for the BDMR4103 Evaluation Board. The reference numbers correspond to those used in the schematics. The board contains a total of 190 components. Note that, since different manufacturers categorize their products in different ways, some of the categories shown in Table 6.1 may not be relevant for all products. Key to packaging information: * The numbers shown in the packaging information frequently refer to the number of pins on the package. For example, 14PDIP indicates a 14-pin dual inline package, 44 PLCC indicates a 44-pin plastic leaded chip carrier, and so forth. In other cases, the number refers to a standard packaging type, such as capacitor package 1206. * In the case of onboard devices, the numbers (C1, J1, and so forth) represent board locations. Items designated ACC, are removable accessory modules, such as the SDRAM DIMM, that are supplied with the board. TinyRISC(R) BDMR4103 Evaluation Board User's Guide 6-1 6-2 Table 6.1 BDMR4103 Bill of Materials Qty. Reference Designator(s) Bill of Materials Device Name Package Value/Type Manufacturer Manufacturer's Part Number 1 ACC1 16 Mbytes SDRAM DIMM 100-pin DIMM - Micron MT2LSDT432UG-10 1 ACC2 Power Supply - 5V@4A Phihong PSA-30U050 1 B1 Lithium Battery Battery 3V Panasonic BR1225-1HC 3 C1, C2, C11 Capacitors 0805 20 pF - - 1 C3 Capacitor 1206 0.47 F - - 10 C4, C5, C13- 16, C18-21 Tantalum Capacitors - 22 F - - 3 C6, C8, C9 1206 Capacitors 1206 0.33 F - - 2 C7, C10 0805 Capacitors 0805 0.047 F - - 1 C12 0805 Capacitor 0805 47 pF - - 1 C17 Tantalum Capacitor - 10 F - - 52 CX1-49, CX60-62, Capacitors 0805 0.1 F - - 2 CX58, CX59 Capacitors 0805 0.01 F - - 2 D1, D2 Small LEDs 1206 Green Hewlett Packard HSMG-C650 2 D3, D6 Small LEDs 1206 Yellow HSMY-C650 2 D4, D5 Small LEDs 1206 Red HSMR-C650 (Sheet 1 of 6) Table 6.1 BDMR4103 Bill of Materials (Cont.) Qty. Reference Designator(s) Device Name Package Value/Type Manufacturer Manufacturer's Part Number 2 HS1, HS2 Heatsinks TO-220-HS - AAVID 577002B00000 1 J1 Power Plug R/A 2.1 mm - Switchcraft RAPC722 1 J2 150-Pin DIN 41612 Connector Typec R/A Pins Amp 650907-5 1 J3 100-Pin DIMM Socket 100-Pin DIMM - Molex 71251-5101 1 J4 16-Pin Header 16-Pin Header, 8 x 2, 0.1 x 0.1 - - - 1 J5 52-Pin High-Speed Header 52-Pin Header, 0.05 x 0.05 - Mill-Max 852-10-052-30-001 1 J7 RJ45 Connector - - - - 1 J8 10-Pin Header 10-Pin Header, 0.1 x 0.1 - - - 2 J9, J10 9-Pin D Subconnector MIL-C-24308 R/A Male - - 1 J11 8 x 1 Header 8-Pin .025 Square 1x8 - - - 14 JP1-12, JP18 2-Pin Headers for Jumpers 2-Pin .025 Square - - - 4 JP14-17 3-Pin Headers for Jumpers 3-Pin .025 Square - - - 1 R1 Resistor 0805 10 M - - 2 R2, R11 Resistors 0805 1.5 k - - 6-3 (Sheet 2 of 6) 6-4 Table 6.1 BDMR4103 Bill of Materials (Cont.) Bill of Materials Qty. Reference Designator(s) Device Name Package Value/Type Manufacturer Manufacturer's Part Number 1 R3 Resistor 0805 20 - - 5 R4-7, R17 Resistors 0805 130 - - 9 R8-10, R20-23, R26 Resistors 0805 10 k - - 1 R12 Resistor 0805 1 M - - 1 R13 Resistor 0805 330 - - 2 R14 Resistor 0805 54.9 1% - - 1 R15 Resistor 0805 124 1% - - 1 R18 Resistor 0805 4.3 - - 1 R19, R28 Resistors 0805 0.0 - - 1 S1 SPST Switch 2-Pin DIP Switch - Alcoswitch TP11CGPC0 6 TP1-6 Test Points .025 Square Pin - - - 1 U1 LR4103 Microprocessor 256 PBGA - LSI Logic - 6 U2-3, U18, U20, U38 16-Pin 15-Resistor Arrays 16-Pin QSOP 4.7 k Bourns 2QSP16-TJ2-XXX 1 U5 Oscillator 14-Pin DIP Socket - - - 1 U6 Oscillator 14-Pin DIP 1.8432 MHz - - (Sheet 3 of 6) Table 6.1 BDMR4103 Bill of Materials (Cont.) Qty. Reference Designator(s) Device Name Package Value/Type Manufacturer Manufacturer's Part Number 4 U7-9 16-Pin 8-Resistor Arrays 16-Pin QSOP 33 Bourns 2QSP16-TJ1-XXX 1 U10 Ethernet Transformer 10BASE-T Module 16-Pin Small - Pulse PE-68025 1 U11 74LCX14 14-Pin SOIC - National Semiconductor 74LCX14M 1 U12 1 Mbyte FLASH ROM 40-Pin TSOP - Advanced Micro Devices AM29F080-90EC 1 U13 1 Kbyte EEPROM IIC 8-Pin SOIC - Fairchild Semiconductor NS24C08M8 1 U14 Max 3245 RS232 transceiver 28-Pin SSOP - Maxim MAX3245CAI 1 U15 Small 3.3 V Oscillator 4-Pin SOJ 20 MHz - - 1 U16 Linear Adjustable Voltage Regulator TO-220 - Linear LT1084CT 1 U17 Small 16-Pin 8-Resistor Array 16-Pin QSOP 1 k Bourns 2QSP16-TJ1-XXX 1 U19 PCNet PCI Device (Ethernet Controller) 144-Pin TQFP - Advanced Micro Devices AM79C970AVC 1 U22 74LCX16244 (Address Buffer) 48-Pin TSSOP - National Semiconductor 74LCX16244MTD 1 U24 UART 44-Pin PLCC - National Semiconductor PC16550DV 6-5 (Sheet 4 of 6) 6-6 Table 6.1 BDMR4103 Bill of Materials (Cont.) Bill of Materials Qty. Reference Designator(s) Device Name Package Value/Type Manufacturer Manufacturer's Part Number 1 U25 32-Pin DIP Socket 32-Pin DIP - - - 4 U26-29 32 x 8 SRAM 28SOJ300MIL - IDT IDT71V254SA12Y 1 U30 74LCX245 20-Pin SOIC - National Semiconductor 74LCX245WM 2 U31, U39 Tiny UHS and Gate SOT23-5 - Fairchild NC7SZ08M5 1 U32 74LCX541 20-Pin SOIC - National Semiconductor 74LCX541WM 1 U33 Max 708 8-Pin SOIC - Maxim MAX708CSA 1 U34 74FCT543 24-Pin QSOP - Quality Semiconductor QS74FCT543ATQ 1 U35 7-Segment Display 10-Pin DIP - Hewlett Packard HDSP-F101 1 U36 3.3 V Linear Regulator TO-220 - Linear LT1084CT-3.3 1 U37 IIC Real-Time Clock 8-Pin SOIC - Dallas Semiconductor DS1307Z 1 U41 Dual FET Bus Switch 8-Pin SOIC - Texas Instruments SN74CBTD3306D 1 U42 CPLD ISP (PAL) 44-Pin TQFP - Lattice Semiconductor ISPLSI2032V-100LT44 1 X1 Crystal HC 28.75 MHz - - (Sheet 5 of 6) Table 6.1 BDMR4103 Bill of Materials (Cont.) Qty. Reference Designator(s) Device Name Package Value/Type Manufacturer Manufacturer's Part Number 1 X2 Crystal HC 14.7456 MHz - - 1 X3 Crystal Cylinder 32.768 KHz - - (Sheet 6 of 6) 6-7 6-8 Bill of Materials Customer Feedback We would appreciate your feedback on this document. Please copy the following page, add your comments, and fax it to us at the number shown. If appropriate, please also fax copies of any marked-up pages from this document. Important: Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. Reader's Comments Fax your comments to: LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: TinyRISC(R) BDMR4103 Evaluation Board User's Guide. Place a check mark in the appropriate blank for each category. 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Tel: 801.974.9953 Sales Offices and Design Resource Centers LSI Logic Corporation Corporate Headquarters 1551 McCarthy Blvd Milpitas CA 95035 Tel: 408.433.8000 Fax: 408.433.8989 Fort Collins 2001 Danfield Court Fort Collins, CO 80525 Tel: 970.223.5100 Fax: 970.206.5549 New Jersey Red Bank 125 Half Mile Road Suite 200 Red Bank, NJ 07701 Tel: 732.933.2656 Fax: 732.933.2643 NORTH AMERICA Florida Boca Raton Cherry Hill - Mint Technology California Irvine 2255 Glades Road Suite 324A Boca Raton, FL 33431 Tel: 561.989.3236 Fax: 561.989.3237 Tel: 856.489.5530 Fax: 856.489.5531 Georgia Alpharetta New York Fairport 2475 North Winds Parkway Suite 200 Alpharetta, GA 30004 550 Willowbrook Office Park Fairport, NY 14450 18301 Von Karman Ave Suite 900 Irvine, CA 92612 Tel: 949.809.4600 Fax: 949.809.4444 Pleasanton Design Center 5050 Hopyard Road, 3rd Floor Suite 300 Pleasanton, CA 94588 Tel: 925.730.8800 Fax: 925.730.8700 Tel: 770.753.6146 Fax: 770.753.6147 Illinois Oakbrook Terrace 215 Longstone Drive Cherry Hill, NJ 08003 Tel: 716.218.0020 Fax: 716.218.9010 North Carolina Raleigh Phase II 4601 Six Forks Road Suite 528 Raleigh, NC 27609 Tel: 630.954.2234 Fax: 630.954.2235 Tel: 919.785.4520 Fax: 919.783.8909 Kentucky Bowling Green Oregon Beaverton 1551 McCarthy Blvd Sales Office M/S C-500 Milpitas, CA 95035 1262 Chestnut Street Bowling Green, KY 42101 15455 NW Greenbrier Parkway Suite 235 Beaverton, OR 97006 Fax: 408.954.3353 Maryland Bethesda 7585 Ronson Road Suite 100 San Diego, CA 92111 Tel: 858.467.6981 Fax: 858.496.0548 Silicon Valley Tel: 408.433.8000 Design Center M/S C-410 Tel: 408.433.8000 Fax: 408.433.7695 Wireless Design Center 11452 El Camino Real Suite 210 San Diego, CA 92130 Tel: 858.350.5560 Fax: 858.350.0171 Colorado Boulder 4940 Pearl East Circle Suite 201 Boulder, CO 80301 Tel: 303.447.3800 Fax: 303.541.0641 Colorado Springs Tel: 270.793.0010 Fax: 270.793.0040 6903 Rockledge Drive Suite 230 Bethesda, MD 20817 Tel: 301.897.5800 Fax: 301.897.8389 Massachusetts Waltham 200 West Street Waltham, MA 02451 Tel: 781.890.0180 Fax: 781.890.6158 Tel: 503.645.0589 Fax: 503.645.6612 Texas Austin 9020 Capital of TX Highway North Building 1 Suite 150 Austin, TX 78759 Tel: 512.388.7294 Fax: 512.388.4171 Plano 500 North Central Expressway Suite 440 Plano, TX 75074 Tel: 972.244.5000 Burlington - Mint Technology Fax: 972.244.5001 77 South Bedford Street Burlington, MA 01803 Houston Tel: 781.685.3800 Fax: 781.685.3801 20405 State Highway 249 Suite 450 Houston, TX 77070 4420 Arrowswest Drive Colorado Springs, CO 80907 Minnesota Minneapolis Tel: 719.533.7000 Fax: 719.533.7020 8300 Norman Center Drive Suite 730 Minneapolis, MN 55437 Tel: 612.921.8300 Fax: 612.921.8399 260 Hearst Way Suite 400 Kanata, ON K2L 3H1 Tel: 613.592.1263 Fax: 613.592.3253 Two Mid American Plaza Suite 800 Oakbrook Terrace, IL 60181 San Diego Canada Ontario Ottawa Tel: 281.379.7800 Fax: 281.379.7818 INTERNATIONAL France Paris LSI Logic S.A. Immeuble Europa 53 bis Avenue de l'Europe B.P. 139 78148 Velizy-Villacoublay Cedex, Paris Tel: 33.1.34.63.13.13 Fax: 33.1.34.63.13.19 Germany Munich LSI Logic GmbH Orleansstrasse 4 81669 Munich Tel: 49.89.4.58.33.0 Fax: 49.89.4.58.33.108 Stuttgart Mittlerer Pfad 4 D-70499 Stuttgart Tel: 49.711.13.96.90 Fax: 49.711.86.61.428 Italy Milan LSI Logic S.P.A. Centro Direzionale Colleoni Palazzo Orione Ingresso 1 20041 Agrate Brianza, Milano Tel: 39.039.687371 Fax: 39.039.6057867 Japan Tokyo LSI Logic K.K. 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Beijing Representative Office Room 708 Canway Building 66 Nan Li Shi Lu Xicheng District Beijing 100045, China Tel: 86.10.6804.2534 to 38 Fax: 86.10.6804.2521 France Rungis Cedex Azzurri Technology France 22 Rue Saarinen Sillic 274 94578 Rungis Cedex Tel: 33.1.41806310 Fax: 33.1.41730340 Germany Haar EBV Elektronik Tel: 852.2428.0008 Fax: 852.2401.2105 Serial System (HK) Ltd 2301 Nanyang Plaza 57 Hung To Road, Kwun Tong Kowloon, Hong Kong Tel: 852.2995.7538 Fax: 852.2950.0386 India Bangalore Spike Technologies India Private Ltd 951, Vijayalakshmi Complex, 2nd Floor, 24th Main, J P Nagar II Phase, Bangalore, India 560078 Tel: 91.80.664.5530 Fax: 91.80.664.9748 Macnica Corporation Tel: 44.1628.826826 Fax: 44.1628.829730 Hakusan High-Tech Park 1-22-2 Hadusan, Midori-Ku, Yokohama-City, 226-8505 Milton Keynes Ingram Micro (UK) Ltd Tel: 81.45.939.6140 Fax: 81.45.939.6141 The Netherlands Eindhoven Acal Nederland b.v. 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Tel: 886.2.2788.3656 Fax: 886.2.2788.3568 Prospect Technology Corporation, Ltd 4Fl., No. 34, Chu Luen Street Taipei, Taiwan, R.O.C. Tel: 886.2.2721.9533 Fax: 886.2.2773.3756 Marubeni Solutions 1-26-20 Higashi Shibuya-ku, Tokyo 150-0001 Garamonde Drive Wymbush Milton Keynes Buckinghamshire MK8 8DF Beatrix de Rijkweg 8 5657 EG Eindhoven Taiwan Taipei Avnet-Mercuries Corporation, Ltd Tel: 81.3.3264.0326 Fax: 81.3.3261.3984 Tel: 49.2957.79.1692 Fax: 49.2957.79.9341 16 Grove Park Business Estate Waltham Road White Waltham Maidenhead, Berkshire SL6 3LW 11 Rozanis Street P.O. Box 39300 Tel Aviv 61392 Tel: 972.3.6458777 Fax: 972.3.6458666 United Kingdom Maidenhead Azzurri Technology Ltd Tel: 81.45.474.9037 Fax: 81.45.474.9065 Tel: 41.32.3743232 Fax: 41.32.3743233 Sogo Kojimachi No.3 Bldg 1-6 Kojimachi Chiyoda-ku, Tokyo 102-8730 Graf-Zepplin-Str 14 D-33181 Wuennenberg-Haaren 2-15-10 Shin Yokohama Kohoku-ku Yokohama-City, 222-8580 Israel Tel Aviv Eastronics Ltd Hans-Pinsel Str. 4 D-85540 Haar Wuennenberg-Haaren Peacock AG Yokohama-City Innotech Wintech Microeletronics Co., Ltd 7F., No. 34, Sec. 3, Pateh Road Taipei, Taiwan, R.O.C. Tel: 886.2.2579.5858 Fax: 886.2.2570.3123 Tel: 44.1793.849933 Fax: 44.1793.859555 Sales Offices with Design Resource Centers