BDMR4103 - LSI Logic Corporation

Order Number C14071

TinyRISC® BDMR4103

Ev aluation Board

User’s Guide

July 2000

This document contains proprietary information of LSI Logic Corporation. The

information contained herein is not to be used by or disclosed to third parties

without the express written permission of an ofﬁcer of LSI Logic Corporation.

Document DB15-000161-00, First Edition (July 2000). This document describes

revision A of the LSI Logic Corporation TinyRISC®BDMR4103 Evaluation Board

User’s Guide and will remain the ofﬁcial reference source for all

revisions/releases of this product until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products

described herein at any time without notice. LSI Logic does not assume any

responsibility or liability arising out of the application or use of any product

described herein, except as expressly agreed to in writing by LSI Logic; nor does

the purchase or use of a product from LSI Logic convey a license under any

patent rights, copyrights, trademark rights, or any other of the intellectual

property rights of LSI Logic or third parties.

TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, TinyRISC, and MiniRISC are registered trademarks

and SerialICE is a trademark of LSI Logic Corporation. All other brand and

product names may be trademarks of their respective companies.

Preface iii

Preface

This book is the primary reference and user’s guide for the TinyRISC®

BDMR4103 Evaluation Board. This guide describes the basic features of

the evaluation board, including hookup procedures and system

conﬁguration. For additional information that relates to the board and its

components, refer to “Related Publications,” on page iv.

Audience

This document assumes that you are familiar with microprocessors and

related support devices. The people who beneﬁt from this book are:

•Engineers and managers who are evaluating the LR4103

microprocessor for possible use in a system

•Engineers who are designing the microprocessor into a system

Organization

This document has the following chapters:

•Chapter 1, Introduction, gives an overview of the BDMR4103

Evaluation Board and describes its features.

•Chapter 2, Installation Procedures, explains how to connect power

to the BDMR4103 Evaluation Board, go through a quick board check

procedure, and install jumpers.

•Chapter 3, Board Design and Layout, describes the design and

layout of the BDMR4103 Evaluation Board.

•Chapter 4, PAL Equations, provides the PAL equations for the

BDMR4103 Evaluation Board.

•Chapter 5, Schematics, contains the schematics for the BDMR4103

Evaluation Board.

•Chapter 6, Bill of Materials, lists the bill of materials for the

BDMR4103 Evaluation Board.

iv Preface

Related Publications

TinyRISC

EZ4103 EasyMACRO Microprocessor and FBusMacro

Technical Manual,

LSI Logic Corporation, Order Number C14068.

TinyRISC

LR4103 Microprocessor Technical Manual,

LSI Logic

Corporation, Document Number DB14-000081-00.

TinyRISC

BDMR4103 Evaluation Kit Getting Started

, LSI Logic

Corporation, Document Number DB15-000095-00.

MIPS PROM Monitor and C Run-Time Library User’s Guide

, LSI Logic

Corporation, Order Number C14017.A.

The C Programming Language

, 2nd edition 1988, by B Kerringhan and

D. Ritchie, Prentice Hall.

PC16550D Universal Asynchronous Receiver Transmitter with FIFOs,

National Semiconductor Corp

Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller

for PCI Local Bus Product,

Advanced Micro Devices.

DS1307/DS1308 64 X 8 Serial Real Time Clock

, DALLAS

Semiconductor.

Conventions Used in This Manual

The word

assert

means to drive a signal true or active. The word

deassert

means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the preﬁx “0x”—for example,

0x32CF. Binary numbers are indicated by the preﬁx “0b”—for example,

0b0011.0010.1100.1111.

All signals with names ending in “N” are active LOW; otherwise, signals

are active HIGH.

Preface v

Abbreviations

The following abbreviations are used in this manual. Note that

abbreviated signal names are not listed:

ASE Application Speciﬁc Extension

CPLD Complex Programmable Logic Device

DIMM Dual Inline Memory Module

DIN Deutsches Institut für Normung

DIP Dual In-line Package

DMA Direct Memory Access

DRAM Dynamic Random Access Memory

EDO Extended Data Output

EEPROM Electronically Erasable Programmable Read Only Memory

EJTAG Enhanced Joint Test Action Group

EPROM Erasable Programmable Read Only Memory

FAPI FBus Advanced Peripheral Interface

FBM FBusMACRO

FET Field Effect Transistor

ICE In-Circuit Emulation

ISA Instruction Set Architecture

ISP In-System Programmable

JEDEC Joint Electrical Device Engineering Committee

JTAG Joint Test Action Group

kΩKilo-ohm

Kbyte Kilobyte

LED Light Emitting Diode

MΩMegaohm

Mbyte Megabyte

vi Preface

PAL Programmable Array Logic

PBGA Plastic Ball Grid Array

PCI Peripheral Component Interface

PLCC Plastic Leaded Chip Carrier

PLD Programmable Logic Device

PLL Phase-Locked Loop

PROM Programmable Read Only Memory

QSOP Quarter Size Outline Package

R/A Right Angle

RTC Real Time Clock

SDRAM Synchronous DRAM

SOIC Small Outline Integrated Circuit

SOJ Small Outline J-bend

SPST Single-Pole Single-throw

SRAM Static RAM

SSOP Shrink Small Outline Package

TAP Test Access Port

TP Test Point

TQFP Thin Quad Flat Package

TSOP Thin Small Outline Package

TSSOP Thin Shrink Small Outline Package

UART Universal Asynchronous Receiver Transmitter

UHS Ultra High Speed

µF Microfarad

ΩOhm

Contents vii
Contents
Chapter 1 Introduction
1 Product Summary 1-1
2 Product Features 1-2
3 Debug Environment Overview 1-3
3.1 PROM-Based Debug Environments 1-3
3.2 EJTAG Debug Environment 1-3
4 Block Diagram 1-4
Chapter 2 Installation Procedures
1 Quick Check 2-1
1.1 Checking the Board 2-2
1.2 Resolving Problems 2-4
2 Jumper Settings 2-5
2.1 Select PLLN (JP1) 2-9
2.2 Divide C1 (JP2) and Divide C0 (JP3) 2-9
2.3 Divide A1 (JP4) and Divide A0 (JP5) 2-10
2.4 Endian Selection (JP6) 2-11
2.5 PLL Range Select (JP7) 2-11
2.6 Alternate Boot Program Selection (JP8) 2-11
2.7 Boot Device Selection (JP9) 2-11
2.8 Connect 3.3 V Power (JP10) 2-12
2.9 Connect CPU I/O Ring Power (JP11) 2-12
2.10 Connect VDD Core Power (JP12) 2-12
2.11 Clock Source Selection (JP14) 2-13
2.12 SerialICE-1 Input Data Selection (JP15) 2-13
2.13 SerialICE-1 Clock Selection (JP16) 2-13
2.14 EDO/SDRAM Selection (JP17) 2-13

viii Contents
Chapter 3 Board Design and Layout
1 Board Layout 3-2
2 External Interfaces 3-3
2.1 Expansion Connector (J2) 3-4
2.2 DIMM Connector (J3) 3-7
2.3 Serial Port Connector (J10) 3-9
2.4 RS-232 Serial Connector for SerialICE-1
Debug Interface(J9) 3-10
2.5 SerialICE-1 Connector (J8) 3-11
2.6 Ethernet Connector (J7) 3-12
2.7 EJTAG Connectors 3-13
Overview of EJTAG Functions 3-13
EJTAG Connector (J4) 3-13
EJTAG Connector (J5) 3-15
2.8 PAL Programming Connector (J11) 3-18
2.9 Power Supply Connector (J1) 3-19
3 Indicators 3-20
3.1 Power LED 3-20
3.2 Ethernet LEDs 3-21
3.3 Debug LED 3-21
3.4 7-Segment Display 3-22
4 System Memory 3-23
4.1 Synchronous DRAM Dual Inline Memory
Module (SDRAM DIMM) 3-23
4.2 Static RAM (SRAM) 3-23
4.3 Boot EPROMs 3-23
5 Memory Map 3-24
6 Two-Wire Serial Bus Peripheral Devices 3-26
6.1 Real-Time Clock (RTC) 3-26
6.2 EEPROM 3-28
6.3 Serial Presence Detect (SPD) 3-28
6.4 LR4103 Interrupts 3-29
7 Device Registers 3-29
7.1 PC16550D UART Registers 3-30
7.2 Am79C970A Ethernet Controller 3-31
Chapter 4 PAL Equations

Contents ix
Chapter 5 Schematics
1 Microprocessor and Clock Circuitry 5-2
2 ROMs, SRAMs, and Address Latches 5-4
3 Ethernet and DRAM Circuitry 5-6
4 Miscellaneous Circuitry and Connectors 5-8
5 Expansion Connector and Boot Device Selection
Circuitry 5-10
6 Power and Reset Circuitry 5-12
7 EJTAG Connectors 5-14
Chapter 6 Bill of Materials
Customer Feedback
Figures 1.1 BDMR4103 Block Diagram 1-4
1 View of the BDMR4103 Quick Check Components 2-2
2 Jumper Positions 2-5
3 Jumper Locations on the BDMR4103 Evaluation Board 2-6
1 BDMR4103 Evaluation Board Layout 3-2
2 Expansion Connector 3-5
3 DIMM Connector Pin Numbers 3-7
4 Serial Port Connector 3-9
5 RS-232 SerialICE-1 Connector 3-10
6 SerialICE-1 Connector 3-11
7 Ethernet 10BASE-T Connector 3-12
8 EJTAG Connector J4 3-14
9 EJTAG Connector J5 3-15
10 PAL Programming Connector 3-18
11 Power Supply Connector 3-19
12 Indicator Positions 3-20
13 Ethernet Indicator Positions 3-21
14 7-Segment Display 3-22
1 Microprocessor and Clock Circuitry 5-3
2 ROMs, SRAMs, and Address Latches 5-5
3 Ethernet and DRAM Circuitry 5-7

x Contents
4 Miscellaneous Circuitry and Connectors 5-9
5 Expansion Connector and Boot Device Selection
Circuitry 5-11
6 Power and Reset Circuitry 5-13
7 EJTAG Connectors 5-15
Tables 2.1 Default Jumper Settings 2-7
2 JP2 and JP3 Jumper Settings 2-10
3 JP4 and JP5 Jumper Settings 2-10
4 JP9 Jumper Settings 2-12
1 Summary of LR4103 Interface Connector Functions 3-3
2 Expansion Connector Pin Designations 3-5
3 DIMM Connector Pin Assignments 3-8
4 Serial Port Connector Pin Assignments 3-9
5 RS-232 SerialICE-1 Connector Pin Assignments 3-10
6 SerialICE-1 Header Pin Assignments 3-11
7 Ethernet Connector Pin Assignments 3-12
8 EJTAG Connector J4 Pin Assignment 3-14
9 EJTAG Connector J5 Pin Assignments 3-15
10 PAL Programming Connector Pin Assignments 3-19
11 Ethernet Indicator Functions 3-21
12 7-Segment Display Settings 3-22
13 Boot EPROM Addressing 3-24
14 Physical Memory Map 3-25
15 Real-Time Clock Addressing 3-27
16 RTC Registers 3-27
17 EEPROM Addressing 3-28
18 SPD EEPROM Addressing 3-28
19 BDMR4103 Interrupts 3-29
20 UART Registers 3-30
21 Ethernet Controller User Registers 3-31
1 BDMR4103 Bill of Materials 6-2

TinyRISC

BDMR4103 Evaluation Board User’s Guide 1-1

Chapter 1

Introduction

This chapter gives an overview of the BDMR4103 Evaluation Board.

Topics covered in the chapter include:

•Section 1.1, “Product Summary”

•Section 1.2, “Product Features”

•Section 1.3, “Debug Environment Overview”

•Section 1.4, “Block Diagram”

1.1 Product Summary

The BDMR4103 Evaluation Board is designed for use with the LSI Logic

TinyRISC LR4103 reference device. You can use the evaluation board to

•Develop application software before (or in parallel with) designing a

system on a chip

•Evaluate the memory system design price/performance trade-off by

running an actual benchmark program

Together with a PC or UNIX host, the evaluation board provides you with

a complete environment for hardware and software development and

debugging. Access to off-board logic through a 150-pin AMP expansion

connector and the capability to download software through

communication ports allows you to verify the functionality of your system

before protoyping the hardware.

1-2 Introduction

1.2 Product Features

The features of the BDMR4103 Evaluation Board are:

•A TinyRISC LR4103 processor that provides a 120 MHz evaluation

target

•128 Kbytes of on-board SRAM

•A plug-in DRAM DIMM (dual inline memory module); the DIMM

connector accepts any standard 100-pin JEDEC (Joint Electrical

Device Engineering Committee) DIMM; a 16 Mbyte SDRAM DIMM is

supplied with board

•1 Mbyte of FLASH EPROM; the EPROM contains a powerful monitor

and debugger for downloading and debugging user programs

•A 1 Kbyte EEPROM for the conﬁguration parameters

•Real-Time Clock (RTC)

•An on-board 16550 UART (universal asynchronous

receiver/transmitter) with one RS-232C serial port

•SerialICE™-1 on-chip debugging capabilities

•EJTAG debugging capabilities

•A 7-segment display for status display and debug use

•An on-board AM79C970A PCnet Ethernet controller with a

10BASE-T interface

•A 150-pin AMP expansion connector that provides easy access to

the evaluation board

•Support for 3.3 V devices

Debug Environment Overview 1-3

1.3 Debug Environment Overview

The BDMR4103 evaluation board offers debug support through a PROM

monitor-based debug environment (PMON and SerialICE-1 debug

interface) and EJTAG, a nonintrusive on-chip MIPS standard debug

environment.

For more information on setting up the three debug environments, please

refer to the

TinyRISC BDMR4103 Evaluation Kit Getting Started.

1.3.1 PROM-Based Debug Environments

PMON is a conventional assembly-level PROM-based debug monitor.

PMON supports stand-alone operation and operation as the backend for

a source-level debugger. The principal disadvantage of PMON is

memory usage. PMON takes up approximately 300 Kbytes of target

memory.

The BDMR4103 evaluation board is shipped with PMON stored in the

lower 512 Kbyte region of the FLASH memory at U12. Communication is

done through the RS-232 serial port and downloaded through the

RS-232 connector at J9 or the Ethernet connector at J7.

The BDMR4103 evaluation board also offers the SerialICE-1 debug

environment. The SerialICE-1 debug interface provides the same debug

features as PMON, but does it with less than 1 Kbyte of target memory.

Use the SerialICE-1 debug interface with either an assembly-level or a

source-level debugger. Communication and download is provided

through the SerialICE-1 RS-232 serial port (J9) or the TTL-level 10-pin

header (J8).

1.3.2 EJTAG Debug Environment

EJTAG (Extended Joint Test Action Group) is a standard on-chip MIPS

debugging environment. EJTAG does not require target system memory.

To use EJTAG, the user needs to set up the memory map for the

BDMR4103 evaluation board since it has a programmable memory

controller. The user can either accomplish this in application code or use

the sample boot-up code provided in the upper 512 Kbyte region of the

FLASH EPROM memory. The user must run this boot-up code before

1-4 Introduction

downloading application programs to the evaluation board using an

assembly-level or source-level debugger. Communication and download

occurs through the EJTAG connector at J4.

1.4 Block Diagram

Figure 1.1 shows a high level block diagram of the BDMR4103 evaluation

board.

Figure 1.1 BDMR4103 Block Diagram

LR4103

Microprocessor

Address Bus

Data Bus

SerialICE-1 Circuitry

EJTAG

Connectors

for Debug

128 Kbytes

SRAM 1 Mbyte

FLASH

1 Mbyte

EPROM

16 Mbytes

SDRAM

16550

UART Ethernet

Control

150-Pin

10BASE-T

Ethernet Connector

Serial

Port

7-Segment

Display

EPROM

Expansion

Connector

EEPROM

RTC

I2C Devices

TinyRISC

BDMR4103 Evaluation Board User’s Guide 2-1

Chapter 2

Installation Procedures

This chapter describes the installation procedure for the BDMR4103

Evaluation Board. Topics covered in the chapter include:

•Section 2.1, “Quick Check”

•Section 2.2, “Jumper Settings”

2.1 Quick Check

Figure 2.1 shows a simpliﬁed view of the BDMR4103 board with the

components referenced in this section. Figure 3.1,onpage 3-2, shows a

more detailed view of the board. Major connectors and the LR4103

processor are shown in Figure 2.1 to provide an orientation.

2-2 Installation Procedures

Figure 2.1 View of the BDMR4103 Quick Check Components

2.1.1 Checking the Board

You can check the evaluation board by booting the PROM monitor

program. The BDMR4103 board is shipped with a monitor program

burned into the AM29F080 FLASH EPROM at location U12.

Use the following procedure to check the board:

J9 J10

SerialICE-1 RS232 Port Serial Port

LR4103 Reference Device

Microprocessor

U16

U36

U12

FLASH

EPROM

U25

EPROM

U13

C50

B50

A50

Power

Supply

Connector

SI Oscillator

1 Mbyte

Power

LED

mproc

OSC

mproc

Crystal Core

Power

3.3 V

1 Kbyte EEPROM

100-Pin DIMM ConnectorJ3

Reset

Button

PinsPins

100

JP9

JP8

JP7

JP6

JP5

JP4

JP3

JP2

JP1

Ethernet

(RJ45) Port

SerialICE-1

Header J8

150-Pin DIN Connector

Quick Check 2-3

1. Using a standard RS-232C cable, connect the serial port (J10) to

one of the following:

– A terminal console.

– A workstation or PC running a terminal emulator program.

Standard VT100-type terminals and PC AT-compatible PCs

operating in VT100 emulation mode are suitable. To emulate a

VT100 terminal on a PC, use the Hyperterminal application in

Microsoft Windows.

Set the terminal software for the following:

– 9600 baud

– 8 data bits

– no parity

– 1 stop bit

Section 3.2.3, “Serial Port Connector (J10),” on page 3-9 describes

the serial port connector.

2. Set the following jumpers: (Refer to Figure 2.3)

– Remove JP9 to select the FLASH EPROM at location U12 as the

boot device.

– Remove JP8 to select the correct boot program within the

FLASH EPROM.

– Remove JP6 to select big-endian addressing mode.

3. LSI Logic provides an AC adapter with the BDMR4103 board. Power

from the adapter is supplied to the board by means of the standard

DC power connector at location J1. Figure 2.1 shows the position of

the DC connector on the evaluation board. Section 3.2.9, “Power

Supply Connector (J1),” on page 3-19, describes the connector.

To apply power to the board, plug the DC power connector on the

AC adapter into the on-board power connector (J1) and plug the

three-pin AC connector on the adapter into main building power. The

power supply provided with the board will operate with AC power in

the range of 100 V–240 V, at 50/60 Hz. When power is applied to the

board, the power LED at D5 lights up.

2-4 Installation Procedures

4. The following events then occur:

– The terminal screen displays a banner.

– The monitor prompt appears on the screen.

– The terminal displays the start-up message.

5. After the start-up message, the monitor displays the following

prompt:

PMON>

This prompt may vary slightly depending on the terminal display type

and settings. When you see the prompt, the system is ready for use.

2.1.2 Resolving Problems

If nothing appears on the screen when you power up the board, check

the following:

1. Is the power adapter plugged into the BDMR4103 board and into the

AC building supply?

2. Is the LED at D5 lit?

3. Is the RS-232C cable correctly installed at location J10?

4. Are the jumpers set for correct operation, as described in

Section 2.1.1, “Checking the Board”, step 2.?

5. If you are using a PC, is it operating in standard VT100 terminal

emulation mode?

If problems persist, contact your LSI Logic sales representative for

further assistance.

Jumper Settings 2-5
2.2 Jumper Settings
The BDMR4103 board has both 2- and 3-pin jumpers. As shown in
Figure 2.2, the 2-pin jumpers are described as being either in (installed)
or out (not installed), and the 3-pin jumpers are described as being in
positions 1−2, positions 2−3, or out.
Figure 2.2 Jumper Positions
All jumpers are identiﬁed by a number of the form
JPnn
(JP1, JP2, and
so forth) on the BDMR4103 board. Figure 2.3 on page 2-6 shows the
locations of the jumpers on the evaluation board. Connectors are shown
in Figure 2.3 on page 2-6 to provide the proper orientation. Table 2.1 on
page 2-7 summarizes the jumper functions and indicates the defaults
(factory settings). Sections 2.2.1 through 2.2.14 provide more detailed
information about jumper settings.
After performing the Quick Check in Section 2.1, disconnect the power
connection from the board and set the jumpers.
1 1
1
333
Positions 1−2 Positions 2−3 OutOutIn
Two-Pin Jumpers Three-Pin Jumpers
12 12 2 2 2

2-6 Installation Procedures

Figure 2.3 Jumper Locations on the BDMR4103 Evaluation Board

J7 J9 J10

JP9

JP8

JP7

JP6

JP5

JP4

JP3

JP2

JP1

U24

JP17

JP 14

JP16

JP15

JP13

JP12

JP11

JP10

JP9 Boot Device Selection

JP4 Divide A1

JP3 Divide Clock 0

JP2 Divide Clock 1

JP1 PLLN Selection

JP8 Alternate Boot Program Selection

JP7 PLL Range Selector

JP6 Endian Selection

JP5 Divide A0

JP14 Clock Source Selection

JP13 VDD Core Voltage Selection

JP12 Connect/ Disconnect

JP11 Connect/Disconnect

JP10 Connect/Disconnect +3 V Power

JP17 Address Line Conﬁguration for SDRAM and EDO DRAM

JP16 SerialICE-1 Clock Selection

JP15 SerialICE-1 Input Data Selection

When installed,

these jumpers

tie the related

input to the

microprocessor

low.

LR4103

Microprocessor

I/O Power

LR4103 Core Power

LR4103

Control PCLK Freq.

Control PBCLK Freq.

321

Jumper Settings 2-7
Table 2.1 Default Jumper Settings
Jumper Jumper Name Setting Function Implemented Reference
JP1 Select PLLN In
(Default) Selects the PLL (phase-locked loop) circuit
as the clock source for the LR4103. Section
2.2.1,
page 2-9
Out Selects the input clock as the clock source
for the LR4103.
JP2 and
JP3 Divide C[1:0] Default:
JP2 In
JP3 In
See
Table 2.2
Control the PBCLK frequency.
The default settings select a PBCLK
frequency equal to 1/3 PCLK.
Section
2.2.2,
page 2-9
JP4 and
JP5 Divide A[1:0] Default:
JP4 In
JP5 Out
See
Table 2.3
Control the PCLK frequency.
The default settings select a PCLK
frequency equal to 4 x the input clock.
Section
2.2.3,
page 2-10
JP6 Endian
Selection Out
(Default) Selects big endian mode. Section
2.2.4,
page 2-11
In Selects little endian mode.
JP7 PLL Range
Selector In
(Default) 100–250 MHz
200–500 MHz
Section
2.2.5,
page 2-11
Out
JP8 Alternate Boot
Program
Selection
In Inverts the A19 input to the boot device to
allow the selection of an alternate boot
program.
Section
2.2.6,
page 2-11
Out
(Default) A19 input to the boot device is not inverted.
JP9 Boot Device
Selection In Selects the EPROM at U25 as the boot
device. Section
2.2.7,
page 2-11
Out
(Default) Selects the FLASH EPROM at U12 as the
boot device.
JP10 Connect 3.3 V In
(Default) Connects 3.3 V power to the onboard
devices. Section
2.2.8,
page 2-12
Out Disconnects 3.3 V power from the onboard
devices for test purposes.
(Sheet 1 of 2)

2-8 Installation Procedures
JP11 Connect CPU
Power In
(Default) Connects the 3.3 V power to the LR4103
VDDIO pins. Section
2.2.9,
page 2-12
Out Disconnects 3.3 V power from the LR4103
VDDIO pins for test purposes.
JP12 Connect VDD
Core Power In
(Default) Connects power to the LR4103 VDD_CORE
pins. Section
2.2.10,
page 2-12
Out Disconnects power from the LR4103
VDD_CORE pins for test purposes.
JP14 Oscillator/
Crystal Clock
Selection
Positions
1–2 Enables the oscillator at U5 to provide the
clock input to the LR4103 microprocessor. Section
2.2.11,
page 2-13
Positions
2–3
(Default)
Enables the X1 crystal to provide the clock
input to the LR4103 microprocessor.
JP15 SerialICE-1
Input Data
Selection
Positions
1–2
(Default)
The connector at J9 provides the data. Section
2.2.12,
page 2-13
Positions
2–3 The connector at J8 provides the data.
J16 SerialICE-1
Clock Selection Positions
1–2
(Default)
The on-board oscillator (U6) supplies the
SerialICE-1 clock. Section
2.2.13,
page 2-13
Positions
2–3 The connector at J8 provides the
SerialICE-1 clock.
JP17 SDRAM/EDO
Selection—
Controls
AddressInputto
DRAM DIMM
Module
Positions
1–2
(Default)
Address lines are conﬁgured for SDRAM. Section
2.2.14,
page 2-13
Positions
2–3 Address lines are conﬁgured for EDO
(extended data output) DRAM.
Table 2.1 Default Jumper Settings (Cont.)
Jumper Jumper Name Setting Function Implemented Reference
(Sheet 2 of 2)

Jumper Settings 2-9

2.2.1 Select PLLN (JP1)

This jumper selects the clock source for the LR4103 microprocessor. The

default setting is installed.

When JP1 is installed, the SELECT_PLLN input to the clock circuitry in

the microprocessor is tied low. This means that on reset, the CLKSEL bit

of the SCR2 register in the LR4103 is cleared, thus selecting the PLL

(phase-locked loop) circuit as the clock source for the LR4103.

When JP1 is not installed, the SELECT_PLLN input to the clock circuitry

in the microprocessor is tied high. This means that on reset, the CLKSEL

bit of the SCR2 register in the LR4103 chip is set, thus selecting the

input clock as the clock source for the LR4103.

You can use software at any time to overwrite the CLKSEL bit in the

SCR2 register originally set by this jumper.

2.2.2 Divide C1 (JP2) and Divide C0 (JP3)

These jumpers control the PBCLK frequency. The PBCLK is used as the

clock for the PCI devices connected to the LR4103 microprocessor.

When the jumpers are installed, they tie the inputs to the clock circuitry

in the microprocessor low. When they are not installed, the inputs are

high. On reset, the values set by these jumpers are loaded into the

CLKDC[1:0] bits in the LR4103 SCR2 register. See the

TinyRISC

EZ4103 EasyMACRO Microprocessor and FBusMacro Technical Manual

for more information.

The frequency of PBCLK is derived by dividing PCLK by the value of

CLKDC[1:0]. Table 2.2 shows the CLKDC values provided by the jumper

settings and the clock frequencies derived from these values.

2-10 Installation Procedures

You can use software at any time to overwrite the DIVC[1:0] values set

by these jumpers in the SCR2 register.

2.2.3 Divide A1 (JP4) and Divide A0 (JP5)

These jumpers control the PCLK frequency by setting the multiplication

value of the LR4103 PLL circuit. PCLK is the processor core clock, and

it is synthesized by multiplying the input clock by the value set on

jumpers JP4 and JP5. Table 2.2 shows the DIVA[1:0] inputs provided by

the jumpers and lists the PCLK frequencies derived from these inputs.

Table 2.2 JP2 and JP3 Jumper Settings

JP2 Setting JP3 Setting CLKDC[1:0] Values PBCLK Frequency

In (Default) In (Default) 0b00 PCLK divided by 3

In Out 0b01 PCLK divided by 1

Out In 0b10 PCLK divided by 2

Out Out 0b11 PCLK divided by 4

Table 2.3 JP4 and JP5 Jumper Settings

JP4 Setting JP5 Setting DIVA[1:0]

Inputs Values Max. PCLK

Frequency1

1. The maximum value is the value derived after reset. The values shown

in the right-hand column are the maximum values possible. A lower value

for PCLK can be obtained using software to program CLKDB[3:0] in the

SCR2 register of the LR4103. You cannot control the DIVA value using

software.

In In 0b00 4 Input*21

In (Default) Out (Default) 0b01 8 Input*41

Out In 0b10 16 Input*81

Out Out 0b11 32 Input*161

Jumper Settings 2-11

2.2.4 Endian Selection (JP6)

Jumper JP6 selects between big endian and little-endian addressing

mode. When the jumper is installed, the endian input to the board,

BIG_ENDIANP, is tied low, meaning the board is in little-endian mode.

When the jumper is not installed, BIG_ENDIANP is tied high, causing the

board to function in big-endian mode. The default is big-endian mode.

2.2.5 PLL Range Select (JP7)

When the JP7 jumper is in, the PLL range is 100–250 MHz. When the

JP7 jumper is out, the PLL range is 200–500 MHz. The PLL runs at twice

the chip clock. The LR4103 is rated for 120 MHz; thus, since

120x2=240, when the jumper JP7 is in, all valid input speeds are

acceptable.

2.2.6 Alternate Boot Program Selection (JP8)

When installed, JP8 inverts the most signiﬁcant address bit (A19) input

to the boot device. When JP8 is not installed, A19 is not inverted. The

default is not installed.

This jumper is used to select between two boot programs installed in the

same 1 Mbyte EPROM. Each boot EPROM can accommodate two boot

programs, provided that neither program is larger than 512 Kbytes. The

alternate program should be programmed at address 0x80000 in the

boot EPROM memory. Setting the most signiﬁcant address bit to the

EPROM HIGH (that is, installing JP8) allows the alternate program to be

selected.

2.2.7 Boot Device Selection (JP9)

The BDMR4103 Evaluation Board accommodates two boot devices: the

EPROM in the DIP socket at location U25, and the onboard FLASH

EPROM at location U12. Jumper JP9 selects between the system boot

devices. The default setting is not installed, causing the system to boot

from the FLASH EPROM at location U12.

2-12 Installation Procedures

The PAL at U42 maps the address of the selected boot device to the

MIPS boot vector address (0x1FC0 0000). Table 2.4 shows the address

spaces for each boot device.

2.2.8 Connect 3.3 V Power (JP10)

When jumper JP10 is installed, 3.3 V power is supplied to the on-board

devices. When the jumper is not installed, there is no 3.3 V power supply

to these devices. This jumper allows you to measure the current used by

3.3 V devices. To do this, remove the jumper and connect a current

meter between the terminals. The default setting is installed.

2.2.9 Connect CPU I/O Ring Power (JP11)

When jumper JP11 is installed, 3.3 V power is supplied to the LR4103

VDDIO pins. When the jumper is not installed, there is no 3.3 V power

supply to these pins. This jumper allows you to measure the current used

by the LR4103 I/O devices. To do this, remove the jumper and connect

a current meter between the terminals. The default setting is installed.

2.2.10 Connect VDD Core Power (JP12)

When jumper JP12 is installed, power is supplied to the LR4103

VDD_CORE pins. When the jumper is not installed, no power is supplied

to these pins. This jumper allows you to measure the current used by the

LR4103 internal logic. To do this, remove the jumper and connect a

current meter between the terminals. The default setting is installed.

VDD_CORE provides power to everything on the LR4103 but the I/O

ring.

Table 2.4 JP9 Jumper Settings

JP9

Setting Boot Device

(Board Location) Boot Device

Address Space Alternate Device

(Board Location) Alternate Device

Address Space

In EPROM (U25) 0x1FC00000–

0x1FCFFFFF FLASH EPROM

(U12) 0x1FD00000–

0X1FDFFFFF

Out

(Default) FLASH EPROM

(U12) 0x1FC00000–

0x1FCFFFFF EPROM (U25) 0x1FD00000–

0X1FDFFFFF

Jumper Settings 2-13

2.2.11 Clock Source Selection (JP14)

The three-position jumper, JP14, selects the clock input to the LR4103

microprocessor. When this jumper is installed in positions 1–2, the

oscillator at location U5 supplies the clock. When it is installed in

positions 2–3, the 25 MHz crystal X1 supplies the clock. The default is

positions 2–3.

2.2.12 SerialICE-1 Input Data Selection (JP15)

The three-position jumper, JP15, selects the source of the SerialICE-1

input data. When this jumper is installed in positions 1–2, the data input

comes from connector J9. When the jumper is in positions 2–3, the data

comes from connector J8. The default is positions 1–2.

2.2.13 SerialICE-1 Clock Selection (JP16)

The three-position jumper, JP16, selects the source of the SerialICE-1

clock. When this jumper is installed in positions 1–2, the on-board

oscillator at location U6 supplies the clock. The clock supplied should be

16x the desired baud rate. When the jumper is installed in positions

2–3, the clock signal is supplied from pin 4 of the connector at location

J8. The default is positions 1–2.

2.2.14 EDO/SDRAM Selection (JP17)

Jumper JP17 enables you to conﬁgure the address lines so that you can

use either SDRAM or EDO DRAM devices on the DIMM installed in the

DIMM slot at location J3. This is accomplished by routing the correct

signal to pin 68 of the DIMM. For SDRAM devices, pin 68 is deﬁned as

bank address 0 (BA0); for EDO DRAM devices, pin 68 is deﬁned as

address 11 (A11).

To conﬁgure the BDMR4103 board for SDRAM, the jumper is installed in

positions 1–2, routing address FADDRP27 to pin 68 of the DIMM socket.

To conﬁgure the BDMR4103 board for EDO DRAM, the jumper is

installed in positions 2–3, routing address FADDRP11 to pin 68. The

default is positions 1–2.

2-14 Installation Procedures

TinyRISC

BDMR4103 Evaluation Board User’s Guide 3-1

Chapter 3

Board Design and

Layout

This chapter describes the board design and layout of the BDMR4103

Evaluation Board as well as elements of the design architecture. Topics

covered in the chapter include:

•Section 3.1, “Board Layout”

•Section 3.2, “External Interfaces”

•Section 3.3, “Indicators”

•Section 3.4, “System Memory”

•Section 3.5, “Memory Map”

•Section 3.6, “Two-Wire Serial Bus Peripheral Devices”

•Section 3.7, “Device Registers”

3-2 Board Design and Layout

3.1 Board Layout

Figure 3.1 shows the placement of the major components on the

BDMR4103 Evaluation Board. Note that the board is not drawn to scale

and the ﬁgure should not be used as a manufacturing aid.

Figure 3.1 BDMR4103 Evaluation Board Layout

SeriaIICE-1 RS232 Port Serial Port

Ethernet 10BASE-T

U10

LR4103 Reference Device

Microprocessor

JP9

JP8

JP7

JP6

JP5

JP4

JP3

JP2

JP1

U16

U36

U35

7-Segment

Display

U24

U14

U19

AM79C970A

U21

U18

U32 U26 U27 U22 U29 U28

32 Kbytes x 8 SRAMs

PCnet TM

Ethernet

Controller

Power

Supply

Connector

Connector SerialICE-1

32 Kbytes x 8 SRAMs

Ethernet

Status Lights

Ethernet

Transformer

PAL

SI Oscillator

16550

Power

LED

Debug

LED D6

EJTAG

OSC mproc

OSC

JP14

µproc

Crystal Core

Power

3.3 V

U30

U38 U2

JP13

JP11

Header

I Kbyte

EEPROM

U13

U30

U17

JP12

JP10

JP17

JP16

JP15

B1 Battery

for Real-Time

Debug

Probe

J7 J9 J10

UART

U42

U37

J11

PAL

Prog.

J3 100-pinDIMM Connector

100

Real-Time

Clock

Factory

Use

Only

Clock

C50

B50

A50 150-Pin DIN Connector

U12

FLASH

EPROM

U25

EPROM

1 Mbyte

Voltage

Regulators

External Interfaces 3-3

3.2 External Interfaces

This section describes the external interfaces to the BDMR4103

Evaluation Board. The connectors that implement the interfaces let you

connect external logic, download software, connect to the Ethernet,

debug the board, program the PAL, and so forth. This section describes

the connectors listed in Table 3.1.Figure 3.1 (page 3-2) shows the

positions of the connectors on the board.

Table 3.1 Summary of LR4103 Interface Connector Functions

Board

Location Connector Name Description Application Main Ref.

J1 Power Supply Standard 5 V, 4.0 A,

DC power connector Connects board to AC

power supply. Page

3-19

J2 Expansion 150-pin DIN connector Connects external

modules to board;

expands design and

debug capabilities.

Page 3-4

J3 DIMM 100-pin DIMM connector Allows a DIMM module

to be installed on the

board, either SDRAM

(Synchronous DRAM) or

EDO (Extended Data

Output).

Page 3-7

J4 EJTAG 16-pin connector Provides basic break

and run control. Allows

you to download

programs and data to

memory. You can use

this connector or

connector J5 to debug

the board

Page

3-13

J5 EJTAG 52-pin connector Provides the same

debugging capabilities

as J4, plus PC trace

capability.

Page

3-15

J6 Debug Probe 20-pin connector Used only for factory

testing. Do not use this

connector.

–

3-4 Board Design and Layout
3.2.1 Expansion Connector (J2)
A 150-pin DIN connector (J2) lets you expand your design and
debugging capability to include external logic. Figure 3.2 on page 3-5
shows the pin numbers for the expansion connector and Table 3.2 on
page 3-5 lists the pin assignments.
Note that the expansion connector signals are not buffered on the
BDMR4103 Evaluation Board. You should buffer these signals when
using them off the evaluation board.
J7 Ethernet 10BASE-T RJ45 connector Connects the board to
the Ethernet using a
standard 10BASE-T
plug.
Page
3-12
J8 SerialICE-1 Interface 10-pin header Provides a logic level
SerialICE-1 interface.
You need special
equipment to use this
interface.
Page
3-11
J9 SerialICE-1 RS232 DB-9 connector Provides a standard
RS232 serial connector
for SerialICE-1 Debug
Interface.
Page
3-10
J10 Serial Port DB-9 connector Allows you to connect a
standard terminal for
RS232 serial I/O
communication.
Page 3-9
J11 PAL Programming Port 8-pin header Allows you to program
the PAL (U42). Page
3-18
Table 3.1 Summary of LR4103 Interface Connector Functions (Cont.)
Board
Location Connector Name Description Application Main Ref.

External Interfaces 3-5

Figure 3.2 Expansion Connector

Table 3.2 Expansion Connector Pin Designations

Pin Signal Name Pin Signal Name Pin Signal Name

A1 +5 V B1 Ground C1 Ground

A2 +5 V B2 Ground C2 Ground

A3 +5 V B3 FADDR12 C3 FADP00

A4 Ground B4 FADDR13 C4 FADP01

A5 Ground B5 FADDR14 C5 FADP02

A6 Ground B6 FADDR15 C6 FADP03

A7 INTP0 B7 FADDR16 C7 FADP04

A8 INTP1 B8 FADDR17 C8 FADP05

A9 INTP2 B9 FADDR18 C9 FADP06

A10 INTP3 B10 FADDR19 C10 FADP07

A11 INTP4 B11 Ground C11 FADP08

A12 INTP5 B12 FADDR20 C12 FADP09

A13 T0_OUTN B13 FADDR21 C13 FADP10

A14 T1_OUTN B14 FADDR22 C14 FADP11

A15 Ground B15 FADDR23 C15 FADP12

A16 NC1B16 AFADDR24 C16 FADP13

A17 BOOTCFG0 B17 FADDR25 C17 FADP14

A18 BOOTCFG1 B18 FADDR26 C18 FADP15

Position #1

Row C

Row B

Row A

A1 Indicator

Position #50

3-6 Board Design and Layout

A19 BOOTCFG2 B19 Ground C19 Ground

A20 NC1B20 SDCASN C20 SDWEN

A21 NC1B21 SDDDMP0 C21 SDDMP1

A22 CWAITP B22 SDCSN0 C22 SDRASN

A23 RSTOUTN B23 FADDR01 C23 FADDRP00

A24 RESETN B24 FADDR03 C24 FADDRP02

A25 Ground B25 FADDR05 C25 FADDRP04

A26 NC1B26 FADDR07 C26 FADDRP06

A27 GP0 B27 FADDR09 C27 FADDRP08

A28 GP1 B28 FADDR11 C28 FADDRP10

A29 GP2 B29 FADDR28 C29 FADDRP27

A30 GP3 B30 SDCSN1 C30 SDCLK0

A31 GP4 B31 SDDMP2 C31 Ground

A32 GP5 B32 SDDMP3 C32 FADP16

A33 Ground B33 Ground C33 FADP17

A34 GPWEN0 B34 FRAMEN C34 FADP18

A35 GPWEN1 B35 IRDYN C35 FADP19

A36 GPWEN2 B36 TRDYN C36 FADP20

A37 GPWEN3 B37 STOPN C37 FADP21

A38 GPRDN B38 DEVSELN C38 FADP22

A39 Ground B39 PBCLK C39 FADP23

A40 GPI00 B40 Ground C40 Ground

A41 GPI01 B41 CEBEN0 C41 FADP24

A42 GPI02 B42 CEBEN1 C42 FADP25

A43 GPI03 B43 CEBEN2 C43 FADP26

Table 3.2 Expansion Connector Pin Designations (Cont.)

Pin Signal Name Pin Signal Name Pin Signal Name

External Interfaces 3-7

3.2.2 DIMM Connector (J3)

A 100-pin DIMM connector (J3), allows you to install a DIMM (Dual Inline

Memory Module) on the board. The connector accommodates DIMMs

populated with SDRAM or EDO devices. Figure 3.3 shows the pin

numbers for this connector and Table 3.3 lists the pin assignments. In

Table 3.3 on page 3-8, “NC” in the Signal Name column signiﬁes No

Connection on the listed pin.

Figure 3.3 DIMM Connector Pin Numbers

A44 NC1B44 CEBEN3 C44 FADP27

A45 Ground B45 SDONEP C45 FADP28

A46 Ground B46 FALEP C46 FADP29

A47 Ground B47 EXP_GNTN C47 FADP30

A48 +3.3 V B48 EXP_REQN C48 FADP31

A49 +3.3 V B49 Ground C49 Ground

A50 +3.3 V B50 Ground C50 Ground

1. Not connected.

Table 3.2 Expansion Connector Pin Designations (Cont.)

Pin Signal Name Pin Signal Name Pin Signal Name

50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 08 06 04 02

49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 09 07 05 03 01

100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52

99 97 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51

PinsPins 1

100

Keys

3-8 Board Design and Layout

Table 3.3 DIMM Connector Pin Assignments

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

1 Ground 26 Ground 51 Ground 76 Ground

2 FADP00 27 +3.3 V 52 FADP08 77 +3.3 V

3 FADP01 28 SDWEN 53 FADP09 78 SDCASN

4 FADP02 29 SDCSN0 54 FADP10 79 SDCSN1

5 FADP03 30 SDCSN0 55 FADP11 80 SDCSN1

6 +3.3 V 31 +3.3 V 56 +3.3 V 81 +3.3 V

7 FADP04 32 NC257 FADP12 82 NC2

8 FADP05 33 NC258 FADP13 83 NC2

9 FADP06 34 NC259 FADP14 84 NC2

10 FADP07 35 NC260 FADP15 85 NC2

11 SDDMP0 36 Ground 61 SDDMP1 86 Ground

12 Ground 37 SDDMP2 62 Ground 87 SDDMP3

13 FADDRP00 38 FADP16 63 FADDRP01 88 FADP24

14 FADDRP02 39 FADP17 64 FADDRP03 89 FADP25

15 FADDRP04 40 FADP18 65 FADDRP05 90 FADP26

16 FADDRP06 41 FADP19 66 FADDRP07 91 FADP27

17 FADDRP08 42 +3.3 V 67 FADDRP09 92 +3.3 V

18 FADDRP10 43 FADP20 68 FADDRP27 (BA0)1

FADDRP11 (A11) 93 FADP28

19 FADDRP28 44 FADP21 69 FADDRP11 94 FADP29

20 NC245 FADP22 70 NC295 FADP30

21 +3.3 V 46 FADP23 71 +3.3 V 96 FADP31

22 NC247 Ground 72 SDRASN 97 Ground

23 NC248 GPI01 73 SDCASN 98 Ground

24 NC249 GPI00 74 NC299 Ground

25 SDCLK0 50 +3.3 V 75 SDCLK0 100 Ground

1. The signal on pin 68 depends upon the setting of JP17. Refer to Section 2.2.14, “EDO/SDRAM

Selection (JP17),” page 2-13.

2. Not connected.

External Interfaces 3-9

3.2.3 Serial Port Connector (J10)

A 9-pin serial port connector (J10) provides connections for serial port

devices. Figure 3.4 shows the pin numbers for this connector and

Table 3.4 lists the pin assignments. The PROM Monitor initializes the

serial port to operate at 9600 baud with eight bits of data, no parity bit,

and one stop bit.

Figure 3.4 Serial Port Connector

RX Ground

RTS CTS

12345

9876

TX DTR

Not connected

DCD Data Carrier Detect

Transmitted Data

Received Data

Request to Send Clear to Send

Data Terminal Ready

DSR Data Set Ready

Table 3.4 Serial Port Connector Pin Assignments

Pin Signal Name Description

1 DCD Data Carrier Detect (Not Connected)

2 RX Received Data

3 TX Transmitted Data

4 DTR Data Terminal Ready (Not Connected)

5 GND Ground

6 DSR Data Set Ready (Not Connected)

7 RTS Request to Send

8 CTS Clear to Send

9 — Not Connected

3-10 Board Design and Layout

3.2.4 RS-232 Serial Connector for SerialICE-1 Debug Interface(J9)

A DB-9 connector (J9) allows you to debug the board using the

SerialICE-1 debug Interface through an RS-232 cable. Pins 1 and 2 of

jumper JP15 need to be shorted to route the RS-232 TX signal to the

ICERXP pin of the LR4103 ICEport. Figure 3.5 shows the pin numbers

for this connector and Table 3.5 lists the signal assignments.

Figure 3.5 RS-232 SerialICE-1 Connector

RX Ground

RTS CTS

12345

9876

TX DTR

Not connected

DCD Data Carrier Detect

Transmitted Data

Received Data

Request to Send Clear to Send

Data Terminal Ready

DSR Data Set Ready

Table 3.5 RS-232 SerialICE-1 Connector Pin Assignments

Pin Signal Name Description

1 DCD Data Carrier Detect (Not Connected)

2 RX Received Data

3 TX Transmitted Data

4 DTR Data Terminal Ready (Not Connected)

5 GND Ground

6 DSR Data Set Ready (Not Connected)

7 RTS Request to Send (Not Connected)

8 CTS Clear to Send (Not Connected)

9 — Not Connected

External Interfaces 3-11

3.2.5 SerialICE-1 Connector (J8)

A 10-pin header (J8) allows you to debug the board using SerialICE-1.

Pins 2 and 3 of jumper JP15 need to be shorted to route the CONN_RXP

signal to the ICERXP pin of the LR4103 ICEport. Figure 3.6 shows the

pin numbers for this connector and Table 3.6 lists the signal assignments.

Figure 3.6 SerialICE-1 Connector

Table 3.6 SerialICE-1 Header Pin Assignments

Pin Signal Name Description

1 CLK_OUT Supplies clock output from the oscillator (U6).

2 — Ground.

3 — Ground.

4 CLK_IN Provides clock source for the LR4103 ICEport

5 — Ground

6 — Ground

7 SI_RESET System Reset

8 CONN_RXP Received Serial Data

9 +5V +5V

10 ICE_TXP Transmitted Serial Data

13579

246810

Input from Oscillator

Ground

SI_RESET

+5 V

Ground

ICECLKP

Ground

CONN_RXP

ICE_TXP Input

3-12 Board Design and Layout

3.2.6 Ethernet Connector (J7)

The Ethernet 10BASE-T connector (J7) is a standard RJ45 connector

that allows you to connect the board to Ethernet. Figure 3.7 shows the

pin numbers for this connector and Table 3.7 lists the pin assignments.

Figure 3.7 Ethernet 10BASE-T Connector

123456

TD− Transmitted Data Return RD− Received Data Return

Not connected Not connected

Not connected

RJ45

RD+ Received Data

TD+ Transmitted Data

Table 3.7 Ethernet Connector Pin Assignments

Pin Name Description

1 TD+ Transmitted Data

2TD−Transmitted Data Return

3 RD+ Received Data

4 NC Not Connected

5 NC Not Connected

6RD−Received Data Return

7 NC Not Connected

8 NC Not Connected

External Interfaces 3-13

3.2.7 EJTAG Connectors

The BDMR4103 has two EJTAG connectors used to debug the board.

The connectors are at locations J4 and J5. This section provides an

overview of EJTAG functions and describes the two EJTAG connectors.

3.2.7.1 Overview of EJTAG Functions

EJTAG is an on-chip debug solution from the MIPS licensees/partners.

EJTAG provides a nonintrusive leading-edge debug tool for the LSI Logic

MiniRISC®and TinyRISC microprocessors in PC and workstation

environments. EJTAG is intended to establish a debug standard among

MIPS partners and simplify the development of systems based on MIPS

microprocessors.

EJTAG allows you to debug user code for the MIPS16 ASE (application

speciﬁc extension) and MIPS I/II/III ISA (instruction set architecture). The

revision of the EJTAG speciﬁcation implemented by LSI Logic is EJTAG

Revision 1.5.3.

The EJTAG functions associated with the BDMR4103 evaluation board

are implemented as hardware. These functions include:

•EJTAG interface and memory

•Software breakpoints

•Single stepping

•DMA support

•Instruction, data, and processor breakpoints

•PC trace (J5)

•Proﬁling

3.2.7.2 EJTAG Connector (J4)

The 16-pin EJTAG connector (J4) allows you to use a subset of the

EJTAG functions, including downloading data and programs to memory

and run control. The connector does not support PC trace. Figure 3.8

shows the pin numbers for this EJTAG connector and Table 3.8 lists the

pin assignments.

3-14 Board Design and Layout

Figure 3.8 EJTAG Connector J4

13579

2468

10 12 14 16

11 13 15

Table 3.8 EJTAG Connector J4 Pin Assignment

Pin Signal Name Input/Output Description

1 TDO O TDO (test data output) performs different functions,

depending on whether or not PC trace mode is turned

on. Connector J4 does not support PC trace, so the

functions of this signal are the same as those when

PC trace mode is turned off. That is, serial output data

is shifted from the JTAG instruction of the data register

to pin 1 (TDO) on the falling edge of the test clock,

TCK. When no data is shifted out, this pin is in a

3-state (high impedance) condition.

2, 5, 8, 10,

11, 14, 15 – – Not connected.

3 TDI/DINT I TDI (test data input)/DINT(debug interrupt).

4 TRST I TRST (test reset) is an active-low, asynchronous,

reset signal that resets the EJTAG module

independently of the processor logic.

6 3.3 V I 3.3 V power.

7 TCK I TCK (test clock) is the input clock used to shift data

into or out of the instruction register or data register.

9 TMS I TMS (test mode select) is decoded by the TAP

controller to control test operation. The signal is

sampled on the rising edge of TCK.

12, 16 – – Ground

13 EJTAG_RESET I This signal is a board level reset signal.

External Interfaces 3-15

3.2.7.3 EJTAG Connector (J5)

The 52-pin EJTAG connector (J5) supports the same EJTAG functions

as the connector at J4. In addition, it supports PC trace. Figure 3.9

shows the pin numbers for the connector and Table 3.9 lists the pin

assignments.

Figure 3.9 EJTAG Connector J5

Table 3.9 EJTAG Connector J5 Pin Assignments

Pin # Signal Name Input/Output Description

1 TRST I TRST (test reset) is an active-low, asynchronous, reset

signal that resets the EJTAG module independently of

the processor logic.

3 TDI/DINT I PC trace mode off: Serial input data (TDI, test data

input) is shifted into the JTAG Instruction register or

Data register on the rising edge of the TCK clock,

depending on the TAP (test access port) controller

state.

PC trace mode on: An active-LOW level on this pin

(DINT, debug interrupt) is used as an interrupt to switch

off PC trace mode. This signal is sampled at the TCK

positive edge or asynchronous to TCK.

5 TDO/TPC O PC trace mode off: Serial output data (TDO) is shifted

from the JTAG instruction of the data register to this pin

on the falling edge of the test clock, TCK. When no

data is shifted out, this pin is in a 3-state (off) condition.

PC trace mode on: This pin provides a nonsequential

program counter (TPC) on each DCLK clock.

7 TMS I TMS (test mode select) is decoded by the TAP

controller to control test operation. The signal is

sampled on the rising edge of TCK.

9 TCK I TCK (test clock) is the input clock used to shift data into

or out of the instruction register or data register.

2 4 6 8 10 12 14 16 18 20 44 46 48 50 52

43 45 47 49 51

1 3 5 7 9 11 13 15 17 19

3-16 Board Design and Layout

11 EJTAG_RESET I This signal is a board level reset signal.

– PCST1_[2:0] O During PC trace mode, the status of the CPU is

encoded for every CPU cycle, using this group of three

status bits. PCST1_[2:0] contains the most recent

status bits.

13 PCST1_ 0 PC status trace set 1, bit 0.

15 PCST1_1 PC status trace set 1, bit 1.

17 PCST1_2 PC status trace set 1, bit 2.

19 DCLK O PC trace clock output. This clock qualiﬁes the address

and status information contained on the TPC and

PCST pins.

21 TPC2 O PC trace out 2. This pin provides a nonsequential

program counter (TPC) bit on each DCLK when M

(where M is the number of address bits output for each

DCLK) is greater than one.

– PCST2_[2:0] O During PC trace mode, the status of the CPU is

encoded for every CPU cycle, using this group of three

status bits. When N (as in DCLK is 1/N processor

clock) is greater than 1, PCST2_[2:0] contains the

second most recent status bits.

23 PCST2_ 0 PC status trace set 2, bit 0.

25 PCST2_1 PC status trace set 2, bit 1.

27 PCST2_2 PC status trace set 2, bit 2.

29 TPC3 O PC trace out 3. This pin provides a nonsequential

program counter (TPC) bit on each DCLK, when M

(where M is the number of address bits output for each

DCLK) is greater than 2.

Table 3.9 EJTAG Connector J5 Pin Assignments (Cont.)

Pin # Signal Name Input/Output Description

External Interfaces 3-17

– PCST3_[2:0] O During PC trace mode, the status of the CPU is

encoded for every CPU cycle using this group of three

status bits. When N (as in DCLK is 1/N processor

clock) is greater than 2, PCST3_[2:0] contains the third

most recent status bits.

31 PCST3_ 0 PC status trace set 3, bit 0.

33 PCST3_1 PC status trace set 3, bit 1.

35 PCST3_2 PC status trace set 3, bit 2.

37 TPC4 O PC trace out 4. This pin provides a nonsequential

program counter (TPC) on each DCLK, when M (where

M is the number of address bits output for each DCLK)

is greater than 2.

– PCST4_[2:0] O During PC trace mode, the status of the CPU is

encoded for every CPU cycle using this group of three

status bits. When N (as in DCLK is 1/N processor

clock) equals 4, PCST4_[2:0] contains the fourth most

recent status bits.

39 PCST4_ 0 PC status trace set 4, bit 0.

41 PCST4_1 PC status trace set 4, bit 1.

43 PCST4_2 PC status trace set 4, bit 2.

45 TPC5 O PC trace out 5. This pin provides a nonsequential

program counter (TPC) on each DCLK, when M (where

M is the number of address bits output for each DCLK)

equals 8.

47 TPC6 O PC trace out 6. This pin provides a nonsequential

program counter (TPC) on each DCLK, when M (where

M is the number of address bits output for each DCLK)

equals 8.

49 TPC7 O PC trace out 7. This pin provides a nonsequential

program counter (TPC) on each DCLK, when M (where

M is the number of address bits output for each DCLK)

equals 8.

Table 3.9 EJTAG Connector J5 Pin Assignments (Cont.)

Pin # Signal Name Input/Output Description

3-18 Board Design and Layout

3.2.8 PAL Programming Connector (J11)

An 8-pin connector (J11) allows you to program the PAL (U42).

Figure 3.10 shows the pin numbers for this connector and Table 3.10 lists

the pin assignments.

Figure 3.10 PAL Programming Connector

51 TPC8 O PC trace out 8. This pin provides a nonsequential

program counter (TPC) on each DCLK, when M (where

M is the number of address bits output for each DCLK)

equals 8.

The following pins are ground: 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38,

40, 42, 44, 46, 48, 50, 52

Table 3.9 EJTAG Connector J5 Pin Assignments (Cont.)

Pin # Signal Name Input/Output Description

Edge of Board

External Interfaces 3-19

3.2.9 Power Supply Connector (J1)

The BDMR4103 Evaluation Board has a standard 5 V, 4.0 A DC power

supply connector (Figure 3.11), at location J1.

Figure 3.11 Power Supply Connector

LSI Logic supplies a switching AC adapter with a standard power inlet

that lets you connect the board to AC power. The adapter takes inputs

from 100–240 V AC, 50–60 Hz, and outputs +5 V DC at 4.0 amps.

The red LED (D5) comes on when power is applied to the board.

Table 3.10 PAL Programming Connector Pin Assignments

Pins Signal Name Description

1 3.3 V 3.3 V Power Input

2 SDO Serial Data Out

3 SDI Serial Data In

4 ISP_EN Program Enable

5 Not Connected –

6 ISP_MODE In-System Programmable Mode

7 Ground Ground

8 ISP_SCLK PAL Program Clock Input

5 V

Ground

3-20 Board Design and Layout

3.3 Indicators

This section describes the following indicators on the BDMR4103 board:

•Power LED

•Ethernet LEDs

•Debug LED

•7-segment display

Figure 3.12 shows the positions of these indicators on the board.

Figure 3.12 Indicator Positions

3.3.1 Power LED

The red power LED (D5) comes on when power is applied to the board

and stays on as long as power is being applied.

Red Power

LED (D5)

Yellow

Debug

LED (D6)

Ethernet

LEDs (D1–D4)

7-Segment

Display (U35)

Indicators 3-21

3.3.2 Ethernet LEDs

There are four LEDs on the edge of the evaluation board, to the left of

the Ethernet connector, as shown in Figure 3.13. These indicators come

on during Ethernet activity. Table 3.11 summarizes the Ethernet indicator

functions

Figure 3.13 Ethernet Indicator Positions

3.3.3 Debug LED

The yellow LED (D6) indicates the board is in debug mode. The LED

lights when the DM bit in the CP0 debug register of the LR4103 is set.

The DM bit is part of the EJTAG debugging system. Refer to

Section 3.2.7.1, “Overview of EJTAG Functions,” on page 3-13.

Table 3.11 Ethernet Indicator Functions

Indicator Location Function

TX D1 Activated to indicate data is being transmitted.

RX D2 Activated to indicate data is being received.

LNK D3 Activated when Ethernet link integrity is good.

COL D4 Activated when a collision occurs; that is, when

two Ethernet devices are trying to transmit at the

same time. (This is not the default function of this

LED2 output from the AM79C970. The Ethernet

controller initialization code should enable this

function.)

D1 D2 D3 D4

Ethernet Indicators

TX RX COLLNK

Edge of

Evaluation

Board

Ethernet 10BASE-T

Connector

Green Green Yellow Red

3-22 Board Design and Layout

3.3.4 7-Segment Display

The 7-segment display (U35) shown in Figure 3.14 is attached to a

memory-mapped latch (register), at location U34. A read operation to the

the segment display. A write operation to the register changes the value

shown on the segment display. Table 3.12 lists the data bit assignments

for each segment. When the related bit is cleared to ‘0,’ the segment

turns on, when the related bit is set to ‘1,’ the segment turns off. The

7-segment display is at address 0x1E00 0020 in the system memory

map and must be accessed with byte operations.

Figure 3.14 7-Segment Display

Table 3.12 7-Segment Display Settings

Data Bit Segment

D0 a

D1 b

D2 c

D3 d

D4 e

D5 f

D6 g

D7 Decimal point

Decimal Point

Example

D0 = 1

D1 = 1

D2 = 0

D3 = 0

D4 = 0

D5 = 0

D6 = 0

D7 = 1

a (D0)

b (D1)

c (D2)

d (D3)

e (D4)

f (D5)

gg (D6)

Segment off

Segment on

No decimal (D7)

Decimal

Point

System Memory 3-23

3.4 System Memory

The BDMR4103 Evaluation Board accommodates a variety of memory

devices, including SDRAM DIMM, SRAM (static RAM), and boot PROM.

This section describes the different memory types and usage. Figure 3.1

on page 3-2 shows the position of the different memory modules on the

board.

3.4.1 Synchronous DRAM Dual Inline Memory Module (SDRAM DIMM)

The BDMR4103 Evaluation Board uses the 16 Mbyte SDRAM DIMM

installed in the DIMM socket as the main system memory. The software

LSI Logic provides initializes the FBM (FbusMACRO) to address the

SDRAM DIMM at memory location 0x0000 0000. The FBM provides a

glueless interface to the SDRAM DIMM. The LR4103 microprocessor

supports other SDRAM DIMM conﬁgurations, as well as EDO DRAM. If

you use DRAM other than the 16 Mbyte SDRAM DIMM, you must modify

the FBM conﬁguration code.

If an external PCI master needs access to the SDRAM, the SDRAM

clock must be set to 33 MHz. CPU to SDRAM accesses also occur at

33 MHz in this case.

3.4.2 Static RAM (SRAM)

The evaluation board also contains 128 Kbytes of SRAM. The software

LSI Logic provides initializes the FBM to address the SRAM at memory

location 0x0E00 0000. The Ethernet controller uses the SRAM devices

to hold its transmit and receive buffers.

This memory is used by an external PCI interface to store temporary

values without constraining the SDRAM clock to 33 MHz.

You can also use the SRAM to store programs or data.

3.4.3 Boot EPROMs

The BDMR4103 board is shipped with an AM29F080, 1 Mbyte, FLASH

EPROM installed at location U12. The board also contains a DIP socket,

at location U25, in which an optional 32-pin UV EPROM may be

installed. The socket accommodates EPROMs up to 1 Mbyte, and the

EPROM installed in this socket sits over the top of the FLASH EPROM

at location U12.

3-24 Board Design and Layout

The boot EPROMs are addressed at the MIPS boot vector address,

which is 0x1FC0 0000. The order in which the boot EPROMs are

addressed decides which EPROM acts as the boot EPROM. This is

determined by jumper JP9. If JP9 is not installed, the AM29F080 at U12

is selected as the boot device. If JP9 is installed, the UV EPROM at U25

is selected as the boot device. The PAL at U42 maps the addresses of

the EPROMs to select the boot and alternate device.

Installing jumper JP8 inverts address bit 19 (A19), the most signiﬁcant

address bit, to the boot EPROM. This allows you to install two boot

programs in the same 1 Mbyte boot EPROM. Each boot program must

be less than 512 Kbytes. The addressing of the nonboot EPROM is not

affected by jumper JP8. Table 3.13 lists boot EPROM addresses with

JP8 installed and JP8 not installed.

3.5 Memory Map

Table 3.14 shows the BDMR4103 memory map. Note that the LR4103

microprocessor contains a programmable memory controller, known as

the FBusMACRO, and that all address mappings shown in Table 3.14

can be altered by software. However, the addresses shown in Table 3.14

are those that LSI Logic uses for any software delivered with the

BDMR4103 Evaluation Board.

All memory and peripheral devices on the BDMR4103 board can be

accessed in either user or kernel mode. In user mode, addresses in

programs (virtual addresses) must be in

kuseg

, that is, in the range

0x0000 0000 to 0x7FFF FFFF. Kernel-mode programs typically use

virtual addresses in

kseg0

(0x8000 0000 to 0x9FFF FFFF) for cacheable

locations, and

kseg1

(0xA000 0000 to 0xBFFF FFFF) for noncacheable

locations.

Table 3.13 Boot EPROM Addressing

LR4103 Address Boot EPROM Address

with JP8 Installed Boot EPROM Address

with JP8 Not Installed

0x1FC0 0000 0x80000 0x00000

0x1FC0 8000 0x00000 0x80000

Memory Map 3-25

Some device selects are partially decoded off chip, using a general

purpose chip select, gp[5:0], and an address offset. These selects are

noted as gpx + offset. This method of decoding chip selects was used

to leave some gp[x] selects free for expansion.

Table 3.14 Physical Memory Map

Address Range Controlling Chip

Select Device Name

0x1FE0 0020

0x1FE0 0000 FAPI AM79C970A Ethernet Controller

0x1FD0 0000

0x1FDF FFFF gp0 + 0x10 0000 1 Mbyte EPROM (U25) or FLASH EPROM (U12)

(EPROM type depends on setting of jumper JP9)

0x1FC0 0000

0x1FCF FFFF gp0 1 Mbyte EPROM (U25) or FLASH EPROM (U12)

(EPROM type depends on setting of jumper JP9)

Unused

0x1E00 003F

0x1E00 0030 gp4 + 0x30 RTC Interrupt Clear

0x1E00 002F

0x1E00 0020 gp4 + 0x20 7-Segment Display

0x1E00 001F

0x1E00 0000 gp4 + 0x0 16550 UART

Unused

0x0E01 FFFF

0x0E00 0000 gp3 128 Kbyte SRAM

Unused

0x00FF FFFF

0x0000 0000 gp2 16 Mbyte SDRAM

3-26 Board Design and Layout

3.6 Two-Wire Serial Bus Peripheral Devices

The BDMR4103 board contains three peripheral devices that use a

standard two-wire serial bus. They are

•A real-time clock (U37)

•A 1 Kbyte EEPROM (U13)

•A serial presence detect (SPD), which is on the DRAM DIMM

The LR4103 microprocessor does not contain any dedicated two-wire

serial bus support hardware, but instead communicates with the two-wire

serial bus peripheral devices using the general purpose I/O pins,

gpIO[1:0], which are driven by software. This section describes each of

the peripheral devices.

The supported devices use a bidirectional two-wire bus and data

transmission protocol. Devices sending data onto the bus are described

as transmitters and the devices receiving data are the receivers. The

device that controls the message is the master and the devices

controlled by the master are slaves. The slave devices must be controlled

by a master device that generates a serial clock (SCL), controls bus

access, and generates start and stop conditions.

3.6.1 Real-Time Clock (RTC)

The BDMR4103 board is equipped with a DALLAS Semiconductor

DS 1307 real-time clock at U37. This RTC provides a battery-backed

clock and date function for the evaluation board. You can also program

the RTC to supply a periodic interrupt to the LR4103. The falling edge of

the SQW (Square Wave) output from the RTC is used to set a latch in

the PLD (programmable logic device), which then asserts an interrupt

(int5) to the LR4103 microprocessor. The interrupt is cleared by writing

to location gp4 + 0x30 (0x1E00 0030).

Two-Wire Serial Bus Peripheral Devices 3-27

Table 3.15 shows the address space for the RTC.

Table 3.16 shows the RTC registers.

Table 3.15 Real-Time Clock Addressing

Device ID Address Read/Write

1101 0b000 1 = Read

0=Write

Table 3.16 RTC Registers

Name Address Register Bits Range

765 43210

Seconds 0x00 CH110 Seconds Seconds 00–59

Minutes 0x01 – 10 Minutes Minutes 00–59

Hours 0x02 – 12/24 10/AM

or PM 10 Hour Hour 01−12 +

AM/PM

00−23

Day 0x03 – – – – – Day 1−7

Date 0x04 – – 10 Date Date 01−28/29

01−30

01−31

Month 0x05 – – – 10

Month Month 01−12

Year 0x06 10 Year Year 00–99

Control 0x07 OUT2– – SQWE3– – RS1 RS0 –

RAM 0x08–

0x3F 56 8-bit registers –

1. Clock Halt. When HIGH, the oscillator is disabled. When LOW, the oscillator is enabled.

2. Output control. This bit controls the output level of the SQW/OUT pin when the oscillator is disabled.

If SQWE is LOW, the level on the SQW/OUT pin is HIGH if OUT is HIGH and LOW if OUT is LOW.

3. Square Wave Enable. When HIGH, enables oscillator output. Frequency is controlled by the Rate

Select bits of the Control register (RS[1:0]). Available frequencies are 1 Hz (RS[1:0] = 00),

4.096 KHz (RS[1:0] = 01), 8.192 KHz (RS[1:0] = 10), and 32.768 KHz (RS[1:0] = 11).

3-28 Board Design and Layout

For detailed information about the RTC, refer to the DALLAS

Semiconductor datasheet for the

DS1307/DS1308 64 X 8 Serial Real

Time Clock

3.6.2 EEPROM

The BDMR4103 Evaluation Board is equipped with an NM24C08 1 Kbyte

EEPROM that provides nonvolatile storage for board identiﬁcation and

conﬁguration information. Table 3.17 shows the address of the EEPROM.

3.6.3 Serial Presence Detect (SPD)

The 100-pin DIMM installed in the DIMM socket (J3) is equipped with an

SPD EEPROM. The SPD EEPROM contains information about the types

and conﬁguration of the memory devices installed on the DIMM. You can

use the information in the SPD EEPROM to conﬁgure the BDMR4103

board to operate with different types of DIMMs. Table 3.18 shows the

address of the SPD EEPROM.

Table 3.17 EEPROM Addressing

Device ID Address Read/Write

1010 0b1xx 1 = Read

0=Write

Table 3.18 SPD EEPROM Addressing

Device ID Address Read/Write

1010 0b000 1 = Read

0=Write

Device Registers 3-29

3.6.4 LR4103 Interrupts

Table 3.19 shows how the interrupts from the evaluation board are

connected to the LR4103 microprocessor.

3.7 Device Registers

This section describes the BDMR4103 Evaluation Board devices that

have registers. They are:

•PC16550D UART (U24)

•Am79C970A Ethernet Controller (U19)

The real-time clock (U37) also has registers, which are described in

Table 3.16,onpage 3-27.

Table 3.19 BDMR4103 Interrupts

Interrupt

Number Source Cleared By

0 LR4103 DBE/FBDSTOP Writing to the DBE bit in SCR1 or the

FBDSTOP bit in SCR2 of the LR4103.

1 LR4103 Timer 0 Writing to the bit in Timer 0.

2 SerialICE-1 Debugger Writing to the bit in S1.

3 16550 UART or

LR4103 Timer 1 Clearing the source in the UART or

writing to the bit in Timer 1

4 Ethernet Controller Clearing the source in the Ethernet

Controller

5 Real-Time Clock Writing to gp4 + 0x30 (0x1E000030)

3-30 Board Design and Layout

3.7.1 PC16550D UART Registers

Table 3.20 lists the registers in the National Semiconductor UART at

location U24. For detailed information about the UART, refer to the

PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs

datasheet from National Semiconductor Corporation.

Table 3.20 UART Registers

Address Register Name Access1

1. RO = Read Only, R/W = Read/Write, WO = Write Only

0x1E00 0000 gp4 + 0 Receiver Buffer Register RO

0x1E00 0000 gp4 + 0 Transmitter Holding Register WO

0x1E00 0001 gp4 + 1 Interrupt Enable Register R/W

0x1E00 0002 gp4 + 2 Interrupt Identiﬁcation Register R/W

0x1E00 0002 gp4 + 2 FIFO Control Register WO

0x1E00 0003 gp4 + 3 Line Control Register R/W

0x1E00 0004 gp4 + 4 Modem Control Register R/W

0x1E00 0005 gp4 + 5 Line Status Register R/W

0x1E00 0006 gp4 + 6 Modem Status Register R/W

0x1E00 0007 gp4 + 7 Scratchpad Register R/W

0x1E00 0000 gp4 + 0 Divisor Latch Register (LS) R/W

0x1E00 0001 gp4 + 1 Divisor Latch Register (MS) R/W

Device Registers 3-31

3.7.2 Am79C970A Ethernet Controller

Table 3.21 describes the user registers in the Am79C970A Ethernet

Controller. The PCI conﬁguration registers are accessed with PCI

conﬁguration cycles. The Am79C970A Ethernet Controller responds to a

conﬁguration cycle with A16 = 1.

Table 3.21 Ethernet Controller User Registers

Address A[31:0] Access1Register Name

PCI Conﬁguration Registers

0x1FE9 0000 RO PCI Vendor ID

0x1FE9 0002 RO PCI Device ID

0x1FE9 0004 R/W PCI Command

0x1FE9 0006 R/W PCI Status

0x1FE9 0008 RO PCI Revision ID

0x1FE9 0009 RO PCI Programming Interface

0x1FE9 000A RO PCI Subclass

0x1FE9 000B RO PCI Base-Class

0x1FE9 000C RO PCI Latency Timer

0x1FE9 000E RO PCI Header Type

0x1FE9 0010 R/W PCI I/O Base Address

0x1FE9 0014 R/W PCI Memory Mapped I/O Base Address

0x1FE9 0030 RO PCI Expansion ROM Base Address

0x1FE9 003C R/W PCI Interrupt Line

0x1FE9 003D RO PCI Interrupt Pin

0x1FE9 003E RO PCI MIN_GNT

0x1FE9 003F RO PCI MAX_LAT

3-32 Board Design and Layout

Refer to the

AM79C970A PCnet-PCI II Single-Chip Full Duplex Ethernet

Control for PCI Local Bus Product

datasheet from Advanced Micro

Devices Inc., for more information about the Ethernet Controller

registers.

I/O Registers2

0x1FE0 0010 R/W Register Data Port

0x1FE0 0014 R/W Register Address Port

0x1FE0 0018 R/W Reset

0x1FE0 001C R/W BCR Data Port

1. RO = Read Only, R/W = Read/Write

2. You should use PCI memory access from the FBM (FBusMACRO) to access the I/O registers. I/O

device addresses are determined by the values programmed in the PCI conﬁguration registers.

Table 3.21 Ethernet Controller User Registers (Cont.)

Address A[31:0] Access1Register Name

TinyRISC

BDMR4103 Evaluation Board User’s Guide 4-1

Chapter 4

PAL Equations

This chapter provides the code listing for the Programmable Array Logic

(PAL) at location U42 on the BDMR4103 Evaluation Board.

The pin numbers in the equations refer to the pins on the PAL package

shipped on the BDMR4103 Evaluation Board.

The PAL performs the following tasks:

•Decodes and controls external addresses for ROM devices

Both EPROMs on the evaluation board (the EPROM at U25 and the

Flash EPROM at U12) connect to chip select GP0 and are selected

by signal A20. Jumper JP9 selects the boot device and the

addressing order of each EPROM. Additionally, jumper JP8 sets

which boot program (regular or alternate) the selected EPROM uses.

If JP8 is installed, A19 is inverted and the alternate boot program is

selected. The setting of JP8 does not affect the nonboot ROM. Refer

to Section 2.2, “Jumper Settings,” for more information.

•Decodes external addresses for devices connected to chip select

GP4

Devices connected to GP4 include the UART, seven-segment

display, and the real-time clock interrupt register. An address offset

is required for these devices. Refer to Section 3.5, “Memory Map,”

for each device’s offset value.

•Combines reset signals

The PAL gathers reset signals from other sources and combines

them into a single board-level reset request.

4-2 PAL Equations

•Sets interrupts from RTC

The PAL sets a latch using the falling edge of the RTC’s square ware

output. The latch is used as an interrupt for the LR4103. Write to the

latch to clear it.

•Arbitrates the PCI bus

The PAL allows multiple PCI bus masters to connect to the LR4103.

You can only connect one PCI bus master to the LR4103.

The code in this chapter was up to date at the time of publication. To

verify that you have the latest code, you should contact LSI Logic

Corporation.

module core_logic

title 'lr4103 core logic'

U42 device 'ispLSI';

PLSI PROPERTY 'PART ispLSI2032v-100LT44';

"define pins and nodes

pbclk pin 5; "CLK"

jmp0 pin 2;

jmp1 pin 3;

addr20 pin 37; "used to select between eprom/flash"

addr19 pin 36; "invert a19 to allow 2 boot

"programs in 1 rom"

addr05 pin 35; "used to select between uart/display"

addr04 pin 31; "used to select between rtc_int/display"

gp4 pin 32; "uart/display select"

gp0 pin 33; "eprom/flash select"

rdn pin 42;

we0 pin 44;

resetn pin 4;

flash_sel pin 23;

dip_sel pin 22;

rom_a19 pin 21;

bd_sel pin 20; "buffered data select"

uart_sel pin 26;

read_display pin 12; "7-seg display rd

write_display pin 13; "7-seg display wr

4-3

"*** Arbiter signals ***"

enet_req pin 14 ;

enet_gnt pin 15 istype 'reg_D';

exp_req pin 9 ;

exp_gnt pin 10 istype 'reg_D';

req pin 25 istype 'reg_D';"system req"

gnt pin 24; "system gnt"

sqw_out pin 16; "square wave out from RTC

intp5 pin 34; "interrupt to uP

arb0 node istype 'buffer, reg_D';

arb1 node istype 'buffer, reg_D';

arb2 node istype 'buffer, reg_D';

si_reset pin 41;

ejtag_reset pin 38;

pb_reset pin 43;

rtc_sync1 node istype 'reg_D';

rtc_sync2 node istype 'reg_D';

rtc_sync3 node istype 'reg_D';

rtc_intff node istype 'reg_SR';

4-4 PAL Equations

PLSI PROPERTY 'OPENDRAIN pb_reset';

"**************************************************************************

**"

"constants and state definitions

h,l,x,ck,z = 1,0,.X.,.C.,.Z.;

ARBITER = [arb2,arb1,arb0];

IDLE_ENET = [0,0,0];

IDLE_EXP = [0,0,1];

REQ_ENET = [1,0,0];

REQ_EXP = [1,0,1];

GNT_ENET = [0,1,0];

GNT_EXP = [0,1,1];

RESET = !resetn;

equations

ARBITER.clk = pbclk;

req.clk = pbclk;

enet_gnt.clk= pbclk;

exp_gnt.clk= pbclk;

rtc_sync1.clk= pbclk;

rtc_sync2.clk= pbclk;

rtc_sync3.clk= pbclk;

rtc_intff.clk= pbclk;

!flash_sel = !gp0 & (( jp9 & !addr20 ) # (!jp9 & addr20));

!dip_sel = !gp0 & (( jp9 & addr20 ) # (!jp9 & !addr20));

rom_a19 = ((jp8 # addr20) & addr19) # ((!jp8 & !addr20) & !addr19);

!bd_sel = ( !gp0 # !gp4);

!uart_sel = (!gp4 & !addr05);

!read_display = (!gp4 & addr05 & !addr04 & !rdn );

!write_display = (!gp4 & addr05 & !addr04 & !we0) # (RESET);

4-5

!pb_reset = !si_reset # !ejtag_reset;

pb_reset.en = !si_reset # !ejtag_reset;

rtc_sync1 := sqw_out;

rtc_sync2 := rtc_sync1;

rtc_sync3 := rtc_sync2;

rtc_intff.s = ( !rtc_sync2 & rtc_sync3);"set ff on falling edge

rtc_intff.r = ( !gp4 & addr05 & addr04 ) # (RESET);

intp5 = rtc_intff;

STATE_DIAGRAM ARBITER

state IDLE_ENET:

if (!enet_req) then REQ_ENET with

req := 0;

enet_gnt :=1;

exp_gnt :=1;

endwith;

else if (!exp_req) then REQ_EXP with

req := 0;

enet_gnt :=1;

exp_gnt :=1;

endwith;

else IDLE_ENET with

req := 1;

enet_gnt :=1;

exp_gnt :=1;

endwith;

state IDLE_EXP:

if (!exp_req) then REQ_EXP with

req := 0;

enet_gnt :=1;

exp_gnt :=1;

endwith;

else if (!enet_req) then REQ_ENET with

req := 0;

enet_gnt :=1;

exp_gnt :=1;

endwith;

4-6 PAL Equations

else IDLE_EXP with

req := 1;

enet_gnt :=1;

exp_gnt :=1;

endwith;

state REQ_ENET:

if ( !gnt & !enet_req) then GNT_ENET with

req := 0;

enet_gnt :=0;

exp_gnt :=1;

endwith;

else if ( !enet_req )then REQ_ENET with

req := 0;

enet_gnt :=1;

exp_gnt :=1;

endwith;

else IDLE_EXP with

req := 1;

enet_gnt :=1;

exp_gnt :=1;

endwith;

state REQ_EXP:

if ( !gnt & !exp_req) then GNT_EXP with

req := 0;

enet_gnt :=1;

exp_gnt :=0;

endwith;

else if ( !exp_req )then REQ_ENET with

req := 0;

enet_gnt :=1;

exp_gnt :=1;

endwith;

else IDLE_ENET with

req := 1;

enet_gnt :=1;

exp_gnt :=1;

endwith;

4-7

else if ( !exp_req )then REQ_ENET with

req := 0;

enet_gnt :=1;

exp_gnt :=1;

endwith;

else IDLE_ENET with

req := 1;

enet_gnt :=1;

exp_gnt :=1;

endwith;

state GNT_ENET:

if (!gnt & !enet_req) then GNT_ENET with

req := 0;

enet_gnt :=0;

exp_gnt :=1;

endwith;

else IDLE_EXP with

req := 1;

enet_gnt :=1;

exp_gnt :=1;

endwith;

state GNT_EXP:

if (!gnt & !exp_req) then GNT_EXP with

req := 0;

enet_gnt :=1;

exp_gnt :=0;

endwith;

else IDLE_EXP with

req := 1;

enet_gnt :=1;

exp_gnt :=1;

endwith;

end

4-8 PAL Equations

TinyRISC

BDMR4103 Evaluation Board User’s Guide 5-1

Chapter 5

Schematics

This section contains the following schematics for the BDMR4103

Evaluation Board:

•Section 5.1, “Microprocessor and Clock Circuitry”

•Section 5.2, “ROMs, SRAMs, and Address Latches”

•Section Figure 5.3, “Ethernet and DRAM Circuitry”

•Section 5.4, “Miscellaneous Circuitry and Connectors”

•Expansion Connector and Boot Device Selection Circuitry

•Section 5.6, “Power and Reset Circuitry”

•Section 5.7, “EJTAG Connectors”

The section also provides brief functional descriptions of key

components.

Designations in parentheses (J9, U6, and so on) refer to the location of

the components on the board.

5-2 Schematics

5.1 Microprocessor and Clock Circuitry

The microprocessor and clock circuitry shown in Figure 5.1 performs the

following functions:

•The LR4103 microprocessor (U1) provides a full-speed evaluation

target.

•A crystal (X1) provides the main clock for the LR4103

microprocessor.

•The oscillator (U5) provides an alternate clock for the

microprocessor. This clock is used when an input frequency other

than 25 MHz is needed.

•Jumpers JP1–6, and JP14 control various LR4103 functions. Refer

to Section 2.2, “Jumper Settings” for further information about these

jumpers.

Microprocessor and Clock Circuitry 5-3

Figure 5.1 Microprocessor and Clock Circuitry

9

&38B9''&25(

'&%$















$ % & '

6,=( 5(9(1*

-2+1 .$/'816.,

'$7( 3$*(

7,7/(

352-(&7







&

&38B9'',2

&38B9''&25(

*1'

9&&

1&6=



&38

<

:

<

+

*

%

&

$

&

$

$

%

(

'

%

*

*

7

5

/

/

.

-

5

3

1

1

0

0

1

&

&

*

.

$

3

'

%

%

&

'

'

(

(

)

)

*

+

-

:

<

:

<

:

<

:

<

:

<

:

<

:

<

:

.

.

/

/

0

0

1

1

3

3

5

5

7

7

8

8

9

9

:

<

<

9

<

:

<

:

<

:

$

9

9

9

9

8

7

9

9

9

9

8

9

9

8

9

<

:

)

$

9

9

<

:

:

<

:

<

0

:

%

$

$

%

/

.

(

%

'

-

%

%

&

8

8

7

5

%

7

3

-

-

-

.

.

3

$

%

$

)

)

*

*

+

+

)

+

$

%

&

&

'

(

$

%

&

&

%

$

(

$

%

+

*

<

&

-

$

'

:

3

:

1

3

<

0

5

&

%

$

8











8





62&.(7

23(1

5

5

.

5



-3

3,75673,7&.3,7063,7',B',173,7'2B73&3,5673,%5($.37'&/.3775,*,13775,*287

3,%5($.

3,567

3,7'2B73&

3,7',B',17

3,706

3,7&.

37'&/.

3775,*,1

3775,*287

6'&61

6'&61

6'&$61

6''03

6''03

6''03

6'5$61

6':(1

6''03

6'&61>@6''03>@6'&/.6':(16'5$616'&$61

6'&/.

































.

8

6'&/.

5



5

.



5

&

8)

3)

&

;

,&(&/.3,&(5;3,&(7;3

,&(7;3

,&(&/.3

,&(5;3



-3



-3

*3>@*3,2>@*35'1*3:(1>@9B5(6(715672871&:$,73

&:$,73

*3

9B5(6(71

*3:(1

*3:(1

*3:(1

*35'1

*3,2

*3,2

*3,2

*3,2

*3

*3

*3

*3

*3

*3:(1

5672871





-3

)$/(3

&%(1

&%(1

&%(1

6'21(3

*171

5(41

'(96(/1

67231

75'<1

,5'<1

)5$0(1

3%&/.

&%(1

,173

,173>@7>@B2871

,173

,173

,173

,173

7B2871

7B2871

,173

)$''53>@

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3>@



-3



-3



-3

0

5



-3

3&67B

7&.

706

7567

73&

73&

73&

3&67B

3&67B

3&67B

3&67B

3&67B

3&67B

3&67B

3&67B

3&67B

3&67B

73&

73&

73&

73&

'&/.

7'273&

7',',17

3&67B

'&/.7'273&3&67>@B>@73&>@75677',',177067&.567'(%8*03

'(%8*03

&

3)

5

5



3%&/.)5$0(1,5'<175'<167231'(96(/15(41*1716'21(3&%(1>@)$/(3

3,7567

0+=

.

1&

287

26&

8

&%(1

)$''53

)$'3

)$'3

)$'3

7B2871

7B2871

,17

,17

,17

,17

331$872)'

33'$7$

33'$7$

33'$7$

3,7&.

3,7567

3&67>@

3&67>@

3&67>@

3&67>@

3&67>@

3&67>@

73&

73&

73&

73&

73&

73&

7567

6&$1B(1$%/(3

6&$1B02'(3

',9$

',9$

;7$/

'(%8*03

,''71

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

5(6(71

*3:(1

*3:(1

*3:(1

*3:(1

*35'1

*3,2

*3,2

*3,2

*3,2

*3

*3

*3

*3

*3

*3

)$/(3

&%(1

&%(1

&%(1

*171

5(41

'(96(/1

67231

75'<1

,5'<1

)5$0(1

3%&/.3

6'&$61?6'2(1

6''03?6'&$61

(;7$/

3//9''

3//966

6(/(&7B3//1

',9&

',9&

%,*B(1',$13

&6+7673

6&$1B5$0:(3

6&$1B,13

3021B2873

6&$1B2873

-7$*$/623

7&.

706

7',B',17

7'2B73&

-7$*B7'2

'&/.

73&

3&67>@

3&67>@

3&67>@

3&67>@

3&67>@

3&67>@

,&(&/.3

,&(5;3

,&(7;3

3,706

3,7',B',17

3,7'2B73&

3,567

3,%5($.

37'&/.

3775,*,1

3775,*287

331,1,7

33'$7$

33'$7$

33'$7$

33'$7$

33'$7$

3316752%(

33%86<

331$&.

3316(/(&7,1

336(/(&7

331)$8/7

33(5525

,17

,17

3//(1

3//(1$56

6'&/.3

)$'3

)$'3

5(6(7B2871

&:$,73

6'21(3

6'&61?6'5$61

6'&61?6'5$61

6''03?6'&$61

6''03?6'&$61

6''03?6'&$61

6':(1

6'5$61

6(/B&.2871

3(1$%/(1

&21752/ $''5(66 $'

3&,

'5$0

0,6&

,177,0(5

&/2&.6 (-7$*

6(5,$/

,&(

0(025< ,17(5)$&(

/5

5-4 Schematics

5.2 ROMs, SRAMs, and Address Latches

The ROMSs, SRAMs and address buffers shown in Figure 5.2 perform

the following functions:

•Four 32 Kbyte SRAM devices (U26, U27, U28, and U29) provide the

BDMR4103 board with 128 Kbytes of SRAM, organized as 32 Kbytes

x 32 bits of memory.

•A 1 Mbyte Flash EPROM (U12) is used as the boot device for the

board. This device is shipped with the board. Jumper J9 determines

whether this device or the EPROM at location U25 is the boot device.

When JP9 is not installed, U12 is the boot PROM.

You can store two boot programs in this EPROM, provided that

neither program is larger than 512 Kbytes. Jumper J8 selects

between any two programs installed.

Refer to Section 2.2.7, “Boot Device Selection (JP9),” for more

information about JP9, and to Section 2.2.6, “Alternate Boot Program

Selection (JP8),” for more information about JP8. Refer to

Section 3.4.3, “Boot EPROMs,” for more information on this subject.

•A socket (U25) houses an optional 1 Mbyte of EPROM. When

installed, the EPROM sits over the top of Flash EPROM (U12). You

can use U25 as an alternate boot device for the board by installing

jumper JP9.

You can store two boot programs in this EPROM, provided that

neither program is larger than 512 Kbytes. Jumper J8 selects

between any two programs installed.

•The SN74LCX16244 buffer (U22) buffers the lower order address

bits FADDRP[11:0] for all devices except the DRAM DIMM. This

buffering is provided to reduce the loading and trace length of these

high-speed signals.

•The LCX245 buffer (U30) buffers the data to and from the EPROMs,

the 7-segment display, and the UART. This buffering is provided to

reduce the loading and trace length of these high-speed signals.

ROMs, SRAMs, and Address Latches 5-5

Figure 5.2 ROMs, SRAMs, and Address Latches

'&%$















$ % & '

6,=( 5(9(1*

-2+1 .$/'816.,

'$7( 3$*(

7,7/(

352-(&7







&

$

$

$

$

$

$

$

$

$

$

$

$

$

$

'

'

'

'

'

'

'

'

$

65$0 .[

$

$

$

$

$

$

$

$

$

$

$

$

$

$

'

'

'

'

'

'

'

'

$

65$0 .[

$

$

$

$

$

$

$

$

$

$

$

$

$

$

'

'

'

'

'

'

'

'

$

65$0 .[

$

$

$

$

$

$

$

$

%

%

%

%

%

%

%

%

* ',5

/&;

2(

2(

2

2

2

2

2

2

2

2

,

,

,

,

,

,

,

,

2(

2(

2

2

2

2

2

2

2

2

,

,

,

,

,

,

,

,

61/&;

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

'4

'4

'4

'4

'4

'4

'4

'4

5<%<

5(6(7

) 7623

0[ )ODVK

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

'4

'4

'4

'4

'4

'4

'4

'4

& ',3

0[ (3520

$

$

$

$

$

$

$

$

$

$

$

$

$

$

'

'

'

'

'

'

'

'

$

65$0 .[



5206  65$0





















































8





























































8



































































8









































































8

































 

8

%'$7$>@

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53>@

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53 %$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

%$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53>@

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

%B5'1

%B:(1 %B:(1

*3>@*3,2>@*35'1*3:(1>@)$/(35(6(71

*3

*35'1

*3:(1

*3

*35'1

*3:(1

*3:(1

5(6(71

*3:(1

*35'1

*3

*35'1

*3

*35'1

*3:(1

520B$

%'B6(/1

)/$6+B6(/1

',3B6(/1





















































8





















































8





















































8

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3>@

5-6 Schematics

5.3 Ethernet and DRAM Circuitry

The Ethernet and DRAM circuitry shown in Figure 5.3 performs the

following functions:

•Ethernet circuitry:

– The Ethernet transformer (U10), in conjunction with the Ethernet

controller, connects the evaluation board to an Ethernet LAN

(local area network).

– The AM79C970A Ethernet Controller (U19). The controller, in

conjunction with the transformer, connects the evaluation board

to an Ethernet LAN.

– Refer to Section 3.7.2, “Am79C970A Ethernet Controller,” for

more information about the controller.

– The RJ45 connector (J7) provides the Ethernet hardware

connection.

•The 100-pin socket (J3) accommodates any standard 100-pin

JEDEC DIMM. A 16 Mbytes SDRAM DIMM is supplied with the

board. However, the socket will also accommodate EDO DRAM.

Jumper JP17 is used to select between SDRAM and EDO devices.

The memory installed in the socket at J3 provides the main system

memory for the board.

Refer to Section 3.2.2, “DIMM Connector (J3),” for further information

about the connector, and to Section 3.4.1, “Synchronous DRAM Dual

Inline Memory Module (SDRAM DIMM),” for further information about

the DIMM. Refer to Section 2.2.14, “EDO/SDRAM Selection (JP17),”

for information about the jumper settings.

Ethernet and DRAM Circuitry 5-7

Figure 5.3 Ethernet and DRAM Circuitry

5-

1&

1&

1&

1&

5'

5'

7'

7'

9

'&%$















$ % & '

6,=( 5(9(1*

-2+1 .$/'816.,

'$7( 3$*(

7,7/(

352-(&7







&









/3) /3)

N

38/6( 3(

9

8)





9

&.(

$

$

$

$

$

$

$

$

$

$

$6'5

%$$('2

%$

&$6

&$6'40%

&$6'40%

&$6'40%

&$6'40%

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

'4

5$6

6$

6$

6$6&/

6'$

2(

5$6&6

5$6&6

&.

&.

&.(

5$6&6

5$6&6

:(

'4

$

 3,1 ',00

9

9

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

$'

&%(

&%(

&%(

&%(

&/.

,'6(/

3$5

5;'

5;'

7;'

7;'

7;3

7;3

;7$/

;7$/

'(96(/

)5$0(

*17

,17$

,5'<

/2&.

3(55

5(4

567

6(55

6723

75'<

7',

7'2

7&.

706

/1.67

/('

/('

/('

9''

9''

9''

9''

9''

9''

9''%

9''%

9''%

9''%

966

966

966

966

966

966

966

966

966

966

966

966%

966%

966%

966%

966%

966%

966%

966%

$966

$966

$9''

$9''

$9''

$9''

966

6/((3

3&QHW

$0&$

287

26&

6WDWXV



/1. 5; &2/ 7;

'5$0(7+(51(7

(WKHUQHW





8

0+=

















































































































































































































8





































































































































-

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3>@

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3





-3

(1(7B6(55

(1(7B3(55

(1(7B3$5

(1(7B/2&.

5



&

8)

&;



5

'

<(//2:

'

5('































8



55



5



















-

*5((1

'

*5((1

'

&;

8)

5672871

(1(7B5(41

3%&/.)5$0(1,5'<175'<167231'(96(/15(41*1716'21(3&%(1>@)$/(3

&%(1

3%&/.

)5$0(1

,5'<1

'(96(/1

75'<1

67231

&%(1

&%(1

&%(1

,173

(1(7B*171

*3,2

*3,2>@

*3,2

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53>@

6'&61

6'&$61

6'5$61

6'&61>@6''03>@6'&/.6':(16'5$616'&$61

6''03

6''03

6''03

6''03

6'&61

6':(1

6'&/.

5-8 Schematics
5.4 Miscellaneous Circuitry and Connectors
Figure 5.4 shows the following miscellaneous circuitry and connectors:
•Lattice ISPLSI2032 PLD (U42) (programmable logic device).
•DS1307 real-time clock (U37). Refer to Section 3.6.1, “Real-Time
Clock (RTC),” for further information.
•An NM24C08 1 Kbyte EEPROM (U13). Refer to Section 3.6.2,
“EEPROM,” for further information.
•7-segment display (U35) and the associated data buffer (U34). Refer
to Section 3.3.4, “7-Segment Display,” for further information.
•The PC16550 UART (universal asynchronous receiver transmitter)
(U24) performs serial-to-parallel and parallel-to-serial data
conversions on data received by and transferred from the board. For
additional information about the UART, refer to the National
Semiconductor datasheet,
PC16550D Universal Asynchronous
Receiver/Transmitter with FIFOs
.
•The MAX3245 (U14) RS232 transceiver provides signal voltage level
translation.
•The SerialICE-1 header (J8) allows you to debug the board using
SerialICE-1 inputs. Refer to Section 3.2.5, “SerialICE-1 Connector
(J8),” for further information.
•The RS232 SerialICE-1 port (J9) allows you to debug the board
using SerialICE-1 inputs. Refer to Section 3.2.4, “RS-232 Serial
Connector for SerialICE-1 Debug Interface(J9),” for further
information.
•The RS232 serial port (J10) allows you to connect serial devices to
the board. Refer to Section 3.2.3, “Serial Port Connector (J10),” for
further information.
•The header (J11) is used to program the PAL (U42). Refer to
Section 3.2.8, “PAL Programming Connector (J11),” for further
information.
•Jumpers JP8 (boot program selection), JP9 (boot device selection),
JP15 (SerialICE-1 input data selection), and JP16 (SerialICE-1 clock
selection). Refer to Section 2.2, “Jumper Settings,” for further
information about these jumpers.
•The 1.8432 MHz oscillator (U6), provides an alternate clock source
for the SerialICE-1 debugger.

Miscellaneous Circuitry and Connectors 5-9

Figure 5.4 Miscellaneous Circuitry and Connectors

9 9

9

1&

287

26&

/&;

'&%$















$ % & '

6,=( 5(9(1*

-2+1 .$/'816.,

'$7( 3$*(

7,7/(

352-(&7







&

/&;

&76

'&'

'65

'75

576

/&;

; ;

64:287

9%$7

6'$

6&/

'6

9

6&/

$ $ $

6'$

10&

9





&/.

















7',

7'2

,63(1

706

7&.











































/$77,&( LVS/6,Y

$

%

%

%

%

%

%

%

%

$

$

$

$

$

$

$

/($%2(%$

&($%

2($%/(%$

&(%$

)&7

$1 $1

(

)

'

'

'

'

'

'

'

:5

,17537

&6

$

$

$

$'6

:5

5'

&6

&6

%$8'287

7;5'<

5;5'<

'',6

287

287

'&'

'65

'75

&76

5&/.

;287 ;,1

'

5'

576

6287

6,1

3&

&

&

&

&

)25&(21

*1'

5,15287

5,15287

5,1

5287

5,1

5287

5,1

5287

7,1 7287

7,1 7287

7,1

7287

9

9

9&&

)25&(2))

,19$/,'

0$;

&76

'&'

'65

'75

576

/&;

6(5,$/ 32576(5,$/ ,&(',63/$<

6HULDO 3RUW

6HULDO ,FH



,QYHUW 520 $

%227 )520 ',3-3

-3













- 

8

















-

5$B0$/(





























 

 















8



 







































































8



















8































.8













































8











































































8

-03

-03

520B$

)/$6+B6(/1

',3B6(/1

%'B6(/1

5(41

(1(7B*171

(;3B*171

3%B5(6(7

,173

,&(5;3

,&(&/.3

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$

%'$7$>@

*3,2

*3,2

*3,2>@

%$''53

8$57B6(/1







8

.

5

64:287

;.+=

%

9B/,7+,80













8

&211B5;3



8

&;

8)

;

0+=



8





-3





-3

3)

&

8)

&

8)

&

3)

&

8)

&

,63B(1

3%&/.

6,B5(6(7

(-7$*B5(6(7

(;3B5(41

6,B5(6(7

(1(7B5(41

%B:(1

*3

5672871

5($'B',631

*3



















-

5$B0$/(



8

*171

,&(7;3,&(7;3



8

%B5'1



-3



-3

.

5

5

0

5

.

5

.

)$''53

)$''53





8

0+=

:5,7(B',631

,63B6&/.

6',

,63B02'(

6'2

%$''53

%$''53

%$''53

%$''53>@

,173

5(6(73

%B5'1

%B:(1

8)

&

8)

&

















-

.

5

%$''53

5-10 Schematics

5.5 Expansion Connector and Boot Device Selection Circuitry

The circuitry shown in Figure 5.5 performs the following functions:

•A 150-pin expansion connector (J2) allows you to expand design and

debugging capabilities to include external logic. Refer to

Section 3.2.1, “Expansion Connector (J2),” for further information.

•At reset, the 74LCX541 (U32) provides the boot device chip select

number and the boot device width to the LR4103. The buffer is

enabled with RSTOUTN.

Expansion Connector and Boot Device Selection Circuitry 5-11

Figure 5.5 Expansion Connector and Boot Device Selection Circuitry

9

9

'&%$















$ % & '

6,=( 5(9(1*

-2+1 .$/'816.,

'$7( 3$*(

7,7/(

352-(&7







&

B',1 B',1

9

**

<

<

<

<

<

<

<

<

$

$

$

$

$

$

$

$

/&;

B',1



(;3$16,21 &211(&725

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

-



































8

,173>@7>@B2871

,173

,173

,173

,173

,173

7B2871

,173

,173

,173

,173

,173

,173

7B2871

,173

*3>@*3,2>@*35'1*3:(1>@5(6(715672871&:$,73

*3,2

*35'1

*3:(1

*3:(1

*3:(1

*3:(1

*3,2

*3,2

*3,2

*3,2

*3

*3

*3

*3

*3

5672871

*3

*3,2

*3,2

*3,2

*3:(1

*3:(1

*3:(1

*3:(1

*3

*3

*3

*3

*3

&:$,73

5672871

5(6(71

*3

*35'1

*3,2

)$'3

)$'3>@

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3

)$'3



-3

(;3B5(41

(1(7B5(41

64:287

































8

.

































8

.

































8

.

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

%

-

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

&

-

(;3B*171

(;3B5(41

%227&)*

%227&)*

%227&)*

%227&)*

%227&)*

%227&)*>@

%227&)*

%227&)*

%227&)*

3%&/.)5$0(1,5'<175'<167231'(96(/15(41*1716'21(3&%(1>@)$/(3

'(96(/1

)$/(3

6'21(3

&%(1

&%(1

&%(1

&%(1

3%&/.

67231

75'<1

,5'<1

)5$0(1

&%(1

&%(1

&%(1

)5$0(1

'(96(/1

67231

75'<1

,5'<1

(1(7B6(55

(1(7B3(55

(1(7B3$5

(1(7B/2&.

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53

)$''53>@

6''03

6'&61

6'&61

6''03

6''03

6'&61>@6''03>@6'&/.6':(16'5$616'&$61

6':(1

6''03

6'5$61

6'&$61

6'&/.

5-12 Schematics

5.6 Power and Reset Circuitry

The power and reset circuitry shown in Figure 5.6 performs the following

functions:

•The power connector (J1) supplies the board with DC power by

means of the switching AC adapter. Refer to Section 3.2.9, “Power

Supply Connector (J1),” for further information.

•The red Power LED (D5) comes on when power is applied to the

board, and it stays on while power is being applied.

•The MAX708 device (U33) generates the reset signal for the board.

•The voltage regulator (U16) provides the VDD core voltage. The

voltage regulator (U36) provides the 3.3 V power supply for the

board.

•Heatsink HS1 provides the heatsink for the regulator at U36, and

HS2 provides the heatsink for the regulator at U16.

•Test points TP1, TP2, TP3, TP4, TP5, and TP6 provide grounding

for an oscilloscope during testing.

•0.1 µF decoupling capacitors.

Power and Reset Circuitry 5-13

Figure 5.6 Power and Reset Circuitry

8) 8)

&%7'

8) 8)

8) 8)8) 8)8)8)8)8) 8) 8) 8) 8)

9













8)8)8)8)8)8)

8) 8) 8) 8) 8) 8) 8) 8)

8)8)8)8)8)

8)8)8)8)

8)

8)8)8)

+($76,1.

'&%$















$ % & '

6,=( 5(9(1*

-2+1 .$/'816.,

'$7( 3$*(

7,7/(

352-(&7







&

+($76,1.

&38B9''&25(

8)

9

8)

8) 8)





&38B9'',2













9

&38B9''&25(

&38B9'',2

9

287,1

*1'

/7&7

287,1

$'-

/7&7DGM

9&&

*1'

5(6(7

3),

3)2

5(6(7

0$;

&%7'













8)8)

8)

32:(5 /(' 9 *HQHUDWLRQ FLUFXLW



32:(55(6(7



-3

'2B127B/2$'

5

23(1

&;

&; &;

&

8)

&

8)

&

73





8















8





8





8





-

9B5(6(71

8)

&

8)

&



-3

&

8)

&

8)

&;&;

&;

&;

&;

5(6(71

5(6(73

'

5('



-3

+6



-3

B

5

5

B



5

+6

&; &; &;

&;

&; &; &; &;

&; &; &; &; &;

&;&;&;&;&;&;&;&;

&; &; &; &; &; &;

&

8)

&

8)

&

8)



6

3%B5(6(7

&;&;&;&;&; &; &; &; &;&; &;&;

&;&;

7373 73 73 73





8

&;&;

5-14 Schematics

5.7 EJTAG Connectors

The EJTAG connectors shown in Figure 5.7 performs the following

functions:

•EJTAG connectors and debug indicator:

– EJTAG connector (J4) provides basic EJTAG debugging

capabilities, including break and run control. Refer to

Section 3.2.7.2, “EJTAG Connector (J4),” for additional

information.

– EJTAG connector (J5) provides the same EJTAG debugging

capabilities as J4. In addition, it supports PC trace. Refer to

Section 3.2.7.3, “EJTAG Connector (J5),” for further information.

– The EJTAG connector (J6) is used only for factory testing.

– The yellow LED (D6) comes on when the LR4103 is in debug

mode.

Refer to Section 3.2.7.1, “Overview of EJTAG Functions,” for additional

information about EJTAG functions. For detailed EJTAG information, refer

to the EJTAG speciﬁcation published by Philips Semiconductors and

MIPS licensees.

EJTAG Connectors 5-15

Figure 5.7 EJTAG Connectors

'&%$















$ % & '

6,=( 5(9(1*

-2+1 .$/'816.,

'$7( 3$*(

7,7/(

352-(&7







&

9

*1'

9&&

1&6=

9

/&;

'(%8* $&7,9(

(-7$*







































































































 

-



























-

'2B127B/2$'































8 23(1

5

23(1

.

5



5



















 





-

37'&/.

3,7'2B73&

3,%5($.

3775,*,1

3,7',B',17

3,706

3,7&.

3,567

3775,*287

3,%5($.

3,7'2B73&

3,75673,7&.3,7063,7',B',173,7'2B73&3,5673,%5($.37'&/.3775,*,13775,*287

3,7567

3,7',B',17

3,706

3,7&.

3,567

3775,*,1

3775,*287

37'&/.

3,7567

3&67B

7',',17

7&.

706

(-7$*B5(6(7

'(%8*03

(-7$*B5(6(7

7&.

706

7',',17

7567

7'273&

3&67B

3&67B

'&/.

3&67B

3&67B

3&67B

73&

3&67B

3&67B

3&67B

73&

3&67B

3&67B

3&67B

73&

73&

73&

73&

73&

'&/.7'273&3&67>@B>@73&>@75677',',177067&.(-7$*B5(6(7'(%8*03

(-7$*B5(6(7

7',',17

706

7&.

7567



8

-03

-03

5B%8)B7'2































8









8

































.

8

'

<(//2:

5B3,706

5B3,7&.

5B3,567

5B3,7',B',17

5B3,7567

5B73& 5B73&

5B3&67B 5B3&67B

5B3&67B5B3&67B

5B3&67B 5B3&67B

5B73& 5B73&

5B3&67B 5B3&67B

5B3&67B5B3&67B

5B73&

5B3&67B

5B3&67B

5B3&67B

5B73&

5B73&

5B73&

5B73&































8 































8 

5B3&67B5B3&67B

































8

23(1

5B7'273&5B7'273&

5B3&67B

5B3&67B

5B3&67B

5B'&/.

23(1

5

5-16 Schematics

TinyRISC

BDMR4103 Evaluation Board User’s Guide 6-1

Chapter 6

Bill of Materials

Table 6.1 lists the bill of materials for the BDMR4103 Evaluation Board.

The reference numbers correspond to those used in the schematics. The

board contains a total of 190 components.

Note that, since different manufacturers categorize their products in

different ways, some of the categories shown in Table 6.1 may not be

relevant for all products.

Key to packaging information:

•The numbers shown in the packaging information frequently refer to

the number of pins on the package. For example, 14PDIP indicates

a 14-pin dual inline package, 44 PLCC indicates a 44-pin plastic

leaded chip carrier, and so forth. In other cases, the number refers

to a standard packaging type, such as capacitor package 1206.

•In the case of onboard devices, the numbers (C1, J1, and so forth)

represent board locations. Items designated ACC, are removable

accessory modules, such as the SDRAM DIMM, that are supplied

with the board.

6-2 Bill of Materials

Table 6.1 BDMR4103 Bill of Materials

Qty. Reference

Designator(s) Device Name Package Value/Type Manufacturer Manufacturer’s Part

Number

1 ACC1 16 Mbytes SDRAM

DIMM 100-pin DIMM – Micron MT2LSDT432UG-10

1 ACC2 Power Supply – 5 V @ 4 A Phihong PSA-30U050

1 B1 Lithium Battery Battery 3 V Panasonic BR1225-1HC

3 C1, C2, C11 Capacitors 0805 20 pF – –

1 C3 Capacitor 1206 0.47 µF– –

10 C4, C5, C13–

16, C18-21 Tantalum Capacitors – 22 µF– –

3 C6, C8, C9 1206 Capacitors 1206 0.33 µF– –

2 C7, C10 0805 Capacitors 0805 0.047 µF– –

1 C12 0805 Capacitor 0805 47 pF – –

1 C17 Tantalum Capacitor – 10 µF– –

52 CX1–49,

CX60–62, Capacitors 0805 0.1 µF– –

2 CX58, CX59 Capacitors 0805 0.01 µF– –

2 D1, D2 Small LEDs 1206 Green Hewlett

Packard HSMG-C650

2 D3, D6 Small LEDs 1206 Yellow HSMY-C650

2 D4, D5 Small LEDs 1206 Red HSMR-C650

(Sheet 1 of 6)

6-3

2 HS1, HS2 Heatsinks TO-220-HS – AAVID 577002B00000

1 J1 Power Plug R/A 2.1 mm – Switchcraft RAPC722

1 J2 150-Pin DIN 41612

Connector Typec R/A Pins Amp 650907-5

1 J3 100-Pin DIMM Socket 100-Pin DIMM – Molex 71251-5101

1 J4 16-Pin Header 16-Pin Header, 8 x 2,

0.1 x 0.1 –– –

1 J5 52-Pin High-Speed

Header 52-Pin Header,

0.05 x 0.05 – Mill-Max 852-10-052-30-001

1 J7 RJ45 Connector – – – –

1 J8 10-Pin Header 10-Pin Header,

0.1 x 0.1 –– –

2 J9, J10 9-Pin D Subconnector MIL-C-24308 R/A Male – –

1 J11 8 x 1 Header 8-Pin .025 Square

1x8 –– –

14 JP1–12, JP18 2-Pin Headers for

Jumpers 2-Pin .025 Square – – –

4 JP14–17 3-Pin Headers for

Jumpers 3-Pin .025 Square – – –

1 R1 Resistor 0805 10 MΩ––

2 R2, R11 Resistors 0805 1.5 kΩ––

Table 6.1 BDMR4103 Bill of Materials (Cont.)

Qty. Reference

Designator(s) Device Name Package Value/Type Manufacturer Manufacturer’s Part

Number

(Sheet 2 of 6)

6-4 Bill of Materials

1 R3 Resistor 0805 20 Ω––

5 R4–7, R17 Resistors 0805 130 Ω––

9 R8–10,

R20–23, R26 Resistors 0805 10 kΩ––

1 R12 Resistor 0805 1 MΩ––

1 R13 Resistor 0805 330 Ω––

2 R14 Resistor 0805 54.9 Ω±1% – –

1 R15 Resistor 0805 124 Ω±1% – –

1 R18 Resistor 0805 4.3 Ω––

1 R19, R28 Resistors 0805 0.0 Ω− –

1 S1 SPST Switch 2-Pin DIP Switch – Alcoswitch TP11CGPC0

6 TP1–6 Test Points .025 Square Pin – – –

1 U1 LR4103

Microprocessor 256 PBGA – LSI Logic –

6 U2–3, U18,

U20, U38 16-Pin 15-Resistor

Arrays 16-Pin QSOP 4.7 kΩBourns 2QSP16-TJ2-XXX

1 U5 Oscillator 14-Pin DIP Socket – – –

1 U6 Oscillator 14-Pin DIP 1.8432 MHz – –

Table 6.1 BDMR4103 Bill of Materials (Cont.)

Qty. Reference

Designator(s) Device Name Package Value/Type Manufacturer Manufacturer’s Part

Number

(Sheet 3 of 6)

6-5

4 U7–9 16-Pin 8-Resistor

Arrays 16-Pin QSOP 33 ΩBourns 2QSP16-TJ1-XXX

1 U10 Ethernet Transformer

10BASE-T Module 16-Pin Small – Pulse PE-68025

1 U11 74LCX14 14-Pin SOIC – National

Semiconductor 74LCX14M

1 U12 1 Mbyte FLASH ROM 40-Pin TSOP – Advanced

Micro Devices AM29F080-90EC

1 U13 1 Kbyte EEPROM IIC 8-Pin SOIC – Fairchild

Semiconductor NS24C08M8

1 U14 Max 3245 RS232

transceiver 28-Pin SSOP – Maxim MAX3245CAI

1 U15 Small 3.3 V Oscillator 4-Pin SOJ 20 MHz – –

1 U16 Linear Adjustable Volt-

age Regulator TO-220 – Linear LT1084CT

1 U17 Small 16-Pin 8-Resis-

tor Array 16-Pin QSOP 1 kΩBourns 2QSP16-TJ1-XXX

1 U19 PCNet PCI Device

(Ethernet Controller) 144-Pin TQFP – Advanced

Micro Devices AM79C970AVC

1 U22 74LCX16244 (Address

Buffer) 48-Pin TSSOP – National

Semiconductor 74LCX16244MTD

1 U24 UART 44-Pin PLCC – National

Semiconductor PC16550DV

Table 6.1 BDMR4103 Bill of Materials (Cont.)

Qty. Reference

Designator(s) Device Name Package Value/Type Manufacturer Manufacturer’s Part

Number

(Sheet 4 of 6)

6-6 Bill of Materials

1 U25 32-Pin DIP Socket 32-Pin DIP – – –

4 U26–29 32 x 8 SRAM 28SOJ300MIL – IDT IDT71V254SA12Y

1 U30 74LCX245 20-Pin SOIC −National

Semiconductor 74LCX245WM

2 U31, U39 Tiny UHS and Gate SOT23-5 – Fairchild NC7SZ08M5

1 U32 74LCX541 20-Pin SOIC – National

Semiconductor 74LCX541WM

1 U33 Max 708 8-Pin SOIC – Maxim MAX708CSA

1 U34 74FCT543 24-Pin QSOP – Quality

Semiconductor QS74FCT543ATQ

1 U35 7-Segment Display 10-Pin DIP – Hewlett

Packard HDSP-F101

1 U36 3.3 V Linear Regulator TO-220 – Linear LT1084CT-3.3

1 U37 IIC Real-Time Clock 8-Pin SOIC – Dallas

Semiconductor DS1307Z

1 U41 Dual FET Bus Switch 8-Pin SOIC – Texas

Instruments SN74CBTD3306D

1 U42 CPLD ISP

(PAL) 44-Pin TQFP – Lattice

Semiconductor ISPLSI2032V-100LT44

1 X1 Crystal HC 28.75 MHz – –

Table 6.1 BDMR4103 Bill of Materials (Cont.)

Qty. Reference

Designator(s) Device Name Package Value/Type Manufacturer Manufacturer’s Part

Number

(Sheet 5 of 6)

6-7

1 X2 Crystal HC 14.7456

MHz ––

1 X3 Crystal Cylinder 32.768 KHz – –

Table 6.1 BDMR4103 Bill of Materials (Cont.)

Qty. Reference

Designator(s) Device Name Package Value/Type Manufacturer Manufacturer’s Part

Number

(Sheet 6 of 6)

6-8 Bill of Materials

Customer Feedback

We would appreciate your feedback on this document. Please copy the

following page, add your comments, and fax it to us at the number

shown.

If appropriate, please also fax copies of any marked-up pages from this

document.

Important: Please include your name, phone number, fax number, and

company address so that we may contact you directly for

clariﬁcation or additional information.

Thank you for your help in improving the quality of our documents.

Customer Feedback

Reader’s Comments

Fax your comments to: LSI Logic Corporation

Technical Publications

M/S E-198

Fax: 408.433.4333

Please tell us how you rate this document:

TinyRISC

BDMR4103

Evaluation Board User’s Guide

Place a check mark in the appropriate

blank for each category.

What could we do to improve this document?

If you found errors in this document, please specify the error and page

number. If appropriate, please fax a marked-up copy of the page(s).

Please complete the information below so that we may contact you

directly for clariﬁcation or additional information.

Excellent Good Average Fair Poor

Completeness of information ____ ____ ____ ____ ____

Clarity of information ____ ____ ____ ____ ____

Ease of ﬁnding information ____ ____ ____ ____ ____

Technical content ____ ____ ____ ____ ____

Usefulness of examples and

illustrations ____ ____ ____ ____ ____

Overall manual ____ ____ ____ ____ ____

Name Date

Telephone

Title

Company Name

Street

City, State, Zip

Department Mail Stop

Fax

U.S. Distributors

by State

A. E. Avnet Electronics

http://www.hh.avnet.com

B. M. Bell Microproducts,

Inc. (for HAB’s)

http://www.bellmicro.com

I. E. Insight Electronics

http://www.insight-electronics.com

W. E. Wyle Electronics

http://www.wyle.com

Alabama

Daphne

I. E. Tel: 334.626.6190

Huntsville

A. E. Tel: 256.837.8700

B. M. Tel: 256.705.3559

I. E. Tel: 256.830.1222

W. E. Tel: 800.964.9953

Alaska

A. E. Tel: 800.332.8638

Arizona

Phoenix

A. E. Tel: 480.736.7000

B. M. Tel: 602.267.9551

W. E. Tel: 800.528.4040

Tempe

I. E. Tel: 480.829.1800

Tucson

A. E. Tel: 520.742.0515

Arkansas

W. E. Tel: 972.235.9953

California

Agoura Hills

B. M. Tel: 818.865.0266

Granite Bay

B. M. Tel: 916.523.7047

Irvine

A. E. Tel: 949.789.4100

B. M. Tel: 949.470.2900

I. E. Tel: 949.727.3291

W. E. Tel: 800.626.9953

Los Angeles

A. E. Tel: 818.594.0404

W. E. Tel: 800.288.9953

Sacramento

A. E. Tel: 916.632.4500

W. E. Tel: 800.627.9953

San Diego

A. E. Tel: 858.385.7500

B. M. Tel: 858.597.3010

I. E. Tel: 800.677.6011

W. E. Tel: 800.829.9953

San Jose

A. E. Tel: 408.435.3500

B. M. Tel: 408.436.0881

I. E. Tel: 408.952.7000

Santa Clara

W. E. Tel: 800.866.9953

Woodland Hills

A. E. Tel: 818.594.0404

Westlake Village

I. E. Tel: 818.707.2101

Colorado

Denver

A. E. Tel: 303.790.1662

B. M. Tel: 303.846.3065

W. E. Tel: 800.933.9953

Englewood

I. E. Tel: 303.649.1800

Idaho Springs

B. M. Tel: 303.567.0703

Connecticut

Cheshire

A. E. Tel: 203.271.5700

I. E. Tel: 203.272.5843

Wallingford

W. E. Tel: 800.605.9953

Delaware

North/South

A. E. Tel: 800.526.4812

Tel: 800.638.5988

B. M. Tel: 302.328.8968

W. E. Tel: 856.439.9110

Florida

Altamonte Springs

B. M. Tel: 407.682.1199

I. E. Tel: 407.834.6310

Boca Raton

I. E. Tel: 561.997.2540

Bonita Springs

B. M. Tel: 941.498.6011

Clearwater

I. E. Tel: 727.524.8850

Fort Lauderdale

A. E. Tel: 954.484.5482

W. E. Tel: 800.568.9953

Miami

B. M. Tel: 305.477.6406

Orlando

A. E. Tel: 407.657.3300

W. E. Tel: 407.740.7450

Tampa

W. E. Tel: 800.395.9953

St. Petersburg

A. E. Tel: 727.507.5000

Georgia

Atlanta

A. E. Tel: 770.623.4400

B. M. Tel: 770.980.4922

W. E. Tel: 800.876.9953

Duluth

I. E. Tel: 678.584.0812

Hawaii

A. E. Tel: 800.851.2282

Idaho

A. E. Tel: 801.365.3800

W. E. Tel: 801.974.9953

Illinois

North/South

A. E. Tel: 847.797.7300

Tel: 314.291.5350

Chicago

B. M. Tel: 847.413.8530

W. E. Tel: 800.853.9953

Schaumburg

I. E. Tel: 847.885.9700

Indiana

Fort Wayne

I. E. Tel: 219.436.4250

W. E. Tel: 888.358.9953

Indianapolis

A. E. Tel: 317.575.3500

Iowa

W. E. Tel: 612.853.2280

Cedar Rapids

A. E. Tel: 319.393.0033

Kansas

W. E. Tel: 303.457.9953

Kansas City

A. E. Tel: 913.663.7900

Lenexa

I. E. Tel: 913.492.0408

Kentucky

W. E. Tel: 937.436.9953

Central/Northern/ Western

A. E. Tel: 800.984.9503

Tel: 800.767.0329

Tel: 800.829.0146

Louisiana

W. E. Tel: 713.854.9953

North/South

A. E. Tel: 800.231.0253

Tel: 800.231.5775

Maine

A. E. Tel: 800.272.9255

W. E. Tel: 781.271.9953

Maryland

Baltimore

A. E. Tel: 410.720.3400

W. E. Tel: 800.863.9953

Columbia

B. M. Tel: 800.673.7461

I. E. Tel: 410.381.3131

Massachusetts

Boston

A. E. Tel: 978.532.9808

W. E. Tel: 800.444.9953

Burlington

I. E. Tel: 781.270.9400

Marlborough

B. M. Tel: 800.673.7459

Woburn

B. M. Tel: 800.552.4305

Michigan

Brighton

I. E. Tel: 810.229.7710

Detroit

A. E. Tel: 734.416.5800

W. E. Tel: 888.318.9953

Clarkston

B. M. Tel: 877.922.9363

Minnesota

Champlin

B. M. Tel: 800.557.2566

Eden Prairie

B. M. Tel: 800.255.1469

Minneapolis

A. E. Tel: 612.346.3000

W. E. Tel: 800.860.9953

St. Louis Park

I. E. Tel: 612.525.9999

Mississippi

A. E. Tel: 800.633.2918

W. E. Tel: 256.830.1119

Missouri

W. E. Tel: 630.620.0969

St. Louis

A. E. Tel: 314.291.5350

I. E. Tel: 314.872.2182

Montana

A. E. Tel: 800.526.1741

W. E. Tel: 801.974.9953

Nebraska

A. E. Tel: 800.332.4375

W. E. Tel: 303.457.9953

Nevada

Las Vegas

A. E. Tel: 800.528.8471

W. E. Tel: 702.765.7117

New Hampshire

A. E. Tel: 800.272.9255

W. E. Tel: 781.271.9953

New Jersey

North/South

A. E. Tel: 201.515.1641

Tel: 609.222.6400

Mt. Laurel

I. E. Tel: 856.222.9566

Pine Brook

B. M. Tel: 973.244.9668

W. E. Tel: 800.862.9953

Parsippany

I. E. Tel: 973.299.4425

Wayne

W. E. Tel: 973.237.9010

New Mexico

W. E. Tel: 480.804.7000

Albuquerque

A. E. Tel: 505.293.5119

U.S. Distributors

by State

(Continued)

New York

Hauppauge

I. E. Tel: 516.761.0960

Long Island

A. E. Tel: 516.434.7400

W. E. Tel: 800.861.9953

Rochester

A. E. Tel: 716.475.9130

I. E. Tel: 716.242.7790

W. E. Tel: 800.319.9953

Smithtown

B. M. Tel: 800.543.2008

Syracuse

A. E. Tel: 315.449.4927

North Carolina

Raleigh

A. E. Tel: 919.859.9159

I. E. Tel: 919.873.9922

W. E. Tel: 800.560.9953

North Dakota

A. E. Tel: 800.829.0116

W. E. Tel: 612.853.2280

Ohio

Cleveland

A. E. Tel: 216.498.1100

W. E. Tel: 800.763.9953

Dayton

A. E. Tel: 614.888.3313

I. E. Tel: 937.253.7501

W. E. Tel: 800.575.9953

Strongsville

B. M. Tel: 440.238.0404

Valley View

I. E. Tel: 216.520.4333

Oklahoma

W. E. Tel: 972.235.9953

Tulsa

A. E. Tel: 918.459.6000

I. E. Tel: 918.665.4664

Oregon

Beaverton

B. M. Tel: 503.524.1075

I. E. Tel: 503.644.3300

Portland

A. E. Tel: 503.526.6200

W. E. Tel: 800.879.9953

Pennsylvania

Mercer

I. E. Tel: 412.662.2707

Philadelphia

A. E. Tel: 800.526.4812

B. M. Tel: 877.351.2355

W. E. Tel: 800.871.9953

Pittsburgh

A. E. Tel: 412.281.4150

W. E. Tel: 440.248.9996

Rhode Island

A. E. 800.272.9255

W. E. Tel: 781.271.9953

South Carolina

A. E. Tel: 919.872.0712

W. E. Tel: 919.469.1502

South Dakota

A. E. Tel: 800.829.0116

W. E. Tel: 612.853.2280

Tennessee

W. E. Tel: 256.830.1119

East/West

A. E. Tel: 800.241.8182

Tel: 800.633.2918

Texas

Arlington

B. M. Tel: 817.417.5993

Austin

A. E. Tel: 512.219.3700

B. M. Tel: 512.258.0725

I. E. Tel: 512.719.3090

W. E. Tel: 800.365.9953

Dallas

A. E. Tel: 214.553.4300

B. M. Tel: 972.783.4191

W. E. Tel: 800.955.9953

El Paso

A. E. Tel: 800.526.9238

Houston

A. E. Tel: 713.781.6100

B. M. Tel: 713.917.0663

W. E. Tel: 800.888.9953

Richardson

I. E. Tel: 972.783.0800

Rio Grande Valley

A. E. Tel: 210.412.2047

Stafford

I. E. Tel: 281.277.8200

Utah

Centerville

B. M. Tel: 801.295.3900

Murray

I. E. Tel: 801.288.9001

Salt Lake City

A. E. Tel: 801.365.3800

W. E. Tel: 800.477.9953

Vermont

A. E. Tel: 800.272.9255

W. E. Tel: 716.334.5970

Virginia

A. E. Tel: 800.638.5988

W. E. Tel: 301.604.8488

Haymarket

B. M. Tel: 703.754.3399

Springﬁeld

B. M. Tel: 703.644.9045

Washington

Kirkland

I. E. Tel: 425.820.8100

Maple Valley

B. M. Tel: 206.223.0080

Seattle

A. E. Tel: 425.882.7000

W. E. Tel: 800.248.9953

West Virginia

A. E. Tel: 800.638.5988

Wisconsin

Milwaukee

A. E. Tel: 414.513.1500

W. E. Tel: 800.867.9953

Wauwatosa

I. E. Tel: 414.258.5338

Wyoming

A. E. Tel: 800.332.9326

W. E. Tel: 801.974.9953

Sales Ofﬁces and Design

Resource Centers

LSI Logic Corporation

Corporate Headquarters

1551 McCarthy Blvd

Milpitas CA 95035

Tel: 408.433.8000

Fax: 408.433.8989

NORTH AMERICA

California

Irvine

18301 Von Karman Ave

Suite 900

Irvine, CA 92612

♦Tel: 949.809.4600

Fax: 949.809.4444

Pleasanton Design Center

5050 Hopyard Road, 3rd Floor

Suite 300

Pleasanton, CA 94588

Tel: 925.730.8800

Fax: 925.730.8700

San Diego

7585 Ronson Road

Suite 100

San Diego, CA 92111

Tel: 858.467.6981

Fax: 858.496.0548

Silicon Valley

1551 McCarthy Blvd

Sales Ofﬁce

M/S C-500

Milpitas, CA 95035

♦Tel: 408.433.8000

Fax: 408.954.3353

Design Center

M/S C-410

Tel: 408.433.8000

Fax: 408.433.7695

Wireless Design Center

11452 El Camino Real

Suite 210

San Diego, CA 92130

Tel: 858.350.5560

Fax: 858.350.0171

Colorado

Boulder

4940 Pearl East Circle

Suite 201

Boulder, CO 80301

♦Tel: 303.447.3800

Fax: 303.541.0641

Colorado Springs

4420 Arrowswest Drive

Colorado Springs, CO 80907

Tel: 719.533.7000

Fax: 719.533.7020

Fort Collins

2001 Danﬁeld Court

Fort Collins, CO 80525

Tel: 970.223.5100

Fax: 970.206.5549

Florida

Boca Raton

2255 Glades Road

Suite 324A

Boca Raton, FL 33431

Tel: 561.989.3236

Fax: 561.989.3237

Georgia

Alpharetta

2475 North Winds Parkway

Suite 200

Alpharetta, GA 30004

Tel: 770.753.6146

Fax: 770.753.6147

Illinois

Oakbrook Terrace

Two Mid American Plaza

Suite 800

Oakbrook Terrace, IL 60181

Tel: 630.954.2234

Fax: 630.954.2235

Kentucky

Bowling Green

1262 Chestnut Street

Bowling Green, KY 42101

Tel: 270.793.0010

Fax: 270.793.0040

Maryland

Bethesda

6903 Rockledge Drive

Suite 230

Bethesda, MD 20817

Tel: 301.897.5800

Fax: 301.897.8389

Massachusetts

Waltham

200 West Street

Waltham, MA 02451

♦Tel: 781.890.0180

Fax: 781.890.6158

Burlington - Mint Technology

77 South Bedford Street

Burlington, MA 01803

Tel: 781.685.3800

Fax: 781.685.3801

Minnesota

Minneapolis

8300 Norman Center Drive

Suite 730

Minneapolis, MN 55437

♦Tel: 612.921.8300

Fax: 612.921.8399

New Jersey

Red Bank

125 Half Mile Road

Suite 200

Red Bank, NJ 07701

Tel: 732.933.2656

Fax: 732.933.2643

Cherry Hill - Mint Technology

215 Longstone Drive

Cherry Hill, NJ 08003

Tel: 856.489.5530

Fax: 856.489.5531

New York

Fairport

550 Willowbrook Ofﬁce Park

Fairport, NY 14450

Tel: 716.218.0020

Fax: 716.218.9010

North Carolina

Raleigh

Phase II

4601 Six Forks Road

Suite 528

Raleigh, NC 27609

Tel: 919.785.4520

Fax: 919.783.8909

Oregon

Beaverton

15455 NW Greenbrier Parkway

Suite 235

Beaverton, OR 97006

Tel: 503.645.0589

Fax: 503.645.6612

Texas

Austin

9020 Capital of TX Highway North

Building 1

Suite 150

Austin, TX 78759

Tel: 512.388.7294

Fax: 512.388.4171

Plano

500 North Central Expressway

Suite 440

Plano, TX 75074

♦Tel: 972.244.5000

Fax: 972.244.5001

Houston

20405 State Highway 249

Suite 450

Houston, TX 77070

Tel: 281.379.7800

Fax: 281.379.7818

Canada

Ontario

Ottawa

260 Hearst Way

Suite 400

Kanata, ON K2L 3H1

♦Tel: 613.592.1263

Fax: 613.592.3253

INTERNATIONAL

France

Paris

LSI Logic S.A.

Immeuble Europa

53 bis Avenue de l'Europe

B.P. 139

78148 Velizy-Villacoublay

Cedex, Paris

♦Tel: 33.1.34.63.13.13

Fax: 33.1.34.63.13.19

Germany

Munich

LSI Logic GmbH

Orleansstrasse 4

81669 Munich

♦Tel: 49.89.4.58.33.0

Fax: 49.89.4.58.33.108

Stuttgart

Mittlerer Pfad 4

D-70499 Stuttgart

♦Tel: 49.711.13.96.90

Fax: 49.711.86.61.428

Italy

Milan

LSI Logic S.P.A.

CentroDirezionaleColleoniPalazzo

Orione Ingresso 1

20041 Agrate Brianza, Milano

♦Tel: 39.039.687371

Fax: 39.039.6057867

Japan

Tokyo

LSI Logic K.K.

Rivage-Shinagawa Bldg. 14F

4-1-8 Kounan

Minato-ku, Tokyo 108-0075

♦Tel: 81.3.5463.7821

Fax: 81.3.5463.7820

Osaka

Crystal Tower 14F

1-2-27 Shiromi

Chuo-ku, Osaka 540-6014

♦Tel: 81.6.947.5281

Fax: 81.6.947.5287

Sales Ofﬁces and Design

Resource Centers

(Continued)

Korea

Seoul

LSI Logic Corporation of

Korea Ltd

10th Fl., Haesung 1 Bldg.

942, Daechi-dong,

Kangnam-ku, Seoul, 135-283

Tel: 82.2.528.3400

Fax: 82.2.528.2250

The Netherlands

Eindhoven

LSI Logic Europe Ltd

World Trade Center Eindhoven

Building ‘Rijder’

Bogert 26

5612 LZ Eindhoven

Tel: 31.40.265.3580

Fax: 31.40.296.2109

Singapore

LSI Logic Pte Ltd

7 Temasek Boulevard

#28-02 Suntec Tower One

Singapore 038987

Tel: 65.334.9061

Fax: 65.334.4749

Sweden

Stockholm

LSI Logic AB

Finlandsgatan 14

164 74 Kista

♦Tel: 46.8.444.15.00

Fax: 46.8.750.66.47

Taiwan

Taipei

LSI Logic Asia, Inc.

Taiwan Branch

10/F 156 Min Sheng E. Road

Section 3

Taipei, Taiwan R.O.C.

Tel: 886.2.2718.7828

Fax: 886.2.2718.8869

United Kingdom

Bracknell

LSI Logic Europe Ltd

Greenwood House

London Road

Bracknell, Berkshire RG12 2UB

♦Tel: 44.1344.426544

Fax: 44.1344.481039

♦Sales Ofﬁces with

Design Resource Centers

International Distributors

Australia

New South Wales

Reptechnic Pty Ltd

3/36 Bydown Street

Neutral Bay, NSW 2089

♦Tel: 612.9953.9844

Fax: 612.9953.9683

Belgium

Acal nv/sa

Lozenberg 4

1932 Zaventem

Tel: 32.2.7205983

Fax: 32.2.7251014

China

Beijing

LSI Logic International

Services Inc.

Beijing Representative

Ofﬁce

Room 708

Canway Building

66 Nan Li Shi Lu

Xicheng District

Beijing 100045, China

Tel: 86.10.6804.2534 to 38

Fax: 86.10.6804.2521

France

Rungis Cedex

Azzurri Technology France

22 Rue Saarinen

Sillic 274

94578 Rungis Cedex

Tel: 33.1.41806310

Fax: 33.1.41730340

Germany

Haar

EBV Elektronik

Hans-Pinsel Str. 4

D-85540 Haar

Tel: 49.89.4600980

Fax: 49.89.46009840

Munich

Avnet Emg GmbH

Stahlgruberring 12

81829 Munich

Tel: 49.89.45110102

Fax: 49.89.42.27.75

Wuennenberg-Haaren

Peacock AG

Graf-Zepplin-Str 14

D-33181 Wuennenberg-Haaren

Tel: 49.2957.79.1692

Fax: 49.2957.79.9341

Hong Kong

AVT Industrial Ltd

Unit 608 Tower 1

Cheung Sha Wan Plaza

833 Cheung Sha Wan Road

Kowloon, Hong Kong

Tel: 852.2428.0008

Fax: 852.2401.2105

Serial System (HK) Ltd

2301 Nanyang Plaza

57 Hung To Road, Kwun Tong

Kowloon, Hong Kong

Tel: 852.2995.7538

Fax: 852.2950.0386

India

Bangalore

Spike Technologies India

Private Ltd

951, Vijayalakshmi Complex,

2nd Floor, 24th Main,

J P Nagar II Phase,

Bangalore, India 560078

♦Tel: 91.80.664.5530

Fax: 91.80.664.9748

Israel

Tel Aviv

Eastronics Ltd

11 Rozanis Street

P.O. Box 39300

Tel Aviv 61392

Tel: 972.3.6458777

Fax: 972.3.6458666

Japan

Tokyo

Daito Electron

Sogo Kojimachi No.3 Bldg

1-6 Kojimachi

Chiyoda-ku, Tokyo 102-8730

Tel: 81.3.3264.0326

Fax: 81.3.3261.3984

Global Electronics

Corporation

Nichibei Time24 Bldg. 35 Tansu-cho

Shinjuku-ku, Tokyo 162-0833

Tel: 81.3.3260.1411

Fax: 81.3.3260.7100

Technical Center

Tel: 81.471.43.8200

Marubeni Solutions

1-26-20 Higashi

Shibuya-ku, Tokyo 150-0001

Tel: 81.3.5778.8662

Fax: 81.3.5778.8669

Shinki Electronics

Myuru Daikanyama 3F

3-7-3 Ebisu Minami

Shibuya-ku, Tokyo 150-0022

Tel: 81.3.3760.3110

Fax: 81.3.3760.3101

Yokohama-City

Innotech

2-15-10 Shin Yokohama

Kohoku-ku

Yokohama-City, 222-8580

Tel: 81.45.474.9037

Fax: 81.45.474.9065

Macnica Corporation

Hakusan High-Tech Park

1-22-2 Hadusan, Midori-Ku,

Yokohama-City, 226-8505

Tel: 81.45.939.6140

Fax: 81.45.939.6141

The Netherlands

Eindhoven

Acal Nederland b.v.

Beatrix de Rijkweg 8

5657 EG Eindhoven

Tel: 31.40.2.502602

Fax: 31.40.2.510255

Switzerland

Brugg

LSI Logic Sulzer AG

Mattenstrasse 6a

CH 2555 Brugg

Tel: 41.32.3743232

Fax: 41.32.3743233

Taiwan

Taipei

Avnet-Mercuries

Corporation, Ltd

14F, No. 145,

Sec. 2, Chien Kuo N. Road

Taipei, Taiwan, R.O.C.

Tel: 886.2.2516.7303

Fax: 886.2.2505.7391

Lumax International

Corporation, Ltd

7th Fl., 52, Sec. 3

Nan-Kang Road

Taipei, Taiwan, R.O.C.

Tel: 886.2.2788.3656

Fax: 886.2.2788.3568

Prospect Technology

Corporation, Ltd

4Fl., No. 34, Chu Luen Street

Taipei, Taiwan, R.O.C.

Tel: 886.2.2721.9533

Fax: 886.2.2773.3756

Wintech Microeletronics

Co., Ltd

7F., No. 34, Sec. 3, Pateh Road

Taipei, Taiwan, R.O.C.

Tel: 886.2.2579.5858

Fax: 886.2.2570.3123

United Kingdom

Maidenhead

Azzurri Technology Ltd

16 Grove Park Business Estate

Waltham Road

White Waltham

Maidenhead, Berkshire SL6 3LW

Tel: 44.1628.826826

Fax: 44.1628.829730

Milton Keynes

Ingram Micro (UK) Ltd

Garamonde Drive

Wymbush

Milton Keynes

Buckinghamshire MK8 8DF

Tel: 44.1908.260422

Swindon

EBV Elektronik

12 Interface Business Park

Bincknoll Lane

Wootton Bassett,

Swindon, Wiltshire SN4 8SY

Tel: 44.1793.849933

Fax: 44.1793.859555

♦Sales Ofﬁces with

Design Resource Centers