(spr SIGNAL PROCESSING TECHNOLOGIES HADCS5S74Z FAST, COMPLETE 12-BiT uP COMPATIBLE A/D CONVERTER WITH SAMPLE/HOLD FEATURES Improved Pin-To-Pin Compatible Monolithic Version of the HI574A and AD574A Complete 12-Bit A/D Converter with Sample/Hold, Reference and Clock Low Power Dissipation (150 mW Max) 12-Bit Linearity (Over Temp) 25 ws Max Conversion Time No Negative Supply Required Full Bipolar and Unipolar Input Range GENERAL DESCRIPTION The HADCS574Z is a complete, 12-bit successive approxima- tion A/D converter. The device is integrated on a single die to make it the first monolithic CMOS version of the industry standard devices, HI574A and AD574 too nl 4755 Forge Road, Co. Springs, CO 80807 310 PH: (719) 528-2300; Fax: (719) 528-2370 SP 7 MH 8248917 oo0e714 2:13ELECTRICAL SPECIFICATIONS STAND-ALONE MODE TIMING CHARACTERISTICS Ta = 25 C, Voc = +15.0 V or +42 V, VLoaic = +5 V, unless otherwise specified. TEST TEST HADC574ZC HADC574ZB HADC574ZA 3 PARAMETER CONDITIONS LEVEL | MIN TYP MAX|MIN TYP MAX|MIN TYP MAX} UNITS x AC ELECTRICAL CHARACTERISTICSS turi Low R/C Pulse Width ! 50 50 50 ns tps STS Delay from R/C ! 200 200 200 | ns tHoR Data Valid After R/C Low I 25 25 25 ns EX tus STS Delay After Data Valid l 300 1000 | 300 1000 | 300 1000 } ns tHRH High R/C Pulse Width I 150 150 150 ns tpprR Data Access Time I 150 150 150 [ns SAMPLE AND HOLD Acquisition Time IV 18 #24 34 718 24 34 118 24 34 ps Aperture Uncertainty Time Vv 8 8 8 ns,RMS Figure 3- Low Pulse for R/C ~ Outputs Enabled After Conversion DB11-DB0 DATA VALID > CATA VALID TEST LEVEL CODES TEST LEVEL All electrical characteristics are subject to the | following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. VI Unless otherwise noted, all tests are pulsed tests; therefore, Ty = Tc = Ta. Figure 4- High Pulse for R/C - Outputs Enabled While R/C is High, Otherwise High Impedance HIGH-Z, HIGH-Z DATA VALID DB11-0B0 TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at Ta=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at Ta = 25 C. Parameter is guaranteed over specified temperature range. 4755 Forge Road, Co. Springs, CO 80907 PH: (719) 528-2300; Fax: (719) 528-2370 Ss 3-11 Me 8248917 0002715 157HADC574Z DEFINITION OF SPECIFICATIONS INTEGRAL LINEARITY ERROR Linearity error refers to the deviation of each individual code from a line drawn from zero through full scale with all offset errors nulled out. (See figures 5 and 6.) The point used as zero occurs 1/2 LSB (1.22 mV for a 10 volt span) before the first code transition (all zeros to only the LSB on). Full scale is defined as a level 1 and 1/2 LSB beyond the last code transition (to all ones). The deviation of a code from the true straight line is measured from the middle of each particular code. The HADC574ZAC and BC grades are guaranteed for maxi- mum nonlinearity of +1/2 LSB. For these grades, this means that an analog value that falls exactly in the center of a given code width will result in the correct digital output code. Values nearer the upper or lower transition of the code width may produce the next upper or lower digital output code. The HADC574ZAM, BM, CC and CM grades are guaranteed to +1 LSB maximum error. For these grades, an analog value that falls within a given code width will result in either the correct code for the region or either adjacent one. The linearity is not user-adjustable. DIFFERENTIAL LINEARITY ERROR (NO MISSING CODES) A specification that guarantees no missing codes requires that every code combination appear in a monotonically increasing sequence as the analog input level is increased. Thus every code must have a finite width. For the HADC574Z type AC, BC, AM and BM grades that guarantee no missing codes to 12-bit resolution, all 4096 codes must be present over the entire operating temperature ranges. The HADC574Z CC and CM grades guarantee no missing codes to 11-bit resolution over temperature; this means that all code combinations of the upper 11-bits must be present. In prac- tice, very few of the 12-bit codes are missing. DIFFERENTIAL NONLINEARITY Differential nonlinearity is a measure of how much the actual quantization step width varies from the ideal step width of 1 LSB. Figure 6 shows a differential nonlinearity of 2 LSB - the actual step width is 3 LSB. The HADC5742s specification gives the worst case differential nonlinearity in the A/D transfer function under specified dynamic operating condi- tions. Small, localized differential nonlinearities may be insig- nificant when digitizing full scale signals. However, if a low level input signal happens to fall on the part of the A/D transfer function with the differential nonlinearity error, the effect will be significant. MISSING CODES Missing codes represent a special kind of differential nonlin- earity. The quantization step width for a missing code is 0 LSB which results in a differential nonlinearity of -1 LSB. Figure 6 points out two missed codes in the transfer function. QUANTIZATION UNCERTAINTY Analog-to-digital converters exhibit an inherent quantization uncertainty of +1/2 LSB. This uncertainty is a fundamental characteristic of the quantization process and cannot be reduced for a converter of a given resolution. QUANTIZATION ERROR Quantization error is the fundamental, irreducible error associated with the perfect quantizing of a continuous (analog) signal into a finite number of digital bits (A/D transfer function). A 12-bit A/D converter can represent an input voltage with a best case uncertainty of 1 part in 212 (1 part in 4096). In real A/Ds under dynamic operating conditions, the quantization bands (bit change step vs input amplitude) for certain codes can be significantly larger (or smaller) than the ideal. The ideal width of each quantization step (or band) is Q=FSR/2N where FSR=tfull scale range and N=12. Nonideal quantization bands rep- resent differential non linearity errors. (See figures 5, 6 and 7.) Figure 5- Static Input Conditions Output 7 Codes 7 T Threshold Level T (Band Edge) roy \ L | J \ + Quantization Step 4 | (Or Band) T } t tS RESOLUTION - ACTUAL vs AVAILABLE Jo Output fs Input Voltage The available resolution of an N-bit converter is 2N. This means it is theoretically possible to generate 2N unique output codes. 3-12 me 8248917 OOOe7Lb OFb = 4755 Forge Road, Co. Springs, CO 80907 SPT PH: (719) 528-2300; Fax: (719) 528-2370Figure 6- Dynamic Conditions Output + Codes Integral Nonlinearity = ' ' (Y-1/2 LSB) 4 Missed Codes _ S wy I ~ Nonmonotonic Behavior - Differential Nonlinearity = (X-1 LSB) Input Voltage Figure 7- Quantizing Error Quantizing Error +V2LSB s t.WN NARA KAA a NO ONON NONUN - 72 LSB Wa 1014 100 4 011] o BRB oF g 5 2 wm 3 5 ovo 7] \ T T T T T T T O55 25 386 45 55 65 Analog Input Voltage THROUGHPUT Maximum throughput is the greatest number of conversions per second at which an ADC will deliver its full rate perform- ance. This is equivalent to the inverse of the sum of the multiplex time {if applicable), the S/H settling time and the conversion time. GAIN Gain is the slope of the transfer curve. Gain is generally user adjustable to compensate for long term drift. ACQUISITION TIME/APERTURE DELAY TIME In the HADC574Z, this is the time delay between the R/C falling edge and the actual start of the hold mode in a sample and hold function. APERTURE JITTER This is a specification indicating how much the aperture delay time varies between samples. SUCCESSIVE APPROXIMATION ADC The successive approximation converter uses an architec- ture with inherently high throughput rates that converts high frequency signals with great accuracy. A sample-and-hold type circuit can be used on the input to freeze these signals during conversion. An N-bit successive approximation converter performs a sequence of tests comparing the input voltage to a succes- sively narrower voltage range. The first range is half full scale, the next is quarter full scale, etc., until it reaches the Nth test which narrows it to a range of 1/2N of full scale. The conver- sion time is fixed by the clock frequency and is thus indepen- dent of the input voltage. UNIPOLAR OFFSET The first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the actual transition from that point. This offset can be adjusted as discussed on the following pages. The unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with and without external adjustment. BIPOLAR OFFSET The major carry transition (0111 1111 1111 to 1000 0000 0000) in the bipolar mode should occur for an analog value 1/2 LSB below analog common. The bipolar offset error and tempera- ture coefficient specify the initial deviation and maximum change in the error over temperature. CONVERSION TIME This is the time required to complete a conversion over the specified operating range. Conversion time can be expressed as time/bit for a converter with selectable resolution or as time/conversion when the number of bits is constant. The HADC574Z is specified as time/conversion for all 12-bits. Conversion time should not be confused with maximum allowable analog input frequency which is discussed later. 4755 Forge Road, Co. Springs, CO 80907 PH: (719) 528-2300; Fax: (719) 528-2370 S 3-13 MB 8248917? 0002717? Tec HADC574ZHADC574Z FULL SCALE CALIBRATION ERROR The last transition (from 1111 11111110to 111111111111 1111) should occur for an analog value 1 and 1/2 LSB below the nominal full scale (9.9963 volts for 10.000 voits full scale). The full scale calibration error is the deviation of the actual level at the last transition from the ideal level. This error, which typically is 0.05 to 0.1% of full scale, can be trimmed out as show in figures 11 and 12. The full scale calibration error over temperature is given with and without the initial error trimmed out. The temperature coefficients for each grade indicate the maximum change in the full scale gain from the initial value using the internal 10 volt reference. TEMPERATURE COEFFICIENTS The temperature coefficients for full scale calibration, unipo- lar offset, and bipolar offset specify the maximum change from the initial (25 C) value to the value at Twin or Tmax. POWER SUPPLY REJECTION The standard specifications for the HADC574Z assume +5.00 and +15.00 or +12.00 volt supplies. The only effect of power supply error on the performance of the device will be a small change in the full scale calibration. This will result in a linear change in all fower order codes. The specifications show the maximum change in calibration from the initial value with the supplies at the various limits. CODE WIDTH The fundamental unit for A/D converter specifications is the code width. This is defined as the range of analog input values for which a given digital output code will occur. The nominal value of a code width is equivalent to one least significant bit (LSB) of the full scale range or 2.44 mV out of 10 volts for a 12-bit ADC. LEFT-JUSTIFIED DATA The data format used in the HADC574Z is left-justified. This means that the data represents the analog input as fraction of full scale, ranging from 0 to 4095/4096. This implies a binary point to the left of the MSB. MONOTONICITY This characteristic describes an aspect of the code to code progression from minimum to maximum input. A device is said to be monotonic if the output code continuously in- creases as the input signal increases, and if the output code continuously decreases as the input signal decreases. Figure 6 demonstrates nonmonotonic behavior. CIRCUIT OPERATION The HADC574Z is a complete 12-bit analog-to-digital con- verter that consists of a single chip version of the industry standard 574. This single chip contains a precision 12-bit capacitor digital-to-analog converter (CDAC) with voltage reference, comparator, successive approximation register (SAR), sample-and-hold, clock, output buffers and control circuitry to make it possible to use the HADC574Z with few external components. When the control section of the HADC574Z initiates a conver- sion command, the clock is enabled and the successive- approximation register is reset to all zeros. Once the conver- sion cycle begins, it cannot be stopped or restarted and data is not available from the output buffers. The SAR, timed by the clock, sequences through the conver- sion cycle and returns an end-of-convert flag to the control section of the ADC. The clock is then disabled by the control section, the output status goes low, and the control section is enabled to allow the data to be read by external command. The internal HADC5742Z 12-bit CDAC is sequenced by the SAR starting from the MSB to the LSB at the beginning of the conversion cycle to provide an output voltage from the CDAC that is equal to the input signal voltage (which is divided by the input voltage divider network). The comparator determines whether the addition of each successively-weighted bit volt- age causes the CDAC output voltage summation to greater or less than the input voltage; if the sum is less, the bit is left on; if more, the bit is turned off. After testing all the bits, the SAR contains a 12-bit binary code which accurately repre- sents the input signal to within +1/2 LSB. The internal reference provides the voltage reference to the CDAC with excellent stability over temperature and time. The reference is trimmed to 10.00 volts +1% and can supply up to 2 mA to an external load in addition to that required to drive the reference input resistor (1 mA) and offset resistor (1 mA) when operating with +15 V supplies. If the HADC5742Z is used with +12 V supplies, or if external current must be supplied over the full temperature range, and external buffer amplifier is recommended. Any external load on the HADC574Z refer- ence must remain constant during conversion. The sample-and-hold feature is a bonus of the CDAC archi- tecture. Therefore the majority of the S/H specifications are included within the A/D specifications. Although the sample-and-hold circuit is not implemented in the classical sense, the sampling nature of the capacitive DAC makes the HADC574Z appear to have a built in sample- and-hold. This sample-and-hold action substantially in- creases the signal bandwidth of the HADC574Z over that of similar competing devices. MM 6248917 0002718 569 4755 Forge Road, Co. Springs, CO 80907 PT PH: (719) 528-2300; Fax: (719) 528-2370 Ss.Note that even though the user may use an external sample- and-hold for very high frequency inputs, the internal sample- and-hold still provides a very useful isolation function. Once the internal sampie is taken by the CDAC capacitance, the input of the HADC574Z is disconnected from the users sample-and-hold. This prevents transients occurring during conversion from being inflicted upon the attached sample- and-hold buffer. All other 574 circuits will cause a transient load current on the sample-and-hold which will upset the buffer output and may add error to the conversion itself. Furthermore, the isolation of the input after the acquisition time in the HADC574Z allows the user an opportunity to release the hald on an external sample-and-hold and start it tracking the next sample. This will increase system through- put with the users existing components. SAMPLE AND HOLD FUNCTION When using an external S/H, the HADC574Z acts as any other 574 device because the internal S/H is transparent. The sample/shold function in the HADC574Z is inherent to the capacitor DAC structure, and its timing characteristics are determined by the internally generated clock. However, for limited frequency ranges, the internal S/H may eliminate the need for an external S/H. This function will be explainedin the next two sections. The operation of the S/H function is internal to the HADC574Z and is controlled through the normal R/C control line, (Refer to figure 8.) When the R/C line makes a negative transition, the HADC57472 starts the timing of the sampling and conver- sion. The first two clock cycles are allocated to signal acqui- sition of the input by the CDAC. (This time is defined as Tacq.) Following these two cycles, the input sample is taken and held. The A/D conversion follows this cycle with the duration controlled by the internal clock cycle. Figure 8- Sample and Hold Function (Tacq) Acquisition Time Wait For I Convert Signal | , ae] Wait For Bus Conversion Read te| fr Aperture Vin Jitter Y_, Acquisition Time = Aperture Delay Time = 0.12 X Tcoanvert CDAC Voltage Vand Volts During Tacq, the equivalent circuit of the HADC574Z input is as shown in figure 9 (the time constant of the input is independent of which input level is used). This CDAC capaci- tance must be charged up to the input voltage during Tacq. Since the CDAC time constant is 100 nsecs, there is more than enough time for settling the input to 12-bits of accuracy during Tacg. The excess time left during Tacg allows the user's buffer amp to settle after being switched to the CDAC load. Figure 9- Equivalent HADC574Z Input Circuit | Cag 25 pF Req = 4kQ at any range T= Reg Coq = 100 nsec Note that because the sample is taken relative to the R/C transition, Tacq is also the traditional aperture delay of this internal sample-and-hold. Since Tacq is measured in clock cycles, its duration will vary with the internal clock frequency. This results in Tacq =2.4 psec between units and over temperature. Offset, gain and linearity errors of the S/H circuit as well as the effects of its droop rate are included in the overall specifica- tions for the HADC5742. APERTURE UNCERTAINTY Often the limiting factor in the application of the sample-and- hold is the uncertainty in the time that the actual sample is taken, i.e., the aperture jitter or Tay. The HADC574Z has a nominal aperture jitter of 8 nsec between samples. With this jitter, itis possible to accurately sample a wide range of input signals. The aperture jitter causes an amplitude uncertainty for any input where the valtage is changing. The approximate volt- age error due to aperture jitter depends on the slew rate of the signal at the sample point. (See figure 10.) The magnitude of this change for a sine wave can be calculated: Verr nfVin tag OF fMAX < Vis/(rVin tay)2(N+1) For the HADC574Z, tay=8 nsec, therefore fax <5 KHz. For higher frequency signal inputs, an external sample-and- hold is recommended. TYPICAL INTERFACE CIRCUIT The HADC574Z is a complete A/D converter that is fully operational when powered up and issued a Start Convert Signal. Only a few external components are necessary as shown in figures 11 and 12. The two typical interface circuits are for operating the HADC574Z in either an unipolar or bipolar input mode. Information on these connections and on conditions concerning board layout to achieve the best op- eration are discussed below. For each application of this device, strict attention must be given to power supply decoupling, board layout (to reduce pickup between analog and digital sections), and grounding. Digital timing, calibration and the analog signal source must be considered for correct operation. To achieve specified accuracy, a double-sided printed circuit board with a copper ground plane on the component side is recommended. Keep analog signal traces away from digital lines. It is best to lay the PC board out such that there is an analog section and a digital section with a single point ground connection between the two through an RF bead located as closely to the device as possible. If possible, run analog signals between ground traces and cross digital lines at right angles only. POWER SUPPLIES The supply voltages for the HADC574Z must be kept as quiet as possible from noise pickup and also regulated from transients or drops. Because the part has 12-bit accuracy, voltage spikes on the supply lines can cause several LSB deviations on the output. Switching power supply noise can be a problem. Careful filtering and shielding should be employed to prevent the noise from being picked up by the converter. Capacitor bypass pairs are needed from each supply pin to its respective ground to filter noise and counter the problems caused by the variations in supply current. A 10 uF tantalum and a 0.1 pF ceramic type in parallel between VLoaic (pin 1) and digital common (pin 15), and Vcc (pin 7) and analog common (pin 9) are sufficient. Veg is generated internally so pin 11 may be grounded or connected to a negative supply if the HADC574Z is being used to upgrade an already existing design. GROUNDING CONSIDERATIONS Any ground path from the analog and digital ground should be as low resistance as possible to accommodate the ground currents present with this device. The analog ground current is approximately 6 mADC while the digital ground is 3 MADC. The analog and digital common pins should be tied together as closely to the package as possible to guarantee best performance. The code depen- dent currents flow through the VLogic and Vcc terminals and not through the analog and digital common pins. The HADC574Z may be operated by a pP or in the stand- alone mode. The part has four standard input ranges: 0 V to +10V, 0V to +20 V,+5 V and +10 V. The maximum errors that are listed in the specifications for gain and offset may be adjusted externally to zero as explained in the next two sections. 3-16 Mm 6248917 OO0e72e0 51? 4755 Forge Road, Co. Springs, CO 80907 PT PH: (719) 528-2300; Fax: (719) 528-2370 S$CALIBRATION AND CONNECTION PROCEDURES UNIPOLAR The calibration procedure consists of adjusting the converters most negative output to its ideal value for offset adjustment, and then adjusting the most positive output to its ideal value for gain adjustment. Starting with offset adjustment and referring to figure 11, the midpoint of the first LSB increment should be positioned at the origin to get an output code of all Os. To do this, an input of +1/2 LSB or +1.22 mV for the 10 V range and +2.44 mvV for the 20 V range should be applied to the HADC574Z. Adjust the offset potentiometer R1 for code transition flickers be- tween 0000 0000 0000 and 0000 0000 0001. The gain adjustment should be done at positive full scale. The ideal input corresponding to the last code change is applied. This is 1 and 1/2 LSB below the nominal full scale which is +9.9963 V for the 10 V range and +19.9927 V for the 20 V range. Adjust the gain potentiometer R2 for flicker between codes 1111 11111110 and 1111 1111 1111. If calibration is not necessary for the intended application, replace R2 with a 50 Q, 1% metal film resistor and remove the network from pin 12. Connect pin 12 to pin 9. Connect the analog input to pin 13 for the O V to 10 V range or to pin 14 for the 0 V to 20 V range. Figure 11 - Unipolar Input Connections MSB 27 BIPOLAR The gain and offset errors listed in the specification may be adjusted to zero using the potentiometers Ri and R2. (See figure 12.) If adjustment is not needed, either or both pots may be replaced by a 50 Q, 1% metal film resistor. To calibrate, connect the analog input signal to pin 13 fora +5 V range or to pin 14 for a +10 V range. First apply a DC input voltage 1/2 LSB above negative full scale which is -4.9988 V for the +5 V range or -9.9976 V for the +10 V range. Adjust the offset potentiometer R1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001. Next, apply a DC input voltage 1 and 1/2 LSB below positive full scale which is +4.9963 V for the +5 V range or +9.9927 V for the +10 V range. Adjust the gain potentiometer R2 for flicker between codes 11141 1111 1110 and 111111111111. ALTERNATIVE in some applications, a full scale of 10.24 V (for an LSB of 2.5 mV) or 20.48 V (foran LSB of 5.0 mV) is more convenient. In the Unipolar mode of operation, replace R2 with a 200 Q potentiometer and add 150 Qin series with pin 13 for 10.24 V input range or 500 Q in series with pin 14 for 20.48 V input range. In bipolar mode of operation, replace R1 with a 500 Q potentiometer (in addition to the previous changes). The calibration will remain similar to the standard calibration procedure. Output Bits 26] 26] 24] 23] 22] 21 20 19} 18] 17] 16| LSB RG Ao Controt 12/8 olalala|r cE 100 ke ABV OAM-O +15 V Oto 10V 10VIn 4 ay <= Analog inputs 20 Vin 14 ro0 Ks: O10 20 a Wr BIPOH 12] ow a [ 7 Vrai OU g Ret 10s: A Vret I 19) Lagic > Oscillator Rt Amp (Calibration) + *] oS Nibble A Nibble B Nibbla C Three-State Buffers And Control 28 SiS 1 VLogic ad = tur 18 peND = OfisevGain Ret Trim Network AGND | 9 vec N al ea +15 V = =o0- S 4755 Forge Road, Co. Springs, CO 80907 PH: (719) 528-2300; Fax: (719) 528-2370 Mm 8248917 oooe7e1 453 HADC574ZHADC574Z Figure 12 - Bipolar Input Connections MSB 27 | 26| 25] 24 Output Bits 23] 22] 21|20] 19] 18] 17] 16] LSB Control 3 Ss Nibbie A | Nibble B I Nibble C 6 Logie Thres-Slate Buffers And Cantral 28 eeneee STS +5 1_VLagie 4 Strobe 1 uF 12-Dits = x DGND = Comp ad tovin ia] aw Sampla/Hold cpac | Analog a vse a) Inputs 2ovin ial ow 9h z10V | ero tz] NW 4 100.2 J Ri [ Offsat/Gain Ret Vet Ovlg Ret a! Trim Network Amo fo _ [ 4M 100 2 = = a ' MA YRet '" 10 CONTROLLING THE HADC5742 The HADC574Z can be operated by most microprocessor systems due to the control input pins and on-chip logic. It may also be operated in the stand-alone mode and enabled by the R/C input pin. Full P control consists of selecting an 8 or 12-bit conversion cycle, initiating the conversion, and read- ing the output data when ready. The output read has the options of choosing either 12-bits at once or 8 bits followed by 4-bits in a left-justified format. All five control inputs are TTL/CMOS compatible and include 12/8, CS, Ao, R/E and CE. The use of these inputs in controlling the converters operations is shown in table |, and the internal control logic is shown in a simplified schematic in figure 14. STAND-ALONE OPERATION The simplest interface is a control line connected to R/C . The output controls must be tied to known states as follows: CE and 12/8 are wired high, AoandCS are wired low. The output data arrives in words of 12-bits each. The limits on R/C duty cycle are shown in figures 3 and 4. It may have a duty cycle within and including the extremes shown in the specifica- tions. In general, data may be read when R/C is high unless STS is also high, indicating a conversion is in progress. Figure 13 - Interfacing the HADC574Z to an 8-bit Data Bus Address Bus STs DB11 (MSB} Data Bus DBO (LSB) OGL. COM 15, 3-18 Me 424891? GO0e?ee JIT 4755 Forge Road, Co. Springs, CO 80907 PH: (719) 528-2300; Fax: (719) 528-2370 SPTTable | - Truth Table for the HADC574Z Control Inputs ce S RC 128 Ao Operation 0 x x x x None x 1 x x x None 4 x Initiate 12 bit conversion + 0 x 1 Initiate B bit conversion 1 + a x 0 Initiate 12 bit conversion 1 + x 1 Initiate 8 bit conversion 1 0 ? x 0 Initiate 12 bit conversion 1 9 + x 1 Initiate 8 bit conversion 1 8 1 1 x Enable 12 bit Output 1 0 1 0 0 Enable 8 MSB's Only 1 oO 1 0 1 Enable 4 LSB's Plus 4 Trailing Zeroes CONVERSION LENGTH Aconversion start transition latches the state of Ao as shown in figure 13 and table |. The latched state determines if the conversion stops with 8-bit (Ao high) or continues for 12-bits (Ao low). If all 12-bits are read following an 8-bit conversion, the three LSBs will be a logic 0 and DB3 will be a logic 1. Ao is latched because it is also involved in enabling the output buffers as will be explained later. No other control inputs are latched. CONVERSION START A conversion may be initiated by a logic transition on any of the three inputs: CE, CS, R/C, as shown in table |. The last of the three to reach the correct state starts the conversions, $0 one, two or all three may be dynamically controlled. The nominal delay from each is the same and all three may change state simultaneously. In order to assure that a par- ticular input controls the start of conversion, the other two should be set up at least 50 ns earlier. Refer to the convert mode timing specifications. The Convert Start timing diagram is illustrated in figure 1. The output signal STS is the status flag and goes high only when a conversion is in progress. While STS is high, the output buffers remain in a high impedance state so that data can not be read. Also, when STS is high, an additional Start Convert will not reset the converter or reinitiate a conversion. Note, if Ao changes state after a conversion begins, an additional Start Convert command will latch the new start of Ao and possibly cause a wrong cycle length for that conver- sion (8 versus 12-bits). READING THE OUTPUT DATA The output data buffers remain in a high impedance state until the following four conditions are met: AT ishigh, STSis low, CE is high, and CS is low. The data lines become active in response to the four conditions and output data according to the conditions of 12/8 and Ao. The timing diagram for this process is shown in figure 2. When 12/8 is high, all 12 data outputs become active simultaneously and the Ao input is ignored. This is for easy interface to a 12 or 16-bit data bus. The 12/8 input is usually tied high or low, although it is TTL/CMOS compatible. When 12/8 is low, the output is separated into two 8-bit bytes as shown below: BYTE 1 XXX X XX XK X MSB BYTE 2 XXXX O0O00 LSB This configuration makes it easy to connect to an 8-bit data bus as shown in figure 13. The Ao control can be connected to the least significant bit of the address bus in order to store the output data into two consecutive memory locations. When Ao is pulled low, the 8 MSBs are enabled only. When Ao is high, the 4 MSBs are disabled, bits 4 through 7 are forced to a zero and the four LSBs are enabled. The two byte format is left justified data as shown above and can be considered to have a decimal point or binary to the left of byte 1. Ao may be toggled without damage to the converter at any time. Break-before-make action is guaranteed between the two data bytes. This assures that the outputs which are strapped together in figure 13 will never be enabled at the same time. In figure 2, itcan be seen that a read operation usually begins after the conversion is completed and STS is low. If earlier access is needed, the read can begin no later than the addition of time top and tus before STS goes low. 4755 Forge Road, Co. Springs, CO 80907 PH: (719) 528-2300; Fax: (719) 528-2370 Ss MH 4248917 GO0e?2e3 e2b HADC574ZHADC574Z Figure 14 - Control Logic Nibble B Zero Override > > Niele 8 input Butfers "2 [> ff += nati cs Read Contro} RK Cc 1 oO E0c8 E0C12 Figure 15 - Burn-in Schematic +5.5V 0D c, 12/8 cs 2 Ao Bit 10 +5 V. _ 400 H RIC i OV Iz Bit 9 ce Bits J +165V +15 Bit 7 REF-OUT Bit6 Asynchronous Signals AGND Bit5 REF-IN Bit 4 N NIC BIPOFF +5V =, av 60 Hz 10 Vin $v 20 V In DGND Ry-509, 5%, 1/72W Ro-1kQ, 5%, 1/44W R3-502, 1%, 1/4W GND Ov Ra- 10k, 5%, 1/4W R5-3.9kO, 5%, /4W Cc, -1THF, 5% 3.20 4755 Forge Road, Co. Springs, CO 80907 SPT ~ PH: (719) 528-2300; Fax: (719) 528-2370 M 6248917 OO0e7e4 1bePIN ASSIGNMENTS vy a =] fa) fs) (2) felfe Fo) (-} fe] fol] fe] Pe] EL TOP VIEW VLOGIC 128 cs Ao RIC cE vec REF OUT AGND REF IN NIC (Veg) BIP OFF 10V IN 20V IN sTs OB11 DB10 2 a gq DBI Deo DGND 28 LEAD DIP AO CS 12/8 Vicgic STS BIP 10V IN 20V DGND DBO IN 28 Lead LCC DBIt w o fo ST eT al Cel al Cel 5) Cal Cal Tel Tol Tel [ed Ca] DB10 PIN FUNCTIONS NAME FUNCTION VLoaic Logic Supply Voltage, Nominally +5 V 12/8 Data Mode Selection cs Chip Selection Ao Byte Address/Short Cycle R/C Read/Convert CE Chip Enable Voc Analog Positive Supply Voltage, Nominally +15 V REF OUT Reference Output, Nominally +10 V AGND* Analog Ground REF IN Reference Input N/C (VEE) This pin is not connected to the device. BIP OFF Bipolar Offset 10 VIN 10 Volt Analog Input 20 VIN 20 Volt Analog Input DGND Digital Ground DBO - DB11 Digital Data Output DBi1-MSB DBO-LSB STS Status * The lids on the sidebrazed and LCC packages are internally connected to AGND. S 4755 Forge Road, Co. Springs, CO 80907 PH: (719) 528-2300; Fax: (719) 528-2370 Mm 4248917 OOOe?eS OTS 3-21 HADC574Z