1 of 138GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
GENDOC-054389 July 2013
HD/SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with
SMPTE Audio and Video Processing
GS1671A
www.semtech.com
Key Features
• Operation at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE ST 292, SMPTE ST 259-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
230m at 1.485Gb/s
440m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Integrated audio de-embedder for 8 channels of 48kHz
audio
• Integrated audio clock generator
• Ancillary data extraction
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• Wide temperature range of -40ºC to +85ºC
• Low power operation (typically 480mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
Application: 1080p30 or 720p60 Monitor
Audio
Selector
Video
Processor
10-bit
HV F/PCLK
CTR L/TIMECODE
AES - OUT
AUDIO 1/2
Audio Clocks
Speakers
Display
DAC
DAC
HD-SDI
GS1671A
AUDIO 3/4
AUDIO 5/6
AUDIO 7/8
Application: Multi-format Downconverter
Audio
Processing
& Delay
GS4901
Analog
Sync
Sync
Seperator
10-bit
HV F/PCLK
HD/SD
Serializer
(GS1672)
Video
Downconverter &
Aspect Ratio
Conversion
Memory
10-bit
10-bit SD Bypass
HV F/PCLK
Audio Clocks
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
HD/SD-SDI
SD/HD-SDI
GS1671A
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
Application: Multi-input Video Monitoring System
GS4911
Analog
Sync
Sync
Seperator
Video
Formatter
Video
Memory
HV F/PCLK
Audio Clock s
10-bit
HV F/PCLK
AE S OUT 1/2
AE S OUT 3/4
AE S OUT 5/6
AE S OUT 7/8
HV F/PCLK
HV F/PCLK
Audio
Select
10-bit
10-bit
On Screen
Display
Generator
AES BUS
Audio
Processor
HV/DE/PCLK
DVI/
VGA DAC
Video
Output
HD-SDI
Input 1
GS1671A
GS1671A
GS1671A
HD-SDI
Input 2
HD-SDI
Input n
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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Description
The GS1671A is a multi-rate SDI integrated Receiver which
includes complete SMPTE processing, as per SMPTE ST 292
and SMPTE ST 259-C. The SMPTE processing features can be
bypassed to support signals with other coding schemes.
The GS1671A integrates Semtech's adaptive cable equalizer
technology, achieving unprecedented cable lengths and
jitter tolerance. It features DC restoration to compensate for
the DC content of SMPTE pathological signals.
The device features an Integrated Reclocker with an
internal VCO and a wide Input Jitter Tolerance (IJT) of 0.7UI.
A serial digital loop-through output is provided, which can
be configured to output either reclocked or non-reclocked
serial digital data. The serial digital output can be connected
to an external cable driver.
The device operates in one of four basic modes:
SMPTE mode, DVB-ASI mode, Data-Through mode or
Standby mode.
In SMPTE mode (the default operating mode), the GS1671A
performs full SMPTE processing, and features a number of
data integrity checks and measurement capabilities.
The device also supports ancillary data extraction, and can
provide entire ancillary data packets through
host-accessible registers. It also provides a variety of other
packet detection and error handling features. All of these
processing features are optional, and may be individually
enabled or disabled through register programming.
In DVB-ASI mode, sync word detection, alignment and
8b/10b decoding is applied to the received data stream.
In Data-Through mode all forms of SMPTE and DVB-ASI
processing are disabled, and the device can be used as a
simple serial to parallel converter.
The device can also operate in a lower power Standby
mode. In this mode, no signal processing is carried out and
the parallel output is held static.
Parallel data outputs are provided in 20-bit or 10-bit format
for HD and SD video rates, with a variety of mapping
options. As such, this parallel bus can interface directly with
video processor ICs, and output data can be multiplexed
onto 10 bits for a low pin count interface.
Up to eight channels (two audio groups) of serial digital
audio may be extracted from the video data stream, in
accordance with SMPTE ST 272-C and SMPTE ST 299.
The output audio formats supported by the device include
AES/EBU and I2S, and two other industry standard serial
digital formats. A variety of audio processing features are
provided to ease implementation. Audio clocks are
internally generated and provided by the device.
Application: Multi-format Audio De-embedder Module
PCLK
10 - bit
GS1662
DAC
Switch
Logic
&
Drivers Analog
Audio
Outputs
AES
Audio
Outputs
AUDIO 1/2
AUDIO 3/4
AUDIO 5/6
AUDIO 7/8
Audio Clock s
SD/HD-SDI GS1671A
SD/HD-SDI
Application: Multi-format Digital VTR/Video Server
Stor age :
Tape /HDD/Solid State
Audio
Processor
Video
Processor
10-bit
HVF/PCLK
Audio Out puts
V ideo Output
Audio Clock s
AUDIO 1/2
AUDIO 3/4
AUDIO 5/6
AUDIO 7/8
SD/HD-SDI GS1671A
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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Functional Block Diagram
GS1671A Functional Block Diagram
Buffer Mux
Reclocker
with
Integrated
VCO
SDI
SDO
SDO
Serial
to
Parallel
Converter
Descramble,
Word Align,
Rate Detect
Flywheel
Video
Standard
Detect
TRS
Detect
Timing
Extraction
Mux
DVB-ASI
Decoder
Illegal code
remap,
TRS/
Line Number/
CRS
Insertion,
EDH Packet
Insertion
V/VSync
H/HSync
F/De
Rate_det[1:0]
ANC/
Checksum
/ST 352
Extraction
Audio
De-Embedder,
Audio Clock
Generation
Error Flags
YANC/CANC
LOCKED
DVB_ASI
STANDBY
GSPI and
JTAG Controller
Host
Interface
Output Mux/
Demux
Crystal
Buffer/
Oscillator
LF
LB_CONT
VBG
RC_BYP
I/O Control
TIM861
20BIT/10BIT
SMPTE_BYPASS
IOPROC_EN/DIS
RESET_TRST
CORE_VDD
CORE_GND
IO_VDD
IO_GND
AUDIO_EN/DIS
AOUT_1/2
ACLK
AMCLK
WCLK
SDO_EN/DIS
CS_TMS
SCLK_TCLK
SDIN_TDI
SDOUT_TDO
JTAG/HOST
XTAL1
SW_EN
VCO_VDD
VCO_GND
PLL_VDD
PLL_GND
EQ_VDD
EQ_GND
A_VDD
A_GND
BUFF_VDD
BUFF_GND
Buffer
SDI
AOUT_3/4
AOUT_5/6
AOUT_7/8
XTAL2
XTAL_OUT
NGEN
EQ
AGC+
AGC-
DOUT[19:0]
PCLK
LOCKED
GS1671A HD/SD SDI Receiver
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Contents
1. Pin Out...............................................................................................................................................................8
1.1 Pin Assignment ..................................................................................................................................8
1.2 Pin Descriptions ................................................................................................................................8
2. Electrical Characteristics ......................................................................................................................... 16
2.1 Absolute Maximum Ratings ....................................................................................................... 16
2.2 Recommended Operating Conditions .................................................................................... 16
2.3 DC Electrical Characteristics ..................................................................................................... 17
2.4 AC Electrical Characteristics ..................................................................................................... 19
3. Input/Output Circuits ............................................................................................................................... 23
4. Detailed Description.................................................................................................................................. 26
4.1 Functional Overview .................................................................................................................... 26
4.2 Serial Digital Input ........................................................................................................................ 27
4.2.1 Integrated Adaptive Cable Equalizer.......................................................................... 27
4.3 Serial Digital Loop-Through Output ........................................................................................ 28
4.4 Serial Digital Reclocker ............................................................................................................... 29
4.4.1 PLL Loop Bandwidth ........................................................................................................29
4.5 External Crystal/Reference Clock ...........................................................................................30
4.6 Lock Detect ...................................................................................................................................... 31
4.6.1 Asynchronous Lock .......................................................................................................... 32
4.6.2 Signal Interruption............................................................................................................ 32
4.7 SMPTE Functionality .................................................................................................................... 33
4.7.1 Descrambling and Word Alignment ........................................................................... 33
4.8 Parallel Data Outputs ................................................................................................................... 33
4.8.1 Parallel Data Bus Buffers.................................................................................................33
4.8.2 Parallel Output in SMPTE Mode ................................................................................... 36
4.8.3 Parallel Output in DVB-ASI Mode ............................................................................... 36
4.8.4 Parallel Output in Data-Through Mode ..................................................................... 37
4.8.5 Parallel Output Clock (PCLK)......................................................................................... 37
4.9 Timing Signal Generator ............................................................................................................. 37
4.9.1 Manual Switch Line Lock Handling ............................................................................ 38
4.9.2 Automatic Switch Line Lock Handling....................................................................... 39
4.10 Programmable Multi-function Outputs ............................................................................... 42
4.11 H:V:F Timing Signal Generation ............................................................................................43
4.11.1 CEA-861 Timing Generation ....................................................................................... 44
4.12 Automatic Video Standards Detection ................................................................................ 51
4.12.1 2K Support......................................................................................................................... 53
4.13 Data Format Detection & Indication ..................................................................................... 54
4.14 EDH Detection .............................................................................................................................. 55
4.14.1 EDH Packet Detection ................................................................................................... 55
4.14.2 EDH Flag Detection ........................................................................................................ 55
4.15 Video Signal Error Detection & Indication ......................................................................... 56
4.15.1 TRS Error Detection........................................................................................................ 57
4.15.2 Line Based CRC Error Detection ................................................................................ 57
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4.15.3 EDH CRC Error Detection............................................................................................. 58
4.15.4 HD Line Number Error Detection .............................................................................. 58
4.16 Ancillary Data Detection & Indication ................................................................................. 59
4.16.1 Programmable Ancillary Data Detection................................................................ 60
4.16.2 SMPTE ST 352 Payload Identifier............................................................................... 61
4.16.3 Ancillary Data Checksum Error ................................................................................. 61
4.16.4 Video Standard Error.....................................................................................................62
4.17 Signal Processing ......................................................................................................................... 63
4.17.1 TRS Correction & Insertion........................................................................................... 64
4.17.2 Line Based CRC Correction & Insertion ................................................................... 64
4.17.3 Line Number Error Correction & Insertion ............................................................. 64
4.17.4 ANC Data Checksum Error Correction & Insertion ............................................. 64
4.17.5 EDH CRC Correction & Insertion ............................................................................... 65
4.17.6 Illegal Word Re-mapping ............................................................................................. 65
4.17.7 TRS and Ancillary Data Preamble Remapping...................................................... 65
4.17.8 Ancillary Data Extraction............................................................................................. 65
4.18 Audio De-embedder ................................................................................................................... 69
4.18.1 Serial Audio Data I/O Signals...................................................................................... 70
4.18.2 Serial Audio Data Format Support ............................................................................ 71
4.18.3 Audio Processing............................................................................................................. 75
4.18.4 Error Reporting ................................................................................................................ 82
4.19 GSPI - HOST Interface ................................................................................................................ 83
4.19.1 Command Word Description...................................................................................... 84
4.19.2 Data Read or Write Access........................................................................................... 84
4.19.3 GSPI Timing....................................................................................................................... 85
4.20 Host Interface Register Maps .................................................................................................. 87
4.20.1 Video Core Registers ...................................................................................................... 87
4.20.2 SD Audio Core Registers............................................................................................... 96
4.20.3 HD Audio Core Registers............................................................................................ 111
4.21 JTAG Test Operation ................................................................................................................ 127
4.22 Device Power-up .......................................................................................................................129
4.23 Device Reset ................................................................................................................................129
4.24 Standby Mode ............................................................................................................................ 129
5. Application Reference Design ............................................................................................................. 130
5.1 High Gain Adaptive Cable Equalizers ..................................................................................130
5.2 PCB Layout ..................................................................................................................................... 130
5.3 Typical Application Circuit ...................................................................................................... 131
6. References & Relevant Standards ....................................................................................................... 132
7. Package & Ordering Information ........................................................................................................ 133
7.1 Package Dimensions ...................................................................................................................133
7.2 Packaging Data ............................................................................................................................. 134
7.3 Marking Diagram ......................................................................................................................... 134
7.4 Solder Reflow Profiles ................................................................................................................135
7.5 Ordering Information .................................................................................................................135
GS1671A HD/SD SDI Receiver
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List of Figures
Figure 3-1: Digital Input Pin with Schmitt Trigger .............................................................................. 23
Figure 3-2: Bidirectional Digital Input/Output Pin .............................................................................23
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 24
Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 24
Figure 3-5: VBG .............................................................................................................................................. 24
Figure 3-6: LB_CONT .................................................................................................................................... 25
Figure 3-7: Loop Filter .................................................................................................................................. 25
Figure 3-8: SDO/SDO .................................................................................................................................... 25
Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 25
Figure 4-1: GS1671A Integrated EQ Block Diagram .......................................................................... 28
Figure 4-2: 27MHz Clock Sources ............................................................................................................ 30
Figure 4-3: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 34
Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 35
Figure 4-5: Switch Line Locking on a Non-Standard Switch Line ................................................. 39
Figure 4-6: H:V:F Output Timing - HDTV 20-bit Mode ..................................................................... 43
Figure 4-7: H:V:F Output Timing - HDTV 10-bit Mode ..................................................................... 43
Figure 4-8: H:V:F Output Timing - HD 20-bit Output Mode ............................................................ 43
Figure 4-9: H:V:F Output Timing - HD 10-bit Output Mode ............................................................ 44
Figure 4-10: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 44
Figure 4-11: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 44
Figure 4-12: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 46
Figure 4-13: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 46
Figure 4-14: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 47
Figure 4-15: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 47
Figure 4-16: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 48
Figure 4-17: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 49
Figure 4-18: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 49
Figure 4-19: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 50
Figure 4-20: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 50
Figure 4-21: 2K Feature Enhancement ................................................................................................... 53
Figure 4-22: Y/1ANC and C/2ANC Signal Timing .............................................................................. 60
Figure 4-23: Ancillary Data Extraction - Step A .................................................................................. 66
Figure 4-24: Ancillary Data Extraction - Step B ................................................................................... 67
Figure 4-25: Ancillary Data Extraction - Step C .................................................................................. 68
Figure 4-26: Ancillary Data Extraction - Step D .................................................................................. 68
Figure 4-27: ACLK to Data Signal Output Timing ............................................................................... 70
Figure 4-28: I2S Audio Output Format .................................................................................................... 71
Figure 4-29: AES/EBU Audio Output Format .......................................................................................71
Figure 4-30: Serial Audio, Left Justified, MSB First ............................................................................. 72
Figure 4-31: Serial Audio, Left Justified, LSB First .............................................................................. 72
Figure 4-32: Serial Audio, Right Justified, MSB First ..........................................................................72
Figure 4-33: Serial Audio, Right Justified, LSB First ........................................................................... 72
Figure 4-34: AES/EBU Audio Output to Bit Clock Timing ................................................................ 72
Figure 4-35: ECC 24-bit Array and Examples ...................................................................................... 75
Figure 4-36: Sample Distribution Over Five Video Frames (525-line Systems) ........................ 76
Figure 4-37: Audio Buffer After Initial 26 Sample Write .................................................................. 77
Figure 4-38: Audio Buffer Pointer Boundary Checking .................................................................... 77
Figure 4-39: GSPI Application Interface Connection ........................................................................ 83
Figure 4-40: Command Word Format ..................................................................................................... 84
Figure 4-41: Data Word Format ................................................................................................................ 84
Figure 4-42: Write Mode .............................................................................................................................. 85
GS1671A HD/SD SDI Receiver
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Figure 4-43: Read Mode ............................................................................................................................... 85
Figure 4-44: GSPI Time Delay .................................................................................................................... 85
Figure 4-45: In-Circuit JTAG .................................................................................................................... 127
Figure 4-46: System JTAG .........................................................................................................................128
Figure 4-47: Reset Pulse .............................................................................................................................129
Figure 5-1: Typical Application Circuit ................................................................................................ 131
Figure 7-1: GS1671A Packaging Dimensions .....................................................................................133
Figure 7-2: GS1671A Marking Diagram ...............................................................................................134
Figure 7-3: Pb-Free Solder Reflow Profile ...........................................................................................135
List of Tables
Table 1-1: Pin Descriptions ............................................................................................................................ 8
Table 2-1: Absolute Maximum Ratings................................................................................................... 16
Table 2-2: Recommended Operating Conditions................................................................................ 16
Table 2-3: DC Electrical Characteristics ................................................................................................. 17
Table 2-4: AC Electrical Characteristics ................................................................................................. 19
Table 4-1: Serial Digital Output................................................................................................................. 28
Table 4-2: PLL Loop Bandwidth ................................................................................................................ 29
Table 4-3: Input Clock Requirements...................................................................................................... 30
Table 4-4: Lock Detect Conditions............................................................................................................ 31
Table 4-5: GS1671A Output Video Data Format Selections ............................................................ 35
Table 4-6: GS1671A PCLK Output Rates ................................................................................................ 37
Table 4-7: Switch Line Position for Digital Systems ........................................................................... 40
Table 4-8: Output Signals Available on Programmable Multi-Function Pins............................ 42
Table 4-9: Supported CEA-861 Formats................................................................................................. 44
Table 4-10: CEA861 Timing Formats ....................................................................................................... 45
Table 4-11: Supported Video Standard Codes ..................................................................................... 51
Table 4-12: Data Format Register Codes ................................................................................................ 54
Table 4-13: Error Status Register and Error Mask Register .............................................................. 57
Table 4-14: IOPROC_1 and IOPROC_2 Register Bits.......................................................................... 63
Table 4-15: Serial Audio Pin Descriptions ............................................................................................. 70
Table 4-16: Audio Output Formats........................................................................................................... 71
Table 4-17: Audio Data Packet Detect Register ................................................................................... 73
Table 4-18: Audio Group DID Host Interface Settings....................................................................... 74
Table 4-19: Audio Data and Control Packet DID Setting Register ................................................. 74
Table 4-20: Audio Buffer Pointer Offset Settings ................................................................................ 78
Table 4-21: Audio Channel Mapping Codes ......................................................................................... 79
Table 4-22: Audio Sample Word Lengths .............................................................................................. 79
Table 4-23: Audio Channel Status Information Registers ................................................................ 80
Table 4-24: Audio Channel Status Block for Regenerate Mode Default Settings ..................... 81
Table 4-25: Audio Mute Control Bits ....................................................................................................... 81
Table 4-26: GSPI Time Delay ...................................................................................................................... 85
Table 4-27: GSPI Timing Parameters (50% levels; 3.3V or 1.8V operation) ................................ 86
Table 4-28: Video Core Configuration and Status Registers............................................................ 87
Table 4-29: SD Audio Core Configuration and Status Registers..................................................... 96
Table 4-30: HD Audio Core Configuration and Status Registers.................................................. 111
Table 4-31: ANC Extraction FIFO Access Registers.......................................................................... 126
Table 6-1: SMPTE Standards Reference................................................................................................ 132
Table 7-1: Packaging Data......................................................................................................................... 134
Table 7-2: GS1671A Ordering Information ......................................................................................... 135
GS1671A HD/SD SDI Receiver
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1. Pin Out
1.1 Pin Assignment
1.2 Pin Descriptions
132 45678910
A
B
C
D
E
F
G
H
J
K
PCLK
DVB_ASI
20bit/
10bit
LF
SDO STANDBY
ACLK
JTAG/
HOST
RESET
_TRST
WCLK
A_VDD
CORE
_GND
SDO
VBG
SDI
SDI
BUFF_
VDD
SDO_
EN/DIS
LB_CONT VCO_
VDD
VCO_
GND
RSV
PLL_
VDD
A_GND
A_GND
STAT0 STAT1
STAT2 STAT3
STAT4 STAT5
CORE
_GND
CORE
_GND
CORE
_GND
CORE
_VDD
CORE
_VDD
CORE
_VDD
CORE
_VDD
DOUT1
DOUT0 DOUT2 DOUT3
DOUT4 DOUT5
DOUT6 DOUT7
DOUT8 DOUT9
DOUT10 DOUT11
DOUT14 DOUT13
DOUT16 DOUT15
DOUT18 DOUT17
DOUT19
DOUT12
IO_VDD
IO_GND
PLL_
VDD
PLL_
GND
PLL_
VDD
A_GND
A_GND
A_GND
RC_BYP
SW_EN IO_GND IO_VDD
EQ_VDD EQ_GND PLL_
GND
PLL_
GND
AGCP RSV
SDOUT_
TDO
CS_
TMS
SDIN_
TDI
SCLK_
TCK
SMPTE_
BYPASS IO_GND IO_VDD
AUDIO_
EN/DIS
AMCLK
AOUT
_1/2
AOUT
_3/4
AOUT
_5/6
AOUT
_7/8
TIM_861 XTAL_
OUT
XTAL2
XTAL1
IO_GND
IO_VDD
IOPROC_
EN/DIS
AGCN A_GND
BUFF_
GND
CORE
_GND
Table 1-1: Pin Descriptions
Pin
Number Name Ty pe Description
A1 VBGAnalog Input Band Gap voltage filter connection.
A2 LF Analog Input Loop Filter component connection.
A3 LB_CONT Analog Input Connection for loop bandwidth control resistor.
A4 VCO_VDD Input Power
POWER pin for the VCO. Connect to a 1.2V±5% analog supply
followed by a RC filter (see 5.3 Typical Application Circuit). A 105Ω
1% resistor must be used in the RC filter circuit. VCO_VDD is
nominally 0.7V.
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A5, A6, B5,
B6, C5, C6 STAT[0:5] Output
MULTI-FUNCTIONAL OUTPUT PORT.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Each of the STAT[0:5] pins can be configured individually to output
one of the following signals:
Signal
H/HSYNC
V/VSYNC
F/DE
LOCKED
Y/1ANC
C/2ANC
DATA ERROR
VIDEO ERROR
AUDIO ERROR
EDH DETECTED
CARRIER DETECT
RATE_DET
Default
STAT0
STAT1
STAT2
STAT3
STAT4
−
STAT5
−
−
−
−
−
A7, D10,
G10, K7 IO_VDD Input Power POWER connection for digital I/O. Connect to 3.3V or 1.8V DC
digital.
A8 PCLK Output
PARALLEL DATA BUS CLOCK
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
HD 10-bit modePCLK @ 148.5 or 148.5/1.001MHz
HD 20-bit modePCLK @ 74.25 or 74.25/1.001MHz
SD 10-bit modePCLK @ 27MHz
SD 20-bit modePCLK @ 13.5MHz
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Ty pe Description
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A9, A10, B8,
B9, B10,C8,
C9, C10, E9,
E10
DOUT18, 17, 19,
16, 15, 12, 14, 13,
10, 11
Output
PARALLEL DATA BUS
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
20-bit mode
20bit/10bit = HIGH
SMPTE mode (SMPTE_BYPASS = HIGH
and DVB_ASI = LOW):
Luma data output for SD and HD data
rates
DVB-ASI mode (SMPTE_BYPASS = LOW
and DVB_ASI = HIGH):
Not defined
Data-Through mode (SMPTE_BYPASS =
LOW and DVB_ASI = LOW):
Data output
10-bit mode
20bit/10bit = LOW
SMPTE mode (SMPTE_BYPASS = HIGH
and DVB_ASI = LOW):
Multiplexed Luma/Chroma data output
for SD and HD data rates
DVB-ASI mode (SMPTE_BYPASS = LOW
and DVB_ASI = HIGH):
8b/10b decoded DVB-ASI data
Data-Through mode (SMPTE_BYPASS =
LOW and DVB_ASI = LOW):
Data output
B1 A_VDD Input Power POWER pin for analog circuitry. Connect to 3.3V DC analog.
B2, C3, C4 PLL_VDD Input Power POWER pins for the Reclocker PLL. Connect to 1.2V DC analog.
B3, F2 RSV These pins must be left unconnected.
B4 VCO_GND Input Power GND pin for the VCO. Connect to analog GND.
B7, D9, G9,
J7IO_GND Input Power GND connection for digital I/O. Connect to digital GND.
C1, D1 SDI, SDI Analog Input Serial Digital Differential Input.
C2, D2, D3,
E3, F3, G2A_GND Input Power GND pins for sensitive analog circuitry. Connect to analog GND.
C7RESET_TRSTInput
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to reset the internal operating conditions to default settings
and to reset the JTAG sequence.
Normal mode (JTAG/HOST = LOW):
When LOW, all functional blocks are set to default conditions and
all digital output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG/HOST = HIGH):
When LOW, all functional blocks are set to default and the JTAG test
sequence is reset.
When HIGH, normal operation of the JTAG test sequence resumes
after RESET_TRST is de-asserted.
D4, E4, F4 PLL_GND Input Power GND pins for the Reclocker PLL. Connect to analog GND.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Ty pe Description
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D5, E5, F5,
G4, G5CORE_GND Input Power GND connection for device core. Connect to digital GND.
D6, E6, F6,
G6 CORE_VDD Input Power POWER connection for device core. Connect to 1.2V DC digital.
D7 SW_EN Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable switch-line locking, as described in Section 4.9.1.
D8 JTAG/HOSTInput
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes.
E1 EQ_VDD Input Power POWER pin for SDI buffer. Connect to 3.3V DC analog.
E2 EQ_GND Input Power GND pin for SDI buffer. Connect to analog GND.
E7 SDOUT_TDO Output
COMMUNICATION SIGNAL OUTPUT
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data output/test data out.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test
results from the device.
In host interface mode, this pin is used to read status and
configuration data from the device.
Note: GSPI is slightly different than the SPI. For more details on GSPI,
please refer to 4.19 GSPI - HOST Interface.
E8 SDIN_TDI Input
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data in/test data in.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test data
into the device.
In host interface mode, this pin is used to write address and
configuration data words into the device.
F1, G1AGCP, A GCNAutomatic Gain Control for the equalizer. Attach the AGC capacitor
between these pins.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Ty pe Description
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F7 CS_TMSInput
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Chip select / test mode start.
In JTAG mode (JTAG/HOST = HIGH), this pin is Test Mode Start, used
to control the operation of the JTAG test.
In host interface mode (JTAG/HOST = LOW), this pin operates as the
host interface chip select and is active LOW.
F8 SCLK_TCK Input
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Serial data clock signal.
In JTAG mode (JTAG/HOST = HIGH), this pin is the JTAG clock.
In host interface mode (JTAG/HOST = LOW), this pin is the host
interface serial bit clock.
All JTAG/host interface addresses and data are shifted into/out of
the device synchronously with this clock.
F9, F10, H9,
H10, J8, J9,
J10, K8, K9,
K10
DOUT8, 9, 6, 7, 1,
4, 5, 0, 2, 3 Output
PARALLEL DATA BUS
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
20-bit mode
20bit/10bit = HIGH
SMPTE mode (SMPTE_BYPASS = HIGH
and DVB_ASI = LOW):
Chroma data output for SD and HD
data rates
DVB-ASI mode (SMPTE_BYPASS = LOW
and DVB_ASI = HIGH):
Not defined
Data-Through mode (SMPTE_BYPASS =
LOW and DVB_ASI = LOW):
Data output
10-bit mode
20bit/10bit = LOW Forced LOW
G3RC_BYP Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
When this pin is LOW, the serial digital output is the buffered
version of the input serial data. When this pin is HIGH, the serial
digital output is the reclocked version of the input serial data.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Ty pe Description
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G7SMPTE_BYPASS Input/Output
CONTROL SIGNAL INPUT/OUTPUT
Please refer to the Input/Output Logic parameters in the DC
Electrical Characteristics table for logic level threshold and
compatibility.
Indicates the presence of valid SMPTE data.
When the AUTO/MAN bit in the host interface register is HIGH
(Default), this pin is an OUTPUT. SMPTE_BYPASS is HIGH when the
device locks to a SMPTE compliant input. SMPTE_BYPASS is LOW
under all other conditions.
When the AUTO/MAN bit in the host interface register is LOW, this
pin is an INPUT:
No SMPTE scrambling takes place, and none of the I/O processing
features of the device are available when SMPTE_BYPASS is set
LOW.
When SMPTE_BYPASS is set HIGH, the device carries out SMPTE
scrambling and I/O processing.
When SMPTE_BYPASS and DVB_ASI are both set LOW, the device
operates in Data-Through mode.
G8DVB_ASI Input/Output
CONTROL SIGNAL INPUT
Please refer to the Input/Output Logic parameters in the DC
Electrical Characteristics table for logic level threshold and
compatibility.
Used to enable/disable DVB-ASI data extraction in manual mode.
When the AUTO/MAN bit in the host interface is LOW, this pin is an
input and when the DVB_ASI pin is set HIGH the device will carry out
DVB_ASI data extraction and processing. The SMPTE_BYPASS pin
must be set LOW. When SMPTE_BYPASS and DVB_ASI are both set
LOW, the device operates in Data-Through mode.
When the AUTO/MAN bit in the host interface is HIGH (default),
DVB-ASI is configured as a status output (set LOW), and DVB-ASI
input streams are not supported or recognized.
H1 BUFF_VDD Input Power POWER pin for the serial digital output 50Ω buffer. Connect to 3.3V
DC analog.
H2 BUFF_GND Input Power GND pin for the cable driver buffer. Connect to analog GND.
H3 AUDIO_EN/DISInput
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Enables or disables audio extraction.
H4 WCLK Output
48kHz word clock for Audio.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
H5 TIM_861 Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select CEA-861 timing mode.
When TIM_861 is HIGH, the device outputs CEA 861 timing signals
(HSYNC/VSYNC/DE) instead of H:V:F digital timing signals.
H6XTAL_OUT Digital
Output
Buffered 27MHz crystal output. Can be used to cascade the crystal
signal.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Ty pe Description
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H7 20bit/10bit Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select the output bus width.
HIGH = 20-bit, LOW = 10-bit.
H8 IOPROC_EN/DISInput
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable or disable audio and video processing features.
When IOPROC_EN is HIGH, the audio and video processing features
of the device are enabled. When IOPROC_EN is LOW, the processing
features of the device are disabled, and the device is in a
low-latency operating mode.
J1, K1 SDO, SDO Output
Serial Data Output Signal.
50Ω CML buffer for interfacing to an external cable driver.
Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s
and 270Mb/s.
J2SDO_EN/DIS Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable/disable the serial digital output stage.
When SDO_EN/DIS is LOW, the serial digital output signals, SDO and
SDO, are both pulled HIGH.
When SDO_EN/DIS is HIGH, the serial digital output signals, SDO and
SDO, are enabled.
J3 AOUT_1/2 Output
Serial Audio Output; Channels 1 and 2.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
J4ACLK Output
64fs sample clock for audio.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
J5 AOUT_5/6Output
Serial Audio Output; Channels 5 and 6.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
J6, K6XTAL2, XTAL1 Analog Input Input connection for 27MHz crystal.
K2 STANDBY Input
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
When this pin is set HIGH, the device is placed in a power-saving
mode. No data processing occurs, and the digital I/Os are powered
down.
In this mode, the serial digital output signals, SDO and SDO, are
both pulled HIGH.
K3 AOUT_3/4 Output
Serial Audio Output; Channels 3 and 4.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Ty pe Description
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K4 AMCLK Output
Oversampled master clock for audio (128fs, 256fs, 512fs selectable).
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
K5 AOUT_7/8 Output
Serial Audio Output; Channels 7 and 8.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Table 1-1: Pin Descriptions (Continued)
Pin
Number Name Ty pe Description
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 Recommended Operating Conditions
Table 2-1: Absolute Maximum Ratings
Parameter Value/Units
Supply Voltage, Digital Core (CORE_VDD) -0.3V to +1.5V
Supply Voltage, Digital I/O (IO_VDD) -0.3V to +4.0V
Supply Voltage, Analog 1.2V (PD_VDD, VCO_VDD) -0.3V to +1.5V
Supply Voltage, Analog 3.3V (EQ_VDD, BUFF_VDD,
A_VDD) -0.3V to +4.0V
Input Voltage Range (digital inputs) -2.0V to +5.25V
Operating Temperature Range -20°C to +85°C
Functional Temperature Range -40°C to +85°C
Storage Temperature Range -50°C to +125°C
Peak Reflow Temperature (JEDEC J-STD-020C)260°C
ESD Sensitivity, HBM (JESD22-A114) 2kV
Note:
Absolute Maximum Ratings are those values beyond which damage may occur. Functional
operation under these conditions or at any other condition beyond those indicated in the
AC/DC Electrical Characteristics sections is not implied.
Table 2-2: Recommended Operating Conditions
TA = -20°C to + 85°C, unless otherwise shown.
Parameter Symbol Conditions Min Typ Max Units Notes
Supply Voltage, Digital Core CORE_VDD – 1.14 1.2 1.26V−
Supply Voltage, Digital I/O IO_VDD
1.8V mode 1.71 1.8 1.89 V −
3.3V mode 3.13 3.3 3.47 V −
Supply Voltage, PLL PLL_VDD – 1.14 1.2 1.26V–
Supply Voltage, AnalogA_VDD – 3.13 3.3 3.47 V 1
Supply Voltage, Serial Digital Input EQ_VDD – 3.13 3.3 3.47 V 1
Supply Voltage, CD Buffer BUFF_VDD – 3.13 3.3 3.47 V 1
Note:
1. The 3.3V supplies must track the 3.3V supply of an external CD.
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2.3 DC Electrical Characteristics
Table 2-3: DC Electrical Characteristics
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Units
System
+1.2V Supply Current I1V2
10/20bit HD −170 220 mA
10/20bit SD−140 185 mA
DVB_ASI−130 170 mA
+1.8V Supply Current I1V8
10/20bit HD −15 21 mA
10/20bit SD−47mA
DVB_ASI−46mA
+3.3V Supply Current I3V3
10/20bit HD −110 135 mA
10/20bit SD−90 100 mA
DVB_ASI−90 95 mA
Total Device Power
(IO_VDD = 1.8V) P1D8
10/20bit HD −480 590 mW
10/20bit SD−420 520 mW
DVB_ASI−410 500 mW
Reset −390 −mW
Standby−23 45 mW
Total Device Power
(IO_VDD = 3.3V) P3D3
10/20bit HD −570 730 mW
10/20bit SD−460560mW
DVB_ASI−440 540 mW
Reset −410 −mW
Standby−23 45 mW
Digital I/O
Input Logic LOW VIL 3.3V or 1.8V operation IO_VSS
-0.3 –0.3 x
IO_VDD V
Input Logic HIGHVIH 3.3V or 1.8V operation 0.7 x
IO_VDD –IO_VDD
+0.3 V
Output Logic LOW VOL
IOL = 5mA, 1.8V operation – – 0.2 V
IOL = 8mA, 3.3V operation – – 0.4 V
Output Logic HIGHVOH
IOH = 5mA, 1.8V operation 1.4 – – V
IOH = 8mA, 3.3V operation 2.4 – – V
Serial Input
Serial Input Common
Mode Voltage– 75Ω load–2.2–V
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Serial Output
Serial Output
Common Mode
Voltage
−50Ω loadBUFF_VDD
-(0.6/2)
BUFF_VDD
-(0.45/2)
BUFF_VDD
-(0.35/2) V
Note:
The output drive strength of the digital outputs can be programmed through the host interface. please see Table 4-28: Video Core
Configuration and Status Registers, register 06Dh for details.
Table 2-3: DC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Units
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2.4 AC Electrical Characteristics
Table 2-4: AC Electrical Characteristics
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Units Notes
System
Device Latency:
AUDIO_EN = 1,
SMPTE mode,
IOPROC_EN = 1
HD 79 – 83 PCLK –
SD50–59PCLK –
Device Latency:
AUDIO_EN = 0,
SMPTE mode,
IOPROC_EN = 1
–
HD 44 – 48 PCLK –
SD44–48PCLK –
Device Latency:
AUDIO_EN = 0,
SMPTE mode,
IOPROC_EN = 0
–
HD 33 – 36PCLK –
SD32–35PCLK –
Device Latency:
AUDIO_EN = 0,
SMPTE bypass,
IOPROC_EN = 0
–
HD 6–9PCLK –
SD5–9PCLK –
Device Latency:
DVB-ASI–SD12–16PCLK –
Reset Pulse Width treset –1––ms–
Parallel Output
Parallel Clock FrequencyfPCLK – 13.5 – 148.5 MHz –
Parallel Clock Duty Cycle DCPCLK –40–60% –
Output Data Hold Time (1.8V) toh
HD 10-bit
6pF CLOAD
DBUS1.0 – – ns 1
STAT 1.0 – – ns 1
HD 20-bit
6pF CLOAD
DBUS1.0 – – ns 1
STAT 1.0 – – ns 1
SD 10-bit
6pF CLOAD
DBUS19.4 – – ns 1
STAT 19.4 – – ns 1
SD 20-bit
6pF CLOAD
DBUS38.0 – – ns 1
STAT 38.0 – – ns 1
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Output Data Hold Time (3.3V) toh
HD 10-bit
6pF CLOAD
DBUS1.0 – – ns 2
STAT 1.0 – – ns 2
HD 20-bit
6pF CLOAD
DBUS1.0 – – ns 2
STAT 1.0 – – ns 2
SD 10-bit
6pF CLOAD
DBUS19.4 – – ns 2
STAT 19.4 – – ns 2
SD 20-bit
6pF CLOAD
DBUS38.0 – – ns 2
STAT 38.0 – – ns 2
Output Data Delay Time (1.8V) tod
HD 10-bit
15pF CLOAD
DBUS––3.7ns 3
STAT – – 4.4 ns 3
HD 20-bit
15pF CLOAD
DBUS––3.7ns 3
STAT – – 4.4 ns 3
SD 10-bit
15pF CLOAD
DBUS– – 22.2 ns 3
STAT – – 22.2 ns 3
SD 20-bit
15pF CLOAD
DBUS– – 41.0 ns 3
STAT – – 41.0 ns 3
Output Data Delay Time (3.3V) tod
HD 10-bit
15pF CLOAD
DBUS––3.7ns 4
STAT – – 4.1 ns 4
HD 20-bit
15pF CLOAD
DBUS––3.7ns 4
STAT – – 4.1 ns 4
SD 10-bit
15pF CLOAD
DBUS– – 22.2 ns 4
STAT – – 22.2 ns 4
SD 20-bit
15pF CLOAD
DBUS– – 41.0 ns 4
STAT – – 41.0 ns 4
Output Data Rise/Fall Time (1.8V) tr/tf
All modes
6pF CLOAD
STAT – – 0.4 ns 1
DBUS––0.4ns 1
AUDIO – – 0.6ns 1
All modes
15pF CLOAD
STAT – – 1.5 ns 3
DBUS––1.4ns 3
AUDIO – – 2.3 ns 3
Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Units Notes
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Output Data Rise/Fall Time (3.3V) tr/tf
All modes
6pF CLOAD
STAT – – 0.5 ns 2
DBUS––0.4ns 2
AUDIO – – 0.6ns 2
All modes
15pF CLOAD
STAT – – 1.6ns 4
DBUS––1.4ns 4
AUDIO – – 2.2 ns 4
Serial Digital Input
Serial Input Data Rate DRSDI – 0.27 – 1.485 Gb/s –
Serial Input Voltage SwingΔVSDI
TA =25°C, differential,
270Mb/s & 1.485Gb/s 720 800 950 mVp-p 6
Achievable Cable Length –
Belden 1694A cable, HD 210 230 – m –
Belden 1694A cable, SD 400 440 – m –
Input Return Loss – single ended15 21 – dB7
Input Resistance–single ended–1.52 – kΩ–
Input Capacitance–single ended–1 – pF –
Serial Digital Output
Serial Output Data Rate DRSDO – 0.27 – 1.485 Gb/s –
Serial Output SwingΔVSDO Differential with 100Ω
load320 – 600 mVp-p –
Serial Output Rise Time
20% ~ 80% trSDO – – – 180 ps –
Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Units Notes
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Serial Output Fall Time
20% ~ 80% tfSDO – – – 180 ps –
Serial Output Jitter with
loop-through modetOJ
HD, PRBS23, Belden
1694A cable, 210m – – 100 ps –
SD, PRBS23, Belden
1694A cable, 440m – – 470 ps –
Serial Output Duty Cycle Distortion DCDSDD
HD – 10 – ps –
SD–20–ps–
Synchronous lock time – – – – 25 μs–
Asynchronous lock time – – 0.1 – 20 ms –
Lock time from power-up – After 20 minutes at -20°C–– 5 s –
GSPI
GSPI Input Clock FrequencyfSCLK
50% levels
3.3V or 1.8V operation
––60MHz 5
GSPI Input Clock Duty Cycle DCSCLK 40 50 60% 5
GSPI Input Data Setup Time – 1.5 – – ns 5
GSPI Input Data Hold Time – 1.5 – – ns 5
GSPI Output Data Hold Time – 1.5 – – ns 5
CS low before SCLK rising edge– 1.5––ns5
Time between end of command
word (or data in Auto-Increment
mode) and the first SCLK of the
following data word - write cycle
– 37.1 – – ns 5
Time between end of command
word (or data in Auto-Increment
mode) and the first SCLK of the
following data word - read cycle
– 148.4 – – ns 5
CS high after SCLK falling edge – 37.1 – – ns 5
Notes:
1. 1.89V and 0ºC.
2. 3.47V and 0ºC.
3. 1.71V and 85ºC
4. 3.13V and 85ºC
5. Timing parameters defined in Section 4.19.3
6. 0m cable length
7. Tested on a GS1671 board from 5MHz to 1.485GHz.
Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Units Notes
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3. Input/Output Circuits
Figure 3-1: Digital Input Pin with Schmitt Trigger (20BIT/10BIT, AUDIO_EN/DIS,
CS_TMS, SW_EN, IOPROC_EN/DIS, JTAG/HOST, RC_BYP, RESET_TRST,
SCLK_TCK, SDIN_TDI, SDO_EN/DIS, STANDBY, TIM_861)
Figure 3-2: Bidirectional Digital Input/Output Pin - Configured to Output
unless in Reset Mode. (ACLK, AMCLK, AOUT_1/2, AOUT_3/4, AOUT_5/6,
AOUT_7/8, DVB_ASI, SMPTE_BYPASS, WCLK)
IO_VDD
200Ω
Input Pin
IO_VDD
200Ω
Output Pin
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Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive
strength. These pins are configured to output unless in Reset Mode; in which
case they are high-impedance. The drive strength can be set by writing to
address 06Dh in the host interface register. (DOUT0, DOUT1, DOUT2, DOUT3,
DOUT4, DOUT5, DOUT6, DOUT7, DOUT8, DOUT9, SDOUT_TDO, STAT0, STAT1,
STAT2, STAT3, STAT4, STAT5, XTAL_OUT, DOUT10, DOUT11, DOUT12,
DOUT13, DOUT14, DOUT15, DOUT16, DOUT17, DOUT18, DOUT19, PCLK)
Figure 3-4: XTAL1/XTAL2/XTAL_OUT
Figure 3-5: VBG
IO_VDD
200Ω
Output Pin
XTAL1
XTAL2
XTAL_OUT
VBG
50Ω
2kΩ
A_VDD
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Figure 3-6: LB_CONT
Figure 3-7: Loop Filter
Figure 3-8: SDO/SDO
Figure 3-9: Equalizer Input Equivalent Circuit
Out <0>
Out <1>
EQ_VDD
LB_CONT
50Ω50Ω
SDO
SDO
BUFF_VDD
4k
6k
4k
6k
RC
SDI SDI
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4. Detailed Description
4.1 Functional Overview
The GS1671A is a multi-rate SDI integrated Receiver which includes complete SMPTE
processing, as per SMPTE ST 292 and SMPTE ST 259-C. The SMPTE processing features
can be bypassed to support signals with other coding schemes.
The GS1671A integrates Semtech's adaptive cable equalizer technology, achieving
unprecedented cable lengths and jitter tolerance. It features DC restoration to
compensate for the DC content of SMPTE pathological signals.
The device features an Integrated Reclocker with an internal VCO and a wide
Input Jitter Tolerance (IJT) of 0.7UI.
A serial digital loop through output is provided, which can be configured to output
either reclocked or non-reclocked serial digital data. The Serial Digital Output can be
connected to an external Cable Driver.
The device operates in one of four basic modes: SMPTE mode, DVB-ASI mode,
Data-Through mode or Standby mode.
In SMPTE mode, the GS1671A performs SMPTE de-scrambling and NRZI to NRZ
decoding and word alignment. Line-based CRC errors, line number errors, TRS errors
and ancillary data check sum errors can all be detected. The GS1671A also provides
ancillary data extraction. The entire ancillary data packet is extracted, and written to
host-accessible registers. Other processing functions include H:V:F timing extraction,
Luma and Chroma ancillary data indication, video standard detection, and
SMPTE ST 352 packet detection and decoding. All of the processing features are
optional, and may be enabled or disabled via the Host Interface.
In DVB-ASI mode, 8b/10b decoding is applied to the received data stream.
In Data-Through mode, all forms of SMPTE and DVB-ASI decoding are disabled, and the
device can be used as a simple serial to parallel converter.
The device can also be placed in a lower power Standby mode. In this mode, no signal
processing is carried out and the parallel output is held static. Placing the Receiver in
Standby mode will automatically place the integrated equalizer in power down mode as
well.
Parallel data outputs are provided in 20-bit or 10-bit multiplexed format for HD and SD
video rates. In all cases, this 20-bit parallel bus can be multiplexed onto 10 bits for a low
pin count interface with downstream devices. The associated Parallel Clock input signal
operates at 148.5 or 148.5/1.001MHz (for all HD 10-bit multiplexed modes), 74.25 or
74.25/1.001MHz (for HD 20-bit mode), 27MHz (for SD 10-bit mode) and 13.5MHz (for SD
20-bit mode).
Up to eight channels, in two groups, of serial digital audio may be extracted from the
video data stream, in accordance with SMPTE ST 272 and SMPTE ST 299. The output
signal formats supported by the device include AES/EBU and three other industry
standard serial digital formats. 16, 20 and 24-bit audio formats are supported at 48kHz
synchronous for SD modes and 48kHz synchronous or asynchronous in HD mode.
Additional audio processing features include group selection, channel swapping, ECC
error detection and correction (HD mode only), and audio channel status extraction.
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Audio clock and control signals provided by the device include Word Clock (fs),
Serial Clock (64fs), and Audio Master Clock at user-selectable rates of 128fs, 256fs or
512fs.
4.2 Serial Digital Input
The GS1671A can accept serial digital inputs compliant with SMPTE 292 and
SMPTE ST 259-C.
4.2.1 Integrated Adaptive Cable Equalizer
The GS1671A integrates Semtech's adaptive cable equalizer technology.
The integrated adaptive equalizer can equalize HD and SD serial digital signals, and will
typically equalize 230m of Belden 1694A cable at 1.
485Gb/
s and 440m at 270Mb/s.The
integrated adaptive equalizer is powered from a single +3.3V power supply and
consumes approximately 195mW of power.
The equalizer can be bypassed by programming register 073h through the GSPI
interface.
4.2.1.1 Serial Digital Inputs
The Serial Data Signal may be connected to the input pins (SDI/SDI) in either a
differential or single ended configuration. AC coupling of the inputs is recommended, as
the SDI and SDI inputs are internally biased at approximately 1.8V.
4.2.1.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency
response closely matches the inverse of the cable loss characteristic. In addition, the
variation of the frequency response with control voltage imitates the variation of the
inverse cable loss characteristic with cable length.
The edge energy of the equalized signal is monitored by a detector circuit which
produces an error signal corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is integrated by both an internal and
an external AGC filter capacitor providing a steady control voltage for the gain stage. As
the frequency response of the gain stage is automatically varied by the application of
negative feedback, the edge energy of the equalized signal is kept at a constant level
which is representative of the original edge energy at the transmitter. The equalized
signal is also DC restored, effectively restoring the logic threshold of the equalized signal
to its correct level independent of shifts due to AC-coupling.
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Figure 4-1: GS1671A Integrated EQ Block Diagram
4.3 Serial Digital Loop-Through Output
The GS1671A contains a 100Ω differential serial output buffer which can be configured
to output either a retimed or a buffered version of the serial digital input. The SDO and
SDO outputs of this buffer can interface directly to a 1.485Gb/s-capable, SMPTE
compliant Semtech cable driver. See 5.3 Typical Application Circuit on page 133.
When the RC_BYP pin is set HIGH, the serial digital output is the re-timed version of the
serial input.
When the RC_BYP pin is set LOW, the serial digital output is simply the buffered version
of the serial input, bypassing the internal reclocker.
The output can be disabled by setting the SDO_EN/DIS pin LOW. The output is also
disabled when the STANDBY pin is asserted HIGH. When the output is disabled, both
SDO and SDO pins are set to VDD and remain static.
The SDO output is muted when the RC_BYP pin is set HIGH and the PLL is unlocked
(LOCKED pin is LOW). When muted, the output is held static at logic ‘0’ or logic ‘1’.
Note: The serial digital output is muted when the GS1671A is unlocked.
Equalizer Output
AGC
SDI SDO
SDI SDO
AGCAGC
GAIN_SEL
DC
Restore
Table 4-1: Serial Digital Output
SDO_EN/DIS RC_BYP SDO/SDO
0X Disabled
11 Re-timed
10Buffered (not re-timed)
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4.4 Serial Digital Reclocker
The GS1671A includes both a PLL stage and a sampling stage.
The PLL is comprised of two distinct loops:
• A coarse frequency acquisition loop sets the centre frequency of the integrated
Voltage Controlled Oscillator (VCO) using an external 27MHz reference clock
• A fine frequency and phase locked loop aligns the VCO’s phase and frequency to
the input serial digital stream
The frequency lock loop results in a very fast lock time.
The sampling stage re-times the serial digital input with the locked VCO clock. This
generates a clean serial digital stream, which may be output on the SDO/SDO output
pins and converted to parallel data for further processing. Parallel data is not affected by
RC_BYP. Only the SDO is affected by this pin.
4.4.1 PLL Loop Bandwidth
The fine frequency and phase lock loop in the GS1671A reclocker is non-linear. The PLL
loop bandwidth scales with the jitter amplitude of the input data stream; automatically
reduces bandwidth in response to higher jitter. This allows the PLL to reject more of the
jitter in the input data stream and produce a very clean reclocked output.
The loop bandwidth of the GS1671A PLL is defined with 0.2UI input jitter. The
bandwidth is controlled by the LB_CONT pin. Under nominal conditions, with the
LB_CONT pin floating and 0.2UI input jitter applied, the loop bandwidth is set to 1/1000
of the frequency of the input data stream. Connecting the LB_CONT pin to 3.3V reduces
the bandwidth to half of the nominal setting. Connecting the LB_CONT pin to GND
increases the bandwidth to double the nominal setting. Table 4-2 below summarizes this
information.
Table 4-2: PLL Loop Bandwidth
Input Data Rate LB_CONT Pin Connection Loop Bandwidth (MHz)1
SD
3.3V 0.135
Floating0.27
0V 0.54
HD
3.3V 0.75
Floating1.5
0V 3.0
1Measured with 0.2UI input jitter applied
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4.5 External Crystal/Reference Clock
The GS1671A requires an external 27MHz reference clock for correct operation. This
reference clock is generated by connecting a crystal to the XTAL1 and XTAL2 pins of the
device. See Application Reference Design on page 132. Table 4-3 shows XTAL
characteristics.
Alternately, a 27MHz external clock source can be connected to the XTAL1 pin of the
device, as shown in Figure 4-2.
The frequency variation of the crystal including aging, supply and temperature
variation, should be less than +/-100ppm.
The equivalent series resistance (or motional resistance) should be a maximum of 50Ω.
The external crystal is used in the frequency acquisition process. It has no impact on the
output jitter performance of the part when the part is locked to incoming data. Because
of this, the only key parameter is the frequency variation of the crystal that is stated
above.
Figure 4-2: 27MHz Clock Sources
External Crystal Connection
XTAL1
XTAL2
XTAL1
XTAL2
External Clock Source Connection
16pF
16pF
External
Clock
NC
K6 K6
J6 J6
Notes:
1. Capacitor values listed represent the total capacitance,
including discrete capacitance and parasitic board capacitance.
2.XTAL1 serves as an input, which may alternatively accept a 27MHz clock
source.
Table 4-3: Input Clock Requirements
Parameter Min Typ Max Units
XTAL1 Low Level Input Voltage
(Vil)−−20% of VDD_IO V
XTAL1 High Level Input
Voltage (Vih)80% of VDDIO −−V
XTAL1 Input Slew Rate 2 −−V/ns
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4.6 Lock Detect
The LOCKED output signal is available by default on the STAT3 output pin, but may be
programmed to be output through any one of the six programmable multi-functional
pins of the device: STAT[5:0].
The LOCKED output signal is set HIGH by the Lock Detect block under the following
conditions:
Note 1: The part will lock to ASI in Auto mode, but could falsely unlock for some ASI
input patterns.
Note 2: In Standby mode, the reclocker PLL unlocks. However, the LOCKED signal
retains whatever state it previously held. So, if before Standby assertion, the LOCKED
signal is HIGH, then during standby, it remains HIGH regardless of the status of the PLL.
XTAL1 to XOUT Prop. Delay
(High to Low) 1.3 1.5 2.3 ns
XTAL1 to XOUT Prop. Delay
(Low to High) 1.3 1.62.3 ns
Note:
Valid when the cell is used to buffer an external clock source which is connected to the XTAL1 pin, then nothing
should be connected to the XTAL2 pin.
Table 4-3: Input Clock Requirements (Continued)
Parameter Min Typ Max Units
Table 4-4: Lock Detect Conditions
Mode of Operation Mode Setting Condition for Locked
Data-Through ModeSMPTE_BYPASS = LOW
DVB_ASI = LOW Reclocker PLL is locked.
SMPTE ModeSMPTE_BYPASS = HIGH
DVB_ASI = LOW
Reclocker PLL is locked
two consecutive TRS words are
detected in a two-line window.
SMPTE Mode with Lock
Noise-Immunity
Enabled
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Bit 0x085[10] set to 1
AUTO/MAN = HIGH
Reclocker PLL is locked.
Two consecutive TRS words are
detected in a two-line window. The
last two detected TRS words must
have the same alignment.
Note: Auto mode only. Not supported
in Manual mode.
DVB_ASI Mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
Bit AUTO/MAN = LOW
Reclocker PLL is locked
32 consecutive DVB_ASI words with
no errors are detected within a
128-word window.
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4.6.1 Asynchronous Lock
The lock detection algorithm is a continuous process, beginning at device power-up or
after a system reset. It continues until the device is powered down or held in reset.
The device first determines if a valid serial digital input signal has been presented to the
device. If no valid serial data stream has been detected, the serial data into the device is
considered invalid, and the LOCKED signal is LOW.
Once a valid input signal has been detected, the asynchronous lock algorithm enters a
“hunt” phase, in which the device attempts to detect the presence of either TRS words or
DVB-ASI sync words.
By default, the device powers up in auto mode (the AUTO/MAN bit in the host interface
is set HIGH). In this mode, the device operating frequency toggles between HD and SD
rates as it attempts to lock to the incoming data rate. The PCLK output continues to
operate, and the frequency may switch between 148.5MHz, 74.25MHz, 27MHz and
13.5MHz.
When the device is operating in manual mode (AUTO/MAN bit in the host interface is
LOW), the operating frequency needs to be set through the host interface using the
RATE_DET bit. In this mode, the asynchronous lock algorithm does not toggle the
operating rate of the device and attempts to lock within a single standard. Lock is
achieved within three lines of the selected standard.
4.6.2 Signal Interruption
The device tolerates a signal interruption of up to 10μs without unlocking, as long as no
TRS words are deleted by this interruption. If a signal interruption of greater than 10μs
is detected, the lock detection algorithm may lose the current data rate, and LOCKED
will de-assert until the data rate is re-acquired by the lock detection block.
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4.7 SMPTE Functionality
4.7.1 Descrambling and Word Alignment
The GS1671A performs NRZI to NRZ decoding and data descrambling according to
SMPTE 292/SMPTE ST 259-C and word aligns the data to TRS sync words.
When operating in manual mode (AUTO/MAN = LOW), the device only carries out
SMPTE decoding, descrambling and word alignment when the SMPTE_BYPASS pin is set
HIGH and the DVB_ASI pin is set LOW.
When operating in Auto mode (AUTO/MAN = HIGH), the GS1671A carries out
descrambling and word alignment to enable the detection of TRS sync words. When two
consecutive valid TRS words (SAV and EAV), with the same bit alignment have been
detected, the device word-aligns the data to the TRS ID words.
TRS ID word detection is a continuous process. The device remains in SMPTE mode until
TRS ID words fail to be detected.
Note: Both 8-bit and 10-bit TRS headers are identified by the device.
4.8 Parallel Data Outputs
The parallel data outputs are aligned to the rising edge of the PCLK.
4.8.1 Parallel Data Bus Buffers
The parallel data bus, status signal outputs and control signal input pins are all
connected to high-impedance buffers.
The device supports 1.8 or 3.3V (LVTTL and LVCMOS levels) supplied at the IO_VDD and
IO_GND pins.
All output buffers (including the PCLK output), are set to high-impedance in Reset mode
(RESET_TRST = LOW).
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Figure 4-3: PCLK to Data and Control Signal Output Timing - SDR Mode 1
toh tr/tf (min) C
load
tod tr/tf (max) toh tr/tf (min) tod tr/tf (max)
dbus 1.000ns 0.400ns 3.700ns 1.400ns 1.000ns 0.400ns 3.700ns 1.400ns
stat 1.000ns 0.500ns 4.100ns 1.600ns 1.000ns 0.400ns 4.400ns 1.500ns
10bHD Mode
3.3V 1.8V
6 pF 15 pF 6 pF 15 pF
I/O Timing Specs:
DBUS[19:10]
PCLK_OUT
Cr0Y0 Y1
6.734ns (HD 10-bit)
37.037ns (SD 10-bit)
20%
80%
tr
20%
80%
tf
Cb1
10-bit SDR Mode:
toh
tod
toh tr/tf (min) tod tr/tf (max) toh tr/tf (min) tod tr/tf (max)
dbus 19.400ns 0.400ns 22.200ns 1.400ns 19.400ns 0.400ns 22.200ns 1.400ns
stat 19.400ns 0.500ns 22.200ns 1.600ns 19.400ns 0.400ns 22.200ns 1.500ns
10bSD Mode
3.3V 1.8V
6 pF 15 pF 6 pF 15 pF
C
load
C
load
C
load
C
load
C
load
C
load
C
load
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Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 2
The GS1671A has a 20-bit output parallel bus, which can be configured for different
output formats as shown in Table 4-5.
I/O Timing Specs:
DBUS[9:0]
PCLK_OUT
Cb0 Cr0 Cb1
13.468ns (HD 20-bit)
74.074ns (SD 20-bit)
20%
80%
tr
20%
80%
tf
Cr1
20-bit SDR Mode:
toh
tod
DBUS[19:10] Y0 Y1 Y2 Y3
toh tr/tf (min) C
LOAD
tod tr/tf (max) toh tr/tf (min) tod tr/tf (max)
dbus 1.000ns 0.400ns 3.700ns 1.400ns 1.000ns 0.400ns 3.700ns 1.400ns
stat 1.000ns 0.500ns 4.100ns 1.600ns 1.000ns 0.400ns 4.400ns 1.500ns
20bHD Mode
3.3V
6 pF 15 pF
1.8V
6 pF 15 pF
toh tr/tf (min) tod tr/tf (max) toh tr/tf (min) tod tr/tf (max)
dbus 38.000ns 0.400ns 41.000ns 1.400ns 38.000ns 0.400ns 41.000ns 1.400ns
stat 38.000ns 0.500ns 41.000ns 1.600ns 38.000ns 0.400ns 41.000ns 1.500ns
20bSD Mode
3.3V 1.8V
6 pF 15 pF 6 pF 15 pF
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
Table 4-5: GS1671A Output Video Data Format Selections
Output Data
Format
Pin/Register Bit Settings
DOUT[9:0] DOUT[19:10]
20BIT
/10BIT
RATE_
SEL
SMPTE_
BYPASS DVB-ASI
20-bit
demultiplexed HD
format
HIGHLOW HIGHLOW Chroma Luma
20-bit data output
HD format HIGH LOW LOW LOW DATA DATA
20-bit
demultiplexed SD
format
HIGHHIGHHIGHLOW Chroma Luma
20-bit data output
SD format HIGHHIGH LOW LOW DATA DATA
10-bit multiplexed
HD format LOW LOW HIGH LOW Driven LOW Luma/Chroma
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4.8.2 Parallel Output in SMPTE Mode
When the device is operating in SMPTE mode (SMPTE_BYPASS = HIGH and
DVB_ASI = LOW), data is output in either multiplexed or demultiplexed form depending
on the setting of the 20bit/10bit pin.
When operating in 20-bit mode (20bit/10bit = HIGH), the output data is demultiplexed
Luma and Chroma data for SD and HD data rates.
When operating in 10-bit mode (20bit/10bit = LOW), the output data is multiplexed
Luma and Chroma data for SD and HD data rates. In this mode, the data is presented on
the DOUT[19:10] pins, with DOUT[9:0] being forced LOW.
4.8.3 Parallel Output in DVB-ASI Mode
In DVB-ASI mode, the 20bit/10bit pin must be set LOW to configure the output parallel
bus for 10-bit operation.
DVB-ASI mode is enabled when the AUTO/MAN bit is LOW, SMPTE_BYPASS pin is LOW
and the DVB_ASI pin is HIGH.
The extracted 8-bit data is presented on DOUT[17:10] such that DOUT[17:10] = HOUT ~
AOUT, where AOUT is the least significant bit of the decoded transport stream data.
In addition, the DOUT19 and DOUT18 pins are configured as DVB-ASI status signals
WORDERR and SYNCOUT respectively.
SYNCOUT is HIGH whenever a K28.5 sync character is output from the device.
WORDERR is HIGH whenever the device has detected a running disparity error or
illegal code word.
10-bit data output
HD format LOW LOW LOW LOW Driven LOW DATA
10-bit multiplexed
SD format LOW HIGHHIGH LOW Driven LOW Luma/Chroma
10-bit data output
SD format LOW HIGH LOW LOW Driven LOW DATA
DVB-ASI format LOW HIGH−HIGH
DOUT19 = WORD_ERR
DOUT18 = SYNC_OUT
DOUT17 = H_OUT
DOUT16 = G_OUT
DOUT15 = F_OUT
DOUT14 = E_OUT
DOUT13 = D_OUT
DOUT12 = C_OUT
DOUT11 = B_OUT
DOUT10 = A_OUT
Note: When in Auto Mode, swap RATE_SEL with RATE_DET.
Table 4-5: GS1671A Output Video Data Format Selections (Continued)
Output Data
Format
Pin/Register Bit Settings
DOUT[9:0] DOUT[19:10]
20BIT
/10BIT
RATE_
SEL
SMPTE_
BYPASS DVB-ASI
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4.8.4 Parallel Output in Data-Through Mode
This mode is enabled when the SMPTE_BYPASS and DVB_ASI pins are LOW.
In this mode, data is passed to the output bus without any decoding, descrambling or
word-alignment.
The output data width (10-bit or 20-bit) is controlled by the setting of the 20bit/10bit pin.
4.8.5 Parallel Output Clock (PCLK)
The frequency of the PCLK output signal of the GS1671A is determined by the output
data rate and the 20bit/10bit pin setting. Table 4-6 lists the output signal formats
according to the data format selected in Manual mode (AUTO/MAN bit in the host
interface is set LOW), or detected in Auto mode (AUTO/MAN bit in the host interface is
set HIGH).
4.9 Timing Signal Generator
The GS1671A has an internal timing signal generator which is used to generate digital
FVH timing reference signals, to detect and correct certain error conditions and
automatic video standard detection.
The timing signal generator is only operational in SMPTE mode
(SMPTE_BYPASS = HIGH).
Table 4-6: GS1671A PCLK Output Rates
Output Data
Format
Pin/Control Bit Settings
PCLK Rate
20bit/
10bit RATE_DET SMPTE_
BYPASS DVB-ASI
20-bit demultiplexed
HD format HIGHLOWHIGHLOW 74.25 or
74.25/1.001MHz
20-bit data output
HD format HIGHLOWLOWLOW 74.25 or
74.25/1.001MHz
20-bit demultiplexed
SD format HIGHHIGHHIGH LOW 13.5MHz
20-bit data output
SD format HIGHHIGH LOW LOW 13.5MHz
10-bit multiplexed
HD format LOW LOW HIGHLOW 148.5 or
148.5/1.001MHz
10-bit data output
HD format LOW LOW LOW LOW 148.5 or
148.5/1.001MHz
10-bit multiplexed
SD format LOW HIGHHIGH LOW 27MHz
10-bit data output
SD format LOW HIGH LOW LOW 27MHz
10-bit ASI output
SD format LOW HIGHLOWHIGH 27MHz
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The timing signal generator consists of a number of counters and comparators operating
at video pixel and video line rates. These counters maintain information about the total
line length, active line length, total number of lines per field/frame and total active lines
per field/frame for the received video standard.
It takes one video frame to obtain full synchronization to the received video standard.
Note: Both 8-bit and 10-bit TRS words are identified by the device. Once
synchronization has been achieved, the timing signal generator continues to monitor
the received TRS timing information to maintain synchronization.
The timing signal generator re-synchronizes all pixel and line based counters on every
received TRS ID. Note that for correct operation of the timing signal generator, the
SW_EN input pin must be set LOW, unless manual synchronous switching is enabled
(Section 4.9.1).
4.9.1 Manual Switch Line Lock Handling
The principle of switch line lock handling is that the switching of synchronous video
sources will only disturb the horizontal timing and alignment, whereas the vertical
timing remains in synchronization - i.e. switching between video sources of the same
format.
To account for the horizontal disturbance caused by a synchronous switch, the word
alignment block and timing signal generator automatically re-synchronizes to the new
timing immediately if the synchronous switch happens during the designated switch
line, as defined in SMPTE recommended practice RP168-2002.
The device samples the SW_EN pin on every PCLK cycle. When a Logic LOW to HIGH
transition on this pin is detected anywhere within the active line, the word alignment
block and timing signal generator re-synchronize immediately to the next TRS word.
This allows the system to force immediate lock on any line, if the switch point is
non-standard.
To ensure proper switch line lock handling, the SW_EN signal should be asserted HIGH
anywhere within the active portion of the line on which the switch has taken place, and
should be held HIGH for approximately one video line. After this time period, SW_EN
should be de-asserted. SW_EN should be held LOW during normal device operation.
Note: It is the rising edge of the SW_EN signal, which generates the switch line lock
re-synchronization. This edge must be in the active portion of the line containing the
video switch point.
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Figure 4-5: Switch Line Locking on a Non-Standard Switch Line
4.9.2 Automatic Switch Line Lock Handling
The synchronous switch point is defined for all major video standards in
SMPTE RP168-2002. The device automatically re-synchronizes the word alignment
block and timing signal generator at the switch point, based on the detected video
standard.
The device, as described in Section 4.9.1 and Figure 4-5 above, implements the
re-synchronization process automatically, every field/frame. The switch line is defined
as follows:
• For 525 line interlaced systems: resynchronization takes place at then end of lines 10 & 273
• For 525 line progressive systems: resynchronization takes place at then end of line 10
• For 625 line interlaced systems: resynchronization takes place at then end of lines 6 & 319
• For 625 line progressive systems: resynchronization takes place at then end of line 6
• For 750 line progressive systems: resynchronization takes place at then end of line 7
• For 1125 line interlaced systems: resynchronization takes place at then end of lines 7 & 568
• For 1125 line progressive systems: resynchronization takes place at then end of line 7
Note: Unless indicated by SMPTE ST 352 payload identifier packets, the GS1671A does
not distinguish between 1125-line progressive segmented-frame (PsF) video and
1125-line interlaced video operating at 25 or 30fps. However. PsF video operating at
24fps is detected by the device.
EAV ANC ACTIVE PICTURE EAV ANCSAV EAV ANC ACTIVE PICTURESAV EAV ANC
ACTIVE PICTURE
SAV
EAV ANC SAV
Video source 1
EAV ANC ACTIVE PICTURE EAV ANCSAV EAV ANC ACTIVE PICTURESAV EAV ANC SAV
ACTIVE PICTURE EAV ANC SAV
Video source 2
EAV ANC ACTIVE PICTURESAV EAV ANC SAV
DATA IN
ACTIVE PICTURE EAV ANC SAVANCACTIVE PICTURE EAV ANC SAV
Switch point
TRS position
EAV ANC ACTIVE PICTURESAV EAV ANC SAV ANCACTIVE PICTURE
DATA OUT
ACTIVE PICTURE EAV ANC SAVEAV ANC SAV
SW_EN
switch video source 1 to 2
EAV ANC ACTIVE PICTURE EAV ANCSAV EAV ANC ACTIVE PICTURESAV EAV ANC
ACTIVE PICTURE
SAV
EAV ANC SAV
Video source 1
EAV ANC ACTIVE PICTURE EAV ANCSAV EAV ANC ACTIVE PICTURESAV EAV ANC SAV
ACTIVE PICTURE EAV ANC SAV
Video source 2
EAV ANC ACTIVE PICTURESAV EAV ANC SAV
DATA IN
ACTIVE PICTURE EAV ANC SAVACTIVE PICTURE EAV ANC SAV
Switch point
EAV ANC ACTIVE PICTURESAV EAV ANC SAV ACTIVE PICTURE
DATA OUT
switch video source 2 to 1
EAV ANC SAV ACTIVE PICTURE EAV ANC SAV
Re-synchronization
SW_EN
Re-synchronization
TRS position
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A full list of all major video standards and switching lines is shown in Table 4-7.
Table 4-7: Switch Line Position for Digital Systems
System Frame Rate
& Structure Pixel Structure Signal
Standard
Parallel
Interface
Serial
Interface Line No.
1125
60/I
1920x1080 4:2:2
ST 274 + RP211
ST 292
7/569
50/I ST 274 + RP211
30/P ST 274 + RP211
7
25/P ST 274 + RP211
24/P ST 274 + RP211
30/PsF ST 274 + RP211
25/PsF ST 274 + RP211
24/PsF ST 274 + RP211
750
60/P
1280x720 4:2:2
ST 296
ST 292 7
50/P ST 296
30/P ST 296
25/P ST 296
24/P ST 296
625
50/P 720x576
4:2:2
BT.1358 ST 349 ST 292
6
BT.1358 ST 347 ST 344
BT.1358 BT.1358 BT.1362
4:2:0
BT.1358 ST 349 ST 292
BT.1358 BT.1358 BT.1362
50/I
960x5764:2:2
BT.601 ST 349 ST 292
6/319
BT.601 BT.656ST 259
720x576
4:4:4:4
BT.799 ST 349 ST 292
BT.799 ST 347 ST 344
BT.799 BT.799 ST 344
BT.799 BT.799 −
4:2:2
BT.601 ST 349 ST 292
BT.601 ST 125 ST 259
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525
59.94/P 720x483
4:2:2
ST 293 ST 349 ST 292
10
ST 293 ST 347 ST 344
ST 293 ST 293 ST 294
4:2:0
ST 293 ST 349 ST 292
ST 293 ST 293 ST 294
59.94/I
960x483 4:2:2
ST 267ST 349 ST 292
10/273
ST 267ST 267ST 259
720x483
4:4:4
ST 267ST 349 ST 292
ST 267ST 347 ST 344
ST 267 RP174 ST 344
ST 267 RP175 RP175
4:2:2
ST 125 ST 349 ST 292
ST 125 ST 125 ST 259
HD-SDTI
P or PsF
structure 1920x1080
4:2:2
ST 274 ST 274 +
ST 348
ST 292
7
I structure ST 274 7/569
P structure 1280x720 ST 296ST 296 +
ST 348 7
SDTI
50/I 720x576
4:2:2
BT.656BT.656 +
ST 305
ST 259
6/319
59.94/I 720x483 ST 125 ST 125 +
ST 305 10/273
Table 4-7: Switch Line Position for Digital Systems (Continued)
System Frame Rate
& Structure Pixel Structure Signal
Standard
Parallel
Interface
Serial
Interface Line No.
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4.10 Programmable Multi-function Outputs
The GS1671A has six multi-function output pins, STAT[5:0], which are programmable
via the host interface to output one of the following signals:
Table 4-8: Output Signals Available on Programmable Multi-Function Pins
Status Signal Selection Code Default Output Pin
H/HSYNC (according to TIM_861 Pin) Section 4.11 0000 STAT 0
V/VSYNC (according to TIM_861 Pin) Section 4.11 0001 STAT 1
F/DE (according to TIM_861 Pin) Section 4.11 0010 STAT 2
LOCKED Section 4.60011 STAT 3
Y/1ANC Section 4.160100 STAT 4
C/2ANC Section 4.160101 −
DATA ERROR Section 4.15 0110 STAT 5
VIDEO ERROR 0111 −
AUDIO ERROR 1000 −
EDH DETECTED 1001 −
CARRIER DETECT 1010 −
RATE_DET 1011 −
Note:
Each of the STAT[5:0] pins are configurable individually using the register bits in the host interface; STAT[5:0]_CONFIG (008h/009h).
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4.11 H:V:F Timing Signal Generation
The GS1671A extracts critical timing parameters from the received TRS words.
Horizontal blanking (H), Vertical blanking (V), and Field odd/even (F) timing are output
on the STAT[2:0] pins by default.
Using the H_CONFIG bit in the host interface, the H signal timing can be selected as one
of the following:
1. Active line blanking (H_CONFIG = LOW) - the H output is HIGH for the horizontal
blanking period, including the EAV TRS words.
2. TRS based blanking (H_CONFIG = HIGH) - the H output is set HIGH for the entire
horizontal blanking period as indicated by the H bit in the received TRS signals.
The timing of these signals is shown in Figure 4-6, Figure 4-7, Figure 4-8, Figure 4-9,
Figure 4-10 and Figure 4-11 below.
Note: Both 8-bit and 10-bit TRS words are identified by the device.
Figure 4-6: H:V:F Output Timing - HDTV 20-bit Mode
Figure 4-7: H:V:F Output Timing - HDTV 10-bit Mode
Figure 4-8: H:V:F Output Timing - HD 20-bit Output Mode
PCLK
LUMA DATA
CHROMA DATA
H
0000003FF
0000003FF
V
F
XYZ (SAV)
0000003FF
0000003FF XYZ (SAV)XYZ (EAV)
XYZ (EAV)
0000003FF3FF 000000
PCLK (HD)
H
V
F
MULTIPLEXED Y’CbCr DATA (HD)
0000003FF3FF 000000 XYZ (EAV)
MULTIPLEXED Y’CbCr DATA (HD)
H
V
F
PCLK (HD)
H SIGNAL TIMING: H_CONFIG = LOW H_CONFIG = HIGH
HVF TIMINGAT SAV
HVF TIMINGAT EAV
XYZ (EAV)
XYZ (SAV)
XYZ (SAV)
PCLK
LU M A D A T A IN P U T
CHROMA DATA INPUT
H
X Y Z (EAV)0000003FF
0000003FF
V
F
0000003FF
0000003FFX Y Z (EAV)
X Y Z (SAV)
X Y Z (SAV)
H SIGNAL TIMING:H_CONFIG = LOW H_CONFIG = HIGH
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Figure 4-9: H:V:F Output Timing - HD 10-bit Output Mode
Figure 4-10: H:V:F Output Timing - SD 20-bit Output Mode
Figure 4-11: H:V:F Output Timing - SD 10-bit Output Mode
4.11.1 CEA-861 Timing Generation
The GS1671A is capable of generating CEA 861 timing instead of SMPTE HVF timing for
all of the supported video formats.
This mode is selected when the TIM_861 pin is HIGH.
Horizontal sync (HSYNC), Vertical sync (VSYNC), and Data Enable (DE) timing are
output on the STAT[2:0] pins by default.
Table 4-9 shows the CEA-861 formats supported by the GS1671A:
HVF TIMING AT SAV
0000003FF3FF 000000
PCLK
MULTIPLEXED Y'CbCr D A TA IN P U T
H
V
F
HVF TIMING AT EAV
PCLK
0000003FF3FF X Y Z (EAV)000000
MULTIPLEXED Y'CbCr D A TA IN P U T
H
V
F
X Y Z (EAV)
XYZ (SAV) X Y Z (SAV)
PCLK
CHROMA DATA INPUT
LUMA DATA INPUT
H
0003FF
X Y Z (EAV)000
V
F
0003FF
000
H SIGNAL TIMING:H_CONFIG = LOW H_CONFIG = HIGH
X Y Z (SAV)
MULTIPLEXED Y'CbCr DATA INPUT
PCLK
H
V
F
X Y Z (EAV)0000003FF 0000003FF X Y Z (SAV)
H SIGNAL TIMING:H_CONFIG = LOW H_CONFIG = HIGH
Table 4-9: Supported CEA-861 Formats
Format CEA-861 Format VD_STD[5:0]
720(1440) x 480i @ 59.94/60Hz 6 & 7 16h, 17h, 19h, 1Bh
720(1440) x 576i @ 50Hz 21 & 22 18h, 1Ah
1280 x 720p @ 59.94/60Hz 4 20h, 00h
1280 x 720p @ 50Hz 19 24h, 04h
1920 x 1080i @ 59.94/60Hz 5 2Ah, 0Ah
1920 x 1080i @ 50Hz 20 2Ch, 0Ch
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4.11.1.1 Vertical Timing
When CEA861 timing is selected, the device outputs standards compliant CEA861
timing signals as shown in the figures below; for example 240 active lines per field for
SMPTE ST 125.
The register bit TRS_861 is used to select DFP timing generator mode which follows the
vertical blanking timing as defined by the embedded TRS code words. This setting is
helpful for 525i. When TRS_861 is set LOW, DE will go HIGH for 480 lines out of 525.
When TRS_861 is set HIGH, DE will go HIGH for 487 lines out of 525.
The timing of the CEA 861 timing reference signals can be found in the CEA 861
specifications. For information, they are included in the following diagrams. These
diagrams may not be comprehensive.
1920 x 1080p @ 29.97/30Hz 3412Bh, 0Bh
1920 x 1080p @ 25Hz 3322Dh, 0Dh
1920 x 1080p @ 23.98/24Hz 32 30h, 10h
Note:
1,2: Timing is identical for the corresponding formats.
Table 4-9: Supported CEA-861 Formats (Continued)
Format CEA-861 Format VD_STD[5:0]
Table 4-10: CEA861 Timing Formats
Format Parameters
4 H:V:DE Input Timing 1280 x 720p @ 59.94/60Hz
5 H:V:DE Input Timing 1920 x 1080i @ 59.94/60Hz
6&7 H:V:DE Input Timing 720 (1440) x 480i @ 59.94/60Hz
19 H:V:DE Input Timing 1280 x 720p @ 50Hz
20 H:V:DE Input Timing 1920 x 1080i @ 50Hz
21&22 H:V:DE Input Timing 720 (1440) x 576 @ 50Hz
32 H:V:DE Input Timing 1920 x 1080p @ 23.94/24Hz
33 H:V:DE Input Timing 1920 x 1080p @ 25Hz
34 H:V:DE Input Timing 1920 x 1080p @ 29.97/30Hz
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Figure 4-12: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4)
Figure 4-13: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5)
1660 Total Horizontal Clocks per line
1280 Clocks for Active Video
Data
Enable
220 clocks
40
370
110
HSYNC
Progressive Frame: 30 Vertical Blanking Lines 720 Active Vertical Lines
1650 clocks
Data
Enable
HSYNC
110
VSYNC
260
745 746 747 748 749 750 1 2 3 4 5 6 7 25 26745 746750
~
~
~
~
~
~
~
~
~
~
~
~
148 clocks
1920 Clocks for Active Video280
Data
Enable
HSYNC
VSYNC
1123 1124 1125 1 2 3 4 5 6 7 8
Data
Enable
HSYNC
2200 Total Horizontal Clocks per line
44
88
Field 1: 22 Vertical Blanking Lines
2200 clocks
88
19 20 21 560 561 562
192
540 Active Vertical Lines per field
540 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
192
88
2200 clocks
1100
VSYNC
Data
Enable
HSYNC
560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125
~~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
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Figure 4-14: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7)
Figure 4-15: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19)
1440 Clocks for Active Video
276
Data
Enable
1716 Total Horizontal Clocks per line
HSYNC
Data
Enable
HSYNC
VSYNC
Data
Enable
HSYNC
VSYNC
114 clocks
124
38
Field 1: 22 Vertical Blanking Lines
1716 clocks 238
240 Active Vertical Lines per field
~
~
~
~
38
240 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
~
~
524 525 1 2 3 4 5 6 7 8 9 21 22
~
~
~
~
238
38 1716 clocks 858
261 262 263 264 265 266 267 268 269 270 271 524 525 1284 285
261 262 263
220 clocks
1280 Clocks for Active Video
700
Data
Enable
HSYNC
VSYNC
745 746 747 748 749 750 1 2 3 4 5 6 7
Data
Enable
HSYNC
1980 Total Horizontal Clocks per line
40
440
Progressive Frame: 30 Vertical Blanking Lines
1980 clocks
440
745 746
260
720 Active Vertical Lines
~
~
~
~
~
~
~
25 26
~
~
~
~
750
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Figure 4-16: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20)
148 clocks
1920 Clocks for Active Video720
Data
Enable
HSYNC
2640 Total Horizontal Clocks per line
44
528
VSYNC
1123 1124 1125 1 2 3 4 5 6 7 8
Data
Enable
HSYNC
Field 1: 22 Vertical Blanking Lines
2640 clocks
528
19 20 21 560 561 562
192
540 Active Vertical Lines per field
540 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
192
528
2640 clocks
1320
VSYNC
Data
Enable
HSYNC
560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125
~~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
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Figure 4-17: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22)
Figure 4-18: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32)
1440 Clocks for Active Video
288
Data
Enable
1728 Total Horizontal Clocks per line
HSYNC
138 clocks
126
24
Data
Enable
HSYNC
VSYNC
Data
Enable
HSYNC
VSYNC
Field 1: 24 Vertical Blanking Lines
1728 clocks 264
288 Active Vertical Lines per field
~
~
~
~
24
288 Active Vertical Lines per field
Field 2: 25 Vertical Blanking Lines
~
~
623 624 625 1 2 3 4 5 6 7 22 23
~
~
~
~
264
24
1728 clocks
864
310 311 312 313 314 315 316 317 318 319 320 623 624 625335 336
310 311 312
~
~
148 clocks
1920 Clocks for Active Video830
Data
Enable
HSYNC
2750 Total Horizontal Clocks per line
44
638
VSYNC
1121 1122 1123 1124 1125 1 2 3 4 5 6 7
Data
Enable
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
2750 clocks
638
1121 1122 1123 1124 1125
192
1080 Active Vertical Lines
~
~
~
~
~
~
41 42
~
~
~
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Figure 4-19: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33)
Figure 4-20: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34)
148 clocks
1920 Clocks for Active Video
720
Data
Enable
HSYNC
2640 Total Horizontal Clocks per line
44
528
VSYNC
1121 1122 1123 1124 1125 1 2 3 4 5 6 7
Data
Enable
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
2640 clocks
528
1121 1122 1123 1124 1125
192
1080 Active Vertical Lines
~
~
~
~
~
~
41 42
~
~
~
148 clocks
1920 Clocks for Active Video280
Data
Enable
HSYNC
2200 Total Horizontal Clocks per line
44
88
VSYNC
1121 1122 1123 1124 1125 1 2 3 4 5 6 7
Data
Enable
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
2220 clocks
88
1121 1122 1123 1124 1125
192
1080 Active Vertical Lines
~
~
~
~
~
~
41 42
~
~
~
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4.12 Automatic Video Standards Detection
Using the timing extracted from the received TRS signals, the GS1671A is able to identify
the received video standard.
The total samples per line, active samples per line, total lines per field/frame and active
lines per field/frame are all measured.
Four registers are provided to allow the system to read the video standard information
from the device. These raster structure registers are provided in addition to the
VIDEO_FORMAT_352_A_X and VIDEO_FORMAT_352_B_X registers, and are updated
once per frame at the end of line 12.
The raster structure registers also contain three status bits: STD_LOCK, INT/PROG and
M. The STD_LOCK bit is set HIGH whenever the timing signal generator is fully
synchronized to the incoming standard, and detects it as one of the supported formats.
The INT/PROG bit is set HIGH if the detected video standard is interlaced and LOW if the
detected video standard is progressive. M is set HIGH if the clock frequency includes the
“1000/1001” factor denoting a 23.98, 29.97 or 59.94Hz frame rate.
The video standard code is reported in the VD_STD bits of the host interface register.
Table 4-11 describes the 5-bit codes for the recognized video standards.
Table 4-11: Supported Video Standard Codes
SMPTE
Standard Active Video Area
RATE_
DET
SD/HD
Lines per
Frame
Active Lines
per Frame
Words
per Active
Line
Words per
Line
VD_STD
[5:0]
ST 260 (HD) 1920x1035/60 (2:1) 0 1125 1035 1920 2200 15h
ST 295 (HD) 1920x1080/50 (2:1) 0 1250 1080 1920 237614h
ST 274 (HD)
1920x1080/60 (2:1) or
1920x1080/30 (PsF) 0 1125 1080 1920 2200 0Ah
1920x1080/50 (2:1) or
1920x1080/25 (PsF) 0 1125 1080 1920 2640 0Ch
1920x1080/30 (1:1) 0 1125 1080 1920 2200 0Bh
1920x1080/25 (1:1) 0 1125 1080 1920 2640 0Dh
1920x1080/24 (1:1) 0 1125 1080 1920 2750 10h
1920x1080/24 (PsF) 0 1125 1080 1920 2750 11h
1920x1080/25 (1:1) – EM 0 1125 1080 2304 2640 0Eh
1920x1080/25 (PsF) – EM 0 1125 1080 2304 2640 0Fh
1920x1080/24 (1:1) – EM 0 1125 1080 2400 2750 12h
1920x1080/24 (PsF) – EM 0 1125 1080 2400 2750 13h
ST 296 (HD)
1280x720/30 (1:1) –EM 0 750 720 1280 3300 02h
1280x720/30 (1:1) – EM 0 750 720 2880 3300 03h
1280x720/50 (1:1) 0 750 720 1280 1980 04h
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Note: In certain systems, due to greater ppm offsets in the crystal, the ‘M’ bit may not
assert properly. In such cases, bits 3:0 in Register 06Fh can be increased to a maximum
value of 4.
ST 296 (HD)
1280x720/50 (1:1) – EM 0 750 720 1728 1980 05h
1280x720/25 (1:1) 0 750 720 1280 396006h
1280x720/25 (1:1) – EM 0 750 720 34563960 07h
1280x720/24 (1:1) 0 750 720 1280 4125 08h
1280x720/24 (1:1) – EM 0 750 720 3600 4125 09h
1280x720/60 (1:1) 0 750 720 1280 1650 00h
1280x720/60 (1:1) – EM 0 750 720 1440 1650 01h
ST 125 (SD)
1440x487/60 (2:1) 1 525 244 or 243 1440 171616h
1440x507/60 1 525 254 or 253 1440 171617h
525-line 487 generic1 525 −−171619h
525-line 507 generic1 525 −−17161Bh
ITU-R BT.656
(SD)
1440x576/50 (2:1) Or
dual link progressive) 1625 −1440 1728 18h
625-line generic1625 −−1728 1Ah
Unknown
HD SD/HD = 0 0 −−−−1Dh
Unknown
SDSD/HD = 1 1 −−−−1Eh
2K Standards (see 4.12.1 2K Support)
SMPTE
2048-2-
200x
(4:2:2)
2048x1080/30 (1:1) 0 1125 1080 2048 2200 31h
2048x1080/25 (1:1) 0 1125 1080 2048 2640 32h
2048x1080/24 (1:1) 0 1125 1080 2048 2750 33h
Non
SMPTE
2048-2-
200x
(4:2:2)
2048x1080/60 (2:1) 0 1125 540 2048 2200 3Dh
2048x1080/60 (2:1) 0 1125 540 2048 2640 3Eh
2048x1080/48 (2:1) 0 1125 540 2048 2750 3Fh
Non-SMPTE Unknown 2K 0 −−2048 −3Ah
Notes:
1. The Line Numbers in brackets refer to version zero SMPTE ST 352 packet locations, if they are different from version 1.
2. The part may provide full or limited functionality with standards that are not included in this table. Please consult a Semtech
technical representative.
3. For SD-SDI streams, the device can report an incorrect M value when SMPTE ST 352 packets are presents.
Table 4-11: Supported Video Standard Codes (Continued)
SMPTE
Standard Active Video Area
RATE_
DET
SD/HD
Lines per
Frame
Active Lines
per Frame
Words
per Active
Line
Words per
Line
VD_STD
[5:0]
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By default (after power up or after systems reset), the four RASTER_STRUCTURE,
VD_STD, STD_LOCK and INT/PROG fields are set to zero. These fields are also cleared
when the SMPTE_BYPASS pin is LOW.
4.12.1 2K Support
In order to fully support 2K standards without customer intervention, Semtech provides
FPGA code for enhancing the GS1671A's 2K capability.
The features of the 2K FPGA enhancement are:
• Automatic video standard detection for 2K standards
• 1/1.001 rate detection for 2K standards
• CEA-861 timing generation for 2K standards
• Automatic enabling of audio extraction
This enhancement is an interface between the GS1671A and the customer system. The
behaviour of the GS1671A with or without the additional 2K enhancement FPGA code
is identical from a user-perspective.
Figure 4-21: 2K Feature Enhancement
GS1671A
Host
Interface
Control
PLL
÷2
÷1
GIb_MUX
0
1
GIb_Buf
Level_B
FPGA
Level_B
Vid_Out[19:0]
HVF[2:0]
WO_2K
STAT3
STAT4
STAT5
GS1671A_GSPI_SDI
GS1671A_GSPI_CS
GS1671A_GSPI_SCLK
GS1671A_GSPI_SDOUT
reset
Host_GSPI_CS
Host_GSPI_SCLK
Host_GSPI_SDI
Host_GSPI_SDOUT
Pclk
Pclk_div2
smpte_bypass_i
tim_861
clk_27M_ref
dy_in_i[9:0]
dc_in_i[9:0]
fvh_o[2:0]
Host_GSPI_busy
Level_B
rate_m_o
std_2K_det_o
dy_out_o[9:0]
dc_out_o[9:0]
fvh_i[2:0]
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4.13 Data Format Detection & Indication
In addition to detecting the video standard, the GS1671A detects the data format, i.e.
SDTI, SDI, TDM data (SMPTE ST 346), etc.
This information is represented by bits in the DATA_FORMAT_DSX register accessible
through the host interface.
Data format detection is only carried out when the LOCKED signal is HIGH.
By default (at power up or after system reset), the DATA_FORMAT_DSX register is set to
Fh (undefined). This register is also set as undefined when the LOCKED signal is LOW
and/or the SMPTE_BYPASS pin is LOW.
The data format is determined using the following criteria:
• If TRS ID words are detected but no SDTI header or TDM header is detected, then
the data format is SDI
• If TRS ID words are detected and the SDTI header is available then the format is
SDTI
• If TRS ID words are detected and the TDM data header is detected then the format is
TDM video
• No TRS words are detected, but the PLL is locked, then the data format is unknown
Note: Two data format sets are provided for HD video rates. This is because the Y and
Cr/Cb channels can be used separately to carry SDTI data streams of different data
formats. In SD video mode only the Y data format register contains the data, and the C
register is set to Fh (undefined format).
Table 4-12: Data Format Register Codes
YDATA_FORMAT[3:0] or
CDATA_FORMAT[3:0] Data Format Remarks
0h ~ 05h SDTI SMPTE ST 321 SMPTE ST 322,
SMPTE ST 326
6hSDI −
7h Reserved−
8h TDM SMPTE ST 346
9h HD-SDTI −
Ah ~ Eh Reserved−
Fh Non-SMPTE data
format
Detected data format is not SMPTE.
LOCKED = LOW.
Note: This Data Format register is
invalid in SMPTE_BYPASS mode.
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4.14 EDH Detection
4.14.1 EDH Packet Detection
The GS1671A determines if EDH packets are present in the incoming video data and
asserts the EDH_DETECT status according to the SMPTE standard.
EDH_DETECT is set HIGH when EDH packets have been detected and remains HIGH
until EDH packets are no longer present. It is set LOW at the end of the vertical blanking
(falling edge of V) if an EDH packet has not been detected during vertical blanking.
EDH_DETECT can be programmed to be output on the multi-function output port pins.
The EDH_DETECT bit is also available in the host interface.
4.14.2 EDH Flag Detection
The EDH flags for ancillary data, active picture, and full field regions are extracted from
the detected EDH packets and placed in the EDH_FLAG_IN register.
When the EDH_FLAG_UPDATE_MASK bit in the host interface is set HIGH, the
GS1671A updates the Ancillary Data, Full Field, and Active Picture EDH flags according
to SMPTE RP165. The updated EDH flags are available in the EDH_FLAG_OUT register.
The EDH packet output from the device contains these updated flags.
One set of flags is provided for both fields 1 and 2. The field 1 flag data is overwritten by
the field 2 flag data.
When EDH packets are not detected, the UES flags in the EDH_FLAG_OUT register are
set HIGH to signify that the received signal does not support Error Detection and
Handling. In addition, the EDH_DETECT bit is set LOW. These flags are set regardless of
the setting of the EDH_FLAG_UPDATE_MASK bit.
EDH_FLAG_OUT and EDH_FLAG_IN may be read via the host interface at any time
during the received frame except on the lines defined in SMPTE RP165, when these flags
are updated.
The GS1671A indicates the CRC validity for both active picture and full field CRCs. The
AP_CRC_V bit in the host interface indicates the active picture CRC validity, and the
FF_CRC_V bit indicates the full field CRC validity. When EDH_DETECT = LOW, these
bits are cleared.
The EDH_FLAG_OUT and EDH_FLAG_IN register values remain set until overwritten by
the decoded flags in the next received EDH packet. When an EDH packet is not detected
during vertical blanking, the flag registers are cleared at the end of the vertical blanking
period.
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4.15 Video Signal Error Detection & Indication
The GS1671A includes a number of video signal error detection functions. These are
provided to enhance operation of the device when operating in SMPTE mode
(SMPTE_BYPASS = HIGH). These features are not available in the other operating modes
of the device (i.e. when SMPTE_BYPASS = LOW).
Signal errors that can be detected include:
1. TRS errors.
2. HD line based CRC errors.
3. EDH errors.
4. HD line number errors.
5. Video standard errors.
The device maintains an ERROR_STAT_X register. Each error condition has a specific
flag in the ERROR_STAT_X register, which is set HIGH whenever an error condition is
detected.
An ERROR_MASK register is also provided, allowing the user to select which error
conditions are reported. Each bit of the ERROR_MASK register corresponds to a unique
error type.
Separate SD_AUDIO_ERROR_MASK and HD_AUDIO_ERROR_MASK registers for SD
and HD audio cores are also provided, allowing select error conditions to be reported.
Each bit of each ERROR_MASK register corresponds to a unique error type.
By default (at power up or after system reset), all bits of the ERROR_MASK registers are
zero, enabling all errors to be reported. Individual error detection may be disabled by
setting the corresponding bit HIGH in the mask registers.
Error conditions are indicated by a VIDEO _ERROR signal and an AUDIO_ERROR signal,
which are available for output on the multifunction I/O output pins. The two signals are
also combined into a summary DATA_ERROR signal, which is also available on the
multifunction I/O pins. These signals are normally HIGH, but are set LOW by the device
when an error condition has been detected.
These signals are a logical 'NOR' of the appropriate error status flags stored in the
ERROR_STAT_X register, which are gated by the bit settings in the ERROR_MASK
registers. When an error status bit is HIGH and the corresponding error mask bit is LOW,
the corresponding DATA_ERROR signal is set LOW by the device.
The ERROR_STAT_X registers, and correspondingly the DATA_ERROR, VIDEO_ERROR,
and AUDIO_ERROR signals, are cleared at the start of the next video field or when read
via the host interface, which ever condition occurs first. Note that any AUDIO_ERROR
condition will cause DATA_ERROR to assert. Use the SD_AUDIO_ERROR_MASK and
HD_AUDIO_ERROR_MASK registers if masking these events is desired.
ERROR_STAT_X registers are also cleared under any of the following conditions:
1. LOCKED signal = LOW.
2. SMPTE_BYPASS = LOW.
3. When a change in video standard has been detected.
4. RESET_TRST = LOW
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Table 4-13 shows the ERROR_STAT_X register and ERROR_MASK_X register.
Note: Since the error indication registers are cleared once per field, if an external host
micro is polling the error registers periodically, an error flag may be missed if it is
intermittent, and the polling frequency is less than the field rate.
Note: See Section 4.18 for Audio Error Status.
4.15.1 TRS Error Detection
TRS error flags are generated by the GS1671A under the following two conditions:
1. A phase shift in received TRS timing is observed on a non-switching line.
2. The received TRS Hamming codes are incorrect.
Both SAV and EAV TRS words are checked for timing and data integrity errors.
For HD mode, only the Y channel TRS codes are checked for errors.
Both 8-bit and 10-bit TRS code words are checked for errors.
The SAV_ERR bit of the ERROR_STAT_X register is set HIGH when an SAV TRS error is
detected.
The EAV_ERR bit of the ERROR_STAT_X register is set HIGH when an EAV TRS error is
detected.
4.15.2 Line Based CRC Error Detection
The GS1671A calculates line based CRCs for HD video signals. CRC calculations are
done for each 10-bit channel (Y and C for HD video).
These calculated CRC values are compared with the received CRC values.
If a mismatch in the calculated and received CRC values is detected for Y channel data,
the YCRC_ERR bit in the ERROR_STAT_X register is set HIGH.
Table 4-13: Error Status Register and Error Mask Register
Video Error Status Register Video Error Mask Register
SAV_ERR (02h, 03h) SAV_ERR_MASK (037h, 038h)
EAV_ERR (02h, 03h) EAV_ERR_MASK (037h, 038h)
YCRC_ERR (02h, 03h) YCRC_ERR_MASK (037h, 038h)
CCRC_ERR (02h, 03h) CCRC_ERR_MASK (037h, 038h)
LNUM_ERR (02h, 03h) LNUM_ERR_MASK (037h, 038h)
YCS_ERR (02h, 03h) YCS_ERR_MASK (037h, 038h)
CCS_ERR (02h, 03h) CCS_ERR_MASK (037h, 038h)
AP_CRC_ERR (02h) AP_CRC_ERR_MASK (037h)
FF_CRC_ERR (02h) FF_CRC_ERR_MASK (037h)
VD_STD_ERR (02h, 03h) VD_STD_ERR_MASK (037h)
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If a mismatch in the calculated and received CRC values is detected for C channel data,
the CCRC_ERR bit in the ERROR_STAT_X register is set HIGH.
Y or C CRC errors are also generated if CRC values are not embedded.
Line based CRC errors are only generated when the device is operating in HD mode.
Note: By default, 8-bit to 10-bit TRS remapping is enabled. If an 8-bit input is used, the
HD CRC check is based on the 10-bit remapped value, not the 8-bit value, so the CRC
Error Flag is incorrectly asserted and should be ignored. If 8-bit to 10-bit remapping is
enabled, then CRC correction and insertion should be enabled by setting the
CRC_INS_MASK bit LOW in the IOPROC_1 or IOPROC_2 register. This ensures that the
CRC values are updated.
4.15.3 EDH CRC Error Detection
The GS1671A also calculates Full Field (FF) and Active Picture (AP) CRCs according to
SMPTE RP165 in support of Error Detection and Handling packets in SD signals.
These calculated CRC values are compared with the received CRC values.
Error flags for AP and FF CRC errors are provided and each error flag is a logical OR of
field 1 and field 2 error conditions.
The AP_CRC_ERR bit in the VIDEO_ERROR_STAT_X register is set HIGH when an Active
Picture CRC mismatch has been detected in field 1 or 2.
The FF_CRC_ERR bit in the VIDEO_ERROR_STAT_X register is set HIGH when a Full
Field CRC mismatch has been detected in field 1 or 2.
EDH CRC errors are only indicated when the device is operating in SD mode and when
the device has correctly received EDH packets.
4.15.4 HD Line Number Error Detection
If a mismatch in the calculated and received line numbers is detected, the LNUM_ERR
bit in the VIDEO_ERROR_STAT_X register is set HIGH.
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4.16 Ancillary Data Detection & Indication
The GS1671A detects ancillary data in both the vertical and horizontal ancillary data
spaces. Status signal outputs Y/1ANC and C/2ANC are provided to indicate the position
of ancillary data in the output data streams. These signals may be selected for output on
the multi-function I/O port pins (STAT[5:0]).
The GS1671A indicates the presence of all types of ancillary data by detecting the 000h,
3FFh, 3FFh (00h, FFh, FFh for 8-bit video) ancillary data preamble.
Note: Both 8 and 10-bit ancillary data preambles are detected by the device.
By default (at power up or after system reset) the GS1671A indicates all types of
ancillary data. Up to 5 types of ancillary data can be specifically programmed for
recognition.
For HD video signals, ancillary data may be placed in both the Y and Cb/Cr video data
streams separately. For SD video signals, the ancillary data is multiplexed and combined
into the YCbCr data space.
When operating in HD mode, the Y/1ANC signal is HIGH whenever ancillary data is
detected in the Luma data stream, and C/2ANC is HIGH whenever ancillary data is
detected in the Chroma data stream. The signals are asserted HIGH at the start of the
ancillary data preamble, and remain HIGH until after the ancillary data checksum.
When operating in SD mode, the Y/1ANC and C/2ANC signals depend on the output
data format. For 20-bit demultiplexed data, the Y/1ANC and C/2ANC signals operate
independently to indicate the first and last ancillary Data Word position in the Luma
and/or Chroma data streams. For 10-bit multiplexed data, the Y/1ANC signal is HIGH
whenever ancillary data is detected, and the C/2ANC signal is always LOW.
These status signal outputs are synchronous with PCLK and may be used as
clock-enables for external logic, or as write-enables for an external FIFO or other
memory devices.
The operation of the Y/1ANC and C/2ANC signals is shown below in Figure 4-22.
Note: When I/O processing is disabled, the Y/1ANC and C/2ANC flags may toggle, but
they are invalid and should be ignored.
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Figure 4-22: Y/1ANC and C/2ANC Signal Timing
4.16.1 Programmable Ancillary Data Detection
As described above in Section 4.16, the GS1671A detects and indicates all ancillary data
types by default.
It is possible to program which ancillary data types are to be detected and indicated. Up
to five different ancillary data types may be programmed for detection by the GS1671A
in the ANC_TYPE_DS1 registers for SD and HD.
When so programmed, the GS1671A only indicates the presence of the specified
ancillary data types, ignoring all other ancillary data. For each data type to be detected,
the user must program the DID and/or SDID of that ancillary data type. In the case
where no DID or SDID values are programmed, the GS1671A indicates the presence of
all ancillary data. In the case where one or more, DID and/or SDID values have been
programmed, then only those matching data types are detected and indicated.
The timing of the Y/1ANC and C/2ANC signals in this case is as shown in Figure 4-22.
The GS1671A compares the received DID and/or SDID with the programmed values. If
a match is found, ancillary data is indicated.
For any DID or SDID value set to zero, no comparison or match is made. For example, if
the DID is programmed and the SDID is not programmed, the GS1671A only detects a
match to the DID value.
If both DID and SDID values are non-zero, then the received ancillary data type must
match both the DID and SDID before Y/1ANC and/or C/2ANC is set HIGH.
PCLK
LUM A DATA OUT
CHROMA DATA OUT
Y/1ANC
C/2ANC
PCLK
LUM A DATA OUT
Y/1ANC
PCLK
CHROMA DATA OUT
ANC DATA DETECTION - HDTV 10 BIT OUTPUT MODE
PCLK
MULTIPLEXED
Y'CbCr YCSUM CCSUM
Y DID CANC
3FF000000 FF3FF3FF3
ANC DATA DETECTION - HDTV 20 BIT OUTPUT MODE
BLANK BLANKANC DATADCDBN DID CSUM
ANC DATA CSUMANC DATADCDBN DID ANC DATA
3FF3FF
3FF3FF
000
000
ANC DATA DETECTION - SDTV 20 BIT OUTPUT MODE
CSUM BLANKANC DATAANC DATADCDID ANC DATA
BLANK BLANKANC DATAANC DATA ANC DATA DBN ANC DATA
3FF
BLANK
000 3FF
ANC DATA DETECTION - SDTV 10 BIT OUTPUT MODE
CSUM BLANKANC DATADCDBNDID ANC DATA
3FF
3FF000
MULTIPLEXED
Y'CbCr
Y/1ANC
Y/1ANC
C/2ANC
C/2ANC
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Note: SMPTE ST 352 Payload Identifier packets and Error Detection and Handling
(EDH) Packets are always detected by the GS1671A, irrespective of the settings of the
ANC_TYPE registers.
4.16.2 SMPTE ST 352 Payload Identifier
The GS1671A automatically extracts the SMPTE ST 352 payload identifier present in the
input data stream for SD and HD. The four word payload identifier packets are written
to VIDEO_FORMAT_X_DS1 and VIDEO_FORMAT_X_DS2 bits accessible through the
host interface.
The device also indicates the version of the payload packet in the VERSION_352M bit of
the DATA_FORMAT_DSX register. When the SMPTE ST 352 packet is formatted as a
“version 1” packet, the VERSION_352M bit is set HIGH, when the packet is formatted as
a “version 2” packet, this bit is set LOW.
The VIDEO_FORMAT_352_A_X and VIDEO_FORMAT_352_B_X registers are only
updated if there are no checksum errors in the received SMPTE ST 352 packets.
By default (at power up or after system reset), the VIDEO_FORMAT_X_DS1 and
VIDEO_FORMAT_X_DS2 bits are set to 0, indicating an undefined format.
4.16.2.1 SMPTE ST 352 Payload Identifier Usage
The SMPTE ST 352 Payload Identifier is used to confirm the video format identified by
the Automatic Video Standards Detection block (see Section 4.16.4)
4.16.3 Ancillary Data Checksum Error
The GS1671A calculates checksums for all received ancillary data.
These calculated checksums are compared with the received ancillary data checksum
words.
If a mismatch in the calculated and received checksums is detected, then a checksum
error is indicated.
When operating in HD mode, the device makes comparisons on both the Y and C
channels separately. If an error condition in the Y channel is detected, the YCS_ERR bit
in the VIDEO_ERROR_STAT_X register is set HIGH. If an error condition in the C channel
is detected, the CCS_ERR bit in the VIDEO_ERROR_STAT_X register is set HIGH.
When operating in SD mode, only the YCS_ERR bit is set HIGH when checksum errors
are detected.
4.16.3.1 Programmable Ancillary Data Checksum Calculation
As described above, the GS1671A calculates and compares checksum values for all
ancillary data types by default. It is possible to program which ancillary data types are
checked as described in Section 4.16.1.
When so programmed, the GS1671A only checks ancillary data checksums for the
specified data types, ignoring all other ancillary data.
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The YCS_ERR and/or CCS_ERR bits in the VIDEO_ERROR_STAT_X register are only set
HIGH if an error condition is detected for the programmed ancillary data types.
4.16.4 Video Standard Error
If a mismatch between the received SMPTE ST 352 packets and the calculated video
standard occurs, the GS1671A indicates a video standard error by setting the
VD_STD_ERR bit of the VIDEO_ERROR_STAT_X register HIGH.
The device detects the SMPTE ST 352 Packet version as defined in the SMPTE ST 352
standard. If the incoming packet is Version Zero, then no comparison is made with the
internally generated payload information and the VD_STD_ERR bit is not set HIGH.
Note 1: If the received SMPTE ST 352 packet indicates 25, 30 or 29.97PsF formats, the
device only indicates an error when the video format is actually progressive. The device
detects 24 and 23.98PsF video standards and perform error checking at these rates.
Note 2: VD_STD_ERR_DS1 is set incorrectly for a 1920x1080/PsF/24 payload ID. To
resolve this issue, choose one of the two methods.
• Set the VD_STD_ERR_DS1 mask bit high in the ERROR_MASK_1 register to avoid
having incorrect assertion of the DATA_ERROR pin.
• Monitor the received SMPTE ST0352 packet in the VIDEO_FORMAT_352_A_1 and
VIDEO_FORMAT_352_B_1 registers and compare that to the video format
identified in the VD_STD_DS1 bits in the DATA_FORMAT_DS1 register. Then, make
the determination of whether or not there is a mismatch on their own.
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4.17 Signal Processing
In addition to error detection and indication, the GS1671A can also correct errors,
inserting corrected code words, checksums and CRC values into the data stream.
The following processing can be performed by the GS1671A:
1. TRS error correction and insertion.
2. HD line based CRC correction and insertion.
3. EDH CRC error correction and insertion.
4. HD line number error correction and insertion.
5. Illegal code re-mapping.
6. Ancillary data checksum error correction and insertion.
7. Audio extraction.
All of the above features are only available in SMPTE mode (SMPTE_BYPASS = HIGH).
To enable these features, the IOPROC_EN/DIS pin must be set HIGH, and the individual
feature must be enabled via bits in the IOPROC_1 and/or IOPROC_2 (depending on the
data stream) register(s).
The IOPROC_1 and IOPROC_2 registers contains one bit for each processing feature
allowing each one to be enabled/disabled individually.
By default (at power up or after device reset), all of the IOPROC_1 and IOPROC_2
register bits described in Table 4-14 below are set to zero (0), which enables all of the
processing features.
To disable an individual processing feature, set the corresponding bit to one (1) in the
IOPROC_1 and/or IOPROC_2 register(s).
Table 4-14: IOPROC_1 and IOPROC_2 Register Bits
Processing Feature IOPROC_1
Register Bit
IOPROC_2
Register Bit
TRS error correction and insertion TRS_INS_DS1_MASKTRS_INS_DS2_MASK
Y and C line based CRC error correction CRC_INS_DS1_MASKCRC_INS_DS2_MASK
Y and C line number error correction LNUM_INS_DS1_MASKLNUM_INS_DS2_MASK
Ancillary data check sum correction ANC_CHECKSUM_INSERTION_DS1_MASKANC_CHECKSUM_INSERTION_DS2_MASK
EDH CRC error correction EDH_CRC_INS_MASKN/A
Illegal code re-mappingILLEGAL_WORD_REMAP_DS1_MASKILLEGAL_WORD_REMAP_DS2_MASK
H timing signal configuration H_CONFIGN/A
Update EDH Flags EDH_FLAG_UPDATE_MASKN/A
Audio Data Extraction N/A AUDIO_SEL_DS2_DS1
Ancillary Data Extraction ANC_DATA_EXT_MASKANC_EXT_SEL_DS2_DS1
Audio Extraction AUD_EXT_MASKN/A
Regeneration of ST 352 packets N/A REGEN_352M_MASK
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4.17.1 TRS Correction & Insertion
When TRS Error Correction and Insertion is enabled, the GS1671A generates and
overwrites TRS code words as required.
TRS Word Generation and Insertion is performed using the timing generated by the
Timing Signal Generator, providing an element of noise immunity over using just the
received TRS information.
This feature is enabled when the IOPROC_EN/DIS pin is HIGH and the
TRS_INS_DS1_MASK or TRS_INS_DS2_MASK bits in the IOPROC_1 or IOPROC_2
registers are set LOW. The TRS_INS_DS1_MASK bit is in the IOPROC_1 register and is
used to enable/disable TRS correction and insertion for SD, HD, and 3G-A data streams.
The TRS_INS_DS2_MASK bit is in the IOPROC_2 register and is used to enable/disable
TRS correction and insertion for 3G-B data streams only.
Note: Inserted TRS code words are always 10-bit compliant, irrespective of the bit depth
of the incoming video stream.
4.17.2 Line Based CRC Correction & Insertion
When CRC Error Correction and Insertion is enabled, the GS1671A generates and
inserts line based CRC words into both the Y and C channels of the data stream.
Line based CRC word generation and insertion only occurs in HD mode, and is enabled
in when the IOPROC_EN/DIS pin is HIGH and the CRC_INS_DSX_MASK bit in the
IOPROC_X register is set LOW.
4.17.3 Line Number Error Correction & Insertion
When Line Number Error Correction and Insertion is enabled, the GS1671A calculates
and inserts line numbers into the output data stream. Re-calculated line numbers are
inserted into both the Y and C channels.
Line number generation is in accordance with the relevant HD video standard as
determined by the Automatic Standards Detection block.
This feature is enabled when the device is operating in HD mode, the IOPROC_EN/DIS
pin is HIGH and the LNUM_INS_DSX_MASK bit in the IOPROC_X register is set LOW.
4.17.4 ANC Data Checksum Error Correction & Insertion
When ANC data Checksum Error Correction and Insertion is enabled, the GS1671A
generates and inserts ancillary data checksums for all ancillary data words by default.
Where user specified ancillary data has been programmed (see Section 4.16.1), only the
checksums for the programmed ancillary data are corrected.
This feature is enabled when the IOPROC_EN/DIS pin is HIGH and the
ANC_CHECKSUM_INSERTION_DSX_MASK bit in the IOPROC_X register is set LOW.
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4.17.5 EDH CRC Correction & Insertion
When EDH CRC Error Correction and Insertion is enabled, the GS1671A generates and
overwrites full field and active picture CRC check-words.
Additionally, the device sets the active picture and full field CRC 'V' bits HIGH in the
EDH packet. The AP_CRC_V and FF_CRC_V register bits only report the received EDH
validity flags.
EDH FF and AP CRC's are only inserted when the device is operating in SD mode, and if
the EDH data packet is detected in the received video data.
Although the GS1671A modifies and inserts EDH CRC's and EDH packet checksums,
EDH error flags are only updated when the EDH_FLAG_UPDATE_MASK bit is LOW.
This feature is enabled in SD mode, when the IOPROC_EN/DIS pin is HIGH and the
EDH_CRC_INS_MASK bit in the IOPROC_1 register is set LOW.
4.17.6 Illegal Word Re-mapping
All words within the active picture (outside the horizontal and vertical blanking
periods), between the values of 3FCh and 3FFh are re-mapped to 3FBh. All words within
the active picture area between the values of 000h and 003h are remapped to 004h.
This feature is enabled when the IOPROC_EN/DIS pin is HIGH and the
ILLEGAL_WORD_REMAP_DSX_MASK bit in the IOPROC_X register is set LOW.
4.17.7 TRS and Ancillary Data Preamble Remapping
8-bit TRS and ancillary data preambles are re-mapped to 10-bit values. 8-bit to 10-bit
mapping of TRS headers is only supported if the TRS values are 3FC 000 000. Other
values such as 3FD, 3FE, 3FF, 001, 002 and 003 are not supported. This feature is enabled
by default, and cannot be disabled via the IOPROC_X register.
4.17.8 Ancillary Data Extraction
Ancillary data may be extracted externally from the GS1671A output stream using the
Y/1ANC and C/2ANC signals, and external logic.
As an alternative, the GS1671A includes a FIFO, which extracts ancillary data using read
access via the host interface to ease system implementation. The FIFO stores up to 2048
x 16 bit words of ancillary data in two separate 1024 word memory banks.
The device writes the contents of ANC packets into the FIFO, starting with the first
Ancillary Data Flag (ADF), followed by up to 1024 words.
All Data Identification (DID), Secondary Data Identification (SDID), Data Count (DC),
user data, and checksum words are written into the device memory.
The device detects ancillary data packet DID's placed anywhere in the video data
stream, including the active picture area.
Ancillary data from the Y channel or Data Stream One is placed in the Least Significant
Word (LSW) of the FIFO, allocated to the lower 8 bits of each FIFO address.
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Ancillary data from the C channel or Data Stream Two is placed in the
Most Significant Word (MSW) (upper 8 bits) of each FIFO address.
Note: Please refer to the ANC insertion and Extraction Application Note (Doc ID:
GENDOC-053410), for discrete steps and examples of Ancillary data extraction.
In SD mode, ancillary data is placed in the LSW of the FIFO. The MSW is set to zero.
If the ANC_TYPE registers are all set to zero, the device extracts all types of ancillary
data. If programmable ancillary data extraction is required, then up to five types of
ancillary data to be extracted can be programmed in the ANC_TYPE registers (see
Section 4.16.1).
Additionally, the lines from which the packets are to be extracted can be programmed
into the ANC_LINEA[10:0] and ANC_LINEB[10:0] registers, allowing ancillary data from
a maximum of two lines per frame to be extracted. If only one line number register is
programmed (with the other set to zero), ancillary data packets are extracted from one
line per frame only. When both registers are set to zero, the device extracts packets from
all lines.
To start Ancillary Data Extraction, the ANC_DATA_EXT_MASK bit of the host interface
must be set LOW. Ancillary data packet extraction begins in the following frame (see
Figure 4-23: Ancillary Data Extraction - Step A).
Figure 4-23: Ancillary Data Extraction - Step A
Ancillary data is written into Bank A until full. The Y/1ANC and C/2ANC output flags
can be used to determine the length of the ancillary data extracted and when to begin
reading the extracted data from memory.
While the ANC_DATA_EXT_MASK bit is set LOW, the ANC_DATA_SWITCH bit can be
set HIGH during or after reading the extracted data. New data is then written into Bank
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
0
1023
Application Layer
Read Pointer
Internal Write
Poi nter
Bank A
ANC_DATA_SWITCH = LOW
0
1023
Bank B
800h
800h
BFFh BFFh
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B (up to 1024 x 16-bit words), using the corresponding host interface addresses (see
Figure 4-24: Ancillary Data Extraction - Step B).
Figure 4-24: Ancillary Data Extraction - Step B
To read the new data, toggle the ANC_DATA_SWITCH bit LOW. The old data in Bank A
is cleared to zero and extraction continues in Bank B (see Figure 4-25: Ancillary Data
Extraction - Step C).
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
0
1023
Application Layer
Read Pointer
Internal Write
Pointer
Bank A
ANC_DATA_SWITCH = HIGH
0
1023
Bank B
800h800h
BFFh BFFh
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Figure 4-25: Ancillary Data Extraction - Step C
If the ANC_DATA_SWITCH bit is not toggled, extracted data is written into Bank B until
full. To continue extraction in Bank A, the ANC_DATA_SWITCH bit must be toggled
HIGH (see Figure 4-26: Ancillary Data Extraction - Step D).
Figure 4-26: Ancillary Data Extraction - Step D
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
0
1023
Application Layer
Read Pointer
Internal Write
Pointer
Bank A
ANC_DATA_SWITCH = LOW
0
1023
Bank B
800h 800h
BFFh BFFh
0
1023
Application Layer
Read Pointer
Internal Write
Pointer
Bank A
ANC_DATA_SWITCH = HIGH
0
1023
Bank B
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
800h 800h
BFFh
800h
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Toggling the ANC_DATA_SWITCH bit LOW returns the process to step A (Figure 4-23).
Note 1: Toggling the ANC_DATA_SWITCH must occur at a time when no extraction is
taking place, for example: when the both the Y/1ANC and C/2ANC signals are LOW.
To turn extraction off, the ANC_DATA_EXT_MASK bit must be set HIGH.
In HD mode, the device can detect ancillary data packets in the Luma video data only,
Chroma video data only, or both. By default (at power-up or after a system reset), the
device extracts ancillary data packets from the luma channel only.
To extract packets from the Chroma channel only, the HD_ANC_C2 bit of the host
interface must be set HIGH. To extract packets from both Luma/Data Stream One and
Chroma video data, the HD_ANC_Y1_C2 bit must be set HIGH (the setting of the
HD_ANC_C2 bit is ignored).
The default setting of both the HD_ANC_C2 and HD_ANC_Y1_C2 is LOW. The setting of
these bits is ignored when the device is configured for SD video standards.
Ancillary data packet extraction and deletion is disabled when the IOPROC_EN/DIS pin
is set LOW.
After extraction, the ancillary data may be deleted from the video stream by setting the
ANC_DATA_DEL bit of the host interface HIGH. When set HIGH, all existing ancillary
data is removed and replaced with blanking values. If any of the ANC_TYPE registers are
programmed with a DID and/or DID and SDID, only the ancillary data packets with the
matching IDs are deleted from the video stream.
Note 2: After the ancillary data determined by the ANC_TYPE_X_APX registers has
been deleted, other existing ancillary data may not be contiguous. The device does not
concatenate the remaining ancillary data.
Note 3: Reading extracted ancillary data from the host interface must be performed
while there is a valid video signal present at the serial input and the device is locked
(LOCKED signal is HIGH).
4.18 Audio De-embedder
The GS1671A includes an integrated audio de-embedder which is enabled by default in
SMPTE mode. It can be disabled by setting the AUDIO_EN/DIS pin LOW, or by setting the
host interface AUD_EXT_MASK bit to HIGH, or by keeping IOPROC_EN/DIS pin LOW.
In non-SMPTE modes, the audio de-embedder is not active.
Up to eight channels of audio may be extracted from the received serial digital video
stream. The output signal formats supported by the device include AES/EBU, I2S
(default) and industry standard serial digital formats.
16, 20 and 24-bit audio bit depths are supported for 48kHz synchronous audio for SD
data rates. For HD data rate, 16, 20 and 24-bit audio bit depths are supported for 48kHz
audio. The audio may be synchronous or asynchronous to the video.
Additional audio processing features include audio mute on loss of lock, de-embed and
delete, group selection, audio output re-mapping, ECC error detection and correction
(HD mode only), and audio channel status extraction.
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4.18.1 Serial Audio Data I/O Signals
The Serial Audio Data I/O pins are listed in Table 4-15: Serial Audio Pin Descriptions.
The timing of the serial audio output signals, the ACLK output signal is as shown in
Figure 4-27: ACLK to Data Signal Output Timing.
Figure 4-27: ACLK to Data Signal Output Timing
When AUDIO_EN/DIS is set HIGH, audio extraction is enabled and the audio output
signals are extracted from the video data stream. When set LOW, the serial audio
outputs, ACLK and WCLK outputs are set LOW.
Table 4-15: Serial Audio Pin Descriptions
Pin Name Description
AUDIO_EN/DISEnable Input for Audio Processing
AOUT_1/2 Serial Audio output; Channels 1 and 2
AOUT_3/4 Serial Audio output; Channels 3 and 4
AOUT_5/6Serial Audio Output; Channels 5 and 6
AOUT_7/8 Serial Audio Output; Channels 7 and 8
ACLK 64fs clock
WCLK Word clock
AMCLK Audio Master Clock, selectable 128fs, 256fs, or 512fs
I/O Timing Specs:
AOUT*
ACLK
A1A0 A2
128fs = 162.76ns (AES/EBU)
64fs = 325.52ns (other modes)
20%
80%
tr
20%
80%
tf
A3
Audio Outputs:
toh
tod
toh tr/tf (min) C
LOAD
tod tr/tf (max) toh tr/tf (min) tod tr/tf (max)
AOUT 1.500ns 0.600ns 6 pF 7.000ns 2.200ns 15 pF 1.500ns 0.600ns 6 pF 7.000ns 2.300ns 15 pF
Audio Outputs
3.3V 1.8V
C
LOAD
C
LOAD
C
LOAD
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In addition, all functional logic associated with audio extraction is disabled to reduce
power consumption.
4.18.2 Serial Audio Data Format Support
The GS1671A supports the following serial audio data formats:
•I
2S (default)
•AES/EBU
• Serial Audio Left Justified, MSB First
• Serial Audio Left Justified, LSB First
• Serial Audio Right Justified, MSB First
• Serial Audio Right Justified, LSB First (this mode is not supported in SD)
By default (at power up or after system reset) I2S is selected. The other data formats are
selectable via the host interface using the AMA/AMB[1:0] bits.
The serial audio output formats may use LSB first according to the settings of the control
bits LSB_FIRSTA, LSB_FIRSTB, LSB_FIRSTC, and LSB_FIRSTD. When in I2S mode, these
control bits must all be set LOW (default).
When I2S format is desired, both groups must be set to I2S (for example: AMA = AMB =
11). This is because they share the same WCLK.
Figure 4-28: I2S Audio Output Format
Figure 4-29: AES/EBU Audio Output Format
Table 4-16: Audio Output Formats
AMA/AMB[1:0] Audio Output Format
00 AES/EBU audio output
01 Serial audio output: Left Justified; MSB first
10 Serial audio output: Right Justified; MSB first
11 I2S (Default)
WCLK
ACLK
AOUT[8/7:2/1]
MSB
03212345622
LSB MSB
032 12345622
LSB
Channel A (Left) Channel B (Right)
WCLK
A
CLK
AOUT[8/7:2/1] 123
4
LSB MSB
0
Channel A (Left) Channel B (Right)
5678 27 29
28 30 31 12340 5 6 7 8 27 29
28 30 31
AUXPreamble PCVU LSB MSBAUXPreamble PCVU
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Figure 4-30: Serial Audio, Left Justified, MSB First
Figure 4-31: Serial Audio, Left Justified, LSB First
Figure 4-32: Serial Audio, Right Justified, MSB First
Figure 4-33: Serial Audio, Right Justified, LSB First
4.18.2.1 AES/EBU Mode
In AES/EBU output mode, the audio de-embedder uses a 128fs (6.144MHz audio bit
clock) clock as shown in Figure 4-34.
Figure 4-34: AES/EBU Audio Output to Bit Clock Timing
4.18.2.2 Audio Data Packet Extraction Block
The audio de-embedder looks for audio data packets on every line of the incoming
video.
The audio data must be embedded according to SMPTE ST 272 (SD) or
SMPTE ST 299 (HD).
WCLK
ACLK
AOUT[8/7:2/1] 23
MSB
02212345621
LSB
23
MSB
02212345621
LSB
Channel A (Left) Channel B (Right)
WCLK
ACLK
AOUT[8/7:2/1] 0
LSB
3212221201918172
MSB
0
LSB
3212221201918172
MSB
Channel A (Left) Channel B (Right)
WCLK
ACLK
AOUT[8/7:2/1] 23
MSB
0221220 17181921
LSB
23
MSB
0221220 17181921
LSB
Channel A (Left) Channel B (Right)
WCLK
A
CLK
AOUT[8/7:2/1] 0
LSB
321222136542
MSB
0
LSB
321222136542
MSB
Channel A (Left) Channel B (Right)
AMCLK
(128fs)
AOUT_1/2, AOUT_3/4
AOUT_5/6, AOUT_7/8
6.144MHz
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The Audio Group Detect registers are set HIGH when audio data packets with a
corresponding group DID are detected in the input video stream. The host interface
reports the individual audio groups detected.
When an audio data packet with a DID set in IDA[1:0] and IDB[1:0] is detected, the audio
sample information is extracted and written into the audio FIFO.
The embedded audio group selected by IDA[1:0] is described henceforth in this
document as Group A or Primary Group. The embedded audio group selected by
IDB[1:0] is described henceforth in this document as Group B or Secondary Group.
Due to the large size of the horizontal ancillary data space in 720p/24, 720p/25 and
720p/30 video standards, the maximum number of ancillary data words the audio
de-embedder can process is limited to 1024 when configured for these standards.
4.18.2.3 Audio Control Packets
The audio de-embedder automatically detects the presence of audio control packets in
the video stream. When audio control packets for audio Group A are detected, the
CTRA_DET bit of the host interface is set HIGH. When audio control packets for audio
Group B are detected, the CTRB_DET bit of the host interface is set HIGH.
The audio control packet data is accessible via the host interface.
The audio control packets must be embedded according to SMPTE ST 272 (SD) or
SMPTE ST 299 (HD).
Note: In SD, the control packet host interface registers are updated with new control
packet values, after the CTRA_DET/CTRB_DET flags are cleared. In HD, the update
happens automatically.
4.18.2.4 Setting Packet DID
Table 4-18 below, shows the 2-bit host interface setting for the audio group DID's.
For 24-bit audio support in SD mode, extended audio packets for Group A must have the
same group DID set in IDA[1:0] of the host interface. Extended audio packets for Group
B must have the same group DID set in IDB[1:0] of the host interface.
The audio de-embedder automatically detects the presence of extended audio packets.
When detected, the audio output format is set to 24-bit audio sample word length.
Table 4-17: Audio Data Packet Detect Register
Name Description Default
ADPG4_DET Audio Group Four Data Packet Detection (1: Detected)0
ADPG3_DET Audio Group Three Data Packet Detection (1: Detected)0
ADPG2_DET Audio Group Two Data Packet Detection (1: Detected)0
ADPG1_DET Audio Group One Data Packet Detection (1: Detected)0
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The audio de-embedder defaults to audio Groups One and Two, where Group A is
extracted from packets with audio Group One DID, and Group B from packets with
audio Group Two DID.
Note: To keep sample delays between audio channels the same after changing the
value of IDA or IDB in the SD audio core, the audio FIFOs must be cleared. This is
accomplished by asserting CLEAR_AUDIO and de-asserting at least one frame later.
When the FIFOs are in the clear state, audio will be muted, but audio clocks will continue
to run.
4.18.2.5 Audio Packet Delete Block
To delete all ancillary data with a group DID shown in Table 4-18, the ALL_DEL bit in the
host interface must be set HIGH.
4.18.2.6 ECC Error Detection & Correction Block (HD Mode Only)
The audio de-embedder performs BCH(31,25) forward error detection and correction, as
described in SMPTE ST 299. The error correction for all embedded audio data packets is
activated when the host interface ECC_OFF bit is set LOW (default LOW). The audio
de-embedder corrects any errors in both the audio output and the embedded packet.
When a one-bit error is detected in a bit array of the ECC protected region of the audio
data packet with audio group DID set in IDA[1:0], the ECCA_ERROR flag is set HIGH.
When a one-bit error is detected in the ECC protected region of the audio data packet
with audio group DID set in IDB[1:0], the ECCB_ERROR flag is set HIGH.
Figure 4-35 shows examples of error correction and detection. Up to eight bits in error
can be corrected, providing each bit error is in a different bit array (shown below). When
there are two or more bits in error in the same 24-bit array, the errors are detected, but
not corrected.
Table 4-18: Audio Group DID Host Interface Settings
Audio
Group
SD Data
DID
SD Extended
DID
HD Data
DID
SD Control
DID
HD Control
DID
Host Interface Register Setting
(2-bit)
1 2FFh 1FEh 2E7h 1EFh 1E3h 00b
21FDh 2FCh1E6h 2EEh 2E2h 01b
3 1FBh 2FAh 1E5h 2EDh 2E1h 10b
4 2F9h 1F8h 2E4h 1ECh 1E0h 11b
Table 4-19: Audio Data and Control Packet DID Setting Register
Name Description Default
IDA[1-0] Group A Audio data and control packet DID setting00b
IDB[1-0] Group B Audio data and control packet DID setting01b
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Figure 4-35: ECC 24-bit Array and Examples
4.18.3 Audio Processing
4.18.3.1 Audio Clock Generation
For SD and HD audio, a single set of audio frequencies is generated for all audio
channels, using a Direct Digital Period Synthesizer (DDPS) to minimize jitter.
In SD mode, audio clocks are derived from the PCLK.
In HD mode, the input control for the DDPS is derived from the two embedded audio
clock phase words in the audio data packet corresponding to Group A. The audio clock
phase information used is taken from the first embedded audio packet in the HANC
space. With no embedded audio present, the device will not generate ACLK or WCLK.
The IGNORE_PHASE bit should be asserted in this case to ensure the proper AMCLK
frequency is generated.
The audio de-embedder also includes a Flywheel block to overcome any inconsistencies
in the embedded audio clock phase information.
If the audio phase data is not present in the audio data packets, or is incorrect, the
NO_PHASEA_DATA bit in the host interface is set and the clock will free-run based on
the detected video format, the PCLK and the M value. IGNORE_PHASE should be set
HIGH when NO_PHASEA_DATA is set. This does not occur automatically.
When the IGNORE_PHASE bit in the host interface is set HIGH, it is recommended that
the M value be programmed via the host interface. This can be done by setting the
FORCE_M bit HIGH, and programming the desired value into FORCE_MEQ1001. The
correct value can be obtained by reading the M bit from the Video Core Registers.
If the DDPS is locked to phase data and audio data packets are lost or corrupted, the
Clock Generator will flywheel for up to four audio data packets. If no valid audio data
packet with valid phase data is provided within this time, the Clock Generator will
free-run based on the video format, the PCLK and the M value.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
24-bit array
ADF ADF ADF DID DBN DC CLK CLK CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Errors corrected
ADF ADF ADF DID DBN DC CLK CLK CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Errors detected but not corrected
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If the IGNORE_PHASE bit in the host interface is HIGH, the clock will free-run based on
the video format, the PCLK and the M value, independent of the NO_PHASEA_DATA bit.
In the 720p/24 video format, the total line length is 4125 pixels, which requires a
resolution of 13 bits for the audio clock phase words in the embedded audio data
packets. SMPTE ST 299 only specifies a maximum of 12 bits resolution. Proposed
changes to SMPTE ST 299 suggest using bit 5 of UDW1 (currently reserved and set to
zero) in the audio data packet as the MSB (ck13) for the audio clock phase data,
providing 13 bits resolution.
Some audio encoders may hold the clock phase value at a maximum value when
reached, until reset at the end of the line. This produces a small amount of audio phase
jitter for the period of one sample.
To overcome this issue, the audio de-embedder checks for all cases. On detection of the
maximum value, a comparison is made between previous clock phases and the correct
position interpolated. If the clock phase data value starts to decrease, the de-embedder
checks to see if bit 5 (ck13) of UDW1 in the audio data packet is set. If ck13 is set, the
correct value is used. If ck13 is not set, the correct position is interpolated.
4.18.3.2 Detect Five-Frame Sequence Block
Five-frame sequence detection is required for 525-line based video formats only. The
audio de-embedder checks the Audio Frame Number sequence in the audio control
packets, when present. If the audio frame sequence is running (repeated 1 to 5 count),
the audio de-embedder uses this information to determine the five-frame sequence. If
the audio control packet is not present, or the Audio Frame Number words are set to
200h, the audio de-embedder detects the five-frame sequence by counting the number
of samples per frame. Figure 4-36 shows the number of samples per frame over a
five-frame sequence.
Figure 4-36: Sample Distribution Over Five Video Frames (525-line Systems)
When the audio inputs are asynchronously switched or disrupted, the audio
de-embedder continues to write audio samples into the audio buffer, based on the
current five-frame sequence. The de-embedder then re-locks to the new five-frame
sequence, at which point a sample may be lost.
Note: In SD, all four channel pairs must follow the same five-frame sequence.
4.18.3.3 Audio FIFO Block
The function of the FIFO block is to change the audio data word rate from the ANC rate
multiplexed with the video signal to the 48kHz audio output rate.
Frame 1 1 emarF5 emarF4 emarF3 emarF2 emarF5 emarF
1602 2061206120612061 1601 1601
8008 Samples
1602 Repeat
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The audio FIFO block contains the audio sample buffers; one per audio channel. Each
buffer is 36 audio samples deep. At power up or reset, the read pointer is held at the zero
position until 26 samples have been written into the FIFO (allows for six lines per frame
with no audio samples; a maximum of 4 samples per line in SD Mode). See Figure 4-37.
Figure 4-37: Audio Buffer After Initial 26 Sample Write
The position of the write pointer with respect to the read pointer is monitored
continuously. If the write pointer is less than 6 samples ahead of the read pointer (point
A in Figure 4-38), a sample is repeated from the read-side of the FIFO. If the write pointer
is less than six samples behind the read pointer (point B in Figure 4-38), a sample is
dropped. This avoids buffer underflow/overflow conditions.
Figure 4-38: Audio Buffer Pointer Boundary Checking
The repeat or drop sample operation is performed a maximum of 28 consecutive times,
after which the audio outputs are muted (all sample data set to zero). In SD Mode, 26
samples are required to be written into the FIFO prior to starting the read operation
again.
The audio buffer pointer offset may be reduced from 26 samples to 12 or 6 samples using
the OS_SEL[1:0] bits in the host interface. The default setting is 26 samples (see
Table 4-20).
When the OS_SEL[1:0] bits are set for six-sample pointer offset, no boundary-checking
is performed.
025 35
Audio Buffer
Write
Pointer
Address
Read
Pointer
029 35
Read
Pointer
A
5
B
Audio Buffer
Address
Write
Pointer
Write
Pointer
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In HD mode the audio FIFO is a maximum of 10 samples deep. According to
SMPTE ST 299, audio samples are multiplexed immediately in the next HANC region
after the audio sample occurs.
Sample Delay
When extracting SD audio, certain conditions can cause the sample delay through the
audio FIFOs to be 1-4 samples different between channels.
If delays through the audio FIFOs must be the same, it is recommended that the FIFO
size gets set to 22 or 16 with OS_SEL[1:0]. Additionally, the audio FIFO must be cleared
when either of the following occurs:
1. Loss of lock. The FIFO should be cleared when the part has relocked.
2. When one of the groups of audio disappears and re-appears. Poll the audio data
packet detected registers ADPG1_DET, ADPG2_DET, ADPG3_DET, and ADPG4_DET
once every frame. If one of the groups currently de-embedded disappears and
re-appears, clear the audio FIFO after the group re-appears.
Clear the audio FIFO by asserting CLEAR_AUDIO and de-asserting at least one frame
later. When the FIFOs are in the clear state, audio will be muted but audio clocks will
continue to run.
When switching between 525 and 625 formats, it is recommended that the device be
reset to keep the delays through the audio FIFO the same between channels.
4.18.3.4 Audio Crosspoint Block
The Audio Crosspoint is used for audio output channel re-mapping. This feature allows
any of the selected audio channels in Group A or Group B to be output on any of the eight
output channels. The default setting is for one to one mapping, where AOUT_1/2 is
extracted from Group A CH1 and CH2, AOUT_3/4 is extracted from Group A CH3 and
CH4, and so on.
Note: If audio samples from embedded audio packets with the group set in IDA[1:0] are
to be paired with samples from the group set in IDB[1:0], all of the channels must have
been derived from the same Word Clock and must be synchronous.
The output channel is set in the OPn_SRC[2:0] host interface registers. Table 4-21 lists the
3-bit address for audio channel mapping.
Table 4-20: Audio Buffer Pointer Offset Settings
OS_SEL[1:0] Buffer Pointer Offset
00 26 samples (default)
01 12 samples
10 6 samples
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4.18.3.5 Serial Audio Output Word Length
The audio output, in serial modes, has a selectable 24, 20 or 16-bit sample word length.
The ASWL[1:0] host interface register is used to configure the audio output sample word
length. Figure 4-22 shows the host interface 2-bit code for setting the audio sample word
length. When the presence of extended audio packets is detected in SD modes, the audio
de-embedder defaults to 24-bit audio sample word length.
4.18.3.6 Audio Channel Status
The GS1671A detects the AES/EBU Audio Channel Status (ACS) block information for
each of the selected channel pairs.
ACS data detection is indicated by corresponding ACS_DET flag bits in the host
interface. The flag is cleared by writing to the same location.
Audio Channel Status Read
AES/EBU ACS data is available separately for each of the channels in a stereo pair. The
GS1671A defaults to reading the first channel of each pair. There are 184 bits in each
Table 4-21: Audio Channel Mapping Codes
Audio Output Channel 3-bit Host Interface
Source Address
1000
2001
3010
4011
5100
6101
7110
8111
Table 4-22: Audio Sample Word Lengths
ASWL[1:0] Audio Sample Word Length
(SD)
Audio Sample Word Length
(HD)
00 24-bit 24-bit
01 20-bit 20-bit
10 16-bit 16-bit
11 Auto 24/20-bit (Default) Reserved (Default)*
*Note: By default, for HD at power-up, the word length is invalid. The desired word
length should be programmed through the host interface.
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ACS packet, which are written to twelve 16-bit right-justified registers in the host
interface.
The ACS_USE_SECOND bit (default LOW) selects the second channel in each audio pair
when set HIGH.
Once all of the ACS data for a channel has been acquired, the corresponding ACS_DET
bit is set, and acquisition stops. The ACS data is overwritten with new data when the
ACS_DET bit is cleared in the system.
Audio Channel Status Regeneration
When the ACS_REGEN bit in the host interface is set HIGH, the audio de-embedder
embeds the 24 bytes of the Audio Channel Status information programmed in the
ACSR[183:0] registers into the 'C' bit of the AES/EBU outputs. The same Audio Channel
Status information is used for all output channels.
In order to apply ACSR data;
• Set the ACS_REGEN bit to logic HIGH
• Write the desired ACSR data to the ACSR registers
• Set the ACS_APPLY bit to HIGH
At the next status boundary, the device outputs the contents of the ACSR registers as
ACS data. This event may occur at a different time for each of the output channels. While
waiting for the status boundary, the device sets the appropriate ACS_APPLY_WAIT[A:D]
flag.
Table 4-23 shows the host interface default settings for the Audio Channel Status block.
The audio de-embedder automatically generates the CRC word.
Table 4-23: Audio Channel Status Information Registers
Name Description Default
ACSR[7-0] Audio channel status block byte 0 set. Used when ACS_REGEN is set HIGH 85h
ACSR[15-8] Audio channel status block byte 1 set. Used when ACS_REGEN is set HIGH 08h
ACSR[23-16]Audio channel status block byte 2 set. Used when ACS_REGEN is set HIGH 28h (SD) 2Ch (HD)
ACSR[31-24]:
ACSR[183-176]Audio channel status block data for bytes 3 to 22. Used when ACS_REGEN is set HIGH 00h
ACS_REGEN Audio channel status regenerate 0
ACS_APPLY Apply new ACSR data 0
ACS_APPLY_W
AIT[A:D] Waiting to apply new ACSR data 0
ACS[7-0]:
ACS[183-176]Audio channel status block data for bytes 0 to 22 00h: 00h
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4.18.3.7 Audio Mute
When the MUTE bits in the host interface are set HIGH, the audio outputs are muted (all
audio sample bits are set to zero). To set all the audio output channels to mute, set the
host interface MUTE_ALL bit HIGH.
Mute On Loss Of Lock
When the GS1671A loses lock (LOCKED signal is LOW), the audio de-embedder sets all
audio outputs LOW (no audio formatting is performed). The ACLK, WCLK and AMCLK
outputs are also forced LOW.
Table 4-24: Audio Channel Status Block for Regenerate Mode Default Settings
Name Byte Bit Default Mode
PRO 0 0 1bProfessional use of channel status block
Emphasis 0 2-4 100b100b None. Rec. manual override disabled
Sample Frequency06-7 01b48kHz. Manual override or auto disabled
Channel Mode10-30001bTwo channels. Manual override disabled
AUX 2 0-2
000bSD Modes: Maximum audio word length is 20 bits
001bHD Mode: Maximum audio word length is 24 bits
Source Word Length 2 3-5 101bMaximum word length (based on AUX setting).
24-bit for HD Mode; 20-bit for SD Modes
All other bits set to zero
Table 4-25: Audio Mute Control Bits
Name Description Default
MUTE_ALL Ch1-8 audio mute enable (1: Enabled)0
MUTE8 Ch8 audio mute enable (1: Enabled)0
MUTE7 Ch7 audio mute enable (1: Enabled)0
MUTE6Ch6 audio mute enable (1: Enabled)0
MUTE5 Ch5 audio mute enable (1: Enabled)0
MUTE4 Ch4 audio mute enable (1: Enabled)0
MUTE3 Ch3 audio mute enable (1: Enabled)0
MUTE2 Ch2 audio mute enable (1: Enabled)0
MUTE1 Ch1 audio mute enable (1: Enabled)0
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4.18.4 Error Reporting
4.18.4.1 Data Block Number Error
When the 1-255 count sequence in the Data Block Number (DBN) word of Group A audio
data packets is discontinuous, the DBNA_ERR bit in the host interface (DBN_ERR
register for SD, ACS_DET register for HD) is set HIGH. When the 1-255 count sequence
in the DBN word of Group B audio data packets is discontinuous, the DBNB_ERR bit in
the host interface (DBN_ERR register for SD, ACS_DET register for HD) register is set
HIGH.
4.18.4.2 ECC Error
The GS1671A monitors the ECC error status of the two selected audio groups, as
described in Section 4.18.2.6 on page 74.
The ECC[N]_ERROR flags also have associated SD_AUDIO_ERROR_MASK and
HD_AUDIO_ERROR_MASK register flags for configuration of error reporting in the
Receiver. The ECC[N]_ERROR flags remain set until read via the host interface.
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4.19 GSPI - HOST Interface
The GSPI, or Gennum Serial Peripheral Interface, is a four-wire interface provided to
allow the system to access additional status and control information through
configuration registers in the GS1671A.
The GSPI is comprised of a Serial Data Input signal (SDIN), Serial Data Output signal
(SDOUT), an active low Chip Select (CS), and a Burst Clock (SCLK).
Because these pins are shared with the JTAG interface port, an additional control signal
pin JTAG/HOST is provided.
When JTAG/HOST is LOW, the GSPI interface is enabled. When JTAG/HOST is HIGH, the
JTAG interface is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS signals must be provided by the
system. The SDOUT pin is a non-clocked loop-through of SDIN and may be connected to
the SDIN of another device, allowing multiple devices to be connected to the GSPI chain.
See Section 4.19.2 for details. The interface is illustrated in the Figure 4-39 below.
Note: When using more than one Semtech serializer or deserializer (SerDes) in the same
design, the SDOUT pins of multiple SerDes ICs must not be bussed together as was done
with older generations of Semtech SerDes ICs
Figure 4-39: GSPI Application Interface Connection
All read or write access to the GS1671A is initiated and terminated by the system host
processor. Each access always begins with a Command/Address Word, followed by a
data write to, or data read from, the GS1671A.
Application Host
SCLK SCLK
SCLK
CS1
SDOUT SDIN
SDOUT
SDOUT
CS
SDIN
SDIN
CS2
GS1671A
GS1671A
CS
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4.19.1 Command Word Description
The Command Word consists of a 16-bit word transmitted MSB first and contains a
read/write bit, an Auto-Increment bit and a 12-bit address.
Figure 4-40: Command Word Format
Command Words are clocked into the GS1671A on the rising edge of the Serial Clock
SCLK, which operates in a burst fashion. The chip select (CS) signal must be set low a
minimum of 1.5ns (t0 in Figure 4-42) before the first clock edge to ensure proper
operation.
When the Auto-Increment bit is set LOW, each Command Word must be followed by
only one Data Word to ensure proper operation.
If the Auto-Increment bit is set HIGH, the following Data Word is written into the
address specified in the Command Word, and subsequent Data Words are written into
incremental addresses from the first Data Word. This facilitates multiple address writes
without sending a Command Word for each Data Word.
Note: The RSV bits in the GSPI command word can be set to zero as placeholder, though
these bits are not used.
4.19.2 Data Read or Write Access
During a read sequence (Command Word R/W bit set HIGH) serial data is transmitted or
received MSB first, synchronous with the rising edge of the serial clock SCLK. The Chip
Select (CS) signal must be set low a minimum of 1.5ns (t0 in Figure 4-42) before the first
clock edge to ensure proper operation. The first bit (MSB) of the Serial Output (SDOUT)
is available (t5 in Figure 4-43) following the last falling SCLK edge of the read
Command Word, the remaining bits are clocked out on the negative edges of SCLK.
Note: When several devices are connected to the GSPI chain, only one CS may be
asserted during a read sequence.
During a write sequence (Command Word R/W bit set LOW), a wait state of 37.1ns (t4 in
Figure 4-42) is required between the Command Word and the following Data Word. This
wait state must also be maintained between successive Command Word/Data Word
write sequences. When Auto Increment mode is selected (AutoInc = 1), the wait state
must be maintained between successive Data Words after the initial
Command Word/Data Word sequence.
During the write sequence, all Command and following Data Words input at the SDIN
pin are output at the SDOUT pin unchanged. When several devices are connected to the
GSPI chain, data can be written simultaneously to all the devices which have CS set
LOW.
Figure 4-41: Data Word Format
R/W RSV RSV AutoInc A0
A1A2A3A4A5A6A7A8A9A11 A10
MSB LSB
D15 D14 D13 D12 D0D1D2D3D4D5D6D7D8D9D11 D10
MSB LSB
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4.19.3 GSPI Timing
Write and Read Mode timing for the GSPI interface are shown in Figure 4-42 and
Figure 4-43 below:
Figure 4-42: Write Mode
Figure 4-43: Read Mode
Figure 4-44: GSPI Time Delay
R/W RSV RSV Auto
_In c A0A1A2A3A4A5A6A7A8A9A11 A10 D15 D14 D13 D12 D0D1D2D3D4D5D6D7D8D9D1 1 D1 0
SCLK _TCLK
CS _TMS
SDIN_TDI
SDOUT _TDO
t
0
t
3
t
1
t
2
R/W RSV RSV Auto
_Inc A0A1A2A3A4A5A6A7A8A9A1 1 A1 0 D15 D14 D13 D12 D0D1D2D3D4D5D6D7D8D9D1 1 D1 0
t
8
t
4
t
7
R/W RSV RSV Au t o
_Inc A0A1A2A3A4A5A6A7A8A9A11 A10
D15D14D13D12 D0D1D2D3D4D5D6D7D8D9D1 1 D 1 0
SCLK _TCLK
CS _ T MS
SDIN_TDI
SDOUT _TDO
t
5
R/W R SV R SV Aut o
_Inc A0A1A2A3A4A5A6A7A8A9A1 1 A 1 0
t
6
SDIN_TDI data_0
SDIN_TDI to SDOUT_TDO combinational path for daisy chain connection of multiple GS1671A devices.
SDOUT_TDO data_0
TDELAY
Table 4-26: GSPI Time Delay
Parameter Symbol Conditions Min Typ Max Units
Delay time tDELAY 50% levels;
1.8V operation −−13.1 ns
Delay time tDELAY 50% levels;
3.3V operation −−9.7 ns
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This timing must be satisfied across all ambient temperature and power supply
operating conditions, as described in the Electrical Characteristics on page 16.
Table 4-27: GSPI Timing Parameters (50% levels; 3.3V or 1.8V operation)
Parameter Symbol Min Ty p Max Units
CS low before SCLK rising edget01.5 −−ns
SCLK periodt116.67−−ns
SCLK duty cycle t240 50 60%
Input data setup time t31.5 −−ns
Time between end of Command Word (or data in
Auto-Increment mode) and the first SCLK of the
following Data Word – write cycle
t4
PCLK (MHz) ns
−−ns
unlocked100
27.0 37.1
74.25 13.5
148.5 6.7
Time between end of Command Word (or data in
Auto-Increment mode) and the first SCLK of the
following Data Word – read cycle.
t5
PCLK (MHz) ns
−−ns
unlocked−
27.0 148.4
74.25 53.9
148.5 27
Time between end of Command Word (or data in
Auto-Increment mode) and the first SCLK of the
following Data Word – read cycle - ANC FIFO Read
t5222.6−−ns
Output hold time (15pF load)t61.5 −−ns
CS high after last SCLK rising edget7
PCLK (MHz) ns
−−ns
unlocked445
27.0 37.1
74.25 13.5
148.5 6.7
Input data hold time t81.5 −−ns
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4.20 Host Interface Register Maps
Note: The GS1671A only accepts write/read commands to/from the Audio Register
Maps when the audio core is locked to the incoming video data rate. The Video Register
Map is always active, whether valid serial input data is present or not.
4.20.1 Video Core Registers
Table 4-28: Video Core Configuration and Status Registers
Address Register Name Bit Name Bit Description R/W Default
000h IOPROC_1
RSVD 15 Reserved. R 0
TRS_WORD_REMAP_DS1
_DISABLE 14 Disables 8-bit TRS word remapping
for HD and SD inputs. R/W 0
RSVD 13 Reserved.R/W 0
EDH_FLAG_UPDATE
_MASK12 Disables updating of EDH error
flags. R/W 0
EDH_CRC_INS_MASK11
Disables EDH_CRC error correction
and insertion. R/W 0
H_CONFIG10
Selects the H blanking indication:
0: Active line blanking - the H
output is HIGH for all the
horizontal blanking period,
including the EAV and SAV TRS
words.
1: TRS based blanking - the H
output is set HIGH for the entire
horizontal blanking period as
indicated by the H bit in the
received TRS signals.
This signal is only valid when
TIM_861 is set to '0' (via pin or host
interface).
R/W 0
ANC_DATA_EXT_MASK9
Disables ancillary data extraction
FIFO. R/W 0
AUD_EXT_MASK8Disables audio extraction block. R/W 0
TIM_861_PIN_DISABLE 7
Disable TIM_861 pin control when
set to '1', and use TIMING_861 bit
instead.
R/W 0
TIMING_8616
Selects the output timing reference
format: 0 = Digital FVH timing
output; 1 = CEA-861 timing output.
R/W 0
RSVD 5Reserved.R/W 0
ILLEGAL_WORD_REMAP
_DS1_MASK4Disables illegal word remapping
for HD and SD inputs. R/W 0
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000h IOPROC_1
ANC_CHECKSUM
_INSERTION_DS1_MASK3Disables insertion of ancillary data
checksums for HD and SD inputs. R/W 0
CRC_INS_DS1_MASK2
Disables insertion of HD CRC words
for HD inputs. R/W 0
LNUM_INS_DS1_MASK1
Disables insertion of line numbers
for HD inputs. R/W 0
TRS_INS_DS1_MASK0
Disables insertion of TRS words for
HD and SD inputs. R/W 0
001h IOPROC_2
RSVD 15 Reserved.R/W N/A
NONINV 14
With DISB_AUTDET set HIGH, if this
bit is asserted (HIGH), forces
non-inverted MPEG-2 decoding. If
deasserted (LOW), forces inverted
MPEG-2 decoding. Applicable in
DVB-ASI mode only.
R/W 0
DISB_AUTDET 13
Disables auto detection of inverted
DVB ASI MPEG-2 data when HIGH.
When LOW, NONINV is ignored
and the DVB decoder auto detects
for inverted MPEG-2 data.
Applicable in DVB-ASI mode only.
R/W 0
RSVD 12-0 Reserved.R/W N/A
002h ERROR_STAT_1
RSVD 15-11 Reserved.ROCW 0
VD_STD_ERR_DS110
Video Standard Error indication for
HD and SD inputs. ROCW0
FF_CRC_ERR 9 EDH Full Frame CRC error
indication. ROCW0
AP_CRC_ERR 8 EDH Active Picture CRC error
indication. ROCW0
RSVD 7Reserved.ROCW 0
CCS_ERR_DS16
Chroma ancillary data checksum
error indication for HD and SD
inputs.
ROCW0
YCS_ERR_DS15
Luma ancillary data checksum error
indication for HD and SD inputs. ROCW0
CCRC_ERR_DS14
Chroma CRC error indication for
HD inputs. ROCW0
YCRC_ERR_DS13
Luma CRC error indication for HD
inputs. ROCW0
LNUM_ERR_DS12
Line number error indication for
HD inputs. ROCW0
SAV_ERR_DS11
SAV error indication for HD and SD
inputs. ROCW0
EAV_ERR_DS10
EAV error indication for HD and SD
inputs. ROCW0
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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003h RSVD RSVD 15-0 Reserved.ROCW N/A
004h EDH_FLAG_IN
EDH_DETECT15Embedded EDH packet detected.R 0
ANC_UES_IN 14 Ancillary data – unknown error
status flag.R0
ANC_IDA_IN 13 Ancillary data – internal error
detected already flag.R0
ANC_IDH_IN 12 Ancillary data – internal error
detected here flagR0
ANC_EDA_IN 11 Ancillary data – error detected
already flag.R0
ANC_EDH_IN 10 Ancillary data – error detected here
flag.R0
FF_UES_IN 9 EDH Full Field – unknown error
status flag.R0
FF_IDA_IN 8 EDH Full Field – internal error
detected already flag.R0
FF_IDH_IN 7 EDH Full Field – internal error
detected here flag.R0
FF_EDA_IN 6EDH Full Field – error detected
already flag.R0
FF_EDH_IN 5 EDH Full Field – error detected here
flag.R0
AP_UES_IN 4 EDH Active Picture – unknown
error status flag.R0
AP_IDA_IN 3 EDH Active Picture – internal error
detected already flag.R0
AP_IDH_IN 2 EDH Active Picture – internal error
detected here flag.R0
AP_EDA_IN 1 EDH Active Picture – error detected
already flag.R0
AP_EDH_IN 0 EDH Active Picture – error detected
here flag.R0
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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000h IOPROC_1
ANC_CHECKSUM
_INSERTION_DS1_MASK3Disables insertion of ancillary data
checksums for HD and SD inputs. R/W 0
CRC_INS_DS1_MASK2
Disables insertion of HD CRC words
for HD inputs. R/W 0
LNUM_INS_DS1_MASK1
Disables insertion of line numbers
for HD inputs. R/W 0
TRS_INS_DS1_MASK0
Disables insertion of TRS words for
HD and SD inputs. R/W 0
001h IOPROC_2
RSVD 15 Reserved.R/W N/A
NONINV 14
With DISB_AUTDET set HIGH, if this
bit is asserted (HIGH), forces
non-inverted MPEG-2 decoding. If
deasserted (LOW), forces inverted
MPEG-2 decoding. Applicable in
DVB-ASI mode only.
R/W 0
DISB_AUTDET 13
Disables auto detection of inverted
DVB ASI MPEG-2 data when HIGH.
When LOW, NONINV is ignored
and the DVB decoder auto detects
for inverted MPEG-2 data.
Applicable in DVB-ASI mode only.
R/W 0
RSVD 12-0 Reserved.R/W N/A
002h ERROR_STAT_1
RSVD 15-11 Reserved.ROCW 0
VD_STD_ERR_DS110
Video Standard Error indication for
HD and SD inputs. ROCW0
FF_CRC_ERR 9 EDH Full Frame CRC error
indication. ROCW0
AP_CRC_ERR 8 EDH Active Picture CRC error
indication. ROCW0
RSVD 7Reserved.ROCW 0
CCS_ERR_DS16
Chroma ancillary data checksum
error indication for HD and SD
inputs.
ROCW0
YCS_ERR_DS15
Luma ancillary data checksum error
indication for HD and SD inputs. ROCW0
CCRC_ERR_DS14
Chroma CRC error indication for
HD inputs. ROCW0
YCRC_ERR_DS13
Luma CRC error indication for HD
inputs. ROCW0
LNUM_ERR_DS12
Line number error indication for
HD inputs. ROCW0
SAV_ERR_DS11
SAV error indication for HD and SD
inputs. ROCW0
EAV_ERR_DS10
EAV error indication for HD and SD
inputs. ROCW0
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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003h RSVD RSVD 15-0 Reserved.ROCW N/A
004h EDH_FLAG_IN
EDH_DETECT15Embedded EDH packet detected.R 0
ANC_UES_IN 14 Ancillary data – unknown error
status flag.R0
ANC_IDA_IN 13 Ancillary data – internal error
detected already flag.R0
ANC_IDH_IN 12 Ancillary data – internal error
detected here flagR0
ANC_EDA_IN 11 Ancillary data – error detected
already flag.R0
ANC_EDH_IN 10 Ancillary data – error detected here
flag.R0
FF_UES_IN 9 EDH Full Field – unknown error
status flag.R0
FF_IDA_IN 8 EDH Full Field – internal error
detected already flag.R0
FF_IDH_IN 7 EDH Full Field – internal error
detected here flag.R0
FF_EDA_IN 6EDH Full Field – error detected
already flag.R0
FF_EDH_IN 5 EDH Full Field – error detected here
flag.R0
AP_UES_IN 4 EDH Active Picture – unknown
error status flag.R0
AP_IDA_IN 3 EDH Active Picture – internal error
detected already flag.R0
AP_IDH_IN 2 EDH Active Picture – internal error
detected here flag.R0
AP_EDA_IN 1 EDH Active Picture – error detected
already flag.R0
AP_EDH_IN 0 EDH Active Picture – error detected
here flag.R0
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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005h EDH_FLAG_OUT
RSVD 15 Reserved. R 0
ANC_UES14 Ancillary data – Unknown Error
Status flag.R1
ANC_IDA 13 Ancillary data – Internal error
Detected Already flag.R0
ANC_IDH 12 Ancillary data – Internal error
Detected Here flag.R0
ANC_EDA 11 Ancillary data – Error Detected
Already flag.R0
ANC_EDH 10 Ancillary data – Error Detected
Here flag.R0
FF_UES9EDH Full Field – Unknown Error
Status flag.R1
FF_IDA 8 EDH Full Field – Internal error
Detected Already flag.R0
FF_IDH 7 EDH Full Field – Internal error
Detected Here flag.R0
FF_EDA 6EDH Full Field – Error Detected
Already flag.R0
FF_EDH 5 EDH Full Field – Error Detected
Here flag.R0
AP_UES4EDH Active Picture – Unknown
Error Status flag.R1
AP_IDA 3 EDH Active Picture – Internal error
Detected Already flag.R0
AP_IDH 2 EDH Active Picture – Internal error
Detected Here flag.R0
AP_EDA 1 EDH Active Picture – Error Detected
Already flag.R0
AP_EDH 0 EDH Active Picture – Error Detected
Here flag.R0
006h7_DS1
FF_CRC_V 15 EDH Full Field CRC Validity bit. R 0
AP_CRC_V 14 EDH Active Picture CRC Validity bit. R 0
VD_STD_DS1 13-8 Detected Video Standard for HD
and SD inputs. R29
CDATA_FORMAT_DS17-4
Data format as indicated in
Chroma channel for HD and SD
inputs.
R15
YDATA_FORMAT_DS13-0
Data format as indicated in Luma
channel for HD and SD inputs. R15
007h RSVD RSVD 15-0 Reserved. R N/A
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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008h IO_CONFIG
RSVD 15 Reserved.RW 0
STAT2_CONFIG14-10
Configure STAT2 output pin:
00000: H Blanking when TIM_861 =
0; HSYNC when TIM_861 = 1
00001: V Blanking when TIM_861 =
0; VSYNC when TIM_861 = 1
00010: F bit when TIM_861 = 0;
Data Enable (DE) when TIM_861 =
1
00011: LOCKED
00100: Y/1ANC: ANC indication
(SD), Luma ANC indication (HD)
00101: C/2ANC: Chroma ANC
indication (HD)
00110: Data Error
00111: Video Error
01000: Audio Error
01001: EDH Detected
01010: Carrier Detect
01011: RATE_DET
01100 - 11111: Reserved
RW 2
STAT1_CONFIG9-5 Configure STAT1 output pin. (Refer
to above for decoding)RW 1
STAT0_CONFIG4-0 Configure STAT0 output pin. (Refer
to above for decoding)RW 0
009h IO_CONFIG2
RSVD 15 Reserved.RW 0
STAT5_CONFIG14-10 Configure STAT5 output pin. (Refer
to above for decoding)RW 6
STAT4_CONFIG9-5 Configure STAT4 output pin. (Refer
to above for decoding)RW 4
STAT3_CONFIG4-0 Configure STAT3 output pin. (Refer
to above for decoding)RW 3
00Ah ANC_CONTROL
RSVD 15-4 Reserved.RW 0
ANC_DATA_SWITCH3Switches between FIFO memories. RW 0
ANC_DATA_DEL 2
Remove Ancillary Data from
output video stream, set to Luma
and Chroma blanking values.
RW 0
HD_ANC_Y1_C21
Extract Ancillary data from Luma
and Chroma channels (HD inputs). RW 0
HD_ANC_C20
Extract Ancillary data only from
Chroma channel (HD inputs). RW 0
00Bh ANC_LINE_A
RSVD 15-11 Reserved.R/W 0
ANC_LINE_A 10-0 Video Line to extract Ancillary data
from. R/W 0
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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00ChANC_LINE_B
RSVD 15-11 Reserved.R/W 0
ANC_LINE_B 10-0 Second video Line to extract
Ancillary data from. R/W 0
00Dh -
00Eh RSVD RSVD 15-0 Reserved. R 0
00Fh ANC_TYPE_1_AP
1ANC_TYPE1_DS1 15-0
Programmable DID/SDID pair #1 to
extract from HD and SD input
formats ([15:8] = DID, [7:0] =SDID).
R/W 0
010h ANC_TYPE_2_AP
1ANC_TYPE2_DS1 15-0
Programmable DID/SDID pair #2 to
extract from HD and SD input
formats ([15:8] = DID, [7:0] =SDID).
R/W 0
011h ANC_TYPE_3
_AP1 ANC_TYPE3_DS1 15-0
Programmable DID/SDID pair #3 to
extract from HD and SD input
formats ([15:8] = DID, [7:0] =SDID).
R/W 0
012h ANC_TYPE_4
_AP1 ANC_TYPE4_DS1 15-0
Programmable DID/SDID pair #4 to
extract from HD and SD input
formats ([15:8] = DID, [7:0] =SDID).
R/W 0
013h ANC_TYPE_5
_AP1 ANC_TYPE5_DS1 15-0
Programmable DID/SDID pair #5 to
extract from HD and SD input
formats ([15:8] = DID, [7:0] =SDID).
R/W 0
014h -
018h RSVD RSVD 15-0 Reserved.R/W N/A
019h VIDEO_FORMAT
_352_A_1
VIDEO_FORMAT_2_DS1 15-8 SMPTE ST 352 embedded packet –
byte 2. R0
VIDEO_FORMAT_1_DS17-0
SMPTE ST 352 embedded packet –
byte 1: [7]: Version identifier [6:0]:
Video Payload Identifier.
R0
01Ah VIDEO_FORMAT
_352_B_1
VIDEO_FORMAT_4_DS1 15-8 SMPTE ST 352 embedded packet –
byte 4. R0
VIDEO_FORMAT_3_DS17-0
SMPTE ST 352 embedded packet –
byte 3. R0
01Bh -
01Eh RSVD RSVD 15-0 Reserved.R/W N/A
01Fh RASTER_STRUC_
1
RSVD 15-14 Reserved. R 0
WORDS_PER_ACTLINE 13-0 Words Per Active Line. R 0
020h RASTER_STRUC_
2
RSVD 15-14 Reserved. R 0
WORDS_PER_LINE 13-0 Total Words Per Line. R 0
021h RASTER_STRUC_
3
RSVD 15-11 Reserved. R 0
LINES_PER_FRAME 10-0 Total Lines Per Frame. R 0
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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022h RASTER_STRUC_
4
RATE_SEL_READBACK 15-14
Read back detected data rate:
0 = HD,
1,3=SD,
2=Reserved
R0
M13
Specifies detected M value
0: 1.000
1: 1.001
R0
Note: In certain systems, due to greater ppm offsets in the crystal, the ‘M’ bit may not assert
properly. In such cases, bits 3:0 in Register 06Fh can be increased to a maximum value of 4.
STD_LOCK12Video standard lock. R 0
INT_PROG11 Interlaced or progressive. R 0
ACTLINE_PER_FIELD 10-0 Active lines per frame. R 0
023h FLYWHEEL
_STATUS
RSVD 15-2 Reserved. R 0
V_LOCK_DS11
Indicates that the timing signal
generator is locked to vertical
timing (HD and SD inputs).
R0
H_LOCK_DS10
Indicates that the timing signal
generator is locked to horizontal
timing (HD and SD inputs).
R0
024h RATE_SEL
RSVD 15-3 Reserved. R 0
AUTO/MAN 2Detect data rate automatically (1)
or program manually (0). R/W 1
RATE_SEL_TOP 1-0
Programmable rate select in
manual mode:
0 = HD,
1,3=SD,
2=Reserved
R/W 0
025h TIM_861_
FORMAT
RSVD 15-7 Reserved. R 0
FORMAT_ERR 6Indicates standard is not
recognized for CEA 861 conversion. R1
FORMAT_ID_8615-0
CEA-861 format ID of input video
stream. Refer to Table 4-9.R0
026hTIM_861_CFG
RSVD 15-3 Reserved. R 0
VSYNC_INVERT 2 Invert output VSYNC pulse. R/W 0
HSYNC_INVERT 1 Invert output HSYNC pulse. R/W 0
TRS_8610
Sets the timing reference outputs
to DFP timing mode when set to
'1'. By default, the timing
reference outputs follow CEA-861
timing mode. Only valid when
TIM_861 is set to '1'.
R/W 0
027h -
036hRSVD RSVD −Reserved. R 0
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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037h ERROR_MASK_1
RSVD 15-11 Reserved. R 0
ERROR_MASK_1 10-0
Error mask for global error vector
(HD, SD):
bit[0]: EAV_ERR_DS1 mask
bit[1]: SAV_ERR_DS1 mask
bit[2]: LNUM_ERR_DS1 mask
bit[3]: YCRC_ERR_DS1 mask
bit[4]: CCRC_ERR_DS1 mask
bit[5]: YCS_ERR_DS1 mask
bit[6]: CCS_ERR_DS1 mask
bit[7]: Reserved
bit[8]: AP_CRC_ERR mask
bit[9]: FF_CRC_ERR mask
bit[10]: VD_STD_ERR_DS1 mask
R/W 0
038h ERROR_MASK_2 RSVD 15-0 Reserved. R 0
039h ACGEN_CTRL
RSVD 15-5 Reserved. R 0
SCLK_INV 4 Invert polarity of output serial
audio clock. R/W 0
AMCLK_INV 3 Invert polarity of output audio
master clock. R/W 0
RSVD 2Reserved.R/W 0
AMCLK_SEL 1-0
Audio Master Clock Select.
0: 128 fs
1: 256 fs
2: 512 fs
R/W 0
03Ah
-6Bh RSVD RSVD 15-0 Reserved. R 0
06ChCLK_GEN
RSVD 15-5 Reserved.R/W 0
DEL_LINE_OFFSET 4-0 Controls the offset for the delay
line. R/W 0
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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06Dh IO_DRIVE
_STRENGTH
RSVD 15-6Reserved.R/W 0
IO_DS_CTRL_DOUT_MSB5-4
Drive strength adjustment for
DOUT[19:10] outputs and PCLK
output:
00: 4mA;
01: 8mA;
10: 10mA(1.8V), 12mA(3.3V);
11: 12mA(1.8V), 16mA(3.3V)
R/W 2
IO_DS_CTRL_STAT 3-2
Drive strength adjustment for
STAT[5:0] outputs:
00: 4mA;
01: 6mA;
10: 8mA(1.8V), 10mA(3.3V);
11: 10mA(1.8V), 12mA(3.3V)
R/W 2
IO_DS_CTRL_DOUT_LSB1-0
Drive strength adjustment for
DOUT[9:0] outputs:
00: 4mA;
01: 6mA;
10: 8mA(1.8V), 10mA(3.3V);
11: 10mA(1.8V), 12mA(3.3V)
R/W 3
06Eh
- 072h RSVD RSVD −Reserved.R/W 0
073h EQ_BYPASS
RSVD 15-10 Reserved.R/W 0
EQ_BYPASS 90: non-bypass EQ
1: bypass EQ R/W 0
RSVD 8-0 Reserved.R/W 0
074h
-084h RSVD RSVD 15-0 Reserved.R/W 0
085h
RSVD RSVD 15-11 Reserved.R/W 0
LOCK_NOISE
_IMM_INCRLOCK_NOISE_IMM_INCR10
Enables extra noise-immunity on
SMPTE detected lock when HIGH
by forcing detection of three TRS
words with the last two TRS words
having the same alignment before
locking to SMPTE. Enable this only
for AUTO/MAN = HIGH.
RW 0
RSVD RSVD 9-0 Reserved.R/W 0
Table 4-28: Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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Final Data Sheet Rev. 2
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4.20.2 SD Audio Core Registers
Note: The GS1671A only accepts write/read commands to/from the SD Audio Register
Map when the audio core is locked to the incoming SD video format.
Table 4-29: SD Audio Core Configuration and Status Registers
Address Register Name Bit Name Bit Description R/W Default
400h CFG_AUD
RSVD 15-14 Reserved.R/W 0
ALL_DEL 13
Selects deletion of all audio data
and all audio control packets.
0: Do not delete existing audio
packets
1: Delete existing audio packets
R/W 0
MUTE_ALL 12
Mute all output channels.
0: Normal
1: Muted
R/W 0
ACS_USE_SECOND 11 Extract Audio Channel Status from
second channel pair. R/W 0
CLEAR_AUDIO 10 Clears all audio FIFO buffers and
puts them in start-up state. R/W 0
OS_SEL 9-8
Specifies the audio FIFO buffer
size.
00: 36 samples deep, 26 sample
start-up count
01: 22 samples deep, 12 sample
start-up count
10: 16 samples deep, 6 sample
start-up count
11: Reserved
Note: The default 36-sample deep
FIFO size is not supported if each
audio channel must have the same
sample delay.
R/W 0
LSB_FIRSTD 7
Causes the channel 7 and 8 output
format to use LSB first.
0: MSB first
1: LSB first
R/W 0
LSB_FIRSTC6
Causes the channel 5 and 6 output
format to use LSB first.
0: MSB first
1: LSB first
R/W 0
LSB_FIRSTB 5
Causes the channel 3 and 4 output
format to use LSB first.
0: MSB first
1: LSB first
R/W 0
LSB_FIRSTA 4
Causes the channel 1 and 2 output
format to use LSB first.
0: MSB first
1: LSB first
R/W 0
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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400h CFG_AUD
IDB 3-2
Specifies the Secondary audio
group to extract.
00: Audio group #1
01: Audio group #2
10: Audio group #3
11: Audio group #4
Note 1: Should IDA and IDB be set
to the same value, they
automatically revert to their
default values.
Note 2: The Mute function will
remove invalid data.
R/W 1
IDA 1-0
Specifies the Primary audio group
to extract.
00: Audio group #1
01: Audio group #2
10: Audio group #3
11: Audio group #4
Note 1: Should IDA and IDB be set
to the same value, they
automatically revert to their
default values.
Note 2: The Mute function will
remove invalid data.
R/W 0
401h DBN_ERR
EXT_DET3_4B 15
Set when Secondary group
channels 3 and 4 have extended
data. Write ‘1’ to clear.
ROCW0
EXT_DET1_2B 14
Set when Secondary group
channels 1 and 2 have extended
data. Write ‘1’ to clear.
ROCW0
EXT_DET3_4A 13
Set when Primary group channels 3
and 4 have extended data. Write
‘1’ to clear.
ROCW0
EXT_DET1_2A 12
Set when Primary group channels 1
and 2 have extended data. Write
‘1’ to clear.
ROCW0
CTL_DBNB_ERR 11
Set when Secondary group control
packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
ROCW0
CTL_DBNA_ERR 10
Set when Primary group control
packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
ROCW0
EXT_DBNB_ERR 9
Set when Secondary group
extended data packet Data Block
Number sequence is discontinuous.
Write ‘1’ to clear.
ROCW0
EXT_DBNA_ERR 8
Set when Primary group extended
data packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
ROCW0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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401h DBN_ERR
SAMP_DBNB_ERR 7
Set when Secondary group data
packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
ROCW0
SAMP_DBNA_ERR 6
Set when Primary group data
packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
ROCW0
CTRB_DET 5
Set when Secondary group audio
control packet is detected. Write
‘1’ to clear.
ROCW0
CTRA_DET 4
Set when Primary group audio
control packet is detected. Write
‘1’ to clear.
ROCW0
ACS_DET3_4B 3
Secondary group audio status
detected for channels 3 and 4.
Write ‘1’ to clear.
ROCW0
ACS_DET1_2B 2
Secondary group audio status
detected for channels 1 and 2.
Write ‘1’ to clear.
ROCW0
ACS_DET3_4A 1
Primary group audio status
detected for channels 3 and 4.
Write ‘1’ to clear.
ROCW0
ACS_DET1_2A 0
Primary group audio status
detected for channels 1 and 2.
Write ‘1’ to clear.
ROCW0
402h REGEN
RSVD 15-2 Reserved.R/W 0
ACS_APPLY 1
Cause channel status data in
ACSR[183:0] to be transferred to
the channel status replacement
mechanism. The transfer does not
occur until the next status
boundary.
R/W 0
ACS_REGEN 0
Specifies that Audio Channel
Status of all channels should be
replaced with ACSR[183:0] field.
0: Do not replace Channel Status
1: Replace Channel Status of all
channels
R/W 0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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403h AUD_DET
IDB_READBACK 15-14 Actual value of IDB in the
hardware. R1
IDA_READBACK 13-12 Actual value of IDA in the
hardware. R0
XDPG4_DET 11
Set while embedded Group 4
audio extended packets are
detected.
R0
XDPG3_DET 10
Set while embedded Group 3
audio extended packets are
detected.
R0
XDPG2_DET 9
Set while embedded Group 2
audio extended packets are
detected.
R0
XDPG1_DET 8
Set while embedded Group 1
audio extended packets are
detected.
R0
ADPG4_DET 7 Set while Group 4 audio data
packets are detected.R0
ADPG3_DET 6Set while Group 3 audio data
packets are detected.R0
ADPG2_DET 5 Set while Group 2 audio data
packets are detected.R0
ADPG1_DET 4 Set while Group 1 audio data
packets are detected.R0
ACS_APPLY_WAITD 3
Set while output channels 7 and 8
are waiting for a status boundary
to apply the ACSR[183:0] data.
R0
ACS_APPLY_WAITC2
Set while output channels 5 and 6
are waiting for a status boundary
to apply the ACSR[183:0] data.
R0
ACS_APPLY_WAITB 1
Set while output channels 3 and 4
are waiting for a status boundary
to apply the ACSR[183:0] data.
R0
ACS_APPLY_WAITA 0
Set while output channels 1 and 2
are waiting for a status boundary
to apply the ACSR[183:0] data.
R0
404h CSUM_ERR_DET
RSVD 15-1 Reserved.R/W 0
CSUM_ERROR 0 Embedded packet checksum error
detected. Write ‘1’ to clear. ROCW0
405h CH_MUTE
RSVD 15-8 Reserved.R/W 0
MUTE 7-0
Mute output channels 8..91 Where
bits 7:0 = channel 8:1
1: Mute
0: Normal
R/W 0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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406hCH_VALID
RSVD 15-8 Reserved.R/W 0
CH4_VALIDB 7 Secondary group channel 4 sample
validity flag.R0
CH3_VALIDB 6Secondary group channel 3 sample
validity flag.R0
CH2_VALIDB 5 Secondary group channel 2 sample
validity flag.R0
CH1_VALIDB 4 Secondary group channel 1 sample
validity flag.R0
CH4_VALIDA 3 Primary group channel 4 sample
validity flag.R0
CH3_VALIDA 2 Primary group channel 3 sample
validity flag.R0
CH2_VALIDA 1 Primary group channel 2 sample
validity flag.R0
CH1_VALIDA 0 Primary group channel 1 sample
validity flag.R0
407h SD_AUDIO_ERR
OR_MASK
RSVD 15 Reserved.R/W 0
EN_NOT_LOCKED 14 Asserts
interrupt
when LOCKED
signal is not asserted.R/W 0
EN_NO_VIDEO 13 Asserts
interrupt
when video
format is unknown. R/W 0
EN_CSUM_ERROR 12 Asserts
interrupt
when checksum
error is detected.R/W 0
EN_ACS_DET3_4B 11 Asserts
interrupt
when
EN_ACS_DET3_4B flag is set. R/W 0
EN_ACS_DET1_2B 10 Asserts
interrupt
when
EN_ACS_DET1_2B flag is set. R/W 0
EN_ACS_DET3_4A 9 Asserts
interrupt
when
EN_ACS_DET3_4A flag is set. R/W 0
EN_ACS_DET1_2A 8 Asserts
interrupt
when
EN_ACS_DET1_2A flag is set. R/W 0
EN_CTRB_DET 7 Asserts
interrupt
when
EN_CTRB_DET flag is set. R/W 0
EN_CTRA_DET 6Asserts
interrupt
when
EN_CTRA_DET flag is set. R/W 0
EN_DBNB_ERR 5 Asserts
interrupt
when
EN_DBNB_ERR flag is set. R/W 0
EN_DBNA_ERR 4 Asserts
interrupt
when
EN_DBNA_ERR flag is set. R/W 0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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407h SD_AUDIO_ERR
OR_MASK
EN_ADPG4_DET 3 Asserts
interrupt
when the
ADPG4_DET flag is set. R/W 0
EN_ADPG3_DET 2 Asserts
interrupt
when the
ADPG3_DET flag is set. R/W 0
EN_ADPG2_DET 1 Asserts
interrupt
when the
ADPG2_DET flag is set. R/W 0
EN_ADPG1_DET 0 Asserts
interrupt
when the
ADPG1_DET flag is set. R/W 0
408h CFG_OUTPUT
ASWLD 15-14
Output channels 7 and 8 word
length.
00: 24 bits
01: 20 bits
10: 16 bits
11: Automatic 20-bit or 24-bit
R/W 3
ASWLC13-12 Output channels 5 and 6 word
length. (See above for decoding)R/W 3
ASWLB 11-10 Output channels 3 and 4 word
length. (See above for decoding)R/W 3
ASWLA 9-8 Output channels 1 and 2 word
length. (See above for decoding)R/W 3
AMD 7-6
Output channels 7 and 8 format
selector.
00: AES/EBU audio output
01: Serial audio output: Left
justified; MSB first
10: Serial audio output: Right
justified; MSB first
11: I2S serial audio output
R/W 3
AMC5-4 Output channels 5 and 6 format
selector. (See above for decoding). R/W 3
AMB 3-2 Output channels 3 and 4 format
selector. (See above for decoding). R/W 3
AMA 1-0 Output channels 1 and 2 format
selector. (See above for decoding). R/W 3
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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409h OUTPUT_SEL_1
RSVD 15-12 Reserved.R/W 0
OP4_SRC11-9
Output channel 4 source selector.
000: Primary audio group channel
1
001: Primary audio group channel
2
010: Primary audio group channel
3
011: Primary audio group channel
4
100: Secondary audio group
channel 1
101: Secondary audio group
channel 2
110: Secondary audio group
channel 3
111: Secondary audio group
channel 4
R/W 3
OP3_SRC8-6Output channel 3 source selector
(Decode as above). R/W 2
OP2_SRC5-3 Output channel 2 source selector
(Decode as above). R/W 1
OP1_SRC2-0 Output channel 1 source selector
(Decode as above). R/W 0
40Ah OUTPUT_SEL_2
RSVD 15-12 Reserved.R/W 0
OP8_SRC11-9
Output channel 8 source selector.
000: Primary audio group channel
1
001: Primary audio group channel
2
010: Primary audio group channel
3
011: Primary audio group channel
4
100: Secondary audio group
channel 1
101: Secondary audio group
channel 2
110: Secondary audio group
channel 3
111: Secondary audio group
channel 4
R/W 7
OP7_SRC8-6Output channel 7 source selector
(Decode as above). R/W 6
OP6_SRC5-3 Output channel 6 source selector
(Decode as above). R/W 5
OP5_SRC2-0 Output channel 5 source selector
(Decode as above). R/W 4
40Bh -
41Fh RSVD RSVD −Reserved.− −
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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420h AFNA12
RSVD 15-9 Reserved.R/W 0
AFN1_2A 8-0 Primary group audio frame
number for channels 1 and 2. R0
421h AFNA34
RSVD 15-9 Reserved.R/W 0
AFN3_4A 8-0 Primary group audio frame
number for channels 3 and 4. R0
422h RATEA
RSVD 15-8 Reserved.R/W 0
RATE3_4A 7-5 Primary group sampling frequency
for channels 3 and 4 R0
ASX3_4A 4 Primary group asynchronous mode
for channels 3 and 4. R0
RATE1_2A 3-1 Primary group sampling frequency
for channels 1 and 2. R0
ASX1_2A 0 Primary group asynchronous mode
for channels 1 and 2. R0
423h ACT_A
RSVD 15-4 Reserved.R/W 0
ACTA 3-0 Primary group active channels. R 0
424h PRIM_AUD_
DELAY_1
RSVD 15-9 Reserved.R/W 0
DEL1A_1 8-1 Primary Audio group delay data
for channel 1. R0
EBIT1A 0 Primary Audio group delay data
valid flag for channel 1. R0
425h PRIM_AUD_
DELAY_2
RSVD 15-9 Reserved.R/W 0
DEL1A_2 8-0 Primary Audio group delay data
for channel 1. R0
426hPRIM_AUD_
DELAY_3
RSVD 15-9 Reserved.R/W 0
DEL1A_3 8-0 Primary Audio group delay data
for channel 1. R0
427h PRIM_AUD_
DELAY_4
RSVD 15-9 Reserved.R/W 0
DEL2A_4 8-1 Primary Audio group delay data
for channel 2. R0
EBIT2A 0 Primary Audio group delay data
valid flag for channel 2. R0
428h PRIM_AUD_
DELAY_5
RSVD 15-9 Reserved.R/W 0
DEL2A_5 8-0 Primary Audio group delay data
for channel 2. R0
429h PRIM_AUD_
DELAY_6
RSVD 15-9 Reserved.R/W 0
DEL2A_68-0 Primary Audio group delay data
for channel 2. R0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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42Ah PRIM_AUD_
DELAY_7
RSVD 15-9 Reserved.R/W 0
DEL3A_7 8-1 Primary Audio group delay data
for channel 3. R0
EBIT3A 0 Primary Audio group delay data
valid flag for channel 3. R0
42Bh PRIM_AUD_
DELAY_8
RSVD 15-9 Reserved.R/W 0
DEL3A_8 8-0 Primary Audio group delay data
for channel 3. R0
42ChPRIM_AUD_
DELAY_9
RSVD 15-9 Reserved.R/W 0
DEL3A_9 8-0 Primary Audio group delay data
for channel 3. R0
42Dh PRIM_AUD_
DELAY_10
RSVD 15-9 Reserved.R/W 0
DEL4A_10 8-1 Primary Audio group delay data
for channel 4. R0
EBIT4A 0 Primary Audio group delay data
valid flag for channel 4. R0
42Eh PRIM_AUD_
DELAY_11
RSVD 15-9 Reserved.R/W 0
DEL4A_11 8-0 Primary Audio group delay data
for channel 4. R0
42Fh PRIM_AUD_
DELAY_12
RSVD 15-9 Reserved.R/W 0
DEL4A_12 8-0 Primary Audio group delay data
for channel 4. R0
430h AFNB12
RSVD 15-9 Reserved.R/W 0
AFN1_2B 8-0 Secondary group audio frame
number for channels 1 and 2. R0
431h AFNB34
RSVD 15-9 Reserved.R/W 0
AFN3_4B 8-0 Secondary group audio frame
number for channels 3 and 4. R0
432h RATEB
RSVD 15-8 Reserved. R 0
RATE3_4B 7-5 Secondary group sampling
frequency for channels 3 and 4. R0
ASX3_4B 4 Secondary group asynchronous
mode for channels 3 and 4. R0
RATE1_2B 3-1 Secondary group sampling
frequency for channels 1 and 2. R0
ASX1_2B 0 Secondary group asynchronous
mode for channels 1 and 2. R0
433h ACT_B
RSVD 15-4 Reserved.R/W 0
ACTB 3-0 Secondary group active channels. R 0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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434h SEC_AUD_
DELAY_!
RSVD 15-9 Reserved.R/W 0
DEL1B_1 8-1 Secondary Audio group delay data
for channel 1. R0
EBIT1B 0 Secondary Audio group delay data
valid flag for channel 1. R0
435h SEC_AUD
DELAY_2
RSVD 15-9 Reserved.R/W
DEL1B_2 8-0 Secondary Audio group delay data
for channel 1. R0
436hSEC_AUD_
DELAY_3
RSVD 15-9 Reserved.R/W 0
DEL1B_3 8-0 Secondary Audio group delay data
for channel 1. R0
437h SEC_AUD
DELAY_4
RSVD 15-9 Reserved.R/W 0
DEL2B_4 8-1 Secondary Audio group delay data
for channel 2. R0
EBIT2B 0 Secondary Audio group delay data
valid flag for channel 2. R0
438h SEC_AUD
DELAY_5
RSVD 15-9 Reserved.R/W 0
DEL2B_5 8-0 Secondary Audio group delay data
for channel 2. R0
439h SEC_AUD
DELAY_6
RSVD 15-9 Reserved.R/W 0
DEL2B_68-0 Secondary Audio group delay data
for channel 2. R0
43Ah SEC_AUD
DELAY_7
RSVD 15-9 Reserved.R/W 0
DEL3B_7 8-1 Secondary Audio group delay data
for channel 3. R0
EBIT3B 0 Secondary Audio group delay data
valid flag for channel 3. R0
43Bh SEC_AUD
DELAY_8
RSVD 15-9 Reserved.R/W 0
DEL3B_8 8-0 Secondary Audio group delay data
for channel 3. R0
43ChSEC_AUD
DELAY_9
RSVD 15-9 Reserved.R/W 0
DEL3B_9 8-0 Secondary Audio group delay data
for channel 3. R0
43Dh SEC_AUD
DELAY_10
RSVD 15-9 Reserved.R/W 0
DEL4B_10 8-1 Secondary Audio group delay data
for channel 4. R0
EBIT4B 0 Secondary Audio group delay data
valid flag for channel 4. R0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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43Eh SEC_AUD_
DELAY_11
RSVD 15-9 Reserved.R/W 0
DEL4B_11 8-0 Secondary Audio group delay data
for channel 4. R0
43Fh SEC_AUD_
DELAY_12
RSVD 15-9 Reserved.R/W 0
DEL4B_12 8-0 Secondary Audio group delay data
for channel 4. R0
440h ACSR1_2A_BYTE
0_1 ACSR1_2A_0 15-0
Bytes 0 [7:0] and 1 [15:8] of audio
group A channel status for
channels 1 and 2
R0
441h ACSR1_2A_BYTE
2_3 ACSR1_2A_2 15-0
Bytes 2 [7:0] and 3 [15:8] of audio
group A channel status for
channels 1 and 2
R0
442h ACSR1_2A_BYTE
4_5 ACSR1_2A_4 15-0
Bytes 4 [7:0] and 5 [15:8] of audio
group A channel status for
channels 1 and 2
R0
443h ACSR1_2A_BYTE
6_7 ACSR1_2A_615-0
Bytes 6 [7:0] and 7 [15:8] of audio
group A channel status for
channels 1 and 2
R0
444h ACSR1_2A_BYTE
8_9 ACSR1_2A_8 15-0
Bytes 8 [7:0] and 9 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
445H ACSR1_2A_BYTE
10_11 ACSR1_2A_10 15-0
Bytes 10 [7:0] and 11 [15:8] of
audio group A channel status for
channels 1 and 2.
R0
446HACSR1_2A_BYTE
12_13 ACSR1_2A_12 15-0
Bytes 12 [7:0] and 13 [15:8] of
audio group A channel status for
channels 1 and 2.
R0
447h ACSR1_2A_BYTE
14_15 ACSR1_2A_14 15-0
Bytes 14 [7:0] and 15 [15:8] of
audio group A channel status for
channels 1 and 2.
R0
448h ACSR1_2A_BYTE
16_17 ACSR1_2A_1615-0
Bytes 16 [7:0] and 17 [15:8] of
audio group A channel status for
channels 1 and 2.
R0
449h ACSR1_2A_BYTE
18_19 ACSR1_2A_18 15-0
Bytes 18 [7:0] and 19 [15:8] of
audio group A channel status for
channels 1 and 2.
R0
44Ah ACSR1_2A_BYTE
20_21 ACSR1_2A_20 15-0
Bytes 20 [7:0] and 21 [15:8] of
audio group A channel status for
channels 1 and 2.
R0
44Bh ACRS1_2A_
BYTE22
RSVD 15-8 Reserved.R/W 0
ACSR1_2A_22 7-0 Bytes 22 of audio group A channel
status for channels 1 and 2. R0
44Ch -
44Fh RSVD RSVD 15-0 Reserved.R/W 0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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450h ACSR3_4A
BYTE0_1 ACSR3_4A_0 15-0
Bytes 0 [7:0] and 1 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
451h ACSR3_4A
BYTE2_3 ACSR3_4A_2 15-0
Bytes 2 [7:0] and 3 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
452h ACSR3_4A_BYTE
4_5 ACSR3_4A_4 15-0
Bytes 4 [7:0] and 5 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
453h ACSR3_4A_BYTE
6_7 ACSR3_4A_615-0
Bytes 6 [7:0] and 7 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
454h ACSR3_4A_BYTE
8_9 ACSR3_4A_8 15-0
Bytes 8 [7:0] and 9 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
455h ACSR3_4A_BYTE
10_11 ACSR3_4A_10 15-0
Bytes 10 [7:0] and 11 [15:8] of
audio group A channel status for
channels 3 and 4.
R0
456hACSR3_4A_BYTE
12_13 ACSR3_4A_12 15-0
Bytes 12 [7:0] and 13 [15:8] of
audio group A channel status for
channels 3 and 4.
R0
457h ACSR3_4A_BYTE
14_15 ACSR3_4A_14 15-0
Bytes 14 [7:0] and 15 [15:8] of
audio group A channel status for
channels 3 and 4.
R0
458h ACSR3_4A_BYTE
16_17 ACSR3_4A_1615-0
Bytes 16 [7:0] and 17 [15:8] of
audio group A channel status for
channels 3 and 4.
R0
459h ACSR3_4A_BYTE
18_19 ACSR3_4A_18 15-0
Bytes 18 [7:0] and 19 [15:8] of
audio group A channel status for
channels 3 and 4.
R0
45Ah ACSR3_4A_BYTE
20_21 ACSR3_4A_20 15-0
Bytes 20 [7:0] and 21 [15:8] of
audio group A channel status for
channels 3 and 4.
R0
45Bh ACSR3_4A_BYTE
22
RSVD 15-8 Reserved.R/W 0
ACSR3_4A_22 7-0 Bytes 22 of audio group A channel
status for channels 3 and 4. R0
45Ch -
45Fh RSVD RSVD 15-0 Reserved.R/W 0
460h ACSR1_2B_BYTE
0_1 ACSR1_2B_0 15-0
Bytes 0 [7:0] and 1 [15:8] of audio
group B channel status for
channels 1 and 2.
R0
461h ACSR1_2B_BYTE
2_3 ACSR1_2B_2 15-0
Bytes 2 [7:0] and 3 [15:8] of audio
group B channel status for
channels 1 and 2.
R0
462h ACSR1_2B_BYTE
4_5 ACSR1_2B_4 15-0
Bytes 4 [7:0] and 5 [15:8] of audio
group B channel status for
channels 1 and 2.
R0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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463h ACSR1_2B_BYTE
6_7 ACSR1_2B_615-0
Bytes 6 [7:0] and 7 [15:8] of audio
group B channel status for
channels 1 and 2.
R0
464h ACSR1_2B_BYTE
8_9 ACSR1_2B_8 15-0
Bytes 8 [7:0] and 9 [15:8] of audio
group B channel status for
channels 1 and 2.
R0
465h ACSR1_2B_BYTE
10_11 ACSR1_2B_10 15-0
Bytes 10 [7:0] and 11 [15:8] of
audio group B channel status for
channels 1 and 2.
R0
466hACSR1_2B_BYTE
12_13 ACSR1_2B_12 15-0
Bytes 12 [7:0] and 13 [15:8] of
audio group B channel status for
channels 1 and 2.
R0
467h ACSR1_2B_BYTE
14_15 ACSR1_2B_14 15-0
Bytes 14 [7:0] and 15 [15:8] of
audio group B channel status for
channels 1 and 2.
R0
468h ACSR1_2B_BYTE
16_17 ACSR1_2B_1615-0
Bytes 16 [7:0] and 17 [15:8] of
audio group B channel status for
channels 1 and 2.
R0
469h ACSR1_2B_BYTE
18_19 ACSR1_2B_18 15-0
Bytes 18 [7:0] and 19 [15:8] of
audio group B channel status for
channels 1 and 2.
R0
46Ah ACSR1_2B_BYTE
20_21 ACSR1_2B_20 15-0
Bytes 20 [7:0] and 21 [15:8] of
audio group B channel status for
channels 1 and 2.
R0
46Bh ACSR1_2B_BYTE
22
RSVD 15-8 Reserved.R/W 0
ACSR1_2B_22 7-0 Bytes 22 of audio group B channel
status for channels 1 and 2. R0
46Ch -
46Fh RSVD RSVD 15-0 Reserved.R/W 0
470h ACSR3_4B_BYTE
0_1 ACSR3_4B_0 15-0
Bytes 0 [7:0] and 1 [15:8] of audio
group B channel status for
channels 3 and 4.
R0
471h ACSR3_4B_BYTE
2_3 ACSR3_4B_2 15-0
Bytes 2 [7:0] and 3 [15:8] of audio
group B channel status for
channels 3 and 4.
R0
472h ACSR3_4B_BYTE
4_5 ACSR3_4B_4 15-0
Bytes 4 [7:0] and 5 [15:8] of audio
group B channel status for
channels 3 and 4.
R0
473h ACSR3_4B_BYTE
6_7 ACSR3_4B_615-0
Bytes 6 [7:0] and 7 [15:8] of audio
group B channel status for
channels 3 and 4.
R0
474h ACSR3_4B_BYTE
8_9 ACSR3_4B_8 15-0
Bytes 8 [7:0] and 9 [15:8] of audio
group B channel status for
channels 3 and 4.
R 0
475h ACSR3_4B_BYTE
10_11 ACSR3_4B_10 15-0
Bytes 10 [7:0] and 11 [15:8] of
audio group B channel status for
channels 3 and 4.
R0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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476hACSR3_4B_BYTE
12_13 ACSR3_4B_12 15-0
Bytes 12 [7:0] and 13 [15:8] of
audio group B channel status for
channels 3 and 4.
R0
477h ACSR3_4B_BYTE
14_15 ACSR3_4B_14 15-0
Bytes 14 [7:0] and 15 [15:8] of
audio group B channel status for
channels 3 and 4.
R0
478h ACSR3_4A_BYTE
16_17 ACSR3_4B_1615-0
Bytes 16 [7:0] and 17 [15:8] of
audio group B channel status for
channels 3 and 4.
R0
479h ACSR3_4A_BYTE
18_19 ACSR3_4B_18 15-0
Bytes 18 [7:0] and 19 [15:8] of
audio group B channel status for
channels 3 and 4.
R0
47Ah ACSR3_4A_BYTE
20_21 ACSR3_4B_20 15-0
Bytes 20 [7:0] and 21 [15:8] of
audio group B channel status for
channels 3 and 4.
R0
47Bh ACSR3_4A_BYTE
22
RSVD 15-8 Reserved.R/W 0
ACSR3_4B_22 7-0 Bytes 22 of audio group B channel
status for channels 3 and 4. R0
47Ch -
47Fh RSVD RSVD 15-0 Reserved.R/W 0
480h ACSR_BYTE_0 ACSR_BYTE0 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register for 23 registers.
R0
481h ACSR_BYTE_1 ACSR_BYTE1 7-0 −W0
482h ACSR_BYTE_2 ACSR_BYTE2 7-0 −W0
483h ACSR_BYTE_3 ACSR_BYTE3 7-0 −W0
484h ACSR_BYTE_4 ACSR_BYTE4 7-0 −W0
485h ACSR_BYTE_5 ACSR_BYTE5 7-0 −W0
486hACSR_BYTE_6ACSR_BYTE67-0 −W0
487h ACSR_BYTE_7 ACSR_BYTE7 7-0 −W0
488h ACSR_BYTE_8 ACSR_BYTE8 7-0 −W0
489h ACSR_BYTE_9 ACSR_BYTE9 7-0 −W0
48Ah ACSR_BYTE_10 ACSR_BYTE10 7-0 −W0
48Bh ACSR_BYTE_11 ACSR_BYTE11 7-0 −W0
48ChACSR_BYTE_12 ACSR_BYTE12 7-0 −W0
48Dh ACSR_BYTE_13 ACSR_BYTE13 7-0 −W0
48Eh ACSR_BYTE_14 ACSR_BYTE14 7-0 −W0
48Fh ACSR_BYTE_15 ACSR_BYTE15 7-0 −W0
490h ACSR_BYTE_16ACSR_BYTE167-0 −W0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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491h ACSR_BYTE_17 ACSR_BYTE17 7-0 −W0
492h ACSR_BYTE_18 ACSR_BYTE18 7-0 −W0
493h ACSR_BYTE_19 ACSR_BYTE19 7-0 −W0
494h ACSR_BYTE_20 ACSR_BYTE20 7-0 −R/W 0
495h ACSR_BYTE_21 ACSR_BYTE21 7-0 −R/W 0
496hACSR_BYTE_22 ACSR_BYTE22 7-0 −R/W 0
Table 4-29: SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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4.20.3 HD Audio Core Registers
Note: The GS1671A only accepts write/read commands to/from the HD Audio Register
Map when the audio core is locked to the incoming HD video format.
Table 4-30: HD Audio Core Configuration and Status Registers
Address Register Name Bit Name Bit Description R/W Default
200h CFG_AUD
ECC_OFF 15 Disables ECC error correction. R/W 0
ALL_DEL 14
Selects deletion of all audio data
and all audio control packets
0: Do not delete existing audio
control packets
1: Delete existing audio control
packets.
R/W 0
MUTE_ALL 13
Mute all output channels
0: Normal
1: Muted
R/W 0
ACS_USE_SECOND 12 Extract Audio Channel Status from
second channel pair. R/W 0
ASWLB 11-10
Secondary group output word
length.
00: 24 bits
01: 20 bits
10: 16 bits
11: invalid
R/W 3
ASWLA 9-8
Primary group output word length.
00: 24 bits
01: 20 bits
10: 16 bits
11: invalid
R/W 3
AMB 7-6
Secondary group output format
selector.
00: AES/EBU audio output
01: Serial audio output: left
justified MSB first
10: Serial audio output: right
justified. MSB first
11: I2S serial audio output
R/W 3
AMA 5-4
Primary group output format
selector.
00: AES/EBU audio output
01: Serial audio output: left
justified MSB first
10: Serial audio output: right
justified MSB first
11: I2S serial audio output
R/W 3
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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200h CFG_AUD
IDB 3-2
Specifies the Secondary audio
group to extract.
00: Audio group #1
01: Audio group #2
10: Audio group #3
11: Audio group #4
Note: Should IDA and IDB be set to
the same value, they automatically
revert to their default values.
R/W 1
IDA 1-0
Specifies the Primary audio group
to extract.
00: Audio group #1
01: Audio group #2
10: Audio group #3
11: Audio group #4
Note: Should IDA and IDB be set to
the same value, they automatically
revert to their default values.
R/W 0
201h ACS_DET
RSVD 15-8 Reserved.R/W 0
DBNB_ERR 7
Set when Secondary group audio
Data Block Number sequence is
discontinuous.
ROCW0
DBNA_ERR 6
Set when Primary group audio
Data Block Number sequence is
discontinuous.
ROCW0
CTRB_DET 5 Set when Secondary group audio
control packet is detected.ROCW0
CTRA_DET 4 Set when Primary group audio
control packet is detected.ROCW0
ACS_DET3_4B 3 Secondary group audio status
detected for channels 3 and 4. ROCW0
ACS_DET1_2B 2 Secondary group audio status
detected for channels 1 and 2. ROCW0
ACS_DET3_4A 1 Primary group audio status
detected for channels 3 and 4. ROCW0
ACS_DET1_2A 0 Primary group audio status
detected for channels 1 and 2. ROCW0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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202h AUD_DET1
RSVD 15-9 Reserved. R 0
IDB_READBACK8-7
Actual value of IDB in the
hardware. R1
IDA_READBACK6-5 Actual value of IDA in the
hardware. R0
ADPG4_DET 4 Set while Group 4 audio data
packets are detected.R0
ADPG3_DET 3 Set while Group 3 audio data
packets are detected.R0
ADPG2_DET 2 Set while Group 2 audio data
packets are detected.R0
ADPG1_DET 1 Set while Group 1 audio data
packets are detected.R0
ACS_APPLY_WAIT 0
ACS_APPLY_WAIT: Set while output
channels 1 and 2 are waiting for a
status boundary to apply the
ACSR[183:0] data.
R0
203h AUD_DET2
RSVD 15-2 Reserved.R/W 0
ECCA_ERROR 1 Primary group audio data packet
error detected. ROCW0
ECCB_ERROR 0 Secondary group audio data packet
error detected.ROCW0
204h REGEN
RSVD 15-2 Reserved.R/W 0
ACS_APPLY 1
Cause channel status data in
ACSR[183:0] to be transferred to
the channel status replacement
mechanism. The transfer does not
occur until the next status
boundary.
R/W 0
ACS_REGEN 0
Specifies that Audio Channel Status
of all channels should be replaced
with ACSR[183:0] field.
0: Do not replace Channel Status
1: Replace Channel Status of all
channels
R/W 0
205h CH_MUTE
RSVD 15 Reserved.R/W 0
MUTEB 7-4
Mute Secondary output channels
4..1 Where bits 7:4 = channel 4:1
1: Mute
0: Normal
R/W 0
MUTEA 3-0
Mute Primary output channels 4..1
Where bits 3:0 = channel 4:1
1: Mute
0: Normal
R/W 0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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206hCH_VALID
RSVD 15-8 Reserved.R/W 0
CH4_VALIDB 7 Secondary group channel 4 sample
validity flag.R0
CH3_VALIDB 6Secondary group channel 3 sample
validity flag.R0
CH2_VALIDB 5 Secondary group channel 2 sample
validity flag.R0
CH1_VALIDB 4 Secondary group channel 1 sample
validity flag.R0
CH4_VALIDA 3 Primary group channel 4 sample
validity flag.R0
CH3_VALIDA 2 Primary group channel 3 sample
validity flag.R0
CH2_VALIDA 1 Primary group channel 2 sample
validity flag.R0
CH1_VALIDA 0 Primary group channel 1 sample
validity flag.R0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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207h HD_AUDIO_ERR
OR_MASK
RSVD 15 Reserved.R/W 0
EN_MISSING_PHASE14
Asserts AUDIO_ERROR when
chosen group's phase data is
missing
R/W 0
EN_ACS_DET3_4B 13 Asserts AUDIO_ERROR when
ACS_DET3_4B flag is set. R/W 0
EN_ACS_DET1_2B 12 Asserts AUDIO_ERROR when
ACS_DET1_2B flag is set. R/W 0
EN_ACS_DET3_4A 11 Asserts AUDIO_ERROR when
ACS_DET3_4A flag is set. R/W 0
EN_ACS_DET1_2A 10 Asserts AUDIO_ERROR when
ACS_DET1_2A flag is set. R/W 0
EN_CTRB_DET 9 Asserts AUDIO_ERROR when
CTRB_DET flag is set. R/W 0
EN_CTRA_DET 8 Asserts AUDIO_ERROR when
CTRA_DET flag is set. R/W 0
EN_DBNB_ERR 7 Asserts AUDIO_ERROR when
DBNB_ERR flag is set. R/W 0
EN_DBNA_ERR 6Asserts AUDIO_ERROR when
DBNA_ERR flag is set. R/W 0
EN_ECCB_ERR 5 Asserts AUDIO_ERROR when
ECCB_ERR flag is set. R/W 0
EN_ECCA_ERR 4 Asserts AUDIO_ERROR when
ECCA_ERR flag is set. R/W 0
EN_ADPG4_DET 3 Asserts AUDIO_ERROR when
ADPG4_DET flag is set. R/W 0
EN_ADPG3_DET 2 Asserts AUDIO_ERROR when
ADPG3_DET flag is set. R/W 0
EN_ADPG2_DET 1 Asserts AUDIO_ERROR when
ADPG2_DET flag is set. R/W 0
EN_ADPG1_DET 0 Asserts AUDIO_ERROR when
ADPG1_DET flag is set. R/W 0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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208h CFG_AUD_2
RSVD 15-11 Reserved.R/W 0
SEL_PHASE_SRC10 Selects between the Primary and
Secondary embedded phase info. R/W 0
LSB_FIRSTB 9 Causes the Secondary group serial
output formats to use LSB first. R/W 0
LSB_FIRSTA 8 Causes the Primary group serial
output formats to use LSB first. R/W 0
FORCE_M 7
Disables M value detection and
forces M value to that specified by
FORCE_MEQ1001.
R/W 0
FORCE_MEQ1001 6
Specifies M value when FORCE_M is
set.
1: M= 1.001
0: M = 1.000
R/W 0
IGNORE_PHASE5
Causes the Demultiplexer to ignore
the embedded clock info in both
the Primary and Secondary group
audio data packets. Clock is
generated based on the video
format and M value.
R/W 0
FORCE_ACLK128 4
Causes the core to ignore
embedded clock info and derive
phase information from ACLK128.
R/W 0
EN_NOT_LOCKED 3 Asserts AUDIO_ERRORwhen locked
is not asserted.R/W 0
EN_NO_VIDEO 2 Asserts AUDIO_ERROR when the
video format is unknown. R/W 0
EN_NO_PHASEB 1 Asserts AUDIO_ERROR when
NO_PHASEB_DATA is set. R/W 0
EN_NO_PHASEA 0 Asserts AUDIO_ERROR when
NO_PHASEA_DATA is set. R/W 0
Note: With these bits enabled, a change status will cause AUDIO_ERROR to assert, DATA_ERROR will assert each time AUDIO_ERROR
is asserted.
209h CFG_AUD_3
RSVD 15-3 Reserved.R/W 0
MISSING_PHASE2
Embedded phase info for chosen
group missing or incorrect. R0
NO_PHASEB_DATA 1 Secondary group has invalid
embedded clock information. R0
NO_PHASEA_DATA 0 Primary group has invalid
embedded clock information. R0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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20Ah OUTPUT_SEL_1
RSVD 15-12 Reserved. R 0
OP4_SRC11-9
Output channel 4 source selector.
000: Primary audio group channel 1
001: Primary audio group channel 2
010: Primary audio group channel 3
011: Primary audio group channel 4
100: Secondary audio group
channel 1
101: Secondary audio group
channel 2
110: Secondary audio group
channel 3
111: Secondary audio group
channel 4
R/W 3
OP3_SRC8-6Output channel 3 source selector
(Decode as above). R/W 2
OP2_SRC5-3 Output channel 2 source selector
(Decode as above). R/W 1
OP1_SRC2-0 Output channel 1 source selector
(Decode as above). R/W 0
20Bh OUTPUT_SEL_2
RSVD 15-12 Reserved.R/W 0
OP8_SRC11-9
Output channel 8 source selector.
000: Primary audio group channel 1
001: Primary audio group channel 2
010: Primary audio group channel 3
011: Primary audio group channel 4
100: Secondary audio group
channel 1
101: Secondary audio group
channel 2
110: Secondary audio group
channel 3
111: Secondary audio group
channel 4
R/W 7
OP7_SRC8-6Output channel 7 source selector
(Decode as above). R/W 6
OP6_SRC5-3 Output channel 6 source selector
(Decode as above). R/W 5
OP5_SRC2-0 Output channel 5 source selector
(Decode as above). R/W 4
20Ch -
21Fh RSVD RSVD −Reserved.− −
220h AFNA
RSVD 15-9 Reserved.R/W 0
AFNA 8-0 Primary group audio frame
number. R0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
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221h RATEA
RSVD 15-4 Reserved.R/W 0
RATEA 3-1 Primary group sampling frequency
for channels 1 and 2. R0
ASXA 0 Primary group asynchronous mode
for channels 1 and 2. R0
222h ACTA
RSVD 15-4 Reserved.R/W 0
ACTA 3-0 Primary group active channels. R 0
223h PRIM_AUD
_DELAY_1
RSVD 15-9 Reserved.R/W 0
DEL1_2A_1 8-1 Primary Audio group delay data for
channels 1 and 2 [7:0]. R0
EBIT1_2A 0 Primary Audio group delay data
valid flag for channels 1 and 2. R0
224h PRIM_AUD
_DELAY_2
RSVD 15-9 Reserved.R/W 0
DEL1_2A_2 8-0 Primary Audio group delay data for
channels 1 and 2 [16:8]. R0
225h PRIM_AUD
_DELAY_3
RSVD 15-9 Reserved.R/W 0
DEL1_2A_3 8-0 Primary Audio group delay data for
channels 1 and 2 [25:17]. R0
226hPRIM_AUD
_DELAY_4
RSVD 15-9 Reserved.R/W 0
DEL3_4A_4 8-1 Primary Audio group delay data for
channels 3 and 4 [7:0]. R0
EBIT3_4A 0 Primary Audio group delay data
valid flag for channels 3 and 4. R0
227h PRIM_AUD
_DELAY_5
RSVD 15-9 Reserved.R/W 0
DEL3_4A_5 8-0 Primary Audio group delay data for
channels 3 and 4 [16:8]. R0
228h PRIM_AUD
_DELAY_6
RSVD 15-9 Reserved.R/W 0
DEL3_4A_68-0 Primary Audio group delay data for
channels 3 and 4 [25:17]. R0
229h -
22Fh RSVD RSVD −Reserved.R/W 0
230h AFNB
RSVD 15-9 Reserved.R/W 0
AFNB 8-0 Secondary group audio frame
number. R0
231h RATEB
RSVD 15-4 Reserved.R/W 0
RATEB 3-1 Secondary group sampling
frequency for channels 1 and 2. R0
ASXB 0 Secondary group asynchronous
mode for channels 1 and 2. R0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
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232h ACTB
RSVD 15-4 Reserved.R/W 0
ACTB 3-0 Secondary group active channels. R 0
233h SEC_AUD_DELAY
_1
RSVD 15-9 Reserved.R/W 0
DEL1_2B_1 8-1 Secondary Audio group delay data
valid flag for channels 1 and 2. R0
EBIT1_2B 0 Secondary Audio group delay data
for channels 1 and 2 [7:0]. R0
234h SEC_AUD_DELAY
_2
RSVD 15-9 Reserved.R/W 0
DEL1_2B_2 8-0 Secondary Audio group delay data
for channels 1 and 2 [16:8]. R0
235h SEC_AUD_DELAY
_3
RSVD 15-9 Reserved.R/W 0
DEL1_2B_3 8-0 Secondary Audio group delay data
for channels 1 and 2 [25:17]. R0
236hSEC_AUD_DELAY
_4
RSVD 15-9 Reserved.R/W 0
DEL3_4B_4 8-1 Secondary Audio group delay data
for channels 3 and 4 [7:0]. R0
EBIT3_4B 0 Secondary Audio group delay data
valid flag for channels 3 and 4. R0
237h SEC_AUD_DELAY
_5
RSVD 15-9 Reserved.R/W 0
DEL3_4B_5 8-0 Secondary Audio group delay data
for channels 3 and 4 [16:8]. R0
238h SEC_AUD_DELAY
_6
RSVD 15-9 Reserved.R/W 0
DEL3_4B_68-0 Secondary Audio group delay data
for channels 3 and 4 [25:17]. R0
239h -
23Fh RSVD RSVD −Reserved.R/W 0
240h ACSR1_2A_BYTE
0_1 ACSR1_2A_0 15-0
Bytes 0 [7:0] and 1 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
241h ACSR1_2A_BYTE
2_3 ACSR1_2A_2 15-0
Bytes 2 [7:0] and 3 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
242h ACSR1_2A_BYTE
4_5 ACSR1_2A_4 15-0
Bytes 4 [7:0] and 5 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
243h ACSR1_2A_BYTE
6_7 ACSR1_2A_615-0
Bytes 6 [7:0] and 7 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
244h ACSR1_2A_BYTE
8_9 ACSR1_2A_8 15-0
Bytes 8 [7:0] and 9 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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245h ACSR1_2A_BYTE
10_11 ACSR1_2A_10 15-0
Bytes 10 [7:0] and 11 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
246hACSR1_2A_BYTE
12_13 ACSR1_2A_12 15-0
Bytes 12 [7:0] and 13 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
247h ACSR1_2A_BYTE
14_15 ACSR1_2A_14 15-0
Bytes 14 [7:0] and 15 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
248h ACSR1_2A_BYTE
16_17 ACSR1_2A_1615-0
Bytes 16 [7:0] and 17 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
249h ACSR1_2A_BYTE
18_19 ACSR1_2A_18 15-0
Bytes 18 [7:0] and 19 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
24Ah ACSR1_2A_BYTE
20_21 ACSR1_2A_20 15-0
Bytes 20 [7:0] and 21 [15:8] of audio
group A channel status for
channels 1 and 2.
R0
24Bh ACSR1_2A_BYTE
22
RSVD 15-8 Reserved.R/W 0
ACSR1_2A_22 7-0 Bytes 22 of audio group A channel
status for channels 1 and 2. R0
24Ch -
24Fh RSVD RSVD 15-0 Reserved.R/W 0
250h ACSR3_4A_BYTE
0_1 ACSR3_4A_0 15-0
Bytes 0 [7:0] and 1 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
251h ACSR3_4A_BYTE
2_3 ACSR3_4A_2 15-0
Bytes 2 [7:0] and 3 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
252h ACSR3_4A_BYTE
4_5 ACSR3_4A_4 15-0
Bytes 4 [7:0] and 5 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
253h ACSR3_4A_BYTE
6_7 ACSR3_4A_615-0
Bytes 6 [7:0] and 7 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
254h ACSR3_4A_BYTE
8_9 ACSR3_4A_8 15-0
Bytes 8 [7:0] and 9 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
255h ACSR3_4A_BYTE
10_11 ACSR3_4A_10 15-0
Bytes 10 [7:0] and 11 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
256hACSR3_4A_BYTE
12_13 ACSR3_4A_12 15-0
Bytes 12 [7:0] and 13 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
257h ACSR3_4A_BYTE
14_15 ACSR3_4A_14 15-0
Bytes 14 [7:0] and 15 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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123 of 138
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258h ACSR3_4A_BYTE
16_17 ACSR3_4A_1615-0
Bytes 16 [7:0] and 17 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
259h ACSR3_4A_BYTE
18_19 ACSR3_4A_18 15-0
Bytes 18 [7:0] and 19 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
25Ah ACSR3_4A_BYTE
20_21 ACSR3_4A_20 15-0
Bytes 20 [7:0] and 21 [15:8] of audio
group A channel status for
channels 3 and 4.
R0
25Bh ACSR3_4A_BYTE
22
RSVD 15-8 Reserved.R/W 0
ACSR3_4A_22 7-0 Bytes 22 of audio group A channel
status for channels 3 and 4. R0
25Ch -
25Fh RSVD RSVD 15-0 Reserved.R/W 0
260h ACSR1_2B_BYTE
0_1 ACSR1_2B_0 15-0
Bytes 0 [7:0] and 1 [15:8] of audio
group B channel status for channels
1 and 2.
R0
261h ACSR1_2B_BYTE
2_3 ACSR1_2B_2 15-0
Bytes 2 [7:0] and 3 [15:8] of audio
group B channel status for channels
1 and 2.
R0
262h ACSR1_2B_BYTE
4_5 ACSR1_2B_4 15-0
Bytes 4 [7:0] and 5 [15:8] of audio
group B channel status for channels
1 and 2.
R0
263h ACSR1_2B_BYTE
6_7 ACSR1_2B_615-0
Bytes 6 [7:0] and 7 [15:8] of audio
group B channel status for channels
1 and 2.
R0
264h ACSR1_2B_BYTE
8_9 ACSR1_2B_8 15-0
Bytes 8 [7:0] and 9 [15:8] of audio
group B channel status for channels
1 and 2.
R0
265h ACSR1_2B_BYTE
10_11 ACSR1_2B_10 15-0
Bytes 10 [7:0] and 11 [15:8] of audio
group B channel status for channels
1 and 2.
R0
266hACSR1_2B_BYTE
12_13 ACSR1_2B_12 15-0
Bytes 12 [7:0] and 13 [15:8] of audio
group B channel status for channels
1 and 2.
R0
267h ACSR1_2B_BYTE
14_15 ACSR1_2B_14 15-0
Bytes 14 [7:0] and 15 [15:8] of audio
group B channel status for channels
1 and 2.
R0
268h ACSR1_2B_BYTE
16_17 ACSR1_2B_1615-0
Bytes 16 [7:0] and 17 [15:8] of audio
group B channel status for channels
1 and 2.
R0
269h ACSR1_2B_BYTE
18_19 ACSR1_2B_18 15-0
Bytes 18 [7:0] and 19 [15:8] of audio
group B channel status for channels
1 and 2.
R0
26Ah ACSR1_2B_BYTE
20_21 ACSR1_2B_20 15-0
Bytes 20 [7:0] and 21 [15:8] of audio
group B channel status for channels
1 and 2.
R0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
GENDOC-054389 July 2013
124 of 138
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26Bh ACSR1_2B_BYTE
22
RSVD 15-8 Reserved.R/W 0
ACSR1_2B_22 7-0 Bytes 22 of audio group B channel
status for channels 1 and 2. R0
26Ch -
26Fh RSVD RSVD 15-0 Reserved.R/W 0
270h ACSR3_4B_BYTE
0_1 ACSR3_4B_0 15-0
Bytes 0 [7:0] and 1 [15:8] of audio
group B channel status for channels
3 and 4.
R0
271h ACSR3_4B_BYTE
2_3 ACSR3_4B_2 15-0
Bytes 2 [7:0] and 3 [15:8] of audio
group B channel status for channels
3 and 4.
R0
272h ACSR3_4B_BYTE
4_5 ACSR3_4B_4 15-0
Bytes 4 [7:0] and 5 [15:8] of audio
group B channel status for channels
3 and 4.
R0
273h ACSR3_4B_BYTE
6_7 ACSR3_4B_615-0
Bytes 6 [7:0] and 7 [15:8] of audio
group B channel status for channels
3 and 4.
R0
274h ACSR3_4B_BYTE
8_9 ACSR3_4B_8 15-0
Bytes 8 [7:0] and 9 [15:8] of audio
group B channel status for channels
3 and 4.
R0
275h ACSR3_4B_BYTE
10_11 ACSR3_4B_10 15-0
Bytes 10 [7:0] and 11 [15:8] of audio
group B channel status for channels
3 and 4.
R0
276hACSR3_4B_BYTE
12_13 ACSR3_4B_12 15-0
Bytes 12 [7:0] and 13 [15:8] of audio
group B channel status for channels
3 and 4.
R0
277h ACSR3_4B_BYTE
14_15 ACSR3_4B_14 15-0
Bytes 14 [7:0] and 15 [15:8] of audio
group B channel status for channels
3 and 4.
R0
278h ACSR3_4B_BYTE
16_17 ACSR3_4B_1615-0
Bytes 16 [7:0] and 17 [15:8] of audio
group B channel status for channels
3 and 4.
R0
279h ACSR3_4B_BYTE
18_19 ACSR3_4B_18 15-0
Bytes 18 [7:0] and 19 [15:8] of audio
group B channel status for channels
3 and 4.
R0
27Ah ACSR3_4B_BYTE
20_21 ACSR3_4B_20 15-0
Bytes 20 [7:0] and 21 [15:8] of audio
group B channel status for channels
3 and 4.
R0
27Bh ACSR3_4B_BYTE
22
RSVD 15-8 Reserved.R/W 0
ACSR3_4B_22 7-0 Bytes 22 of audio group B channel
status for channels 3 and 4. R0
27Ch -
27Fh RSVD RSVD 15-0 Reserved.R/W 0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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125 of 138
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280h ACSR_BYTE_0
RSVD 15-8 Reserved.R/W 0
ACSR0 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
281h ACSR_BYTE_1
RSVD 15-8 Reserved.R/W 0
ACSR1 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
282h ACSR_BYTE_2
RSVD 15-8 Reserved.R/W 0
ACSR2 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
283h ACSR_BYTE_3
RSVD 15-8 Reserved.R/W 0
ACSR3 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
284h ACSR_BYTE_4
RSVD 15-8 Reserved.R/W 0
ACSR4 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
285h ACSR_BYTE_5
RSVD 15-8 Reserved.R/W 0
ACSR5 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
286hACSR_BYTE_6
RSVD 15-8 Reserved.R/W 0
ACSR67-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
GENDOC-054389 July 2013
126 of 138
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287h ACSR_BYTE_7
RSVD 15-8 Reserved.R/W 0
ACSR7 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
288h ACSR_BYTE_8
RSVD 15-8 Reserved.R/W 0
ACSR8 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
289h ACSR_BYTE_9
RSVD 15-8 Reserved.R/W 0
ACSR9 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
28Ah ACSR_BYTE_10
RSVD 15-8 Reserved.R/W 0
ACSR10 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
28Bh ACSR_BYTE_11
RSVD 15-8 Reserved.R/W 0
ACSR11 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
28ChACSR_BYTE_12
RSVD 15-8 Reserved.R/W 0
ACSR12 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
28Dh ACSR_BYTE_13
RSVD 15-8 Reserved.R/W 0
ACSR13 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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127 of 138
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28Eh ACSR_BYTE_14
RSVD 15-8 Reserved.R/W 0
ACSR14 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
28Fh ACSR_BYTE_15
RSVD 15-8 Reserved.R/W 0
ACSR15 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
290h ACSR_BYTE_16
RSVD 15-8 Reserved.R/W 0
ACSR167-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
291h ACSR_BYTE_17
RSVD 15-8 Reserved.R/W 0
ACSR17 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
292h ACSR_BYTE_18
RSVD 15-8 Reserved.R/W 0
ACSR18 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
293h ACSR_BYTE_19
RSVD 15-8 Reserved.R/W 0
ACSR19 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
294h ACSR_BYTE_20
RSVD 15-8 Reserved.R/W 0
ACSR20 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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128 of 138
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Legend:
R = Read only
ROCW = Read Only, Clear on Write
R/W = Read or Write
W = Write only
295h ACSR_BYTE_21
RSVD 15-8 Reserved.R/W 0
ACSR21 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
296hACSR_BYTE_22
RSVD 15-8 Reserved.R/W 0
ACSR22 7-0
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
W0
297h RSVD RSVD 15-0 Reserved. R 29
Table 4-30: HD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name Bit Description R/W Default
Table 4-31: ANC Extraction FIFO Access Registers
Address Register Name Bit Description R/W Default
800h -
BFFh ANC_PACKET_BANK 15-0
Extracted Ancillary Data 91024 words.
Bit 15-8: Most Significant Word (MSW).
Bit 7-0: Least Significant Word (LSW).
See Section 4.17.8.
R0
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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129 of 138
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4.21 JTAG Test Operation
When the JTAG/HOST pin of the GS1671A is set HIGH, the host interface port is
configured for JTAG test operation. In this mode, pins E7, F8, F7, and E8 become TDO,
TCK, TMS, and TDI. In addition, the RESET_TRST pin operates as the test reset pin.
Boundary scan testing using the JTAG interface is enabled in this mode.
There are two ways in which JTAG can be used:
1. As a stand-alone JTAG interface to be used at in-circuit ATE
(Automatic Test Equipment) during PCB assembly.
2. Under control of a host processor for applications such as system power on self
tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other devices
driving the digital I/O pins. If the tests are to be applied only at ATE, this can be
accomplished with tri-state buffers used in conjunction with the JTAG/HOST input
signal. This is shown in Figure 4-45.
Figure 4-45: In-Circuit JTAG
Alternatively, if the test capabilities are to be used in the system, the host processor may
still control the JTAG/HOST input signal, but some means for tri-stating the host must
exist in order to use the interface at ATE. This is represented in Figure 4-46.
Application HOST
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG/HOST
In-circuit ATE probe
GS1671A
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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130 of 138
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Figure 4-46: System JTAG
Scan coverage is limited to digital pins only. There is no scan coverage for analog pins
VCO, SDO/SDO, RSET, LF, and CP_RES.
The JTAG/HOST pin must be held LOW during scan and therefore has no scan coverage.
Please contact your Semtech representative to obtain the BSDL model for the GS1671A.
Application HOST
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG/HOST
In-circuit ATE probe
Tri-State
GS1671A
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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4.22 Device Power-up
Because the GS1671A is designed to operate in a multi-voltage environment, any
power-up sequence is allowed. The charge pump, phase detector, core logic, serial
digital output and I/O buffers can all be powered up in any order.
Note: Power ramp-up time (10% to 90%) ≥ 40μs.
4.23 Device Reset
Note: At power-up, the device must be reset to operate correctly.
In order to initialize all internal operating conditions to their default states, hold the
RESET_TRST signal LOW for a minimum of treset = 1ms after all power supplies are
stable. There are no requirements for power supply sequencing.
When held in reset, all device outputs are driven to a high-impedance state.
Figure 4-47: Reset Pulse
4.24 Standby Mode
The STANDBY pin reduces power to a minimum by disabling all circuits except for the
register configuration. Upon removal of the signal to the STANDBY pin, the device
returns to its previous operating condition within 1 second, without requiring input
from the host interface.
Note: In standby mode or reset, the crystal buffer output remains enabled. This allows
users to reset the GS1671A device without resetting other downstream devices that are
using the same reference. This also allows users to put the GS1671A device in standby
mode and still use the loop-through mode.
Supply Voltage
RESET_TRST
treset
95% of Nominal Level
Nominal Level
Reset Reset
treset
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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5. Application Reference Design
5.1 High Gain Adaptive Cable Equalizers
The GS1671A has an integrated adaptive cable equalizer. In order to extend the cable
length that an equalizer will remain operational at, it is necessary for the equalizer to
have high gain.
A video cable equalizer must provide wide band gain over a range of frequencies in
order to accommodate the range of data rates and signal patterns that are present in a
SMPTE compliant serial video stream.
Small levels of signal or noise present at the input pins of the GS1671A may cause
chatter at the output. In order to prevent this from happening, particular attention must
be paid to board layout.
5.2 PCB Layout
Special attention must be paid to component layout when designing
Serial Digital Interfaces for HDTV. An FR-4 dielectric can be used, however, controlled
impedance transmission lines are required for PCB traces longer than approximately
1cm. Note the following PCB artwork features used to optimise performance:
• The PCB ground plane is removed under the GS1671A input components to
minimize parasitic capacitance.
• High speed traces are curved to minimize impedance changes.
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
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5.3 Typical Application Circuit
Figure 5-1: Typical Application Circuit
CD_VDD
Host Interface & Control
CS10-27.000M
16p
16p
CD_VDD
AUDIO WORD CLOCK
470n
+1.2V_A
0R
0R
10n
+1.2V
10n
10n
10n 10n
4. For impedance controlled signal layout, refer to PCB layout guide.
IO_VDD
+1.2V
DOUT[19:0]
10n
Power Filtering
10n 10n
AUDIO OU TPUT CH 1 & 2SDIN_TDI
DNP
SCLK_TCK
4u7
22R
22R
10n 49R9
49R9
Close to
pin 1 & 2
of GS2978
AUDIO OU TPUT CH 3 & 4
CS_TMS
+1.2V_A IO_VDD
+3.3V_A
R7
105R
+1.2V
C18
33u
+1.2V_A
LOCKED (DEF AULT, PROGRAMMABLE)
22R
R19
DNP
+3.3V_A
22R
0R
10n10n
Place close to GS1671A
AUDIO OU TPUT CH 5 & 6
1
3
2
UCBBJE20-1
CD_DI SABLEb
Y/1AN C (DEFAULT, PROGRAMMABLE)
PCLK
22R
DATA_ERRORb (D EFAULT, PROGRAMMABLE)
1u
22R
AUDIO OU TPUT CH 7 & 8
SDI Input
H/HSYNC (DEFAULT, PROGRAMMABLE)
1u
A_GND
22R
10n
CD SLEW R ATE SELECT
VBG
A1
LF
A2
LB_CONT
A3
VCO_VDD A4
STAT0 A5
STAT1 A6
STAT2 B5
STAT3 B6
STAT4 C5
STAT5 C6
IO_VDD A7
PCLK A8
DOUT 0 K8
DOUT 1 J8
DOUT 2 K9
DOUT 3 K10
DOUT 4 J9
DOUT 5 J10
DOUT 6 H9
DOUT 7 H10
DOUT 8 F9
DOUT 9 F10
DOUT 10 E9
DOUT 11 E10
DOUT 12 C8
DOUT 13 C10
DOUT 14 C9
DOUT 15 B10
DOUT 16 B9
DOUT 17 A10
DOUT 18 A9
DOUT 19 B8
A_VDD B1
PLL_VDD B2
RSV
B3
VCO_GND
B4
IO_GND
B7
SDI
C1
A_GND
C2
PLL_VDD C3
PLL_VDD C4
RESET_TRST
C7
SDI
D1
A_GND
D2
A_GND
D3
PLL_GND
D4
CORE_GND
D5 CORE_VDD D6
SW_EN
D7
JTAG/HOST
D8
IO_GND
D9 IO_VDD D10
EQ_VDD E1
A_GND
E3
PLL_GND
E4
CORE_GND
E5 CORE_VDD E6
SDOUT_TDO
E7
SDIN_TDI
E8
F1
AGCN
F2
A_GND
F3
PLL_GND
F4
CORE_GND
F5 CORE_VDD F6
CS_TMS
F7 SCLK_TCK
F8
G1
G2
RC_BY P
G3
RSV
G4
CORE_GND
G5 CORE_VDD G6
SMPTE_BY PASS
G7
DVB_ASI
G8
IO_GND
G9 IO_VDD G10
BUF_VDD H1
BUF_GND
H2
AUDIO_EN /DIS
H3
WCLK H4
TIM_8 61
H5
XTAL_OUT
H6
20BIT/10BIT
H7 IOPROC_EN /DIS
H8
SDO J1
SDO_EN/D IS
J2
AOUT_1/2 J3
ACLK J4
AOUT_5/6 J5
XTAL2
J6
IO_GND
J7
SDO K1
STANDBY
K2
AOUT_3/4 K3
AMCLK K4
AOUT_7/8 K5
XTAL1
K6
IO_VDD K7
SDI_GND
E2
GS1671A
SMPTE_BY PASS
1u
Place clos e to GS1671A
+3.3V_A
10n
V/VSY N C (DEFAULT, PROGRAMMABLE)
22R
1u
F/DE (D EFAULT, PROGRAMMABLE)
22R
22R
22R
3. For analog power and ground isolation, refer to PCB layout guide.
DVB_ASI
Power Decoupling
22R
Place clos e to GS1671A
22R
SDOUT_TDO
SW_EN
1u
22R
AUDIO_EN /DIS
1u
22R
IOPROC_EN/DIS
75-ohm Traces
CD_DI SABLEb
22R
75R
4u7
SDI Loop-Through Output
20BIT/10BIT
75R
5n6
10n
+3.3V_A
10n 10n
1
3
2
UCBBJE20-1
22R
RC_BYP
75R
75R
IO_VDD
1u
22R
JTAG/HOST
75R
6n2
75R
22R
1u
37R4
1u
22R
STANDBY
RESET_TRST
22R
2. The value of the series resistors on video data, clock, and timing
connections should be determined by board signal integrity test.
22R
22R
22R
SDO_EN/D IS
22R
+3.3V
TP
CD_VDD
0R
10n10n
47n
SDI
2
VEE
3
NC
14
RSET
4
NC
16
SD/HD 10
SDO 11
SDI
1
VCC 9
SDO 12
NC
13
DISABLE
6
RSVD
7
NC
8
NC
15
NC
5
TAB
17
GS2978-CNE3
10n
+1.2V_A
10n 10n
22R
10n
AUDIO MASTER CLOC K
10n
Audio Data
and Clock
Output
DOUT[19:0]
TIM_861
22R
750R
1. DNP (Do Not Populate).
Notes:
AUDIO SER IAL BIT CLOCK
1u
Video Data, Clock & Timing Output
A_GND
A_GND
A_GND
A_GND
A_GND
A_GND
A_GND
A_GND
A_GND
CD_VDD
A_GND
A_GND
A_GND A_GND
A_GND
A_GND
470n
AGCP
CORE_GND
A_GND
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
GENDOC-054389 July 2013
134 of 138
www.semtech.com
6. References & Relevant Standards
Table 6-1: SMPTE Standards Reference
SMPTE ST 125 Component video signal 4:2:2 – bit parallel interface
SMPTE ST 259 10-bit 4:2:2 Component and 4fsc Composite Digital Signals - Serial Digital
Interface
SMPTE ST 2601125 / 60 high definition production system – digital representation and
bit parallel interface
SMPTE ST 267Bit parallel digital interface – component video signal 4:2:2 16 x 9 aspect
ratio
SMPTE ST 272 Formatting AES/EBU Audio and Auxiliary Data into Digital Video Ancillary
Data Space
SMPTE ST 274 1920 x 1080 scanning analog and parallel digital interfaces for multiple
picture rates
SMPTE ST 291 Ancillary Data Packet and Space Formatting
SMPTE ST 292 Bit-Serial Digital Interface for High-Definition Television Systems
SMPTE ST 293 720 x 483 active line at 59.94Hz progressive scan production – digital
representation
SMPTE ST 2961280 x 720 scanning, analog and digital representation and analog
interface
SMPTE ST 299 24-Bit Digital Audio Format for HDTV Bit-Serial Interface
SMPTE ST 305 Serial Data Transport Interface
SMPTE ST 348 High Data-Rate Serial Data Transport Interface (HD-SDTI)
SMPTE ST 352 Video Payload Identification for Digital Television Interfaces
SMPTE ST 372 Dual Link ST 292 Interface for 1920 x 1080 Picture Raster
SMPTE RP165Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital
Interfaces for Television
SMPTE RP168Definition of Vertical Interval Switching Point for Synchronous Video
Switching
CEA 861Video Timing Requirements
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
GENDOC-054389 July 2013
135 of 138
www.semtech.com
7. Package & Ordering Information
7.1 Package Dimensions
Figure 7-1: GS1671A Packaging Dimensions
0.366
(0.366)
TOP VIEW BOTTOM VIEW
PIN 1 CORNER 12345678910
A
B
C
D
E
F
G
H
J
K
*THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC M0192 (LOW PROFILE BGA FAMILY)
0.70±0.05
SEATING PLANE
0.25 C
C
PACKAGE OUTLINE
100L LBGA
PACKAGE SIZE: 11 x 11 x 1.71mm
1.00
0.50 0.70
Ball Pitch:
Ball Diameter: Mold Thickness:
Substrate Thickness:
10
A
B
C
D
E
F
G
H
J
K
123456789
BA
0.20(4X)
0.15
1.700 MAX
0.30~0.50
9.00
1.00
11±0.10
PIN 1 CORNER
AB
C
C
Φ0.10
Φ0.25
Φ0.40~0.60(100X)
1.00
9.00
11±0.10
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
GENDOC-054389 July 2013
136 of 138
www.semtech.com
7.2 Packaging Data
7.3 Marking Diagram
Figure 7-2: GS1671A Marking Diagram
Table 7-1: Packaging Data
Parameter Value
Package Type 11mm x 11mm 100-ball LBGA
Package Drawing
Reference
JEDEC M0192 (with exceptions noted in Package Dimensions on
page 135).
Moisture Sensitivity Level 3
Junction to Case Thermal
Resistance, θj-c15.4°C/W
Junction to Air Thermal
Resistance, θj-a (at zero
airflow)
37.1°C/W
Junction to Board
Thermal Resistance, θj-b26.4°C/W
Psi, ψ0.4°C/W
Pb-free and RoHS
Compliant Yes
GS1671A
XXXXXXE3
YYWW
Pin 1 ID
XXXXXX - Last 6 digits (excluding decimal)
of SAP Batch Assembly (FIN) as listed
on Packing Slip.
E3 - Pb-free & Green indicator
YYWW - Date Code
GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
GENDOC-054389 July 2013
137 of 138
www.semtech.com
7.4 Solder Reflow Profiles
The GS1671A is available in a Pb-free package. It is recommended that the Pb-free
package be soldered with Pb-free paste using the reflow profile shown in Figure 7-3.
Figure 7-3: Pb-Free Solder Reflow Profile
7.5 Ordering Information
Revision History
25°C
150°C
200°C
217°C
260°C
250°C
Time
Temperature
8 min. max
60-180 sec. max
60-150 sec.
20-40 sec.
3°C/sec max
6°C/sec max
Table 7-2: GS1671A Ordering Information
Part Number Package Pb-free Temperature Range
GS1671AIBE3 100-ball BGA Yes -40°C to 85°C
GS1671AIBTE3
(250pc tape and reel) 100-ball BGA Yes -40°C to 85°C
Version ECO PCN Date Changes and/or Modifications
2 014961– August 2013
Clarified IOPROC_EN/DIS register configuration throughout
Section 4. Added note to Section 4.19. Updated SMPTE format
throughout document.
1 158468–September 2012 Changes throughout the document.
0 154534 – July 2010 New document.
© Semtech 2010
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DOCUMENT IDENTIFICATION
FINAL DATA SHEET
Information relating to this product and the application or design described
herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or
for the application or design described herein. Semtech reserves the right to
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GS1671A HD/SD SDI Receiver
Final Data Sheet Rev. 2
GENDOC-054389 July 2013
138 of 138
138
Contact Information
Semtech Corporation
Gennum Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
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