THC63LVD104C - THine Electronics, Inc.

THC63LVD104C_Rev.2.1_E

THC63LVD104C

112MHz 30Bits COLOR LVDS Receiver

General Description

The THC63LVD104C receiver is designed to support

pixel data transmission between Host and Flat Panel

Display from NTSC up to SXGA resolutions. The

THC63LVD104C converts the LVDS data streams back

into 35bits of CMOS/TTL data with the choice of the

rising edge or falling edge clock for the convenience

with a variety of LCD panel controllers.At a transmit

clock frequency of 112MHz, 30bits of RGB data and

5bits of timing and control data (HSYNC,

VSYNC,DE,CNTL1,CNTL2) are transmitted at an

effective rate of 784Mbps per LVDS channel.Using a

112MHz clock, the data throughput is 490Mbytes per

second.

Features

•Wide dot clock range: 8-112MHz suited for NTSC,

VGA, SVGA, XGA, and SXGA

•PLL requires no external components

•50% output clo c k d ut y cycle

•TTL clock edge programmable

•Power down mode

•Low power single 3.3V CMOS design

•64pin TQFP

•Backward compatible with THC63LVDF64x

(18bits) / F84x(24bits)

•Pin compatible with THC63LVD104A

•Fail-safe for Open LVDS Input

Block Diagram

LVDS INPUT CMOS/TTL OUTPUT

RCLK+/-

(8 to

112

MHz)

PLL

RA+/-

RB+/-

RC+/-

RD+/-

RE+/-

TEST

PD

OE

R/F

RA6-RA0

RB6-RB0

RC6-RC0

RD6-RD0

RE6-RE0

CLKOUT

SERIAL TO PARALLEL

CMOS/TTL INPUT

7

THC63LVD104C_Rev.2.1_E

THine

Pin Out

RB6

CLKOUT

GND

RC0

RC1

RC2

RC3

RC4

RC5

VCC

RC6

RD0

RD1

RD2

RD3

RD4

GND

TEST

PD

OE

R/F

RE6

RE5

RE4

VCC

RE3

RE2

RE1

RE0

RD6

RD5

GND

RA-

RA+

RB-

RB+

LVCC

RC-

RC+

RCLK-

RCLK+

LGND

RD-

RD+

RE-

RE+

PGND

PVCC

VCC

RA0

RA1

RA2

GND

RA3

RA4

RA5

RA6

RB0

RB1

VCC

RB2

RB3

RB4

RB5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

THC63LVD104C_Rev.2.1_E

THine

Pin Description

** Rxn

x = A,B,C,D,E

n = 0,1,2,3,4,5,6

Pin Name Pin # Type Description

RA+, RA- 50, 49 LVDS IN

LVDS Data In.

RB+, RB- 52, 51 LVDS IN

RC+, RC- 55, 54 LVDS IN

RD+, RD- 60, 59 LVDS IN

RE+,RE- 62, 61 LVDS IN

RCLK+, RCLK- 57, 56 LVDS IN LVDS Clock In.

RA6 ~ RA0 40,41,42,43,45,46,47 OUT

CMOS/TTL Data Outputs.

RB6 ~ RB0 32,33,34,35,36,38,39 OUT

RC6 ~ RC0 22,24,25,26,27,28,29 OUT

RD6 ~ RD0 14,15,17,18,19,20,21 OUT

RE6 ~ RE0 6,7,8,10 ,11,12,13 OUT

TEST 2 IN Test pin, must be “L” for normal operation.

PD 3 IN H: Normal operation,

L: Power down (all outputs are “L”)

OE 4 IN H: Output en able (Normal operation).

L: Output disable(all outputs are Hi-Z)

R/F 5 IN Output Clock Triggering Edge Select.

H: Rising edge, L: Falling edge

VCC 9,23,37,48 Power Power Supply Pins for TTL outputs and digital circuitry.

CLKOUT 31 OUT Clock out.

GND 1,16,30,44 Ground Ground Pins for TTL outputs and digital circuitry.

LVCC 53 Power Power Supply Pin for LVDS inputs.

LGND 58 Ground Ground Pin for LVDS inputs.

PVCC 64 Power Power Supply Pin for PLL circuitry.

PGND 63 Ground Ground Pin for PLL circuitry.

PD R/F OE Data Outputs

(Rxn) CLKOUT

0 0 0 Hi-Z Hi-Z

0 0 1 All 0 Fixed Low

0 1 0 Hi-Z Hi-Z

0 1 1 All 0 Fixed Low

1 0 0 Hi-Z Hi-Z

1 0 1 Data Out The falling edge closer to the center of the data eye.

1 1 0 Hi-Z Hi-Z

1 1 1 Data Out The rising edge closer to the center of the data eye.

THC63LVD104C_Rev.2.1_E

THine

Absolute Maximum Ratings 1

Electrical Characteristics

CMOS/TTL DC Specifications VCC =LVCC=PVCC= 3.0V ~ 3.6V, Ta = -20 ~ +85

LVDS Receiver DC Specifications VCC =LVCC=PVCC= 3.0V ~ 3.6V, Ta = -20 ~ +85

Supply Voltage (VCC=VCC=LVCC=PVCC) -0.3V ~ +4.0V

CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V)

CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V)

LVDS Receiver Input Voltage -0.3V ~ (VCC + 0.3V)

Output Current -30mA ~ 30mA

Junction Tem p er a tur e +125

Storage Temperature Range -55 ~ +150

Reflow Peak Temperature / Time +260 / 10sec.

Maximum Power Dissipation @+25 2.1W

1. “Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed. They

are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics”

specify conditions for device operation.

Symbol Parameter Conditions Min. Typ. Max. Units

VIH High Level Input Voltage 2.0 VCC V

VIL Low Level Input Voltage GND 0.8 V

VOH High Level Output Voltage IOH= -4mA (data)

IOH= -8mA (clock) 2.4 V

VOL Low Level Output Voltage IOL= 4mA (data)

IOL= 8mA (clock) 0.4 V

IINC Input Current μA

Symbol Parameter Conditions Min. Typ. Max. Units

VTH Differential Input High Threshold VIC= 1.2V 100 mV

VTL Differential Input Low Threshold VIC= 1.2V -100 mV

IINL Input Current VIN= 2.4V / 0V

VCC= 3.6V 30 μA

°C

°C°C

°C

°C°C

0V VIN VCC

≤≤ 10±

°C°C

THC63LVD104C_Rev.2.1_E

THine

Supply Current

VCC =LVCC=PVCC= 3.0V ~ 3.6V, Ta = -20 ~ +85

*The trade-off between the output load and the ambient temperature exists so that the junction temperature does not

exceed 125 .

Symbol Parameter Conditions Typ. Max. Units

IRCCW

Receiver Supply

Current

(LVDS Full Toggle)

fCLKOUT = 75MHz CL=8pF,Vcc=3.6V,

Ta= -20 ~ 85 205 mA

fCLKOUT = 90MHz 236 mA

fCLKOUT = 112MHz CL=8pF,Vcc=3.6V,

Ta= -20 ~70 * 280 mA

IRCCS Receiver Power Down

Supply Current PD = L 25 μA

°C°C

°C

CLKOUT

Rx0

LVDS Full Toggle Pattern

Rx1

Rx2

Rx3

Rx4

Rx5

Rx6

x=A,B,C,D,E

THC63LVD104C_Rev.2.1_E

THine

Output load limitation

The output load is limited so that the junction temperature does not exceed 125 .°C

0.0

5.0

10.0

15.0

20.0

25.0

828486888108

Frequency[MHz]

Output Load[pF]

Ta=70℃

Ta=85℃

THC63LVD104C_Rev.2.1_E

THine

Switching Characteristics

VCC =LVCC=PVCC= 3.0V ~ 3.6V, Ta = -20 ~+85

Symbol Parameter Min. Typ. Max. Units

tRCP CLKOUT Period 8.92 T 125.0 ns

tRCH CLKOUT High Time ns

tRCL CLKOUT Low Time ns

tRS TTL Data Setup to CLKOUT ns

tRH TTL Data Hold from CLKOUT ns

tTLH TTL Low to High Transition Time 1.0 3.0 ns

tTHL TTL High to Low Transition Time 1.0 3.0 ns

tSK Receiver Skew

Margin

CLKOUT=50MHz -1000 0 1000 ps

CLKOUT=75MHz -550 0 550 ps

CLKOUT=90MHz -400 0 400 ps

CLKOUT=112MHz -250 0 250 ps

tRIP1 Input Data Position0 - tSK 0+ tSK ns

tRIP0 Input Data Position1 ns

tRIP6 Input Data Position2 ns

tRIP5 Input Data Position3 ns

tRIP4 Input Data Position4 ns

tRIP3 Input Data Position5 ns

tRIP2 Input Data Position6 ns

tRPLL Phase Lock Loo p Set 10.0 ms

tRCD RCLK +/- to

CLKOUT Delay CLKOUT=75MHz 46.5 52.5 ns

tRCIP CLKIN Period 8.92 125.0 ns

°C°C

T

2

---

T

2

---

4

7

---tRCP 1–

3

7

---tRCP 1–

tRCIP

7

--------------t

SK

–tRCIP

7

--------------tRCIP

7

--------------t

SK

+

2tRCIP

7

--------------t

SK

–2tRCIP

7

--------------2

tRCIP

7

--------------t

SK

+

3tRCIP

7

--------------t

SK

–3tRCIP

7

--------------3

tRCIP

7

--------------t

SK

+

4tRCIP

7

--------------t

SK

–4tRCIP

7

--------------4

tRCIP

7

--------------t

SK

+

5tRCIP

7

--------------t

SK

–5tRCIP

7

--------------5

tRCIP

7

--------------t

SK

+

6tRCIP

7

--------------t

SK

–6tRCIP

7

--------------6

tRCIP

7

--------------t

SK

+

THC63LVD104C_Rev.2.1_E

THine

x = A,B,C,D,E

n = 0,1,2,3,4,5,6

VCC/2

R/F = L

R/F = H

tRCP

tRS tRH

tRCH tRCL

CLKOUT

Rxn

VCC/2

AC Timing Diagrams

TTL Outputs

TTL Output

TTL Output Load

20%

80%

20%

80%

tTLH tTHL

C

L

=8pF

THC63LVD104C_Rev.2.1_E

AC Timing Diagrams

Phase Lock Loop Set Time

VCC 3.0V

2.0V

tRPLL

RCLK+/-

PD

CLKOUT

Vdiff=0V

RCLK+

RCLK +/- to CLKOUT Delay

Current Data

VCC/2

tRCD

Current Data

Rxn

x = A,B,C,D,E

n = 0,1,2,3,4,5,6

Note:

1)Vdiff = (RCLK+) - (RCL K-)

Ry+/-

y = A,B,C,D,E

CLKOUT

R/F = L

THC63LVD104C_Rev.2.1_E

AC Timing Diagrams

Vdiff = 0V Vdiff = 0V

RCLK+

tRIP1 tRIP0

tRIP6

tRIP5

tRIP4

tRIP3

tRIP2

LVDS Inputs

RE6 RE5 RE4 RE3 RE2 RE1 RE0

RE+/-

RD6 RD5 RD4 RD3 RD2 RD1 RD0

RD+/-

RC6 RC5 RC4 RC3 RC2 RC1 RC0

RC+/-

RB6 RB5 RB4 RB3 RB2 RB1 RB0

RB+/-

RA6 RA5 RA4 RA3 RA2 RA1 RA0

RA+/-

(Differential)

Next Cycle

Previous Cycle Current Cycle

RE3’ RE2’ RE1’ RE0’

RD3’ RD2’ RD1’ RD0’

RC3’ RC2’ RC1’ RC0’

RB3’ RB2’ RB1’ RB0’

RA3’ RA2’ RA1’ RA0’

RE6’’

RD6’’

RC6’’

RB6’’

RA6’’

tRCIP

THC63LVD104C_Rev.2.1_E

THine

Note

1)Power On Sequence

Power on LVDS-Tx after THC63LVD104C.

2)Cable Connection and Disconnection

Don't connect and disconnect the LVDS cable, when the power is supplied to the system.

3)GND Connection

Connect the each GND of the PCB which LVDS-Tx and THC63LVD104C on it. It is better for EMI reduction to place

GND cable as close to LVDS cable as possible.

4)Multi Drop Connection

Multi drop connection is not recommended.

5)Asynchronous use

Asynchronous use such as following systems are not recommended.

THC63LVD104C

LVDS-Tx THC63LVD104C

TCLK+

TCLK-

THC63LVD104C

THC63LVD104CLVDS-Tx

LVDS-Tx

IC

CLKOUT

DATA

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

THC63LVD104C

IC

TCLK+

TCLK-

TCLK+

TCLK-

CLKOUT

DATA

IC

THC63LVD104C_Rev.2.1_E

Package

S

SEATING PLANE

0.08 M

0.10

1.00 REF.

0.60+/-0.15

0.25mm

GAGE PLANE

0.20+/-0.03

1.00+/-0.05

0.05~0.15

1.2 Max

0.50 BSC. 0.09~0.20

S

3.5+/-3.5 de gree

10.00 BSC.

12.00 BSC.

Unit : mm

THC63LVD104C

THC63LVD104C_Rev.2.1_E

Notices and Requests

1. The product specifications described in this material are subject to change without prior notice.

2. The circuit diagrams described in this material are examples of the application which may not

always apply to the customer's design. We are not responsible for possible errors and omissions

in this material. Please note if errors or omissions should be found in this material, we may not

be able to correct them immediately.

3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to

third parties the contents of this material without our prior permission is prohibited.

4. Note that if infringement of any third party's industrial ownership should occur by using this

product, we will be exempted from the responsibility unless it directly relates to the production

process or functions of the product.

5. This product is presumed to be used for general electric equipment, not for the applications

which require very high reliability (including medical equipment directly concerning people's

life, aerospace equipment, or nuclear control equipment). Also, when using this product for the

equipment concerned with the control and safety of the transportation means, the traffic signal

equipment, or various Types of safety equipment, please do it after applying appropriate

measures to the product.

6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur

with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you

are encouraged to have suff iciently redundant or error preventive design applied to the use of the

product so as not to have our product cause any social or public damage.

7. Please note that this product is not designed to be radiation-proof.

8. Customers are asked, if required, to judge by themselves if this product falls under the category

of strategic goods under the Foreign Exchange and Foreign Trade Control Law.

THine Electronics, Inc.

E-mail: sales@thine.co.jp