VIPer20/SP/DIP - VIPer20A/ASP/ADIP (R) SMPS PRIMARY I.C. TYPE VIPer20/SP/DIP VIPer20A/ASP/ADIP VDSS 620V 700V In 0.5 A 0.5 A RDS(on) 16 18 PENTAWATT HV ADJUSTABLE SWITCHING FREQUENCY UP TO 200 kHz CURRENT MODE CONTROL SOFT START AND SHUT DOWN CONTROL AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET "BLUE ANGEL" NORM (<1W TOTAL POWER CONSUMPTION) INTERNALLY TRIMMED ZENER REFERENCE UNDERVOLTAGE LOCK-OUT WITH HYSTERESIS INTEGRATED START-UP SUPPLY AVALANCHE RUGGED OVERTEMPERATURE PROTECTION LOW STAND-BY CURRENT ADJUSTABLE CURRENT LIMITATION PENTAWATT HV (022Y) 10 1 DIP-8 PowerSO-10TM DESCRIPTION VIPer20/20A, made using VIPower M0 Technology, combines on the same silicon chip a state-of-the-art PWM circuit together with an optimized high voltage avalanche rugged Vertical Power MOSFET (620V or 700V / 0.5A). Typical applications cover off line power supplies with a secondary power capability of 10W in wide range condition and 20W in single range or with doubler configuration. It is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. Burst mode operation is an additional feature of this device, offering the possibility to operate in stand-by mode without extra components. BLOCK DIAGRAM DRAIN OSC ON/OFF OSCILLATOR SECURITY LATCH UVLO LOGIC VDD R/S PWM LATCH FF Q S R1 S FF Q R2 R3 OVERTEMP. DETECTOR 0.5 V + _ _ 13 V 1.7 s delay 250 ns Blanking + 0.5V _ + 6 V/A _ CURRENT AMPLIFIER ERROR AMPLIFIER + COMP July 2002 SOURCE FC00491 4.5 V 1/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP ABSOLUTE MAXIMUM RATING Symbol VDS ID VDD VOSC VCOMP ICOMP Vesd ID(AR) Ptot Tj Tstg Parameter Continuous Drain-Source Voltage (Tj=25 to 125C) for VIPer20/SP/DIP for VIPer20A/ASP/ADIP Maximum Current Supply Voltage Voltage Range Input Voltage Range Input Maximum Continuous Current Electrostatic Discharge (R =1.5k; C=100pF) Avalanche Drain-Source Current, Repetitive or Not Repetitive (TC=100C; Pulse width limited by Tj max; < 1%) for VIPer20/SP/DIP for VIPer20A/ASP/ADIP Power Dissipation at Tc=25C Junction Operating Temperature Storage Temperature Value Unit -0.3 to 620 V -0.3 to 700 Internally limited 0 to 15 0 to VDD 0 to 5 2 4000 V A V V V mA V 0.5 A 0.4 A 57 Internally limited -65 to 150 W C C THERMAL DATA Symbol Rthj-pin Rthj-case Rthj-amb. Parameter Thermal Resistance Junction-pin Max Thermal Resistance Junction-case Max Thermal Resistance Ambient-case Max PENTAWATT PowerSO-10TM (*) 2.0 70 2.0 60 DIP-8 20 Unit C/W C/W C/W 35 (#) (*) When mounted using the minimum recommended pad size on FR-4 board. (#) On multylayer PCB. CONNECTION DIAGRAMS (Top View) PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10TM DIP-8 OSC 1 8 Vdd DRAIN DRAIN SOURCE COMP DRAIN 4 5 DRAIN SC10540 CURRENT AND VOLTAGE CONVENTIONS IDD ID VDD IOSC DRAIN OSC 13V + COMP SOURCE VDD VDS ICOMP VOSC VCOMP FC00020 2/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP ORDERING NUMBERS PENTAWATT HV VIPer20 VIPer20A PENTAWATT HV (022Y) VIPer20 (022Y) VIPer20A (022Y) PowerSO-10TM VIPer20SP VIPer20ASP DIP-8 VIPer20DIP VIPer20ADIP PINS FUNCTIONAL DESCRIPTION DRAIN PIN: Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power. source, and can easily be connected to the output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the VDD voltage, which cannot overpass 13V. The output voltage will be somewhat higher than the nominal one, but still under control. COMP PIN: This pin provides two functions: SOURCE Pin: Power MOSFET source pin. Primary side circuit common ground connection. VDD Pin: This pin provides two functions: - It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below 8V, the start-up current source is activated and the output power MOSFET is switched off until the VDD voltage reaches 11V. During this phase, the internal current consumption is reduced, the VDD pin sources a current of about 2mA and the COMP pin is shorted to ground. After that, the current source is shut down, and the device tries to start up by switching again. - This pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is used to maintain VDD at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put on VDD pin by transformer design, in order to stick the output of the transconductance amplifier to the high state. The COMP pin behaves as a constant current 3/25 1 - It is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. Its bandwidth can easily be adjusted to the needed value with usual components value. As stated above, secondary regulation configurations are also implemented through the COMP pin. - When the COMP voltage goes below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle for the power MOSFET. This feature can be used to switch off the converter, and is automatically activated by the regulation loop (whatever is the configuration) to provide a burst mode operation in case of negligible output power or open load condition. OSC PIN: An Rt-Ct network must be connected on that pin to define the switching frequency. Note that despite the connection of Rt to VDD, no significant frequency change occurs for VDD varying from 8V to 15V. It also provides a synchronization capability, when connected to an external frequency source. VIPer20/SP/DIP - VIPer20A/ASP/ADIP AVALANCHE CHARACTERISTICS Symbol ID(AR) E(ar) Parameter Avalanche Current, Repetitive or Not Repetitive (pulse widht limited by Tj max; < 1%) for VIPer20/SP/DIP for VIPer20A/ASP/ADIP Single Pulse Avalanche Energy (starting Tj =25C, I D=ID(ar)) (see fig.12) (see fig.12) Max Value Unit 0.5 A 0.4 A 10 mJ ELECTRICAL CHARACTERISTICS (Tj=25C; VDD=13V, unless otherwise specified) POWER SECTION Symbol BVDSS IDSS RDS(on) Parameter Drain-Source Voltage Off-State Drain Current Static Drain-Source On Resistance tf Fall Time tr Rise Time Coss Output Capacitance Test Conditions ID=1mA; VCOMP=0V for VIPer20/SP/DIP for VIPer20A/ASP/ADIP (see fig.5) Min Typ Max Unit 620 V 700 V VCOMP=0V; Tj=125C VDS=620V for VIPer20/SP/DIP VDS=700V for VIPer20A/ASP/ADIP ID=0.4A for VIPer20/SP/DIP for VIPer20A/ASP/ADIP ID=0.4A; Tj=100C for VIPer20/SP/DIP for VIPer20A/ASP/ADIP 1.0 mA 1.0 mA 13.5 16 15.5 18 29 32 ID=0.2A; VIN=300V (1) (See fig. 3) 100 ns ID=.4A; VIN=300V (1) (See fig. 3) VDS=25V 50 ns 90 pF (1) On Inductive Load, Clamped. SUPPLY SECTION Symbol Parameter Test Conditions Min Max Unit mA 16 mA IDDch IDD0 Operating Supply Current VDD=12V; FSW=0kHz (see fig. 2) 12 Operating Supply Current Operating Supply Current Undervoltage Shutdown Undervoltage Reset Hysteresis Start-up 13 14 8 11 3 IDD1 IDD2 VDDoff VDDon VDDhyst VDD=5V; VDS=35V (see fig. 2 and fig. 15) Typ -2 Start-Up Charging Current VDD=12V; Fsw=100kHz VDD=12V; Fsw=200kHz (See fig. 2) (See fig. 2) (See fig. 2) 7.5 2.4 9 12 mA mA V V V 4/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP ELECTRICAL CHARACTERISTICS (continued) OSCILLATOR SECTION Symbol FSW VOSCih VOSCil Parameter Oscillator Frequency Total Variation Test Conditions Rt=8.2K; Ct=2.4nF VDD=9 to 15V; with Rt 1%; Ct 5% (see fig. 6 and fig. 9) Min Typ Max Unit 90 100 110 kHz Oscillator Peak Voltage Oscillator Valley Voltage 7.1 3.7 V V ERROR AMPLIFIER SECTION Symbol VDDreg VDDreg Parameter VDD Regulation Point Total Variation Test Conditions ICOMP=0mA (see fig. 1) Tj=0 to 100C GBW Unity Gain Bandwidth From Input =VDD to Output = VCOMP COMP pin is open (see fig. 10) AVOL Gm Open Loop Voltage Gain DC Transconductance Output Low Level Output High Level Output Low Current Capability Output High Current Capability VCOMPLO VCOMPHI ICOMPLO ICOMPHI COMP pin is open VCOMP=2.5V ICOMP= -400A; VDD=14V ICOMP=400A; VDD=12V (see fig. 10) (see fig. 1) Min 12.6 Typ 13 2 150 45 1.1 52 1.5 0.2 4.5 Max 13.4 1.9 Unit V % kHz dB mA/V V V VCOMP=2.5V; VDD=14V -600 A VCOMP=2.5V; VDD=12V 600 A PWM COMPARATOR SECTION Symbol HID VCOMPoff IDpeak td tb ton(min) Parameter VCOMP / IDPEAK VCOMP Offset Peak Current Limitation Current Sense Delay to Turn-Off Blanking Time Minimum On Time Test Conditions VCOMP=1 to 3 V IDPEAK=10mA VDD=12V; COMP pin open Min 4.2 0.5 ID=1A Typ 6 0.5 0.67 Max 7.8 0.9 250 Unit V/A V A ns 250 350 360 ns ns Typ 0.5 1.7 Max 5 Unit V s 170 190 C SHUTDOWN AND OVERTEMPERATURE SECTION Symbol VCOMPth tDISsu Ttsd Thyst 5/25 Parameter Restart Threshold Disable Set Up Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis Test Conditions Min (see fig. 4) (see fig. 4) (See fig. 8) (See fig. 8) 140 40 C VIPer20/SP/DIP - VIPer20A/ASP/ADIP Figure 2: Undervoltage Lockout Figure 1: VDD Regulation Point ICOMP IDD Slope = Gm in mA/V ICOMPHI IDD0 VDD 0 VDDhyst ICOMPLO VDDoff VDS= 35 V Fsw = 0 VDDon VDD IDDch VDDreg FC00150 Figure 3: Transition Time FC00170 Figure 4: Shut Down Action VOSC ID t VCOMP 10% Ipeak VDS tDISsu t t VCOMPth 90% VD ID 10% VD t tf t tr ENABLE FC00160 ENABLE DISABLE FC00060 Figure 5: Breakdown Voltage Vs. Temperature Figure 6: Typical Frequency Variation FC00180 1.15 FC00190 (%) BVDSS (Normalized) 1 0 1.1 -1 -2 1.05 -3 1 -4 0.95 -5 0 20 40 60 80 100 120 Temperature (C) 0 20 40 60 80 100 120 140 Temperature (C) 6/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP Figure 7: Start-Up Waveforms Figure 8: Overtemperature Protection TJ Ttsc Ttsd-Thyst t Vdd Vddon Vddoff t Id t Vcomp t SC10191 7/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP Figure 9: Oscillator For Rt >1.2K and Ct 15nF if FSW 40KHz VDD Rt OSC 2.3 550 F SW = ------------ 1 - ---------------------- R t Ct Rt - 150 FC00050 Ct Forbidden area 880 Ct(nF) = 22nF Fsw(kHz) 15nF Forbidden area 40kHz Fsw Oscillator frequency vs Rt and Ct FC00030 1,000 Ct = 1.5 nF 500 Ct = 2.7 nF Frequency (kHz) Ct ~360 CLK 300 Ct = 4.7 nF 200 Ct = 10 nF 100 50 30 1 2 3 5 10 20 30 50 Rt (k) 8/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP Figure 10: Error Amplifier Frequency Response FC00200 60 RCOMP = + Voltage Gain (dB) RCOMP = 270k 40 RCOMP = 82k RCOMP = 27k 20 RCOMP = 12k 0 (20) 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1,000 Figure 11: Error Amplifier Phase Response FC00210 200 RCOMP = + 150 RCOMP = 270k Phase () RCOMP = 82k RCOMP = 27k 100 RCOMP = 12k 50 0 (50) 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1,000 9/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP Figure 12: Avalanche Test Circuit L1 1mH 2 VDD 1 3 DRAIN OSC 13V BT1 0 to 20V + COMP BT2 12V C1 47uF 16V Q1 2 x STHV102FI in parallel R1 SOURCE 5 4 47 GENERATOR INPUT 500us PULSE U1 VIPer20 R2 1k R3 100 FC00196 10/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP Figure 13: Off Line Power Supply With Auxiliary Supply Feedback F1 C1 BR1 TR2 TR1 D2 AC IN L2 +Vcc D1 R9 C2 C7 C9 R1 C3 GND D3 C10 R7 C4 R2 VDD DRAIN OSC VIPer20 + 13V COMP SOURCE C5 C6 C11 R3 FC00401 Figure 14: Off Line Power Supply With Optocoupler Feedback F1 BR 1 TR 2 C1 T R1 D2 AC IN L2 +V cc D1 R9 C2 C7 C9 R1 C3 G ND D3 C10 R7 C4 R2 V DD DR AIN OSC 13V V IP er20 + C OM P C5 C11 SO UR CE C6 R6 IS O 1 R3 R4 C8 U2 R5 F C00411 11/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP OPERATION DESCRIPTION: CURRENT MODE TOPOLOGY The current mode control method, like the one integrated in the VIPer20/20A uses two control loops - an inner current control loop and an outer loop for voltage control. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage VS proportional to this current. When VS reaches VCOMP (the amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. Excellent D.C. open loop and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. This results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in the case of short circuit. During the first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on VDD is no longer correct. For specific applications the maximum peak current internally set can be overridden by limiting the voltage excursion externally on the COMP pin. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. STAND-BY MODE Stand-by operation in nearly open load condition automatically leads to a burst mode operation allowing voltage regulation on the secondary side. The transition from normal operation to burst mode operation happens for a power PSTBY given by: 2 1 P STBY = --- L I STBY F SW 2 P Where: LP is the primary inductance of the transformer. FSW is the normal switching frequency. ISTBY is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. This current can be computed as: ( t b + td )V IN I STBY = -------------------------------L P tb + td is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and roughly represents the minimum on time of the device. Note that PSTBY may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13V regulation level forcing the output voltage of the transconductance amplifier to low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power switch is maintained in the off state, resulting in missing cycles and zero duty cycle. As soon as VDD gets back to the regulation level and the VCOMPth threshold is reached, the device operates again. The above cycle repeats itself indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input mains lines. This mode of operation allows the VIPer20/20A to meet the new German "Blue Angel" Norm with less than 1W total power consumption for the system when working in stand-by. The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because of the output capacitors and because of the low output current drawn in such conditions. The normal operation resumes automatically when the power gets back levels which are higher than PSTBY. HIGH VOLTAGE START-UP CURRENT SOURCE An integrated high voltage current source provides a bias current from the DRAIN pin during the startup phase. This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and are also provided to the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the 12/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP where: IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. VDDhyst is the voltage hysteresis of the UVLO logic. Refer to the minimum specified value. Soft start feature can be implemented on the COMP pin through a simple capacitor which will also be used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case of a large regulation loop bandwidth is mandatory, the schematics in figure 16 can be used. It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. If the device is intentionally shut down by putting the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff. This voltage can be used for supplying external functions, provided that their consumption doesn't exceed 0.5mA. Figure 17 shows a typical application of this function, with a latched shut down. Once the "Shutdown" signal has been activated, the device remains in the off state until the input voltage is removed. UVLO logic, the device turns into active mode and starts switching. The start up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on figure 15. In case of abnormal condition where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the external capacitor discharges itself down to the low threshold voltage VDDoff of the UVLO logic, and the device gets back to the inactive state where the internal circuits are in standby mode and the start up current source is activated. The converter enters an endless start up cycle, with a start-up duty cycle defined by the ratio of charging current towards discharging when the VIPer20/20A tries to start. This ratio is fixed by design from 2 to 15, which gives a 12% start up duty cycle while the power dissipation at start up is approximately 0.6 W, for a 230 Vrms input voltage. This low value of start-up duty cycle prevents the stress of the output rectifiers and of the transformer when in short circuit. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching. This time tSS depends on many parameters, among which transformer design, output capacitors, soft start feature and compensation network implemented on the COMP pin. The following formula can be used for defining the minimum capacitor needed: I DD tSS CVDD > -------------------------V DDhyst Figure 15: Behavior of the high voltage current source at start-up VDD 2 mA VDDon VDDoff 15 mA 3 mA VDD 1 mA DRAIN 15 mA CVDD Ref. t Auxiliary primary winding UNDERVOLTAGE LOCK OUT LOGIC VIPer20 Start up duty cycle ~ 12% SOURCE FC00101A 13/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP TRANSCONDUCTANCE ERROR AMPLIFIER The VIPer20/20A includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP) versus change in input voltage (VDD). Thus: G I COMP -----------------------= m V DD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: V COMP V COMP 1 Z COMP = --------------------------- = --------- x --------------------------G V DD I COMP m This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: AVOL = Gm x ZCOMP where Gm value for VIPer50/50A is 1.5 mA/V typically. Gmis well defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define more accurately the transfer function F of the error amplifier, according to the following equation, very similar to the one above: F(S) = Gm x Z(S) The error amplifier frequency response is reported in figure 10 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330 K. More complex impedance can be connected on the COMP pin to Figure 16: Mixed Soft Start and Compensation achieve different compensation laws. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated in figure 18. As shown in figure 18 an additional noise filtering capacitor of 2.2 nF is generally needed to avoid any high frequency interference. It can also be interesting to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. Figure 19 shows such a configuration. Note that R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. EXTERNAL CLOCK SYNCHRONIZATION The OSC pin provides a synchronisation capability, when connected to an external frequency source. Figure 20 shows one possible schematic to be adapted depending on the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor. PRIMARY PEAK CURRENT LIMITATION The primary IDPEAK current and, as resulting effect, the output power can be limited using the simple circuit shown in figure 21. The circuit based on Q1, R1 and R2 clamps the voltage on the Figure 17: Latched Shut Down D2 D3 VIPer20 VDD VDD OSC 13V Q2 R3 + COM P C4 DRAIN OSC 13V SOURCE D1 + COMP SOURCE AUXILIARY WINDING R3 R2 R1 R2 + C3 VIPer20 R1 DRAIN C1 + C2 R4 Shutdown Q1 D1 FC00431 FC00440 14/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP COMP pin in order to limit the primary peak current of the device to a value: - 0.5 V COMP IDPEAK = ------------------------------------H ID where: R1 + R2 V COMP = 0.6 x ---------------------R2 OVER-TEMPERATURE PROTECTION: Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140C while the typical value is 170C. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40C below the shutdown value (see figure 8). The suggested value for R1+R2 is in the range of 220K. Figure 18: Typical Compensation Network Figure 19: Slope Compensation VIPer20 VDD R2 DRAIN R1 - OSC 13V VIPer20 VDD + DRAIN - COMP SOURCE OSC 13V + COMP SOURCE C2 R1 C2 C1 Q1 C1 C3 R3 FC00451 FC00461 Figure 20: External Clock Synchronization Figure 21: Current Limitation Circuit Example VIPer20 VDD OSC 13V VIPer20 VDD DRAIN + COMP SOURCE DRAIN - OSC 13V + COMP SOURCE R1 10 k Q1 R2 FC00470 FC00480 15/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP Figure 22: Input Voltage Surges Protection R1 D1 (Optional) R2 39R Auxilliary winding C1 Bulk capacitor VDD C2 22nF DRAIN OSC 13V + VIPerXX0 COMP SOURCE ELECTRICAL OVER STRESS RUGGEDNESS The VIPer may be submitted to electrical over stress caused by violent input voltage surges or lightning. Following the enclosed Layout Considerations chapter rules is the most of the time sufficient to prevent catastrophic damages, however in some cases the voltage surges coupled through the transformer auxiliary winding can overpass the VDD pin absolute maximum rating voltage value. Such events may trigger the VDD internal protection circuitry which could be damaged by the strong discharge current of the VDD bulk capacitor. The simple RC filter shown in figure 22 can be implemented to improve the application immunity to such surges. 16/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP Figure 23: Recommended Layout T1 D1 C7 D2 R1 2 3 VDD C1 7RVHFRQGDU\ ILOWHULQJDQGORDG DRAIN - 1 OSC 13V )URPLQSXW C5 + COMP GLRGHVEULGJH SOURCE 5 U1 VIPerXX0 R2 4 C6 C2 C3 ISO1 C4 FC00500 LAYOUT CONSIDERATIONS Some simple rules insure a correct running of switching power supplies. They may be classified into two categories: - To minimize power loops: the way the switched power current must be carefully analyzed and the corresponding paths must present the smallest possible inner loop area. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. - To use different tracks for low level signals and power ones. The interferences due to a mixing of signal and power may result in instabilities and/or anomalous behavior of the device in case of violent power surge (Input overvoltages, output short circuits...). In case of VIPer, these rules apply as shown in figure 23. The loops C1-T1-U1, C5-D2-T1, C7-D1T1 must be minimized. C6 must be as close as possible to T1. The signal components C2, ISO1, C3 and C4 use a dedicated track to be connected directly to the source of the device. 17/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP PowerSO-10TM MECHANICAL DATA mm. DIM. MIN. A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) (*) inch TYP 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 MAX. MIN. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 0.132 0.134 0.000 0.016 0.014 0.013 0.009 0.370 0.291 0.366 0.283 0.287 0.232 0.232 1.35 1.40 14.40 14.35 0.049 0.047 0.543 0.545 1.80 1.10 8 8 0.047 0.031 0 2 TYP. MAX. 0.144 0.142 0.004 0.024 0.021 0.022 0.0126 0.378 0.300 0.374 300 0.295 0.240 0.248 1.27 0.050 1.25 1.20 13.80 13.85 0.053 0.055 0.567 0.565 0.50 0.002 1.20 0.80 0 2 0.070 0.043 8 8 (*) Muar only POA P013P B 0.10 A B 10 H E E2 E4 1 SEATING PLANE e B DETAIL "A" h A C 0.25 D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL "A" P095A 18/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP PENTAWATT HV MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.11 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 H2 0.382 10.40 10.05 H3 0.409 10.40 0.396 0.409 L 15.60 17.30 6.14 0.681 L1 14.60 15.22 0.575 0.599 L2 21.20 21.85 0.835 0.860 L3 22.20 22.82 0.874 0.898 L5 2.60 3 0.102 0.118 L6 15.10 15.80 0.594 0.622 L7 6 6.60 0.236 0.260 M 2.50 3.10 0.098 0.122 M1 4.50 5.60 0.177 0.220 R 0.50 0.02 V4 Diam 90 (typ) 3.65 3.85 0.144 0.152 P023H3 19/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP PENTAWATT HV 022Y (VERTICAL HIGH PITCH) MECHANICAL DATA DIM. mm. MIN. inch TYP MAX. MIN. TYP. MAX. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.110 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 H3 10.05 10.40 0.396 0.409 L 16.42 17.42 0.646 0.686 L1 14.60 15.22 0.575 0.599 L3 20.52 21.52 0.808 0.847 H2 10.40 0.409 L5 2.60 3.00 0.102 0.118 L6 15.10 15.80 0.594 0.622 L7 6.00 6.60 0.236 0.260 M 2.50 3.10 0.098 0.122 M1 5.00 5.70 0.197 0.224 R 0.50 V4 90 Diam. 0.020 90 3.70 3.90 0.146 0.154 L L1 E A M M1 C D R Resin between leads L6 L7 V4 H2 H3 H1 G1 G2 F DIA L5 L3 20/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP Plastic DIP-8 MECHANICAL DATA DIM. mm. MIN. TYP MAX. A 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.26 E1 6.10 6.35 7.11 e 2.54 eA 7.62 eB L Package Weight 10.92 2.92 3.30 3.81 Gr. 470 P001 21/25 VIPer20/SP/DIP - VIPer20A/ASP/ADIP PowerSO-10TM SUGGESTED PAD LAYOUT TUBE SHIPMENT (no suffix) 14.6 - 14.9 CASABLANCA B 10.8- 11 MUAR C 6.30 C A A 0.67 - 0.73 10 9 1 9.5 2 3 B 0.54 - 0.6 All dimensions are in mm. 8 7 4 5 1.27 Base Q.ty Bulk Q.ty Tube length ( 0.5) 6 Casablanca Muar 50 50 1000 1000 532 532 A B C ( 0.1) 10.4 16.4 4.9 17.2 0.8 0.8 TAPE AND REEL SHIPMENT (suffix "13TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 24 4 24 1.5 1.5 11.5 6.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 22/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP PENTAWATT HV TUBE SHIPMENT (no suffix) B C Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) 50 1000 532 18 33.1 1 All dimensions are in mm. A 23/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP DIP-8 TUBE SHIPMENT (no suffix) A C B Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) 20 1000 532 8.4 11.2 0.8 All dimensions are in mm. 24/25 1 VIPer20/SP/DIP - VIPer20A/ASP/ADIP Information furnished is believed to be accurate and reliable. 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