July 2002 1/25
®
VIPer20/SP/DIP
- VIPer20A/ASP/ADIP
SMPS PRIMARY I.C .
1
■ ADJUSTABLE SWITCHI NG FREQUENCY UP
TO 200 kHz
■ CURRENT MODE CONTROL
■ SOFT START AND SHUT DOWN CONTROL
■ AUTOMATIC BURST MODE OPERATION IN
STAND- BY CONDITION ABLE TO MEET
“BLUE ANGEL” NORM (<1W TOTAL POWER
CONSUMPTION)
■ INTERNAL LY TRIMMED ZENER REFERENCE
■ UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
■ INTEGRATED START-UP SUPPLY
■ AVALANCHE RUGGED
■ OVERTEMPERATURE PROTECTION
■ LOW STAND-BY CURRENT
■ ADJUSTABLE CURRENT LIMITATION
DESCRIPTION
VIPer20/20A, made using VIPower M0
Technolog y, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620V or 700V / 0.5A).
Typ ica l applicati ons cover off lin e p ower suppl ie s
with a secondary power capability of 10W in wide
range condition and 20W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.
TYPE VDSS InRDS(on)
VIPer20/SP/DIP 620V 0.5 A 16 Ω
V IPer20A/ASP/ADIP 700V 0.5 A 18 Ω
BLO C K DIAGRAM
PENTAWATT HV PENTAWATT HV (022Y)
1
10
PowerSO-10™
VDD
OSC
COMP
DRAIN
SOURCE
13 V
UVLO
LOGIC
SECURITY
LATCH PWM
LATCH
FFFF
R/S SQ
S
R1R2 R3 Q
OSCILLATOR
OVERTEMP.
DETECTOR
ERROR
AMPLIFIER
_
+
0.5 V +
_
1.7
µs
delay
250 ns
Blanking
CURRENT
AMPLIFIER
ON/OFF
0.5V
6 V/A
_
+
+
_
4.5 V
FC00491
DIP-8
2/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
ABSOLUTE MAXIMUM RATING
THERMAL DATA
(*) Wh en m ount ed us ing the m inimum r ec ommended pa d s iz e on FR-4 board .
(#) On multylayer PCB.
CONNECTI ON DIAGRAMS (Top View)
CURRENT AND VOLTAGE CONVENTIONS
Symbol Parameter Value Unit
VDS
Conti nuou s Drain-Source Voltage (Tj=25 to 125°C)
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP -0.3 to 620
-0.3 to 700 V
V
IDMaximum Curr ent In tern al l y l im ited A
VDD Supply Voltage 0 to 15 V
VOSC Volt age Ran ge Input 0 to VDD V
VCOMP Vol tage Range Input 0 to 5 V
ICOMP Maximum Con tinuous Current ± 2mA
V
esd El ectrostat ic Discharge (R =1.5kΩ; C=100pF) 4000 V
ID(AR)
Avalanche Drain-Source Current, Re petit ive or Not Repetit ive
(TC=100°C; Pulse wi dth li m ited by Tj max; δ < 1%)
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP
0.5
0.4 A
A
Ptot Power Dissipation at Tc=25ºC57W
T
j
Junction Operating Temperature Internally limited °C
Tstg Storage Temper ature -65 to 150 °C
Symbol Parameter PENTAWATT PowerSO-10™ (*) DIP-8 Unit
Rthj-pin Thermal Resi stance Ju nction-pin Max 20 °C/W
Rthj-case Thermal Resistance Junction-cas e Ma x 2.0 2.0 °C/W
Rthj-amb. Thermal Resistance Ambient-case Max 70 60 35 (#) °C/W
1
PEN TAW ATT HV PENTA W ATT HV ( 022Y) PowerSO-10™
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VCOMP
VOSC
VDD VDS
ICOMP
IOSC
IDD ID
FC00020
1
4
8
5
OSC
Vdd
SOURCE
COMP
DRAIN
DRAIN
DRAIN
DRAIN
SC10540
DIP-8
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
3/25
ORDERING NUM BERS
PINS FUNCTIONAL DESCRIPTION
DRAIN PIN:
Integrated Power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to han dle an unclamped current during its
norma l opera tion, assu ring self pr otectio n agains t
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
SOURCE Pin:
Power MOSFET source pin. Primary side circuit
common ground connection.
VDD Pin:
This pin provides two functions:
- It corres ponds to th e low voltage su pply of the
control part of the circuit. If VDD goes below 8V,
the s tart- up cur rent sou rce is activated and the
output pow er MOS FET is sw itched off until the
VDD voltage reaches 11V. During this phase,
the internal current consumption is reduced,
the VDD pin sources a current of about 2mA
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
device tries to start up by switching again.
- This pin is also connected to the error amplifier,
in order to allow primary as well as secondary
regulation configurations. In case of primary
regulation, an internal 13V trimmed reference
voltage is used to maintain VDD at 13V. For
secondary regulation, a voltage between 8.5V
and 12.5V will be put on VDD pin by transformer
design, in order to stick the output of the
transconductance amplifier to the high state.
The COMP pi n behaves as a constant current
source, and can easily be connected to the
output of an optocoupler. Note that any
overvoltage due to regulation loop failure is still
detected by the error amplifier through the VDD
voltage, which cannot overpass 13V. The
outp ut voltage will b e somewh at higher t han the
nominal one, but still under control.
COMP PIN:
This pin provi des two functions:
- It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can easily be adjusted to the
needed value with usual components value. As
stated above, secondary regulation
configurations are also implemented through
the COMP pin.
- When the COMP volta ge goes bel ow 0.5V , the
shut-down of the circuit occurs, with a zero
duty cycle fo r the power M OSFET. This feature
can b e used to swi tch off t he c on verte r, an d i s
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
OSC PIN:
An Rt-Ct network must be connected on that pin to
define the switching frequency. Note that despite
the connection of Rt to VDD, no significant
frequenc y chang e oc curs for V DD varying from 8V
to 15V. It also provides a synchronization
capability, when connected to an external
frequency source.
PENTAWATT HV PENTA W ATT HV (022Y) PowerSO -10™DIP-8
VIPer20 VIPer20 (022Y) VIPer20SP VIPer20DIP
VIPer20A VIPer20A (022Y) V IPer20ASP VIPer20ADI P
1
4/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (Tj=25°C; VDD=13V, unless otherwise specified)
POWER SECTI ON
(1) On Induct iv e Load, Clamped.
SUPPLY SEC TI ON
Symbol Parameter Max Value Unit
ID(AR)
Av ala n che Current, Re p eti tiv e or Not Rep eti tiv e
(pulse widht limited by Tj max; δ < 1%)
for VIPer20/SP/DIP
for VIPe r20A/ASP/ADI P (see fig.12)
0.5
0.4 A
A
E(ar) S i n g l e Pu l s e Av alan che En ergy
(s tarting Tj =25º C, ID=ID(ar)) (see fig.12) 10 mJ
S ymbol Parameter Test Conditions Min Typ M ax Unit
BVDSS Drain-Source Voltage ID=1mA; VCOMP=0V
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP (see fig.5) 620
700 V
V
IDSS Off-State Dr ain Current VCOMP=0V; Tj=125°C
VDS=620V for VIPer20/SP/DIP
VDS=700V for VIPer20A/ASP/ADIP 1.0
1.0 mA
mA
RDS(on) Static Drain-Source
On Resistance
ID=0.4A
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP
ID=0.4A; Tj=100°C
for VIPer20/SP/DIP
for VIPer20A/ASP/ADIP
13.5
15.5 16
18
29
32
Ω
Ω
Ω
Ω
tf Fall Time ID=0.2A; VIN=300V (1)
(See fig. 3) 100 ns
tr Rise Time ID=.4A; VIN=300V (1)
(See fig. 3) 50 ns
Coss Output Capacitance VDS=25V 90 pF
S ymbol Parameter Test Conditions Min Typ M ax Unit
IDDch Start-Up Charging
Current VDD=5V; VDS=35V
(see fig. 2 and fig. 15) -2 mA
IDD0 O per ating Su pply Cu rr ent VDD=12V ; F SW=0kHz
(see fig. 2) 12 16 mA
IDD1 O per ating Su pply Cu rr ent VDD=12V ; F sw=100kHz 13 mA
IDD2 O per ating Su pply Cu rr ent VDD=12V ; F sw=200kHz 14 mA
VDDoff Und ervoltage Sh utdown (See fig. 2) 7.5 8 9 V
VDDon Undervoltage Reset (See f ig. 2) 11 12 V
VDDhyst Hyst eres is Star t -u p (See fi g. 2) 2.4 3 V
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
5/25
ELECTRICAL CHARACTERISTICS (continued)
OSCILLATOR SECTION
ERROR A MPLIFIER SECTION
PWM COMPARATOR SECTION
SHUTDOWN AND OVERTEMPE RATURE SECTION
S ymbol Parameter Test Conditions Min Typ M ax Unit
FSW Osc il lator Frequency
Total Variation
Rt=8.2KΩ; Ct=2.4nF
VDD=9 to 15V;
with Rt± 1%; Ct± 5%
(see fig. 6 and fig. 9)
90 100 110 kHz
VOSCih Oscillator Peak Voltage 7.1 V
VOSCil Oscillator Valley Voltage 3.7 V
S ymbol Parameter Test Conditions Min Typ M ax Unit
VDDreg VDD Re gulati on Point ICOMP=0mA (see fi g. 1) 12.6 13 13.4 V
∆VDDreg Total Variation Tj=0 to 100°C 2 %
GBW Unity Gain Bandwidth From Input =VDD to Output = VCOMP
COMP pin is open (see fi g. 10) 150 kHz
AVOL Ope n Loop Volta ge Gai n COMP pin is open (see fig. 10) 45 52 dB
GmDC Transc onduc tance VCOMP=2.5V (see fig. 1) 1.1 1.5 1.9 mA/V
VCOMPLO Output Low Level ICOMP= -400µA; VDD=14V 0.2 V
VCOMPHI Output High Level ICOMP=400µA; VDD=12V 4.5 V
ICOMPLO Output Low Current
Capability VCOMP=2.5V; VDD=14V -600 µA
ICOMPHI Output High Current
Capability VCOMP=2.5V; VDD=12V 600 µA
S ymbol Parameter Test Conditions Min Typ M ax Unit
HID ∆VCOMP / ∆IDPEAK VCOMP=1 to 3 V 4.267.8V/A
V
COMPoff VCOMP Off s e t IDPEAK=10mA 0.5 V
IDpeak Peak Current Limitation VDD=12V; COMP pin open 0.5 0.67 0.9 A
tdCurrent Sense Delay to
Turn-Off ID=1A 250 ns
tbBlanking Time 250 360 ns
ton(min) Mi nimum On Time 350 ns
S ymbol Parameter Test Conditions Min Typ M ax Unit
VCOMPth Restart Threshold (see fi g. 4) 0.5 V
tDISsu Disable Set Up Time (see fi g. 4) 1.7 5 µs
Ttsd T h ermal Sh utdo w n
Temperature (S ee fig. 8) 140 170 190 °C
Thyst T h erma l Shut dow n
Hysteresis (See fig. 8) 40 °C
6/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 3: Transition Tim e Figure 4: Shut Do wn Action
F igure 5: Breakdown Voltage Vs. Temperature Figure 6: Typical Freq uenc y Variation
Figure 1: VDD Re gulation Po int Figure 2: Undervoltage Lockout
ICOMP
ICOMPHI
ICOMPLO VDDreg
0VDD
Slope =
Gm in mA/V
FC00150
VDDon
IDDch
IDD0
VDD
VDDoff
VDS= 3 5 V
Fsw = 0
IDD
VDDhyst
FC00170
ID
VDS
t
t
tf tr
10% Ipeak
10% V D
90% V D
FC00160
VCOMP
VOSC
ID
t
tDISsu
t
t
ENABLE DISABLEENABLE
VCOMPth
FC00060
Temperature (°C )
FC00180
0 20406080100120
0.95
1
1.05
1.1
1.15
BVDSS
(Normalized)
Temperature (°C)
0 20406080100120140
-5
-4
-3
-2
-1
0
1FC00190
(%)
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
7/25
Figure 7: Start-Up Waveforms
Figure 8: Overtemperature Protection
SC10191
TJ
Ttsd-Thyst
Ttsc
Vdd
Vddon
Vddoff
Id
Vcomp
t
t
t
t
8/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 9: Oscillator
1
Rt
Ct
OSC
VDD
~360Ω
CLK
FC00050
1 2 3 5 10 20 30 50
30
50
100
200
300
500
1,000
Rt (kΩ)
Frequency (kHz)
Oscillator frequency vs Rt and Ct
Ct = 1.5 nF
Ct = 2.7 nF
Ct = 4.7 nF
Ct = 10 nF
FC00030FC00030
For Rt >1.2KΩ
and
Ct ≥ 15nF if FSW ≤ 40KHz
FSW 2.3
RtCt
------------ 1550
Rt150
–
----------------------
–


⋅
=
C
t
Fsw
40kHz
15nF
22nF
Forbidden area
Forbidden area
Ct(nF) = Fsw(kHz)
880
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
9/25
Figure 10: Error Amplifier Frequency Response
Figure 11: Error Ampli fier Phase Response
1
0.001 0.01 0.1 1 10 100 1,000
(20)
0
20
40
60
Frequency (kHz)
Voltage Gain (dB)
RCOMP = +∞
RCOMP = 27 0k
RCOMP = 82k
RCOMP = 27 k
RCOMP = 12 k
FC00200
0.001 0.01 0.1 1 10 100 1,000
(50)
0
50
100
150
200
Frequenc y (kHz)
Phase (°)
RCOMP = +∞
RCOMP = 270k
RCOMP = 82k
RCOMP = 27k
RCOMP = 12k
FC00210
10/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 12: Avalanche Test Circuit
1
FC00196
U1
VIPer20
13V
OSC
COMP SOURCE
DRAINVDD
-
+
23
54
1
R3
100
R2
1k
BT2
12V
C1
47uF
16V
Q1
2 x STHV102FI in parallel
R1
47
L1
1mH
GENERATOR INPUT
500us PULSE
BT1
0 to 20V
11/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
1
Figure 13: Off Line P ower Supply With Auxiliary Supply Feedback
Figure 14: Off Line Power Supply With Optocoupler Feedback
AC IN +Vcc
GND
F1
BR1
D3
R9
C1
R7
C4
C2
TR2
R1
C3
D1
D2
C10
TR1
C9
C7
L2
R3
C6
C5
R2
VIPer20
-
+
13V
OSC
COMP SOURCE
DRAINVDD
FC00401
C11
AC IN
F1
BR1
D3
R9
C1
R7
C4
C2
TR2
R1
C3
D1
D2
C10
TR1
C9
C7
L2 +Vcc
GND
C8
C5
R2
VIPer20
U2
R4
R5
ISO1 R6
R3
C6
-
+
13V
OSC
COMP SOURCE
DRAINVDD
FC00411
C11
12/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
OPERATION DESCRIPTION:
CURRENT MODE TOPOLOGY
The current mode control method, like the one
integrated in the VIPer20/20A uses two control
loo ps - an i nner curr ent contro l loop an d an outer
loop for voltage control. When the Power
MOSFET output transistor is on, the inductor
current (primary side of the transformer) is
monitored with a SenseFET technique and
converted into a voltage VS proportional to this
current. When VS reaches VCOMP (the amplified
output volt age erro r) th e powe r s wit ch is swi tched
off. Thus, the outer voltage control loop defines
the level at which the inner loop regulates peak
cu rrent thro ugh the pow er swi tch and the p rimary
winding of the transformer.
Excellent D.C. open loop and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation, instantaneous correction to line
changes and better stability for the voltage
regulation loop.
Current mode topology also ensures good
limitation in the case of short circuit. During the
first phase the output current increases slowly
foll owing the dynamic of the regulation loop. Then
it reaches the maximum limitation current
int erna lly set an d f in ally sto ps becau se the power
supply on VDD is no longer correct. For specific
applications the maximum peak current internally
set can be overridden by limiting the voltage
excursion externally on the COMP pin. An
integrated blanking filter inhibits the PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function prevents anomalous or premature
termination of the switching pulse in the case of
current spikes caused by primary side capacitance
or secondary side recti fier reverse recovery time.
STAND- BY MODE
Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary side.
The transition from normal operation to burst
mode oper ati on happe ns for a power PSTBY given
by:
Where:
LP is the primary inductance of the transformer.
FSW is the normal swi tching frequency.
ISTBY is the minimum controllable current,
corresponding to the minimum on time that the
device is able to provide in normal operation. This
current can be computed as:
tb + td is the sum of the blanking time and of the
propagation time of the internal current sense and
compa rator, and roughly repr esents th e minimu m
on time of the device. Note that PSTBY may be
affected by the efficiency of the converter at low
load, and must include the power drawn on the
prim ary auxiliary voltage.
As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (VCOMP < VCOMPth). This situation leads to
the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as VDD gets
back to the regulation level and the VCOMPth
threshold is reached, the device operates again.
The above cycle repeats itself indefinitely,
providing a burst mode of which the effective duty
cycle is much lower than the minimum one when in
normal operation. The equivalent switching
frequency is also lower than the normal one,
leading to a reduced consumption on the input
mains lines. This mode of operation allows the
VIPer20/20A to meet the new German "Blue
Angel" Norm with less than 1W total power
consumption for the system when working in
stand-by. The output voltage remains regulated
around the normal level, with a low frequency
ripple corresponding to the burst mode. The
amplitude of this ripple is low, because of the
output capacitors and because of the low output
current drawn in such conditions. The normal
operation resumes automatically when the power
gets back levels which are higher than PSTBY.
HIGH VOLTAGE START-UP CURRENT
SOURCE
An integrated high voltage current source provides
a bias current from the DRAIN pin during the start-
up phase. This current is partially absorbed by
internal control circuits which are placed into a
standb y m ode with redu ced consumpti on and are
also pr ovided to the externa l capacitor connect ed
to t he VDD pi n. A s so on a s the volt ag e on this pin
reaches the high voltage threshold VDDon of the
PSTBY 1
2
--- LPI2STBYFSW
=
ISTBY tbtd
+
()V
IN
LP
--------------------------------
=
13/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
UVLO logic, the device turns into active mode and
starts switching.
The start up current generator is switched off, and
the c onver ter sho ul d nor mall y pro vid e the ne eded
current on the VDD pin through the auxiliary
winding of the transformer, as shown on figure 15.
In case of abnor mal condition where the auxiliary
winding is unable to provide the low voltage supply
current to the VDD pin (i.e. short circuit on the
output of the converter), the external capacitor
discharges itself down to the low threshold voltage
VDDoff of the UVLO logic, and the device gets back
to the i nactive state where the internal circuits are
in standby mode and the start up current source is
activated. The converter enters an endless start
up cycle, with a start-up duty cycle def ined by the
ratio of charging current towards discharging when
the VIPer20/20A tries to start. This ratio is fixed by
design from 2 to 15, which gives a 12% start up
duty cycle while the power d issipation at start up is
approximately 0.6 W, for a 230 Vrms input voltage.
This low value of star t-up dut y cycle prevents the
stress of the output rectifiers and of the
transformer when in short circuit.
The ex ter nal ca pac itor CVDD on the VDD pin mu st
be sized according to the time needed by the
converter to start up, when the device starts
switching. This time tSS depends on many
parameters, among which transformer design,
output capacitors, soft start feature and
compensation network implemented on the COMP
pin. The following formula can be used for defining
the minimum capacitor needed:
where:
IDD is the consumption current on the VDD pin
when switching. Refer to specified IDD1 and IDD2
values.
tSS is the start up time of the co nverter when the
device begins to switch. Worst case is generally at
full load.
VDDhyst is the voltage hysteresis of the UVLO
logic. Refer to the minimum specified value.
Soft start feature can be implemented on the
COMP pin through a simple capacitor which will
also be used as the compensation network. In this
case, the regu la tion lo op bandwidth is ra ther low,
because of the large value of this capacitor. In
case of a large regulation loop bandwidth is
mandatory, the schematics in figure 16 can be
used. It mixes a high performance compensation
network together with a separate high value soft
start cap acitor. Both soft sta rt time and regul ation
loop bandwidth can be adjusted separately.
If the d evice is intentionally shut down by putting
the COMP pin to ground, the device is also
performing start-up cycles, and the VDD voltage is
oscillating between VDDon and VDDoff.
This voltage can be used for supplying external
functions, provided that their consumption doesn’t
exceed 0.5mA. Figure 17 shows a typical
application of this function, with a latched shut
down. Once the "Shutdown" signal has been
activated , the de vice re mains in the off state unti l
the input voltage is removed.
CVDD IDDtSS
VDDhyst
--------------------------
>
Figure 15: Behavior of the high voltage current source at start-up
Ref.
UNDERVOLTAGE
LOCK OUT LOGIC
15 mA1 mA
3 mA
2 mA
15 mA
VDD DRAIN
SOURCE
VIPer20
Auxiliary primary
winding
VDD
t
VDDoff
VDDon
Start up duty cycle ~ 12%
CVDD
FC00101A
14/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer20/20A includes a transconductance
error amplifier. Transconductance Gm is the
change in output current (ICOMP) versus change in
input voltage (VDD). Thus:
The output impedance ZCOMP at the output of this
amplifier (COMP pin) can be defined as:
This last equation shows that the open loop gain
AVOL can be related to Gm and ZCOMP:
AVOL = Gm x ZCOMP
where Gm value for VIPer50/50A is 1.5 mA/V
typically.
Gmis well defined by specification, but ZCOMP and
therefore AVOL are subject to large tolerances. An
impedance Z can be connected between the
COMP pin and ground in order to define more
accurately the transfer function F of the error
amplifier, according to the following equation, very
similar to the one above:
F(S) = Gm x Z(S)
The error amplifier frequency response is reported
in figure 10 for different values of a simple
resistance connected on the COMP pin. The
unl oaded tr ansconduc tance er ror amp lifier s hows
an inte r na l ZCOMP of about 330 KΩ. More complex
impedance can be connected on the COMP pin to
achieve different compensation laws. A capacitor
will provide an integrator function, thus eliminating
the DC static error, and a resistance in series
leads to a fl at gain at hi gher fre quency, ins uring a
correct phase margin. This configuration is
illustrated in figure 18.
As show n in figu re 18 an a dditiona l noise filter ing
capacitor of 2.2 nF is generally needed to avoid
any high frequency interference.
It can also be interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50% . Figur e 19 shows
such a configuration. Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
polari ty from the oscil lator sawtooth.
EXT ERNAL CLOCK SYNCHRONIZATION
The OSC pin provides a synchronisation
capability, when connected to an external
frequency source. Figure 20 shows one possible
schematic to be adapted depending on the
specific needs. If the proposed schematic is used,
the pulse duration must be kept at a low value
(500ns is sufficient) for minimizing consumption.
The optocoupler must be able to provide 20mA
through the optotransistor.
PRI MARY PEAK CURRENT LI MITATION
The primary IDPEAK current and, as resulting
effect, the output power can be limited using the
simple circuit shown in figure 21. The circuit based
on Q1, R1 and R2 clamps the voltage on the
Gm∂ICOMP
∂VDD
------------------------
=
ZCOMP ∂VCOMP
∂ICOMP
--------------------------- 1
m
G
--------- ∂VCOMP
∂VDD
---------------------------
×
==
Figure 16: Mixed Soft Start and Compensation Figure 17: Latched Shut Down
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
R1
C1 +C2
D1
R2
R3
D2
D3
+C3
AUXILIARY
WINDING
FC00431
C4
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
Shutdown Q1
Q2
R1
R2R3
R4 D1
FC00440
15/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
COMP pin in order to limit the primary peak current
of the device to a value:
where:
The su ggeste d value for R1+R2 is in the range of
220KΩ.
OVER-TEMPERATURE PROTECTION:
Over-temperature protection is based on chip
temperature sensing. The minimum junction
temperature at which over-temperature cut-out
occurs is 140ºC while the typical value is 170ºC.
The device is automatically restarted when the
junction temperature decreases to the restart
temperature th resho ld that is typic ally 40ºC bel ow
the shutdown value (see figure 8).
IDPEAK VCOMP 0.5
–
HID
-------------------------------------
=
VCOMP 0.6 R1R2
+
R2
----------------------
×
=
Figure 18: Typical Compensation Network
Figure 20: External Clock Synchronization
Figure 19: Slope Compensation
Figure 21: Current Limitation Circuit Example
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
R1
C1
FC00451
C2
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
R1R2
Q1
C2
C1 R3
FC00461
C3
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
10 kΩ
FC00470
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPer20
R1
R2
Q1
FC00480
16/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
Figure 22: Input Volta ge Surg es Protec tion
ELECTRICAL OVER ST RESS RUGGE DNESS
The VIPer may be submitted to electrical over
stress caused by violent input voltage surges or
lightning. Following the enclosed Layout
Considerations chapter rules is the most of the
time sufficient to prevent catastrophic damages,
however in some cases the voltage surges
coupled throug h the transformer auxiliary winding
can overpass the VDD pin absolute maximum
rating voltag e value. S uch ev ents may trigg er the
VDD internal protection circuitry which could be
damaged by the strong discharge current of the
VDD bulk ca pac itor . T he si mp le R C fi lter show n in
figure 22 can be implemented to improve the
application immunity to such surges.
C1
Bulk capacitor
D1
R1
(Optional)
C2
22nF
Auxilliary winding
13V
OSC
COMPSOURCE
DRAIN
VDD
-
+
VIPerXX0
R2
39R
17/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
1
Figure 23: Re comme nded Layout
LAYOUT CONS IDERATIO NS
Some simple rules insure a correct running of
swit ching pow er suppli es. They m ay be classi fied
into two categories:
- To minimize power loops: the way the switched
power current must be carefully analyzed and
the corresponding paths must present the
smallest possible inner loop area. This avoids
radiated EMC noises, conducted EMC noises
by magnetic coupling, and provides a better
efficiency by eliminating parasitic inductances,
especially on secondary side.
- To use different tracks for low level signals and
power ones. T he interfe rence s due to a mi xing
of signal and power may result in instabilities
and/or anomalous behavior of the device in
case of violent power surge (Input overvoltages,
output short circuits...).
In case of VIPer, these rules apply as shown in
figure 23. The loops C1-T1-U1, C 5-D2-T1, C7-D1-
T1 must be minimized. C6 must be as close as
possible to T 1. The sign al co mponents C 2, ISO1,
C3 and C4 use a dedicated track to be connected
directly to the source of the device.
T1
U1
VIPerXX0
13V
OSC
COMP SOURCE
DRAINVDD
-
+
1
5
23
4
C4
C2
C5
C1
D2
R1
R2
D1
C7
C6
C3
ISO1
)URPLQSXW
GLRGHVEULGJH
7RVHFRQGDU\
ILOWHULQJDQGORDG
FC00500
18/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 3.35 3.65 0.132 0.144
A (*) 3.4 3.6 0.134 0.142
A1 0.00 0.10 0.000 0.004
B 0.40 0.60 0.016 0.024
B (*) 0.37 0.53 0.014 0.021
C 0.35 0.55 0.013 0.022
C (*) 0.23 0.32 0.009 0.0126
D 9.40 9.60 0.370 0.378
D1 7.40 7.60 0.291 0.300
E 9.30 9.50 0.366 0.374
E2 7.20 7.60 0.283 300
E2 (*) 7.30 7.50 0.287 0.295
E4 5.90 6.10 0.232 0.240
E4 (*) 5.90 6.30 0.232 0.248
e 1.27 0.050
F 1.25 1.35 0.049 0.053
F (*) 1.20 1.40 0.047 0.055
H 13.80 14.40 0.543 0.567
H (*) 13.85 14.35 0.545 0.565
h 0.50 0.002
L 1.20 1.80 0.047 0.070
L (*) 0.80 1 .10 0.031 0.043
α0º 8º 0º 8º
α (*) 2º 8º 2º 8º
PowerSO-10™ MECHANICAL DATA
(*) Muar only POA P013 P
DETAIL "A"
PLANE
SEATING
α
L
A1
F
A1
h
A
D
D1
= =
= =
E4
0.10 A
C
A
B
B
DETAIL "A"
SEATING
PLAN E
E2
10
1
eB
HE
0.25
P095A
19/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
11
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.11
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.91 5.21 0.193 0.205
G2 7.49 7.80 0.295 0.307
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 15.60 17.30 6.14 0.681
L1 14.60 15.22 0.575 0.599
L2 21.20 21.85 0.835 0.860
L3 22.20 22.82 0.874 0.898
L5 2.60 3 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 4.50 5.60 0.177 0.220
R 0.50 0.02
V4 90° (typ)
Diam 3.65 3.85 0.144 0.152
P023H3
PENTAW ATT HV MECHANICAL DATA
20/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
1
A
C
H2
H3
H1
L5
DIA
L3
L6
L7
F
G1
G2
LL1
D
R
M
M1
E
Resin bet ween
leads
V4
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.91 5.21 0.193 0.205
G2 7.49 7.80 0.295 0.307
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 16.42 17.42 0.646 0.686
L1 14.60 15.22 0.575 0.599
L3 20.52 21.52 0.808 0.847
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 5.00 5.70 0.197 0.224
R 0.50 0.020
V4 90° 90°
Diam. 3.70 3.90 0.146 0.154
PENTAWATT HV 022Y (VERTICAL HIGH PITCH) MECHANICAL DATA
21/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
DIM. mm.
MIN. TYP MAX.
A5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56
b2 1.14 1.52 1.78
c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.26
E1 6.10 6.35 7.11
e2.54
eA 7.62
eB 10.92
L 2.92 3.30 3.81
Packag e Weight Gr. 470
P001
Plasti c DI P-8 MECHANICAL DATA
22/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
1
PowerSO-10™ SUGGESTED PAD LAYOU T
1
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
All dimensions are in mm.
Base Q. ty 600
Bulk Q.ty 600
A (max) 330
B (min ) 1.5
C (± 0. 2) 13
F20.2
G (+ 2 / -0) 24.4
N (min ) 60
T (m ax) 30.4
TAPE DIM ENSI ONS
According to Electronic Industries Association
(EIA) Standard 481 r ev. A, Feb. 1986
A ll dimensions are in mm .
Tape width W 24
Tape Hole Spacing P 0 (± 0.1) 4
Com ponent Spacing P 24
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Com partm ent Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cov er tape.
User direction of feed
6.30
10.8 - 11
14.6 - 14.9
9.5
1
2
3
4
51.27
0.67 - 0.7 3
0.54 - 0.6
10
9
8
7
6
B
A
C
All di m ens ions are in m m .
Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0 .1 )
Casablanca 50 1000 532 10.4 16.4 0.8
Muar 50 1000 532 4.9 17.2 0.8
TUBE SHIPMENT (no suffix)
C
A
B
MUARCASABLANCA
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
23/25
1
PENTAWATT HV TUBE SHIPMENT (no suffix)
All dimensions are in mm.
Base Q.ty 50
Bulk Q.ty 1000
Tube length (± 0.5) 532
A18
B33.1
C (± 0.1) 1
C
B
A
24/25
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
1
DIP-8 TUBE SHIPMENT (no suffix)
A ll dime nsio ns are in mm.
Base Q.ty 20
Bulk Q.ty 1000
Tube length (± 0.5) 532
A8.4
B11.2
C (± 0.1) 0.8
A
B
C
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
25/25
1
Informat ion furnished is believed to be ac c ur ate and rel iable. Howev er, S TMicroelec troni c s as s um es n o r es ponsibility for the co nsequences
of use of such inf ormation nor for any infringement of patents or other rights of third parties which may results from its use. No license is
gran ted by im plication or otherwise unde r any patent or p atent rights of STMi c r oelectronics. Specific atio ns m entioned in this publication are
subj ec t to c hange without n otice. This publicat ion supers edes and replaces all information previously s upplied . STMi c r oelectronics produc ts
are not au thorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST log o is a trademark of STMicroelectronics
2002 STMicroelectronics - Printed in ITALY- All Rights Reserved.
STMicroelectronics GROUP OF C OMPANIES
Aust r alia - Brazil - Canada - Ch ina - Finland - France - Germ any - Hong Kong - India - Isr ael - Italy - J apan - Malay s ia -
Malta - Morocco - Singapore - Spain - Sw eden - Switzer land - Unite d K ingdom - U.S.A.
http://www.st.com