A p p li c a t io n N o t e , DS 1 , Ju l y 2 0 0 0 PEB20256 M u lt i c h a n n e l N e t w o r k I n t e r f a c e Controller for HDLC/PPP M UN I C H 2 5 6 V 2 . 1 PEB22554 Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications QuadFALC V1.3 D a ta C o m N e v e r s t o p t h i n k i n g . Edition 2000-07-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. MUNICH256 Confidential Revision History: 2000-07-01 DS1 Previous Version: Page Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com ABM(R), AOP(R), ARCOFI(R), ARCOFI(R)-BA, ARCOFI(R)-SP, DigiTape(R), EPIC(R)-1, EPIC(R)-S, ELIC(R), FALC(R)54, FALC(R)56, FALC(R)-E1, FALC (R)-LH, IDEC(R), IOM(R), IOM(R)-1, IOM (R)-2, IPAT(R)-2, ISAC(R)-P, ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P TE, ITAC(R), IWE(R), MUSAC(R)-A, OCTAT(R)-P, QUAT(R)-S, SICAT(R), SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4mC, SLICOFI(R) are registered trademarks of Infineon Technologies AG. ACETM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUTTM are trademarks of Infineon Technologies AG. Application Note Connection of MUNICH256 and QuadFALC Application Note 4 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Table of Contents Page 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 2.1 2.2 2.3 2.4 Hardware and Software Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Highway between M256 and QuadFALC . . . . . . . . . . . . . . . . . . . . . Register Setup for MUNICH256 for E1 and T1 Line Speed . . . . . . . . . . . Quadfalc Control Register Settings for E1 and T1 . . . . . . . . . . . . . . . . . . . T1 Channel Translation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Note 5 11 11 12 14 17 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Table of Contents Application Note Page 6 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC List of Tables Figure 1 Figure 2 Figure 3 Page Simple Multiport T1/E1 Linecard with MUNICH256 + QuadFALC(s). . . 9 PCM Highway connection between MUNICH256 and QuadFALC . . . 12 T1 Channel translation modes of QuadFALC . . . . . . . . . . . . . . . . . . . 17 Application Note 7 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC List of Tables Application Note Page 8 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Introduction 1 Introduction This application hint shows how to combine MUNCH256 and QuadFALC in a typical multiport T1/E1 application. The MUNICH256 offers logical 256 channels for HDLC/PPP or transparent protocol handling which can be assigned to a set of 16 ports. Running fully channelized ports (each 64-kbit/s timeslot is driven by one channel) allows the MUNICH256 to supply up to 8 E1 ports or 10 T1 ports. Up to the full 16 ports can be used if multiple timeslots are assigned to one single channel or if complete channels are driven in unchannelized T1/ E1 mode to support high speed links. The MUNICH256 terminates these lines and channels to a standard PCI interface. The QuadFALC is used as framer and line interface unit for the analog frontend to the MUNICH256. A required number of these QuadFALC devices can be connected directly to the PCM highway ports of the MUNICH256. Control of the QuadFALC framers can be done via the LBI or by a dedicated CPU on the LBI side. For details on the differences, refer to the application note "MUNICH256/F/FM Applications". passive Linecard Main Processor MUNICH256 PEB20256 PCM - Ports Bridge A PCI R QuadFALC PEB20554 LBI local System Bus QuadFALC PEB20554 M SPI EPR OM . . . QuadFALC PEB20554 M256_QF.emf Figure 1 Simple Multiport T1/E1 Linecard with MUNICH256 + QuadFALC(s) The block diagram in Figure 1 shows the integration of a passive T1/E1 linecard in a basic PCI system. This example implementation could be used for a cost-effective PCI Network Interface Controller (NIC) for PC-based applications. The basic principle is that there is no processor on the linecard. The peripherals on the card--the QuadFALCs in Application Note 9 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Introduction this case--are controlled by the main processor using the PCI-to-LBI bridge integrated into the MUNICH256/F/FM. The EEPROM is used to load a generic PCI configuration space. This enables the manufacturer of the card to provide unique identification of the board on the PCI bus. The MUNICH256 is always driven in E1 mode, even if a T1 line interface is needed. The adaptation from T1 on the analog side and E1 on the system interface side is done inside the QuadFALC, using one of the channel translation modes. In here, only 24 of the 32 E1 timeslots are used for data transmission. This mode provides high flexibility (for use in T1 or E1) with minimum differences in the setup of both devices. Alternatively for T1 only both, the MUNICH256 and the QuadFALC can also be driven in pure T1 mode (1.544 MBit/s). This document describes the physical connection and the register setup of one MUNICH256 PCM highway port to one core of the QuadFALC. Simply by scaling this on multiple ports and QuadFALC core units the number of ports can be increased easily. Application Note 10 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Hardware and Software Setup 2 Hardware and Software Setup 2.1 PCM Highway between M256 and QuadFALC Connection of the PCM Interface between the QuadFALC and the MUNICH256 can be accomplished in a variety of approaches: * Connect each port of the QuadFALC to separate MUNICH256 ports: The main benefit of this approach is that each port can run at a different speed. Thus, slight tolerances on the T1/E1 data rates will not affect other ports and SLIP situations in the QuadFALC Slip Buffer will be minimized or even eliminated. All available PCM speeds can be used. This document describes a PCM highway clock rate of 2.048 MHz for both, T1 and E1 (T1 via channel translation mode of the QuadFALC). * Connect all four ports of a QuadFALC to one PCM port of the MUNICH256: The main benefit of this implementation is a minimized set of connections between the MUNICH256 and QuadFALC devices and a minimized number of ports used on the MUNICH256. The PCM highway is configured to the 8.192 MBit/s clock rate in MUNICH256 and QuadFALC. Theoretically, the port density could be increased up to 64 (16 ports * 4). In reality, this condensed number of ports is limited by the maximum aggregate clock rate of all active ports (45 MBit/s with 33 MHz PCI and 90 Mbit/s with 66 MHz PCI). As the number of available channels in the MUNICH256 is limited to 256, this approach is primarily to be used for a high number of high-speed channels using multiple timeslots or even a complete T1/E1 port. One disadvantage of this solution is a potentially higher SLIP rate in the combined four T1/E1 lines. On the 8.192 Mbit/s PCM highway, the clock rate for all four T1/E1 links is fixed. This forces the four T1/E1 lines to run at an identical speed. For even slight tolerances from nominal T1/E1 speed, the SLIP buffers in the QuadFALC will have periodic overflows or underruns. * A subset of the second approach is the use of a 4.096 MBit/s PCM interface between the MUNICH256 and the QuadFALC, combining two T1/E1 ports onto one PCM highway. All advantages, disadvantages, and limitations of the second approach also apply to this variation. Because of limitations in different port speeds only the first issue will be explained further on. The other configurations apply to similar hardware setup and a slightly different register configuration. The hardware pin assignment for one single port is shown in Figure 2 below. As the basic principle the QuadFALC provides its receive clock SCLKR to both clock inputs of the MUNICH256, for transmitter and receiver. Both frame synchronization signals are driven by the RPC port of the QuadFALC which is programmed to provide the receive frame synchronization signal. Application Note 11 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Hardware and Software Setup MUNICH256 QuadFALC TD TDI TCLK TSP SCLKR RD RDO RCLK RSP RPC M256QFalc_pins.wmf Figure 2 2.2 PCM Highway connection between MUNICH256 and QuadFALC Register Setup for MUNICH256 for E1 and T1 Line Speed As mentioned above the MUNICH256 always operates in E1 port mode. T1 line speed is archieved by special channel translation in the QuadFALC device. Details on this are described below in Chapter 2.4. PMR Port mode register PCM3..0 1000 This bit field selects E1 mode (2.048 MHz) This setting is necessary for T1 mode too, because the Quadfalc clocking rate is still 2.048 MHz. TBS2..0 011 Transmit bit shift RBS2..0 100 Receive bit shift RIM 0 Enable receive synchronization error interrupt vector mask. Application Note 12 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Hardware and Software Setup TIM 0 Enable transmit synchronization error interrupt Vector mask. RXF 1 Receive data is sampled on the falling edge of the incoming receive clock. TXR 0 Transmit data is updated on the falling edge of the selected transmit clock. RSF 0 Sample receive synchronization pulse on the rising edge of the receive clock. TXF 0 Sample transmit synchronization pulse on the rising edge of the receive clock. Value: RPL 0 Disable remote payload loop. LPL 0 Disable local port loop. 0x80c42000 The following table shows the correspondence between programmed values (TBS2..0, RBS2..0) and bit shift. Table 1 Bitshift and Register Setting Correspondence Application Note Programmed Value Bit Shift 000B -4 001B -3 010B -2 011B -1 100B 0 101B 1 110B 2 111B 3 13 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Hardware and Software Setup 2.3 Quadfalc Control Register Settings for E1 and T1 The following Register setup is necessary to configure the QuadFALC system interface so that it fits to the MUNICH256 as setup and described above. Some register settings are printed in grey colour and apply to QuadFALC chip version 1.1 only. GPC1: Global port configuration 1 CSFP1..0: 11 Value*: 0x60 IPC: FSC pulse is output active low Interrupt port configuration IC1..0: 01 These bits define the function of the interrupt output stage (pin INT) to Push/pull output, active low. Value: PC1..4: 0x01 Port configuration 1-4 RPC 2..0: Receive multifunction port configuration for ports RP(A-D). XPC 2..0: Transmit multifunction port configuration for ports XP(A-D). PC1: RPC2..0: 011 RPA is output RSIGM. XPC2..0: 101 XPA is output XSIGM. Value: 0x35 PC1**: RPC2..0: 000 RPA is intput SYPRQ. XPC2..0: 000 XPA is intput SYPXQ. Value: 0X00 PC2: RPC2..0: 011 RPB is output RSIGM. XPC2..0: 101 XPB is output XSIGM. Value: 0x35 PC3: RPC2..0: 001 RPC is output receive frame sync, RFM. This pin is connected to the TSP abd RSP pins of M256 for each each Port. XPC2..0 111 Value: 0x17 Application Note XPC is output transmit line clock XCLK. 14 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Hardware and Software Setup PC4: RPC2..0: 011 RPD is output RSIGM XPC2..0: 101 XPD is output XSIGM Value: 0x35 PC5: Port configuration 5 CSRP: 1 Config SCLKR Port as output. This pin is connected to the TCLK and RCLK pins of M256 for each port. CRP: 1 Value*: 0x03 Config RCLK port as output. CMR1: Clock mode register 1 Value: Falcnumber * 0x40 This register selects the reference clock for the DCO-R circuitry. Here the recovered clock from the corresponding line interface input is used. CMR2: Clock mode register 2 IRSP 1 The frame sync pulse for the receive system interface is internally sourced by the DCO-R circuitry of each channel. This internally generated frame sync could be output active low. on pin RP(A-D). RPC(2-0) = 001 IRSC 1 The working clock for the receive system interface is sourced internally. IXSP 1 The frame sync pulse for the receive system interface is sourced internally. IXSC 1 The working clock for the transmit system interface is sourced internally by the working clock of the receive system interface. DCF 0 Center Frequency enable 1** inverted implementation in QuadFALC V1.1 Value*: SIC1 0x0F / 0x1F** System interface control 1 SSC1..0 00 2.048 MHz clocking rate on the system highway. This clocking rate is necessary for M256 (E1/T1) Application Note 15 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Hardware and Software Setup SIC1.SSD1 0 FMR1.SSD0 0 and define the data rate on the system Highway to 2.048 Mbit/s. RBS1..0 00 Value*: 0x02 SIC3 Receive Buffer Size : 2 frames System interface control 3 RESX 1 Depending on this bit all transmit system interface data and marker are clocked off or sampled with the rising edge of transmit synchronous pulse. This setting is necessary for M256 (E1/T1) RESR 1 Depending on this bit all receive system interface data and marker are clocked off or sampled with the rising edge of receive synchronous pulse. This setting is necessary for M256 (E1/T1) Value*: XC0, XC1 0x0C Transmit offset configuration Value XC0: 0x00 Value XC1: 0x03 RC0,RC1 Receive offset configuration Value RC0: 0x0C Value RC1: 0x04 FMR1 Framer mode register 1 PMOD 0 PCM 30 or E1 mode. 1 PCM 24 or T1 mode. CTM 0 Channel translation mode 0 (for T1 mode) CTM 1 Channel translation mode 1 (for T1 mode) ECM 0/1 Error Counter Mode Dis/Enable secondly Clearing of Error Counters FMR1.SSD0 0 and SIC1.SSD1 0 define the data rate on the system Highway to 2.048 Mbit/s. Application Note 16 2000-07-01 Application Note Connection of MUNICH256 and QuadFALC Hardware and Software Setup Value*(E1): 0x48 (0x4C with ECM=1) Value*(T1): 0x98 (0x9C with ECM=1) *)Value includes other settings. **)Only for QuadFALC 22554 V1.1 2.4 T1 Channel Translation Modes For T1 line clocking rate is always 1.544 MHz. As mentioned earlier in this document, the system interface always operates at E1 speed (2.048 MBit/s). For T1 line speed the 24 received time-slots are translated into the 32 system time-slots in two different channel translation modes (FMR1.CTM): Figure 3 T1 Channel translation modes of QuadFALC Application Note 17 2000-07-01 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG