CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36
Synchronous Dual-Port RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-06070 Rev. *M Revised December 4, 2012
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synch ronous Dual- Port RAM
Features
■True dual-ported memory cells that allow simultaneous access
of the same memory location
■Synchronous pipelined operation
■Organization of 2-Mbit, 4-Mbit, and 9-Mbit devices
■Pipelined output mode allows fast operation
■0.18-micron Complimentary metal oxide semiconductor
(CMOS) for optimum speed and power
■High-speed clock to data access
■3.3 V low powe r
❐Active as low as 225 mA (typ)
❐Standby as low as 55 mA (typ)
■Mailbox function for message passing
■Global master reset
■Separate byte enables on both ports
■Commercial and industrial temperature ranges
■IEEE 1149.1-compatible Joint test action group (JTAG)
boundary scan
■172-Ball fine-pitch ball grid array (FBGA) (1 mm pitch)
(15 mm × 15 mm)
■176-Pin thin quad plastic flatpack (TQFP)
(24 mm × 24 mm × 1.4 mm)
■Counter wrap around control
❐Internal mask register controls counter wrap-around
❐Counter-interrupt flags to indicate wrap-around
❐Memory block retransmit operation
■Counter readback on address lines
■Mask register readback on address lines
■Dual chip enables on both ports for ea sy depth expansion
Functional Description
The FLEx36™ family includes 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3 V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). Th e internal Write pulse width is independe nt
of the duration of the R/W input signal. Th e internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853V/CY7C0853AV device in this fa mily has limited
features. Please see Address Counter and Mask Register
Operations on page 9 for details.
Product Selection Guide
Density 2-Mbit (64 K × 36) 4-Mbit (128 K × 36) 9-Mbit (256 K × 36)
Part number CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV
Max. speed (MHz) 167 167 133
Max. access time - clock to data (ns) 4.0 4.0 4.7
Typical operating current (mA) 225 225 270
Package 176-pin TQFP, 172-ball FBGA 176-pin TQFP, 172-ball FBGA 172-ball FBGA
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 2 of 39
Logic Block Diagram
The Logic Block Diagram is as follows. [1]
A0L–A17L
CLKL
ADSL
CNTENL
CNTRSTL
True
RAM Array
18
Addr.
Read
Back
CNTINTL
Mask Register
Counter/
Address
Register
CNT/MSKL
Address
Decode
Dual-Ported
Interrupt
Logic
INTL
Reset
Logic JTAG TDO
TMS
TCK
TDI
MRST
DQ9L–DQ17L
DQ0L–DQ8L
I/O
Control
9
9
9
9
DQ18L–DQ26L
DQ27L–DQ35L
CE0L
CE1L
R/WL
B0L
B1L
B2L
B3L
OEL
A0R–A17R
CLKR
ADS
CNTEN
CNTRSTR
18
Addr.
Read
Back
CNTINTR
Mask Register
Counter/
Address
Register
CNT/MSKR
Address
Decode
Interrupt
Logic INTR
DQ9R–DQ17R
DQ0R–DQ8R
I/O
Control 9
9
9
9DQ18R–DQ26R
DQ27R–DQ35R
CE0R
CE1R
R/WR
B0R
B1R
B2R
B3R
OER
Mirror Reg Mirror Reg
Note
1. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 addr ess bits.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 3 of 39
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................7
Master Reset .....................................................................8
Mailbox Interrupts ............................................................8
Address Counter and Mask Register Operations ..........9
Counter Reset Operation ............................................9
Counter Load Operation ..............................................9
Counter Readback Operation ......................................9
Counter Increment Operation ......................................9
Counter Hold Operation ..............................................9
Counter Interrupt .......................................................10
Retransmit .................................................................10
Mask Reset Operation ...............................................10
Mask Load Operation ................................................10
Mask Readback Operation ........................................10
Counting by Two ...... .............. ... ... .............. ... ............10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................13
Performing a TAP Reset ...........................................13
Performing a Pause/Restart ......................................13
Identification Register Definitions ................................13
Scan Registers Sizes .....................................................13
Instruction Identification Codes ....................................13
Maximum Ratings ...........................................................14
Operating Range ..................... .. .............. ... .............. ... ....14
Electrical Characteristics ........... .............. ... .. .................14
Capacitance ....................................................................15
AC Test Load and Waveforms .......................................15
Switching Characteristics ..............................................16
JTAG Timing ...................................................................18
Switching Waveforms ....................................................19
Ordering Information ......................................................31
256 K × 36 (9 M) 3.3 V Synchronous
CY7C0853V/CY7C0853AV Dual-Port SRAM ...................31
128 K × 36 (4 M) 3.3 V Synchronous
CY7C0852V/CY7C0852AV Dual-Port SRAM ...................31
64 K × 36 (2 M) 3.3 V Synchronous
CY7C0851V/CY7C0851AV Dual-Port SRAM ...................31
Ordering Code Definitions .........................................32
Package Diagrams ..........................................................33
Acronyms ........................................................................ 36
Document Conventions ........................... ... .. .............. ...36
Units of Measure .................................................. .. ...36
Document History Page ....... ... .............. ... ... .............. .. ...37
Sales, Solutions, and Legal Information ......................39
Worldwide Sales and Design Support .......................39
Products .................................................................... 39
PSoC Solutions ................................... ... .. .............. ...39
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 4 of 39
Pin Configurations
Figure 1. 172-ball BGA pinout (Top View)
1234567891011121314
ADQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R
BA0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R
CNC A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R NC
DA2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R
EA4L A5L CE1L B0L VDD VSS VDD VDD B0R CE1R A5R A4R
FVDD A6L A7L B1L VDD VSS B1R A7R A6R VDD
GOEL B2L B3L CE0L CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0851AV
CE0R B3R B2R OER
HVSS R/WLA8LCLKL CLKR A8R R/WR VSS
JA9L A10L VSS ADSL VSS VDD ADSR MRST A10R A9R
KA11L A12L A15L[2] CNTRSTL VDD VDD VSS VDD CNTRSTR A15R[2] A12R A11R
LCNT/MSKL A13L CNTENL DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R CNTENR A13R CNT/MSKR
MA16L[2] A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R[2]
NDQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R
PDQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R
Note
2. For CY7C0851V/CY7C0851AV, pins M1 and M14 are NC.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 5 of 39
Figure 2. 172-ball BGA pinout (Top View)
Pin Configurations (continued)
1234567891011121314
ADQ32L DQ30L NC VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS NC DQ30R DQ32R
BA0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R
CA17L A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R A17R
DA2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R
EA4L A5L VDD B0L VDD VSS VDD VDD B0R VDD A5R A4R
FVDD A6L A7L B1L VDD VSS B1R A7R A6R VDD
GOEL B2L B3L VSS CY7C0853V/CY7C0853AV VSS B3R B2R OER
HVSS R/WL A8L CLKL CLKR A8R R/WRVSS
JA9L A10L VSS VSS VSS VDD VSS MRST A10R A9R
KA11L A12L A15L VDD VDD VDD VSS VDD VDD A15R A12R A11R
LVDD A13L VSS DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R VSS A13R VDD
MA16L A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R
NDQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R
PDQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 6 of 39
Figure 3. 176-pin TQF P pinout (Top View)
Pin Configurations (continued)
132
131
130
129
128
127
126
125
124
123
122
104
121
120
119
118
117
116
115
114
113
112
111
110
109
103
108
107
106
105
NC
A6R
A5R
A4R
VDD
VSS
DQ35R
DQ34R
A1R
A2R
A3R
A0R
A7R
B0R
B1R
CE1R
B2R
B3R
OER
CE0R
VDD
VDD
VSS
VSS
R/WR
CLKR
MRST
ADSR
CNTENR
A8R
CNTRSTR
CNT/MSKR
A9R
A10R
A11R
A12R
VSS
VDD
A13R
A14R
A15R[2]
A16R[2]
DQ24R
DQ20R
NC
A6L
A5L
A4L
VDD
VSS
DQ35L
DQ34L
A1L
A2L
A3L
A0L
A7L
B0L
B1L
CE1L
B2L
B3L
OEL
CE0L
VDD
VDD
VSS
VSS
R/WL
CLKL
VSS
ADSL
CNTENL
A8L
CNTRSTL
CNT/MSKL
A9L
A10L
A11L
A12L
VSS
VDD
A13L
A14L
A15L[2]
A16L[2]
DQ24L
DQ20L
DQ33L
DQ32L
DQ31L
VDD
VSS
DQ30L
DQ28L
DQ29L
DQ27L
INTL
CNTINTL
DQ16L
DQ15L
DQ17L
DQ14L
DQ13L
VSS
VDD
DQ12L
DQ11L
DQ10L
DQ9L
DQ9R
DQ10R
DQ11R
DQ12R
VDD
VSS
DQ13R
DQ14R
DQ17R
DQ15R
DQ16R
CNTINTR
INTR
DQ27R
DQ29R
DQ28R
DQ30R
VSS
VDD
DQ31R
DQ32R
DQ33R
DQ26L
DQ23L
DQ22L
VDD
VSS
DQ21L
DQ25L
DQ19L
DQ18L
TDI
TDO
DQ8L
DQ7L
DQ6L
DQ5L
DQ4L
VSS
VDD
DQ3L
DQ2L
DQ1L
DQ0L
DQ0R
DQ1R
DQ2R
DQ3R
VDD
VSS
DQ4R
DQ5R
DQ6R
DQ7R
DQ8R
TMS
TCK
DQ18R
DQ19R
DQ25R
DQ21R
VSS
VDD
DQ22R
DQ23R
DQ26R
102
91
101
100
99
98
97
96
90
95
94
93
92
89
1
2
3
4
5
6
7
8
9
10
11
29
12
13
14
15
16
17
18
19
20
21
22
23
24
30
25
26
27
28
31
42
32
33
34
35
36
37
43
38
39
40
41
44
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 7 of 39
Pin Definitions
Left Port Right Port Description
A0L–A17L[3] A0R–A17R[3] Address inputs.
ADSL[4] ADSR[4] Address strobe input. Used as an address qualifier . This signal should be asserted LOW for the part
using the externally supplied address on the address pins and for loading this address into the burst
address counter.
CE0L[4] CE0R[4] Active LOW chip enable input.
CE1L[4] CE1R[4] Active HIGH chip enable input.
CLKLCLKRClock sign al. Maximum clock input rate is fMAX.
CNTENL[4] CNTENR[4] Counter enable input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL[4] CNTRSTR[4] Counter reset input. Asserting this signal LOW resets to zero the unmasked portion of the burst
address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN.
CNT/MSKL[4] CNT/MSKR[4] Address counter mask register enable input. Asserting this signal LOW enables access to the
mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
DQ0L–DQ35L DQ0R–DQ35R Data bus input/output.
OELOEROutput enable input. This asynchronous sig nal must be asserted LOW to enable the DQ da ta pins
during Read operations.
INTLINTRMailbox interrupt flag output. The mailbox permits communications between ports. The upper two
memory locations can be used for message passing. INTL is asserted LOW when the right port writes
to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when
it reads the contents of its mailbox.
CNTINTL[4] CNTINTR[4] Counter interrupt output. This pin is asserted LOW when the u nmasked portion of the counter is
incremented to all “1s.”
R/WLR/WRRead/Write enable input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory
array.
B0L–B3L B0R–B3R Byte select inputs. Asserting these signals enables Read and Write operations to the corresponding
bytes of the memory array.
MRST Master reset input. MRST is an asynchron ous input sig nal and affects both ports. Asserting MRST
LOW performs all of the reset functions as described in the text. A MRST operation is required at
power up.
TMS JTA G test mode select input. It controls the advance of JTAG TAP state machine. State machine
transitions occur on the rising edge of TCK.
TDI JTAG test data input. Data on the TDI input is shifted serially into selected registers.
TCK JTAG test clock input.
TDO JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS Ground inputs.
VDD Power inputs.
Notes
3. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits.
4. These pins are not available for CY7C0853V/CY7C0853AV device.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 8 of 39
Master Reset
The FLEx36 family devices un dergo a comp lete reset by taking
its MRST input LOW. The MRST input can switch
asynchronously to the cloc ks. The MRST initializes the internal
burst counters to zero, and the counter mask registers to all ones
(completely unmasked). The MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. The MRST must be performed on the FLEx36 family
devices after power up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 1
shows the interrupt operation for both ports of
CY7C853V/CY7C0853A V. The highest memory location, 3FFFF
is the mailbox for the right port and 3FFFE is the mailbox for the
left p ort. Table 1 shows that in order to set the INTR flag, a Write
operation by the le ft port to address 3FFFF a sserts INTR LOW.
At least one byte has to be active for a Write to generate an
interrupt. A valid Read of the 3FFFF location by the right port
resets INTR HIGH. At least one byte has to be active in order for
a Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to is
asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the conten ts of the mailbox. The i nterrupt flag is
set in a flow-thru mode (that is it follows the clock edge of the
writing port). Also , the flag is re set i n a flow-thru mod e (that i s it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an app lication doe s not require message
passing, INT pins should be left open.
Table 1. Interrupt Operation Example [5, 6, 7, 8, 9]
Function Left Port Right Port
R/WLCELA0L–17LINTLR/WRCERA0R–17R INTR
Set right INTR flag L L 3FFFF X X X X L
Reset right INTR flag X X X X H L 3FFFF H
Set left INTL flag X X X L L L 3FFFE X
Reset left INTL flag H L 3FFFE H X X X X
Table 2. Address Counter and Counter-Mas k Register Control Operation (Any Port) [10, 11]
CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description
XLXXXXMaster resetReset address counter to all 0s and mask
register to all 1s.
H H L X X Counter reset Reset counter unmasked portion to all 0s.
H H H L L Counter load Load counter with external address value
presented on address lines.
H H H L H Counter readback Read out cou nter internal value on address
lines.
HHHHLCounter incrementInternally increment address counter value.
HHHHHCounter holdConstantly hold the address value for
multiple clock cycles.
H L L X X Mask reset Reset mask register to all 1s.
H L H L L Mask load Load mask register with value presented on
the address lines.
H L H L H Mask readback Read out mask register value on address
lines.
H L H H X Reserved Operation undefined
Notes
5. 9 M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits.
6. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be assert ed once at the rising edge of the CLK and
can be deasserted after that. Data is out after the following CLK edge and is three-state d after the next CLK edge.
7. OE is “Don’t Care” for mailbox operation.
8. At least one of B0, B1, B2, or B3 must be LOW.
9. A16x is a NC for CY7C0851V/CY7C0851AV, therefore the Interrupt Addresses are FFFF and FFFE.
10.“X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
11. Counter operation and mask register operation is independent of chip enables.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 9 of 39
Address Counter and Mask Register
Operations
This section [12] describes the features only apply to CY7C0851V
/ CY7C0851A V / CY7C0852V / CY7C0852A V devices, but not to
the CY7C0853V/CY7C0853AV device. Each port of these
devices has a programmable burst address counter. The burst
counter contains three registers: a counter register, a mask
register, and a mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Loa d, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Ma sk Reset operations, and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register in to two regions: zero or
more “0s” in the most signific ant bits define the masked region,
one or more “1s” in the least significant bits define the unmasked
region. Bit 0 may also be “0”, masking the least significant
counter bit and causing the counter to increment by two instead
of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit”, below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load operation, and by the MRST.
Tab le 2 on page 8 summarizes the opera tion of these registers
and the required input control signal s. The MRST control signal
is asynchronous. All the other control signals in Table 2 on page
8 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNT EN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This will Read/Write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to 0s. A counter-mask
register is us ed to cont ro l the counter wrap.
Counter Reset Operation
All unmasked bits of the counter are reset to “0.” All masked bits
remain unchanged. The mirror register is loaded with the value
of the burst counter. A Mask Reset followed by a Counter Reset
will reset the counter and mirror registers to 00000, as will master
reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Readb ack Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid tCA2
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) is three-stated. Figure 4 on page 11 shows a
block diagram of the operation.
Counter Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a “1” for a
counter bit to change. The counter registe r is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are “1”, the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being “1s”, a counter interrupt flag
(CNTINT) is asserted. The next Increment returns the counter
register to its initial value, which was stored in the mirror register .
The counter address can i nstead be forced to lo op to 00000 by
externally connecting CNTINT to CNTRST.[13] An increment that
results in one or more of the unmasked bits of the counter being
“0” deasserts the counter interrupt flag. The example in Figure 5
on page 12 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB
and bit “16” as the MSB. The maximum value the mask reg ister
can be loaded with is 1FFFFh. Setting the mask re gister to this
value allows the counter to access the entire memory space. The
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
once the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments it s
internal address value till it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT is issued when th e counter reaches
its maximum value.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Notes
12.This section describes the CY7C0852V/CY7C0852AV, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851V/CY7C0851AV has 16
address bits, register lengths of 16 bits, and a maximum address value of FFFF.
13.CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operat i ng frequency when tied together.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 10 of 39
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, C ounter Load, Mask Reset and
Mask Load operations, and by MRST.
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal “mirror register” is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this “mirror
register”. If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the “mirror register”. Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Mask Reset Operation
The mask register is reset to all “1s”, which unmasks every bit of
the counter. Master reset (MRST) also resets the mask register
to all “1s”.
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment
operations. Permitted values are of the form 2n – 1 or 2n – 2.
From the most significant bit to the least significant bit, permitted
values have zero or more “0s”, one or more “1s”, or one “0”. Thus
1FFFF, 003FE, and 00001 are permitted values, but 1F0FF,
003FC, and 00000 are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readb ack is pipelined; the address is valid t CM2
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) is three-stated. Figure 4 on page 11 shows a
block diagram of the operation.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV as a
72-bit single port SRAM in which the counter of one port counts
even addresses and the counter of the other port counts odd
addresses. This even-odd address scheme stores one half of the
72-bit data in even memory locations, and the other half in odd
memory locations.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 11 of 39
Figure 4. Counter, Mask, and Mirror Logic Block Diagram [14]
From
Mask
Register
Mirror Counter
Address
Decode RAM
Array
Wrap
1
0
Increment
Logic
1
0
+1
+2
1
0
Wrap
Detect
From
Mask
From
Counter
To Counter
Bit 0
Wrap
17 17
17
17
17
1
0
Load/Increment
CNT/MSK
CNTEN
ADS
CNTRST
CLK
Decode
Logic
Bidirectional
Address
Lines Mask
Register
Counter/
Address
Register
From
Address
Lines To Readback
and Address
Decode
17
17
MRST
Note
14.9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits .
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 12 of 39
Figure 5. Programmabl e Counter-Mask Register Operation [15, 16]
216 215 2621
2522
242320
216 215 2621
2522
242320
216 215 2621
2522
242320
216 215 2621
2522
242320
H
H
L
H
11
0s 1
01
0101
00
Xs 1
X0
X0X0
11
Xs 1
X1
X1X1
00
Xs 1
X0
X0X0
Masked Address Unmasked Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Notes
15.9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits .
16.The “X” in this diagram represents the counter upper bits.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 13 of 39
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C0851V / CY7C0851AV / CY7C0852V / CY7C 08 52AV /
CY7C0853V / CY7C0853AV incorporates a n IEEE 1149.1 serial
boundary scan [17] test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1-compliant TAPs. The TA P operates
using JEDEC-standard 3.3 V I/O logic levels. It is compo sed of
three input connections and one output connection re quired by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by fo rcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the devices are operating.
An MRST must be performed on the devices after power-up.
Performing a Pause/Restart
When a SHIFT -DR P AUSE-DR SHIFT -DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester should be configured to never enter the PAUSE-DR state.
Identification Register Definitions
Instruction Field Value Description
Revision number (31:28) 0h Reserved for version number.
Cypress device ID (27:12) C001h Defines Cypress part number for the CY7C0851V/CY7C 0851AV
C002h Defines Cypress part number fo r the CY7C0852V/CY7C0852AV and
CY7C0853V/CY7C0853AV
Cypress JEDEC ID (11:1) 034h Allows unique identification of the DP family device vendor.
ID register presence (0) 1 Indicates the presence of an ID register.
Scan Registers Sizes
Register Name Bit Size
Instruction 4
Bypass 1
Identification 32
Boundary Scan n[18]
Instruction Identification Codes
Instruction Code Description
EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS 1111 Places the BYR between TDI and TDO.
IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ 0111 Places BYR between TDI and TDO. Forces all CY7C0851AV / CY7C0852AV /
CY7C0853AV output drivers to a High Z state.
CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD 1000 Captures the input/output rin g contents. Places BSR between TDI and TDO.
NBSRST 1100 Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED All other codes Other combinations are reserved. Do not use other than the ab ove.
Notes
17.Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
18.See details in the device BSDL files.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 14 of 39
Maximum Ratings
Exceeding maximum ratings [19] may imp air the useful life of the
device. These user guidelines are not tested.
Storage temperature ......................... ..... –65 °C to + 150 °C
Ambient temperature with
Power applied .........................................–55 °C to + 125 °C
Supply voltage to ground potential .............–0.5 V to + 4.6 V
DC voltage applied to
Outputs in High Z state ....... ... ... ..........–0.5 V to VDD + 0.5 V
DC input voltage ...........................–0.5 V to VDD + 0.5 V [20]
Output current into outputs (LOW) .............................20 mA
Static discharge voltage
(JEDEC JESD22-A114-2000B) ..............................> 2000 V
Latch-up current ....................................................> 200 mA
Operating Range
Range Ambient Temperature VDD
Commercial 0 °C to +70 °C 3.3 V ± 165 mV
Industrial –40 °C to +85 °C 3.3 V ± 165 mV
Electrical Characteristics
Over the Operating Range
Parameter Description -167 -133 -100 Unit
Min Typ Max Min Typ Max Min Typ Max
VOH Output HIGH voltage (VDD = Min., IOH= –4.0 mA) 2.4 – – 2.4 – – 2.4 – – V
VOL Output LOW voltage (VDD = Min., IOL= +4.0 mA) – – 0.4 – – 0.4 – – 0.4 V
VIH Input HIGH voltage 2.0 – – 2.0 – – 2.0 – – V
VIL Input LOW voltage – – 0.8 – – 0.8 – – 0.8 V
IOZ Output leakage current –10 – 10 –10 – 10 –10 – 10 A
IIX1 Input leakage current except TDI, TMS, MRST –10 – 10 –10 – 10 –10 – 10 A
IIX2 Input leakage current TDI, TMS, MRST –0.1 – 1.0 –0.1 – 1.0 –0.1 – 1.0 mA
ICC Operating current for
(VDD = Max.,IOUT = 0 mA),
Outputs disabled
CY7C0851V /
CY7C0851AV /
CY7C0852V /
CY7C0852AV
– 225 300 – 225 300 – – – mA
CY7C0853V /
CY7C0853AV – – – – 270 400 – 200 310
ISB1[21] Standby current (both ports TTL level)
CEL and CER VIH, f = fMAX –90115–90115–90115mA
ISB2[21] Standby current (one port TTL level)
CEL | CER VIH, f = fMAX – 160 210 – 160 210 – 160 210 mA
ISB3[21] Standby current (both ports CMOS level)
CEL and CER VDD – 0.2 V, f = 0 –5575–5575–5575mA
ISB4[21] Standby current (one port CMOS level)
CEL | CER VIH, f = fMAX – 160 210 – 160 210 – 160 210 mA
ISB5 Operating current
(VDD = Max, IOUT = 0 mA, f = 0)
Outputs disabled
CY7C0853V /
CY7C0853AV – – – – 70 100 – 70 100 mA
Notes
19.The voltage on any input or I/O pin can not exceed the power pin during power up.
20.Pulse width < 20 ns.
21.ISB1, ISB2, ISB3 and ISB4 are not applicable for CY7C0853V / CY7C0853AV because it can not be powered down by using chip enable pins.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 15 of 39
Capacitance
Part Number [22] Parameter Description Test Conditions Max Unit
C Y 7 C 0 8 5 1 V / CY7C0851A V /
CY7C0852V / CY7 C0852A V CIN Input capacitance TA = 25 °C, f = 1 MHz,
VDD = 3.3 V 13 pF
COUT Output capacitance 10 pF
CY7C0853V / CY7C0853AV CIN Input capacitance 22 pF
COUT Output capacitance 20 pF
AC Test Load and Waveforms Figure 6. AC Test Load and Waveforms
R1 = 590
R2 = 435
C = 5 pF
(b) Three-state Delay (Load 2)
90%
10%
3.0 V
VSS
90%
10%
<2ns <2ns
ALL INPUT PULSES
3.3 V
VTH = 1.5 V
R = 50
Z0 = 50
(a) Normal Load (Load 1)
C = 10 pF
OUTPUT
OUTPUT
Note
22.COUT also references CI/O.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 16 of 39
Switching Characteristics
Over the Operating Range
Parameter Description
-167 -133 -100
Unit
CY7C0851V /
CY7C0851AV /
CY7C0852V /
CY7C0852AV
CY7C0851V /
CY7C0851AV /
CY7C0852V /
CY7C0852AV
CY7C0853V /
CY7C0853AV CY7C0853V /
CY7C0853AV
Min Max Min Max Min Max Min Max
fMAX2 Maximum operating freque ncy – 167 – 133 – 133 – 100 MHz
tCYC2 Clock cycle time 6.0 – 7.5 – 7.5 – 1 0.0 – ns
tCH2 Clock HIGH time 2.7–3.0–3.0–4.0–ns
tCL2 Clock LOW time 2.7–3.0–3.0–4.0–ns
tR[23] Clock rise time –2.0–2.0–2.0 –3.0ns
tF[23] Clock fall time – 2.0 – 2.0 – 2.0 – 3.0 ns
tSA Address setuptime 2.3–2.5–2.5–3.0–ns
tHA Address hold time 0.6–0.6–0.6–0.6–ns
tSB Byte select setup time 2.3–2.5–2.5–3.0–ns
tHB Byte select hold time 0.6–0.6–0.6–0.6–ns
tSC Chip enable setup time 2.3 – 2.5 – NA – NA – ns
tHC Chip enable hold time 0.6 – 0.6 – NA – NA – ns
tSW R/W setup time 2.3–2.5–2.5–3.0–ns
tHW R/W hold time 0.6–0.6–0.6–0.6–ns
tSD Input data setup time 2.3 – 2.5 – 2.5 – 3.0 – ns
tHD Input data hold time 0.6 – 0.6 – 0.6 – 0.6 – ns
tSAD ADS setup time 2.3 – 2.5 – NA – NA – ns
tHAD ADS hold time 0.6 – 0.6 – NA – NA – ns
tSCN CNTEN setup time 2.3 – 2.5 – NA – NA – ns
tHCN CNTEN hold time 0.6 – 0.6 – NA – NA – ns
tSRST CNTRST setup time 2.3 – 2 .5 – NA – NA – ns
tHRST CNTRST hold time 0.6–0.6–NA–NA–ns
tSCM CNT/MSK setup time 2.3 – 2 .5 – NA – NA – ns
tHCM CNT/MSK hold time 0.6 – 0.6 – NA – NA – ns
tOE Output enable to data valid – 4.0 – 4.4 – 4.7 – 5.0 ns
tOLZ[24, 25] OE to Low Z 0–0–0–0–ns
tOHZ[24, 25] OE to High Z 04.004.404.7 05.0ns
tCD2 Clock to data valid –4.0–4.4–4.7 –5.0ns
tCA2 Clock to counter address valid – 4.0 – 4.4 – NA – NA ns
tCM2 Clock to mask register readback
valid –4.0–4.4–NA–NAns
tDC Data output hold after clock HIGH 1.0 – 1.0 – 1.0 – 1.0 – ns
Note
23.Except JTAG signals (tr and tf < 10 ns [max.]).
24.This parameter is guaranteed by design, but it is not production tested.
25.Test conditions used are Load 2.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 17 of 39
tCKHZ[26, 27] Clock HIGH to output Hig h Z 0 4.0 0 4.4 0 4.7 0 5.0 ns
tCKLZ[26, 27] Clock HIGH to output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns
tSINT Clock to INT set time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
tRINT Clock to INT reset time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
tSCINT Clock to CNTINT set time 0.5 5.0 0.5 5.7 NA NA NA NA ns
tRCINT Clock to CNTINT reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns
Port to Port Delays
tCCS Clock to clock skew 5.2–6.0–6.0–8.0–ns
Master Reset Timing
tRS Master reset pulse width 7.0 – 7.5 – 7.5 – 10.0 – ns
tRSS Master reset setup time 6.0–6.0–6.0–8.5–ns
tRSR Master reset recovery time 6.0 – 7.5 – 7.5 – 10.0 – ns
tRSF Master reset to outputs inactive – 10.0 – 10.0 – 10.0 – 10.0 ns
tRSCNTINT Master reset to counter interrupt
flag reset time –10.0–10.0– NA – NAns
Switching Characteristics (continued)
Over the Operating Range
Parameter Description
-167 -133 -100
Unit
CY7C0851V /
CY7C0851AV /
CY7C0852V /
CY7C0852AV
CY7C0851V /
CY7C0851AV /
CY7C0852V /
CY7C0852AV
CY7C0853V /
CY7C0853AV CY7C0853V /
CY7C0853AV
Min Max Min Max Min Max Min Max
Notes
26.This parameter is guaranteed by design, but it is not production tested.
27.Test conditions used are Load 2.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 18 of 39
JTAG Timing
Parameter Description 167/133/100 Unit
Min Max
fJTAG Maximum JTAG TAP controller frequency – 10 MHz
tTCYC TCK clock cycle time 100 – ns
tTH TCK clock HIGH time 40 – ns
tTL TCK clock LOW Time 40 – ns
tTMSS TMS setup to TCK clock rise 10 – ns
tTMSH TMS hold after TCK clock rise 10 – ns
tTDIS TDI setup to TCK clock rise 10 – ns
tTDIH TDI hold after TCK clock rise 10 – ns
tTDOV TCK clock LOW to TDO valid – 30 ns
tTDOX TCK clock LOW to TDO invalid 0 – ns
Figure 7. JTAG Switching Waveform
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
TDO
tTCYC
tTMSH
tTL
tTH
tTMSS
tTDIS tTDIH
tTDOX tTDOV
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 19 of 39
Switching Waveforms
Figure 8. Master Reset
Figure 9. Read Cycle [28, 29, 30, 31, 32]
MRST
tRSR
tRS
INACTIVE ACTIVE
TMS
TDO
INT
CNTINT
tRSF
tRSS
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
tCH2 tCL2
tCYC2
tSC tHC
tSW tHW
tSA tHA
AnAn+1
CLK
CE
R/W
ADDRESS
DATAOUT
OE
An+2 An+3
tSC tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
QnQn+1 Qn+2
1 Latency
B0–B3
tSB tHB
Notes
28.CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
29.OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
30.ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
31.The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
32.Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 20 of 39
Figure 10. Bank Sele ct Read [33, 34]
Figure 11. Read-to-Write-to-Read (OE = LO W) [32, 35, 36, 37, 38]
Switching Waveforms (continued)
Q
3
Q
1
Q
0
Q
2
A
0
A
1
A
2
A
3
A
4
A
5
Q
4
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
t
SC
t
HC
t
SA
t
HA
t
SC
t
HC
t
SC
t
HC
t
SC
t
HC
t
CKHZ
t
DC
t
DC
t
CD2
t
CKLZ
t
CD2
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CH2
t
CL2
t
CYC2
CLK
ADDRESS
(B1)
CE
(B1)
DATA
OUT(B2)
DATA
OUT(B1)
ADDRESS
(B2)
CE
(B2)
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
t
HW
t
SW
t
CD2
t
CKHZ
t
SD
t
HD
NO
OPERATION WRITEREAD READ
CLK
CE
R/W
ADDRESS
DATA
IN
DATA
OUT
A
n
A
n+1
A
n+2
A
n+2
D
n+2
A
n+3
A
n+4
Q
n
Q
n+3
Q
n+1
t
CD2
t
CD2
t
CKLZ
Notes
33.In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV
device from this dat a sheet. ADDRESS(B1) = ADDRESS(B2).
34. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
35.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
36.During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
37. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
38.CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. Wh en R/W first switches lo w , since OE = LOW, the Write opera tion cannot be completed
(labelled as no operation). One clock cycle is required to three-state the I/O fo r the Write operation on the next rising edge of CLK.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 21 of 39
Figure 12. Read-to-Write-to-Read (OE Controlled) [39, 40, 41, 42]
Figure 13. Read with Address Counter Advance [41]
Switching Waveforms (continued)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
AnAn+1 An+2 An+3 An+4 An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
READ READWRITE
Dn+3
Qn
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
OE
Qn+4
tCD2
Qn+1
tCD2
tSA tHA
tCH2 tCL2
tCYC2
CLK
ADDRESS An
COUNTER HOLD
READ WITH COUNTER
tSAD tHAD
tSCN tHCN
tSAD tHAD
tSCN tHCN
Qx–1 QxQnQn+1 Qn+2 Qn+3
tDC
tCD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
ADS
CNTEN
DATAOUT
Notes
39.Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only
40.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
41.CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
42.CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. Whe n R/W first switches low , since OE = LOW , the W rite operation cannot be completed
(labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 22 of 39
Figure 14. Write with Address Counter Advance [43]
Figure 15. Dis abled to Read-to-Read to Read-to-Write
Switching Waveforms (continued)
t
CH2
t
CL2
t
CYC2
A
n
A
n+1
A
n+2
A
n+3
A
n+4
D
n+1
D
n+1
D
n+2
D
n+3
D
n+4
A
n
D
n
t
SAD
t
HAD
t
SCN
t
HCN
t
SD
t
HD
WRITE EXTERN AL WRITE WITH COUNTER
ADDRESS WRITE WITH
COUNTER WRITE COUNTER
HOLD
CLK
ADDRESS
INTERNAL
DATA
IN
ADDRESS
t
SA
t
HA
CNTEN
ADS
t
CD2
CLK
CE
R/W
ADDRESS
DATA
OUT
OE
A
n
A
n+1
A
n+2
A
n+3
A
n+4
Q
n
Q
n+1
Q
n+2
t
CL2
t
CH2
t
CYC2
t
SA
t
HA
t
SC
t
HC
t
HW
t
SW
t
HW
t
SW
t
SA
t
HA
DISABLED READ WRITE READ
READREAD
DATA
IN
D
n+3
t
SD
t
HD
Note
43.CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low , since OE = LOW , the W rite operat ion cannot be completed
(labelled as no operation) . One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 23 of 39
Figure 16. Disabled to Write- to- Read to Write-to-Read
Figure 17. Disabled-to-Read to Disabled-to-Write
Switching Waveforms (continued)
CLK
CE
R/W
ADDRESS
OE
DATA
IN
A
n
A
n+1
A
n+2
A
n+3
A
n+4
t
CL2
t
CH2
t
CYC2
t
SC
t
HC
t
HW
t
SW
t
SA
t
HA
t
CD2
D
n
D
n+2
DATA
OUT
Q
n+1
t
SD
t
HD
Q
n+3
DISABLED WRITE READ WRITE READ READ
t
OE
CLK
CE
R/W
ADDRESS
OE
DATA
IN
A
n
A
n+1
A
n+2
A
n+3
A
n+4
t
CL2
t
CH2
t
CYC2
DATA
OUT
D
n+2
Q
n
t
SC
t
HC
t
HW
t
SW
t
SA
t
HA
t
SD
t
HD
t
CD2
DISABLED WRITE READ
READ
READ DISABLED
t
OE
t
OHZ
Q
n+3
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 24 of 39
Figure 18. Read-to-Read back to Read-to-Read (R/W = HIGH)
Switching Waveforms (continued)
CLK
ADS
ADDRESS
OE
DATAOUT
CNTEN
COUNTER
INTERNAL
ADDRESS
tCL2 tCH2
tCYC2
An+1 An+2 An+3 An+4
An
An+1
Qn+1 Qn+2 Qn+3
tSAD tHAD
tSCN tHCN tSA tHA
READ NO OPERATION READ READ READ
READBACK INCREMENT INCREMENT INCREMENT
INCREMENT
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 25 of 39
Figure 19. Counter Reset [44, 45, 46]
Switching Waveforms (continued)
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT
AnAmAp
Ax01AnAmAp
Q1Qn
Q0
D0
tCH2 tCL2
tCYC2
tSA tHA
tSW tHW
tSRST tHRST
tSD tHD
tCD2 tCD2
tCKLZ
[46]
RESET ADDRESS 0
COUNTER WRITE READ
ADDRESS 0 ADDRESS 1
READ READ
ADDRESS AnADDRESS Am
READ
Notes
44.CE0 = B0–B3 = LOW; CE1 = MRST = CNT/MSK = HIGH.
45.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
46.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 26 of 39
Figure 20. Readback State of Address Counter or Mask Register [47, 48, 49, 50]
Switching Waveforms (continued)
CNTEN
CLK
tCH2 tCL2
tCYC2
ADDRESS
ADS
An
Qx-2 Qx-1 Qn
tSA tHA
tSAD tHAD
tSCN tHCN
LOAD
ADDRESS
EXTERNAL
tCD2
INTERNAL
ADDRESS An+1 An+2
An
tCKHZ
DATAOUT
A
n*
Q
n+3
Qn+1 Qn+2
An+3 An+4
tCKLZ
tCA2 or tCM2
READBACK
INTERNAL
COUNTER
ADDRESS
INCREMENT
EXTERNAL
A0–A16
Notes
47.CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
48.Address in output mode. Host must not be driving address bus af ter tCKLZ in next clock cycle.
49.A ddress in input mode. Host can drive address bus after tCKHZ.
50.An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 27 of 39
Figure 21. Left_Port (L_Port) Write to Right_Port (R_Port) Read [51, 52, 53]
Switching Waveforms (continued)
tSA tHA
tSW tHW
tCH2 tCL2
tCYC2
CLKL
R/WL
An
Dn
tCKHZ tHD
tSA
An
tHA
Qn
tDC
tCCS
tSD tCKLZ
tCH2
tCL2
tCYC2
tCD2
L_PORT
ADDRESS
L_PORT
DATAIN
CLKR
R/WR
R_PORT
ADDRESS
R_PORT
DATAOUT
Notes
51.CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
52.This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data is Read out.
53.If tCCS < minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port 's clock.
If tCCS > minimum specified value, then R_Port is Read the most recent dat a ( written by L_Port) (tCYC2 + tCD2) after the rising edg e of R_Port's clock.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 28 of 39
Figure 22. Counter Interrupt and Retransmit [54, 55, 56, 57, 58]
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
CLK
1FFFD 1FFFF
INTERNAL
ADDRESS Last_Loaded Last_Loaded +1
t
HCM
COUNTER
1FFFE
CNTINT
tSCINT tRCINT
1FFFC
CNTEN
ADS
CNT/MSK
t
SCM
Notes
54.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value
55.CE0 = OE = B0–B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
56.CNTINT is always driven.
57.CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
58.The mask register assumed to have the value of 1FFFFh.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 29 of 39
Figure 23. Ma ilBox Interrupt Timing [59, 60, 61, 62, 63]
Switching Waveforms (continued)
t
CH2
t
CL2
t
CYC2
CLK
L
tCH2 tCL2
tCYC2
CLKR
3FFFF
tSA tHA
An+3
AnAn+1 An+2
L_PORT
ADDRESS
AmAm+4
Am+1 3FFFF Am+3
R_PORT
ADDRESS
INTR
tSA tHA
tSINT tRINT
Notes
59.CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
60.Address “3FFFF” is the mailbox location for R_Port of a 9M device.
61.L_Port is configured for Write operation, and R_Port is configured for Read operation.
62.At least one byte enable (B0 – B3) is required to be active during int errupt operations.
63.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 30 of 39
Table 3. Read/Write and Enable Operation (Any Port) [66, 67, 64, 65]
Inputs Outputs Operation
OE CLK CE0CE1R/W DQ0–DQ35
X H X X High Z Deselected
X X L X High Z Deselected
XLHLD
IN Write
LLHHD
OUT Read
H X L H X High Z Outputs disabled
Notes
64.OE is an asynchronous input signal.
65.When CE changes state, deselection and Read happen after one cycle of latency.
66.9 M device has 18 address bits, 4M device has 17 address bits, and 2 M device has 16 address bits.
67.“X” = “Don’t Care”, “H” = HIGH, “L” = LOW.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 31 of 39
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com
and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
256 K
×
36 (9 M) 3.3 V Synchronous CY7C0853V/CY7C0853AV Dual-Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
133 CY7C0853V-133BBI 51-85146 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch Industrial
CY7C0853V-133BBXI 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch
(Pb-free)
CY7C0853V-133BBC 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch Commercial
100 CY7C0853AV-100BBI 51-85146 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch Industrial
CY7C0853V-100BBC 172-ball BGA (15 × 15 × 1.6 mm) with 1 mm pitch Commercial
128 K
×
36 (4 M) 3.3 V Synchronous CY7C0852V/CY7C0852AV Dual-Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
167 CY7C0852V-167BBC 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch Commercial
CY7C0852AV-167AXC 51-85132 176-pin
TQFP (24 × 24 × 1.4 mm)
(Pb-free)
133 CY7C0852AV-133AXC 51-85132 176-pin
TQFP (24 × 24 × 1.4 mm)
(Pb-free)
CY7C0852AV-133BBI 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch Industrial
CY7C0852AV-133AXI 51-85132 176-pin
TQFP (24 × 24 × 1.4 mm)
(Pb-free)
CY7C0852V-133BBC 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch Commercial
CY7C0852V-133BBI 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch Industrial
64 K
×
36 (2 M) 3.3 V Synchronous CY7C0851V/CY7C0851AV Dual-Port SRAM
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
167 CY7C0851V-167BBC 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch Commercial
CY7C0851AV-167BBXC 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch
(Pb-free)
133 CY7C0851AV-133AXI 51-85132 176-pin
TQFP (24 × 24 × 1.4 mm)
(Pb-free)
Industrial
CY7C0851AV-133BBI 51-85114 172-ball BGA (15 × 15 × 1.25 mm) with 1 mm pitch
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 32 of 39
Ordering Code Definitions
Temperature Range: X = I or C
I = Industrial; C = Commercial
X = Pb-free (RoHS Compliant)
Package Type: X = BB or A
BB = 172-ball BGA
A = 176-pin TQFP
Speed Grade: XXX = 100 MHz or 133 MHz or 167 MHz
X = V or AV
V or AV = 3.3 V
Depth: X = 1 or 2 or 3
1 = 64 K
2 = 128 K
3 = 256 K
Width: 5 = × 36
Family Code: 8 = Synchronous
Port: 0 = Dual Port
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 0 - XXX XXX XX7 X8 5
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 33 of 39
Package Diagrams
Figure 24. 172-ball FBGA (15 × 15 × 1.6 mm) BB172SD (For Single or Stacked Die) Package Outline , 51-8 5146
51-85146 *D
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 34 of 39
Figure 25. 172-ball FBGA (15 × 15 × 1.25 mm) BB172 Package Outline, 51-85114
Package Diagrams (continued)
51-85114 *E
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 35 of 39
Figure 26. 176-pin TQFP (24 × 24 × 1.4 mm) A176S Package Outlin e, 51-851 32
Package Diagrams (continued)
51-85132 *B
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 36 of 39
Acronyms Document Conventions
Units of Measure
Acronym Description
CMOS complementary metal oxide semiconductor
FBGA fine-pitch ball gr id array
I/O input/output
JTAG joint test action group
SRAM static random access memory
TCK test clock input
TDI test data input
TDO test data output
TQFP thin quad flat pack
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
mV millivolt
ns nanosecond
ohm
pF picofarad
Vvolt
Wwatt
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 37 of 39
Document History Page
Document Title: CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV/CY7C0853V/CY7C0853AV,
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM
Document Number: 38-06070
Rev. ECN No. Submission
Date Orig. of
Change Description of Change
** 127809 08/04/03 SPN This data sheet has been extracted from another data sheet: The 2 M / 4 M /
9 M data sheet. The following changes have been made from the original as
pertains to this device:
Updated capacitance values
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Corrected 0853 pins L3 and L12
Added discussion of Pause/Restart for JTAG boundary scan
Power up requirements added to Maximum Ratings information
Revised tCD2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns
Updated ICC numbers
Updated tHA, tHB, tHD for -100 speed
Separated out from the 4 M data sheet
Added 133 MHz Industrial device to Ordering Information table
*A 210948 See ECN YDT Changed mailbox addresses from 1F FFE and 1FFFF to 3FFFE and 3FFFF.
*B 216190 See ECN YDT /
DCON Corrected Revision of Document. CMS does not reflect this rev change.
*C 231996 See ECN YDT Updated Functional Description (Removed “A particular port can write to a
certain location while another port is reading that location.”).
*D 238938 See ECN WWZ Merged 0853 (9 M × 36) with 0852 (4 M × 36) and 0851 (2 M × 36), add 0850
(1 M × 36), to the data sheet.
Added Product Selection Guide.
Added JTAG ID code for 1 M device.
Updated Scan Registers Sizes (Added Note 18 and referred the same note in
the Bit Size ‘n’ of Bondary Scan).
Updated boundary scan section.
Updated function description for the merge and addition.
*E 329122 See ECN SPN Updated Ordering Information (Updated Marketing part numbers).
*F 389877 See ECN KGH Updated Read-to-Write-to-Read timing diagram to reflect accurate bus
turnaround scheme.
Added ISB5
Changed tRSCNTINT to 10 ns
Changed tRSF to 10 ns
Added figure Disabled-to-Read-to-Read-to-Read-to-Write
Added figure Disabled-to-Write-to-Read-to-Write-to-Read
Added figure Disabled-to-Read-to-Disabled-to-Write
Added figure Read-to-Readback-to-Read-to-Read (R/W = HIGH)
Updated Read-to-Write-to-Read timing diagram to correct the data out
schemes
Updated Disabled-to-Read-to-Read-to-Read-to-Write timing diagram to
correct the chip enable, data in, and data out schemes
Updated Disabled-to-Write-to-Read-to-Write-to-Read timing diagram to
correct the chip enable and output enable schemes
Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct the
chip enable and output enable schemes
*G 391597 See ECN SPN Updated counter reset section to reflect mirror register behavior
*H 2544945 07/29/08 VKN /
AESA Updated Ordering Information (Updated part numbers).
Updated in new template.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document Number: 38-06070 Rev. *M Page 38 of 39
*I 2897087 03/22/10 RAME Updated Ordering Informati on (Removed obsolete parts from ordering
information table).
Updated Package Diagrams.
*J 3093275 1 1/23/2010 ADMU Added information for parts CY7C0851V/CY7C0852V/CY7C0853V across the
document.
Added Contents.
Updated Ordering Information (Added new part CY7C0851AV-133BBI in the
ordering information table) and added Orderin g Code Definitions.
Added Acronyms and Units of Measure.
Updated as per new template.
*K 3402163 10/12/2011 ADMU Updated Orde ring Information (Removed pruned parts
CY7C0853AV-100 BBC, CY7C0853AV-133BBC).
Updated Package Diagrams.
*L 3698945 08/07/2012 SMCH Updated title to read as “CY7C0851V/CY7C0851AV/CY7C0852V/
CY7C0852AV/CY7C0853V/CY7C0853AV,
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM”.
Updated Features (Removed CY7C0850AV related information).
Updated Functional Description (Removed CY7C0850A V related information).
Updated Product Selection Guide (Removed CY7C0850AV related
information).
Updated Pin Configurations (Removed CY7C0850AV related information).
Updated Pin Defini tions (Removed CY7C0850AV related information).
Updated Mailbox Interrupts (Removed CY7C0850AV related information).
Updated Address Counter and Mask Register Operations (Removed
CY7C0850AV related information).
Updated IEEE 1 149.1 Serial Boundary Scan (JT A G) (Removed CY7C0850A V
related information).
Updated Identification Register Definitions (Removed CY7C0 850AV related
information).
Updated Electrical Chara c teristics (Removed CY7C0850AV related
information).
Updated Capacitance (Removed CY7C0850AV related information).
Updated Switching Characteristics (Removed CY7C0850 AV related
information).
Updated Package Diagrams (Added another spec 51-85146 for 172-ball BGA
package, spec 51-85132 for 176-pin TQFP package (Changed revision from
*A to *B)).
*M 3829988 12/04/2012 SMCH Updated Logic Block Diagram (for better clarity).
Updated Note 9 refe rred in Table 1 under Mailbox Interrupts.
Updated Figure 4 und er Address Counter and Mask Register Operations.
Updated Note 28 referred in Figure 9 under Switching Waveforms.
Updated Package Diagrams:
spec 51-85114 – Changed revision from *D to *E.
Document History Page (continued)
Document Title: CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV/CY7C0853V/CY7C0853AV,
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM
Document Number: 38-06070
Rev. ECN No. Submission
Date Orig. of
Change Description of Change
Document Number: 38-06070 Rev. *M Revised December 4, 2012 Page 39 of 39
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
© Cypress Semicondu ctor Corpor ation, 2008-2012. The informatio n contai ned herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n express written ag re em en t with Cypress. Furthermor e, Cyp ress doe s not author iz e its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress p roducts in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protec tion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee prod uct to be used only in conj unction with a Cypre ss
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except as specified above is prohibited wi thout
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTA BILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials desc ribed herein. Cypress does n ot
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypr ess does n ot author ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Touch Sen sing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
