M48T513Y-70PM1 - STMicroelectronics, Inc.

1/18

PRELIMINARY DATA

December 1999

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M48T513Y

M48T513V

3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPER® SRAM

■INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL

CIRCUIT, BATTERY, and CRYSTAL

■YEAR 2000 COMPLIA NT

■BCD CODED CENTURY, YEAR, MONTH,

DAY, DATE, HOURS, MINUTES, and

SECONDS

■BATTERY LOW WARNING FLAG

■AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE P ROTEC T ION

■TWO WRITE PROTECT VOLTAGES:

(VPFD = Power-fail Deselect Voltage)

– M48T 513Y : 4.2V ≤ VPFD ≤ 4.5V

– M48T 513V : 2.7V ≤ VPFD ≤ 3.0V

■CONVENTIONAL SRAM OPERATION;

UNLIMITED WRITE CYCLES

■SOFTWARE CONTROLLED CLOCK

CALIBRATION for HIGH ACCURACY

APPLICATIONS

■10 YEARS of DATA RETENTION and CLOCK

OPERATION in the ABSENCE of POWER

■SELF CONTAINED BATTERY and CRYSTAL

in DIP PACKAGE

■MI CR OPRO C ESSOR POWER- O N RES ET

(Valid even during battery back-up mode)

■PR O GRAMM A BLE A L A R M O U TPU T ACTI VE

in BATTERY BACK-UP MODE

DESCRIPTION

The M48T513Y/V TIMEKE EPER R AM is a 512Kb

x 8 non-volatile static RAM and real time clock,

with programm able a larms and a watchdo g t imer.

The special DIP package provides a fu lly integrat-

ed battery back -up memory and real time clock so-

lution. The M48T513Y/V directly replaces industry

standard 512Kb x 8 SRAM. It also provides the

non-volatility of Flash without any req uirement for

special write timing or limitations on the number of

writes that can be performed.

The 36 pin 600 mil DIP Hy brid houses a controller

chip, SRAM , quartz crystal, and a long life lithium

button cell in a single package.

Figure 1. Logic Diagram

AI02308

A0-A18 DQ0-DQ7

VCC

M48T513Y

M48T513V

VSS

W RST

IRQ/FT

RSTIN

WDI

PMLDIP36 (PM)

Module

M48T513Y, M48T513V

2/18

Figu re 2. DIP C on ne ctions

VSS

VCC

AI02307

M48T513Y

M48T513V

DQ0

A13

A10

DQ7

A15

A11

DQ5DQ1

DQ2 DQ3

DQ4

DQ6

A16

A18

A12

A14 W

A17

RSTIN

RST

IRQ/FT

WDI

Table 2. Absolute Maximum Ratings (1)

Note: 1. Stres ses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the devic e. This i s a stress

rating only and function al opera tion of the device at these or any other con di tions above those indic ated in the operational section

of this spec ificati on is not implied. Ex posure t o the abso lute maximum r ating cond itions for ex tended period s of time may affect

reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Nega tive unders hoots below –0.3V are not all owed on any pin while i n the Batte ry Ba ck- up m ode.

Symbol Parameter Value Unit

TAAmbient Operating Temperature 0 to 70 °C

TSTG Storage Temperature (VCC Off, Oscillator Off) –40 to 85 °C

VIO Input or Output Voltages –0.3 to VCC +0.3 V

VCC Supply Voltage M48T513Y –0.3 to 7.0 V

M48T513V –0.3 to 4.6 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

Figure 3 illustrates the static memory array and the

quartz controlled clock oscillator. The clock loca-

tions contain the century, year, month, date, day,

hour, minute, and second in 24 hour B CD f orm at.

Corrections for 28, 29 (lea p year), 30, and 31 day

months are made automatically. The nine clock

bytes (7FFFFh-7FFF9h and 7FFF1h) are not the

actual clock counters, they are memory locations

consisting of BiPORT™ read/write memory cells

within the static RAM array.

Table 1. Signal Names

A0-A18 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

EChip Enable Input

GOutput Enable Input

WWrite Enable Input

WDI Watchdog input

RST Reset Output (open drain)

RSTIN Reset Input

IRQ/FT Interrupt / Frequency Test

Output (open drain)

VCC Supply Voltage

VSS Ground

3/18

M48T513Y, M 48T513V

Figu re 3. Blo ck D ia gra m

AI02584

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

VCC VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

16 x 8

TIMEKEEPER

REGISTERS

524,272 x 8

SRAM ARRAY

A0-A18

DQ0-DQ7

POWER

RST

IRQ/FT

WDI

RSTIN

The M48T513Y/V includes a clock control circuit

which updates the clock bytes with current infor-

mation once per second. The information can be

accessed by t he us er i n t he sa me m anner a s any

other location in the static memory array. Byte

7FFF8h is the clock control register. This byte con-

trols user access to the cl ock inf ormation and also

stores the clock calibration setting.

Byte 7FFF7h contains the watchdog timer set ting.

The watchdog timer can generate either a reset or

an interrupt, depending on the st ate of the Watch-

dog Steering bit (WDS). Bytes 7FFF6h-7FFF2h in-

clude bits that, when programmed, provide for

clock alarm functionality. Alarms are activated

when the register content matches the month,

date, hours, minutes, and seconds of the clock

registers. Byte 7FFF1h contains century informa-

tion. Byte 7FFF0h cont ains additional flag informa-

tion pertaining to the watchdog timer, the alarm

condition and the battery status. The M48T513Y/ V

also has its own Power-Fail Detect circuit. This

control circuitry constantly monitors the supply

voltage for an out of tolerance condition. When

VCC is out of tolerance, the circuit write protects

the TIMEKEEPER register data and external

SRAM, providing data sec urity in the midst of un-

predictable system operation. As VCC falls, the

control circuitry automatically sw itches to t he bat-

tery, maintaining data and clock operation until

valid power is restored.

READ MODE

The M48T513Y/V is in the Read Mode whenever

W (Write Enable) is high and E (Chip Enable) is

low. The unique address specified by the 17 Ad-

dress Inputs defines which one of the 524,272

bytes of data is to be acc ess ed. Vali d data will be

available at the Data I/O pins within tAVQV (Ad-

dress Access Time) after the last address input

signal is stable, providing the E and G access

times are also satisfied. If the E and G access

times are not met, valid dat a will be available after

the latter of the Chi p Enable Access Times (tELQV)

or Output Enable Access Time (tGLQV).

The state of the eight three-state Da ta I/O si gnals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven t o an

indeterminate state until tAVQV. If the Add ress In-

puts are changed while E and G remain active,

output data will remain valid for tAXQX (Output

Data Hold Time) but will go indeterminate until the

next Address Access.

M48T513Y, M48T513V

4/18

Table 3. Operating Modes (1)

No te: 1. X = V IH or VIL; VSO = Batte ry Back-up Swit chover Voltage.

2. See Table 7 for details .

Mode VCC E G W DQ0-DQ7 Power

Deselect

4.5V to 5.5V

3.0V to 3.6V

VIH X X High Z Standby

Write VIL XVIL DIN Active

Read VIL VIL VIH DOUT Active

Read VIL VIH VIH High Z Active

Deselect VSO to VPFD (min) (2) X X X High Z CMOS Standby

Deselect ≤ VSO (2) X X X High Z Battery Back-up Mode

Table 4. AC Measu remen t Conditions

Note that Output Hi-Z is def ined as the point where data is no longer

driven.

Input Rise and Fall Times ≤ 5ns

Input Pulse Voltages 0 to 3V

Input and Output Timing Ref. Voltages 1.5V

data and powering the clock. The internal energy

source will maintain data in the M48T513Y/V for

an accumulated per iod of at least 10 years at room

temperature. As system power rises above VSO,

the battery is disconnected, and t he power supply

is switched to external VCC. Deselect continues for

tREC after VCC reaches VPF D (max). For a further

more detailed review of lifetime calculations,

please see Application Note AN10 12.

WRITE MODE

The M48T513Y/V is in the Write Mode whenever

W (Write Enable) and E (Chip Enable) are low

state after the address inputs are stable.

The start of a wri te is referenced from the la tter oc-

curring falling edge of W or E. A wr ite is terminated

by the earlier rising edge of W or E . The addresses

must be held valid throughout the cycle. E or W

must return high f or a minimum of tEHAX fr om Chip

Enable or tWHAX from Write Enable prior to the ini-

tiation of another read or write cycle. Data-in must

be valid tDVWH prior to the end of write and remain

valid for tWHDX afterward. G should be kept high

during write cycles to avoid bus contention; al-

though, if t he out put bus has bee n act ivated by a

low on E and G a low on W will disable the outputs

tWL QZ after W falls.

DATA RETENTION MODE

With valid VCC applied, the M48T513Y/V operates

as a conventi onal BYTEWIDE static RAM. Shoul d

the supply voltage de cay, the RAM will automati-

cally deselect, write protecting itself when VCC

falls between VPFD (max), VPFD (min) window. All

outputs become high impedance and all inputs are

treated as "don’t care".

Note: A power failure during a write cycle may cor-

rupt data at the current addressed location, but

does not jeopardize the rest of the RAM’s content.

At vo ltage s belo w VPFD (m in), the memory will be

in a write protected state, provided the VCC fall

time is not less than tF. The M48T5 13Y /V ma y re-

spond to transient noise spik es on VCC th a t cros s

into the deselect window during the time the de-

vice is sampling VCC. Therefore, decoupling of the

power supply lines is recomm ended .

When VCC drops below VSO, the control circuit

switches power t o the internal b attery, preserving

Figure 4. AC Testing Load Circuit

Note: Excluding open drain output pins.

AI01803C

CL = 100pF

CL includes JIG capacitance

650Ω

DEVICE

UNDER

TEST

1.75V

5/18

M48T513Y, M 48T513V

TIMEKEEPER REGISTERS

The M48T513Y/V offers 16 internal registers

which contain TIMEKEEPER, Alarm, Watchdog,

Interrupt, Flag, and Control data. These registers

are memory locations which contain external (user

accessible) and internal copies of the data (us ually

referred to as BiPORT™ TIMEKEEPER cells).

The external copies are independent of internal

functions except t hat they are updated periodically

by the simultaneous transfer of the incremented

in te r n a l copy. TI MEKEEPER a nd Alar m Register s

store data in BCD.

CLOCK OPERATIONS

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted bef ore clock data is read to prevent reading

data in transition. Because the BiPORT TIME-

KEEPER cells i n the R AM a r ra y are onl y d a ta r e g -

isters, and not the actual clock counters, updat ing

the registers can b e halted without disturbing the

clock i tse l f.

Updating is halted when a '1' is written to the

READ bit, D6 i n the Control Register (7FFF8h). As

long as a '1' remains in that position, updating is

halted. After a halt is issued, the registers reflect

the count; that is, the day, dat e, and time that were

current at the moment the halt command was is-

s ued. Al l o f th e TI MEKEEPER r egi ster s are updat-

ed simultaneously. A halt will not interrupt an

update in progress. Updating occ urs 1 second a f-

ter the READ bit is reset to a '0'.

Setting the Clock

Bit D7 of the Control Register (7FFF8h) is the

WRITE bit. Setting the WR ITE bit to a '1', like t he

RE AD b i t, halts u p dates to the TIMEKEEPER re g -

isters. The user can then load them with the cor-

rect day, date, and time data in 24 hour BCD

format (see Table 11).

Resetting the WRITE bit to a '0' then transfers the

values of all time registers (7FFFFh-7FFF9h,

7FFF1h) to th e actual TIMEKEEPER counters and

allows normal operation to resume. After the

WRITE bit is reset, the next clock update will occur

approximately one second later.

Note: Upon power-up following a power failure,

both the WRITE bit and the READ bit will be reset

to '0'.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillat or can be turned off to

minimize current drain on the battery. The STOP

bit is located at Bit D7 within 7FFF9h. Setting it to

a '1' stops the oscillator. When reset to a '0', the

M48T513 Y/V oscillator starts within one second.

Note: It is not necessary to set the WRITE bit

when setting or resetting the FREQUE NCY TES T

bit (FT) or the STOP bit (ST ).

SETTING ALARM CLOCK

Registers 7F FF6h-7FFF2 h contain t he alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second or repeat every month, day,

hour, minute, or second. It can also be pro-

grammed to go off while the M48T513Y/V is in the

batt ery back-up to serve as a system wake-up call.

Bits RPT5-RPT1 put the alarm in the repeat mode

of operation. Tabl e 12 shows the po ssible config-

urations. Codes not listed in the table default to the

once per secon d m ode t o qu ick ly alert the us er of

an incorrect alarm setting.

Note: User must transition address (or toggle Chip

Enable) to see Flag Bit change.

When the clock information matches the alarm

clock settings based on the match cr iteria d efined

by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE

(Alarm Flag Enable) is also set, the alarm condi-

tion activates the IRQ/FT pin. To disable alarm,

write ’0’ to the Alarm Date register and RPT1-4.

The IRQ/FT output is cleared by a read to the

Flags register as shown in Figure 11. A subse-

quent read of the Flags register will reset the

Alarm Flag (D6; Register 7FFF 0h).

The IRQ/FT pin can also be activated in the bat-

tery back-up mode. The IRQ/FT will go low if an

alarm occurs and both ABE (Alarm in Battery

Back-up Mode Enable) and AFE are set. The ABE

and AFE bits are reset during power-up, therefore

an alarm generated during power-up will only set

AF. The user can read t he Flag Register at syst em

boot-up to determine if an alarm was generated

while the M48T51 3Y/V was in t he desel ect m ode

during power-up. Figure 12 il l ustrates the back-up

mode alarm timing.

M48T513Y, M48T513V

6/18

Table 5. Capaci tance (1)

(TA = 25 °C, f = 1 MHz)

No te : 1. Effective c apacitance me asured wi th power supply at 5V (M 48T513 Y) or 3.3 V (M48T513V). S ampled only, not 100% tes ted.

2. Outputs desel ected .

Table 6A. DC Characteristics - M48T513Y

(TA = 0 to 70 °C; VCC = 4.5V to 5.5V)

No te : 1. Outputs des el ected .

Table 6B. DC Characteristics - M48T513V

(TA = 0 to 70 °C; VCC = 3.0V to 3.6V)

No te : 1. Outputs des el ected .

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 20 pF

CIO (2) Input / Output Capacitance VOUT = 0V 20 pF

Symbol Parameter Test Condition Min Max Unit

ILI (1) Input Leakage Current 0V ≤ VIN ≤ VCC ±2 µA

ILO (1) Output Leakage Current 0V ≤ VOUT ≤ VCC ±2 µA

ICC Supply Current Outputs open 115 mA

ICC1 Supply Current (Standby) TTL E = VIH 8mA

CC2 Supply Current (Standby) CMOS E = VCC – 0.2V 4mA

IL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage IOH = –1mA 2.4 V

Symbol Parameter Test Condition Min Max Unit

ILI (1) Input Leakage Current 0V ≤ VIN ≤ VCC ±2 µA

ILO (1) Output Leakage Current 0V ≤ VOUT ≤ VCC ±2 µA

ICC Supply Current Outputs open 60 mA

ICC1 Supply Current (Standby) TTL E = VIH 4mA

CC2 Supply Current (Standby) CMOS E = VCC – 0.2V 3mA

IL Input Low Voltage –0.3 0.4 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage IOH = –1mA 2.2 V

7/18

M48T513Y, M 48T513V

Table 7. Power Down/Up Trip Points DC Characteristics (1)

(TA = 0 to 70 °C)

Note: 1. All voltages referenced to VSS.

2. At 25° C.

Table 8. Power Down/Up AC Chara cteri stics

(TA = 0 to 70 °C)

Note: 1. VPFD (ma x) to VPFD ( min) fall time of less than tF m ay r e sul t in de sel ec tio n/ wri te pro te cti on not o cc ur ri ng un ti l 200m s af te r VCC p ass-

es VPFD (min) .

2. VPFD (min) to VSS fall time of less than tFB may cause cor ruption of RAM dat a.

Symbol Parameter Min Typ Max Unit

VPFD Power-fail Deselect Voltage M48T513Y 4.2 4.35 4.5 V

M48T513V 2.7 2.9 3.0 V

VSO Battery Back-up Switchover Voltage M48T513Y 3.0 V

M48T513V VPFD –100mV

tDR (2) Expected Data Reten tion Time 10 YEARS

Symbol Parameter Min Max Unit

tF (1) VPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB (2) VPFD (min) to VSS VCC Fall Time M48T513Y 10 µs

M48T513V 150 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 0µs

RB VSS to VPFD (min) VCC Rise Time 1µs

REC VPFD (max) to RST High 40 200 ms

Figure 5. Power Down/Up Mode AC Waveforms

AI01805

VCC

INPUTS

OUTPUTS

DON'T CARE

HIGH-Z

tFB

tRB

VALID VALID

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

tREC

RST

M48T513Y, M48T513V

8/18

Table 9. Read Mode AC Characteri stics

(TA = 0 to 70 °C)

Note: 1. CL = 100pF.

2. CL = 5pF .

Symbol Parameter

M48T513Y M48T513V

Unit-70 -85

Min Max Min Max

tAVAV Read Cycle Time 70 85 ns

tAVQV (1) Address Valid to Output Valid 70 85 ns

tELQV (1) Chip Enable Low to Output Valid 70 85 ns

tGLQV (1) Output Enable Low to Output Valid 40 55 ns

tELQX (2) Chip Enable Low to Output Transition 5 5 ns

tGLQX (2) Output Enable Low to Output Transition 5 5 ns

tEHQZ (2) Chip Enable High to Output Hi-Z 25 30 ns

tGHQZ (2) Output Enable High to Output Hi-Z 25 30 ns

tAXQX (1) Address Transition to Output Transition 10 5 ns

Figure 6. Address Controlled, Read Mode AC Waveforms

AI02324

tAVAV

tAVQV

tAXQX

DATA VALID

A0-A16

DQ0-DQ7

VALID

DATA VALID

9/18

M48T513Y, M 48T513V

Table 10. Write Mode AC Characteristics

(TA = 0 to 70 °C)

Note: 1. CL = 5pF.

2. If E goes low simultaneously wit h W going low , t he outputs rem ai n in the hi gh i m peda nce state.

Symbol Parameter

M48T513Y M48T513V

Unit-70 -85

Min Max Min Max

tAVAV Write Cycle Time 70 85 ns

tAVWL Address Valid to Write Enable Low 0 0 ns

tAVEL Address Valid to Chip Enable Low 0 0 ns

tWLWH Write Enable Pulse Width 50 60 ns

tELEH Chip Enable Low to Chip Enable High 55 65 ns

tWHAX Write Enable High to Address Transition 5 5 ns

tEHAX Chip Enable High to Address Transition 10 15 ns

tDVWH Input Valid to Write Enable High 30 35 ns

tDVEH Input Valid to Chip Enable High 30 35 ns

tWHDX Write Enable High to Input Transition 5 5 ns

tEHDX Chip Enable High to Input Transition 10 15 ns

tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 30 ns

tAVWH Address Valid to Write Enable High 60 70 ns

tAVEH Address Valid to Chip Enable High 60 70 ns

tWHQX (1, 2) Write Enable High to Output Transition 5 5 ns

WATCHDOG TI MER

The watchdog timer can be used to detect an out-

of-control microprocessor. The us er program s the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address

7FFF7h. Bits BMB4-BMB0 store a binary multiplier

and the two lower order bits RB1-RB0 select the

resolution, where 00 = 1/16 second, 01 = 1/4 sec-

ond, 10 = 1 second, and 11 = 4 seconds. The

amount of time-out is then determined to be the

multiplication of t he five bit m ultiplier value with the

resolution. (For example: writing 00001110 in the

Watchdog Register = 3*1 or 3 s econds).

Note: Accuracy of timer is within ± the selected

resolution.

If the processor does not reset the timer within the

specified period, the M48T513Y/V sets the WDF

(Watchdog Fl ag) and generates a watchdog inter-

rupt or a microprocessor reset. WDF is reset by

reading the Flags Register (Address 7FFF0h). The

most significant bit of the Watchdog Register is the

Watchdog Steering Bit (WDS). When set to a '0 ',

the watchdog will activate the IRQ/FT pin when

timed-out. When WDS is set to a '1', the watc hdog

will out put a negative pulse on th e R S T pin for 40

to 200 ms. The Watchdog register and the F T bit

will reset to a '0' at the end of a Watchdog time-out

when the WDS bi t is set to a '1'. The watchdog ti m-

er can be reset by two methods: 1) a transition

(high-to-low or low-to-high) can be applied to the

Watchdog Input pin (WDI) or 2) the microproces-

sor can perform a write of the Watchdog Regist er.

The time-out period then starts over. The WDI pin

should be tied to VSS if not used. The watchdog

will be reset on each transition (edge) seen by the

WDI pin. In the order to perform a software reset

of the watchdog timer, the original time-out period

can be written into the Watchdog Register, effec-

tively restarting the count-down cycle.

Should the wat chdog t imer time-out, and the WDS

bit is programmed to output an interrupt , a value of

00h needs to be written to the Watchdog Register

in order to clear the IRQ/FT pin. This will also dis-

able the watchdog function until it is again pro-

grammed correctly. A read of the Flags Register

will reset the Watchdog Flag (Bit D7; Register

7FFF0h).

M48T513Y, M48T513V

10/18

Figure 7. Chip Enable or Outp ut Enab le Controll ed, Read Mode AC Waveforms

Figure 8. Write Enable Controlled, Write AC Wavefo rms

AI01197

tAVAV

tAVQV tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A16

DQ0-DQ7

VALID

AI02382

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A16

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

11/18

M48T513Y, M 48T513V

The watchdog function is automatically disabled

upon power-down and the Watchdog Register is

cleared. If the watchdog function i s set t o output to

the IRQ /FT pin and the frequency test function is

activated, the watchdog or alarm function prevails

and the frequency test function is denied.

POWER-ON RESET

The M48T513Y/V continuously monitors VCC.

When V CC falls to the power fail detect trip point,

the RST pull s low (open drain) and remains low on

power-up for 40 t o 200ms after VCC pa sse s VPFD.

The RST pin is an open drain output and an appro-

priate pull-up resist or to VCC shoul d be cho sen t o

control the rise time.

RESET I NPU T ( RSTIN)

The M48T513Y/V provides an independent input

which can generate an out put reset. The duration

and function of this reset is identical to a reset gen-

erated by a power cycle. Table 13 and Figure 13

illu strat e the AC rese t ch ara cteris tics of t his f unc-

tion. Pulses short er t han tR will not gene ra te a re-

set condition. RSTIN is in te rn a lly pu lled up to VCC

through a 100KΩ resistor.

CALIBRATING THE CLOCK

The M48T513Y/V is driven by a quartz controlled

oscillator with a nominal frequency of 32,768Hz.

The devices are factory calibrated at 25°C and

tested for accuracy. Clock accuracy will not ex-

ceed 35 ppm (parts per million) oscillator frequen-

cy error at 25°C, which equates to about * 1.53

minutes per mont h. When the Calibration circuit is

properly employed, accuracy improves to better

than 4 ppm at 25°C. The osci llation rate of crystals

changes with temperature. The M48T513Y/V de-

sign employs periodic counter correction. The cal-

ibration circuit adds or subtracts counts from the

oscillator di vider circuit at the divide by 256 stage,

as shown in Figure 10.

The number of times pulses which are blanked

(subtracted, negative calibration) or split (added,

positive calibration) depends upon the value load-

ed into the five Calibration bits found in the Control

tracting counts slows the cl ock down. The Calibra-

tion bits occupy the five lower order bit s (D4-D0) in

the Control Register 7FFF8h. These bits can be

set to represent any value between 0 and 31 in bi-

nary form. Bit D5 is a Si gn bi t; '1' indicates positive

calibration, '0' indicates negati ve c alibration. Cali-

bration occurs within a 64 minute cycle. The first

62 minutes in the cycle may, once per minute,

have one second either shortened by 128 or

lengthene d by 256 oscillator cycles.

Figure 9. Chip Enable Controlled, Write AC Waveforms

AI02582

tAVAV

tEHAX

tDVWH

A0-A16

DQ0-DQ7

VALID

tAVEL

tAVWL

tELEH

tWHDX

DATA INPUT

M48T513Y, M48T513V

12/18

Figu re 10. Ca l ibr ati on W aveform

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

Table 11. TIMEKEEPER Register M ap

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

7FFFFh 10 Years Year Year 00-99

7FFFEh 0 0 0 10 M Month Month 01-12

7FFFDh 0 0 10 Date Date Date 01-31

7FFFCh 0 FT 0 0 0 Day of Week Day 01-07

7FFFBh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23

7FFFAh 0 10 Minutes Minutes Minutes 00-59

7FFF9h ST 10 Seconds Seconds Secon ds 00-59

7FFF8h W R S Calibration Control

7FFF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

7FFF6h AFE 0 ABE Al 10M Alarm Month A Month 01-12

7FFF5h RPT4 RPT5 Al 10 Date Alarm Date Al Date 01-31

7FFF4h RPT3 0 Al 10 Hours Alarm Hours A Hours 00-23

7FFF3h RPT2 Al 10 Minutes Alarm Minutes A Min 00-59

7FFF2h RPT1 Al 10 Seconds Alarm Seconds A Sec 00-59

7FFF1h 1000 Year 100 Year Century 00-99

7FFF0hWDFAF0BLYYYY Flag

Key s: S = SIGN Bit

FT = FREQUENCY TEST Bit

R = READ Bit

W = WRI T E Bi t

ST = STOP Bit

0 = Must be set to ’0’

Y = '1' or '0'

BL = Battery Low

AF = Alarm F la g

WDS = Wat chdog Steering Bit

BMB0-BMB 4 = Watchd og M ultipli er Bits

R B0-RB1 = Watchdog Resolution Bits

AFE = Alarm Flag Enable

ABE = Alarm in Battery Back-up Mode Enable

R PT1- R PT5 = A l arm Repe at Mode Bit s

WDF = Wat chdog Fl ag

13/18

M48T513Y, M 48T513V

Figure 11. Alarm Interrupt Reset Waveform

Figure 12. Back-up M ode Alarm Waveform s

AI02581

AD0-AD7

ACTIVE FLAG BIT

ADDRESS 1FF0h

IRQ/FT

HIGH-Z

15ns Min

AI01678C

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

AFE bit in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

tREC

If a binary ’1’ is loaded into the register, only the

first 2 minutes in the 64 minute cycle will be modi-

fied; if a binary 6 is loaded, the first 12 will be af-

fected, and so on. Therefore, each calibration step

has the eff ect of adding 512 or subtracting 256 os-

cill ator cycles for every 125, 829, 120 actual oscil-

lator cycles, that is +4.068 or –2.034 ppm of

adjustment per calibration step in the calibration

registe r. Assum ing that the oscilla tor is running at

exactly 32,768Hz, each of the 31 increments in the

Calibration byte would represent +10.7 or –5.35

seconds per month which corresponds to a total

range of +5.5 or –2.75 minutes per month. Figure

10 illustrates a TIMEKEEPER calibration wave-

form.

Two methods are available for ascertaining how

much calibration a given M48T513Y/V may re-

quire. The first involves se tting the clock, letting it

run for a month and compari ng i t to a known accu-

rate reference and recording deviation over a fixed

period of time.

Calibration values, including the number of sec-

onds lost or gained in a given peri od, can be found

in Application Note: TIMEKEEPER CALIBRA-

TION.

M48T513Y, M48T513V

14/18

Table 12. Alarm Repeat Mode

RPT4 RPT3 RPT2 RPT1 Alarm Activated

1 1 1 1 Once per Second

1 1 1 0 Once per Minute

1 1 0 0 Once per Hour

1 0 0 0 Once per Day

1 0 0 0 Once per Month

Figure 13. Supply Voltage Protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

This allows the designer to give the end user the

ability to cali brate the clock as the environment re-

quires, even if the final product is packaged in a

non-user serviceable enclosure. The designer

could provide a simple utility that accesses the

Calibrat i on byte .

The second approach is better suited to a manu-

facturing envi ronment, and involves the use of the

IRQ/FT pin. The pin wil l toggle at 512Hz, when the

Stop bit (ST, D7 of 7FFF9h) is ’0’, the Frequency

Test bit (FT, D6 of 7FFFCh) is ’1’, the Alarm Fl ag

Enable bit (AFE, D7 of 7FFF6h) is ’0’, and the

Watchdog Steering bit (WDS, D7 of 7FFF7h) is ’ 1’

or the Watchdog Register (7FFF7h = 0) is reset.

Note: A 4 second settling time must be allowed

before reading the 512Hz output.

Any deviation from 512Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of

512.010124Hz would indicate a +20 ppm oscillator

frequency error, requiring a –10 (WR001010) to be

loaded into the Calibration Byte for correction.

Note that setting or ch anging the Calibration Byte

does not affect the Frequency test output frequen-

cy.

The IRQ/FT pin is an open d rain out put which re-

quires a pull-up resistor for proper operation. A

500-10kΩ resistor is recommended in order to

control the r ise time. The FT bit is cleared on pow-

er-up.

BATTERY LOW WARNING

The M48T513Y/V automatically performs battery

voltage monitoring upo n power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) bit, Bit D4 of Flags

voltage is found to be less than approximately

2.5V.

If a battery low is generated during a power-up se-

quence, this indicates that the battery is below ap-

proximately 2.5 volts and may not be able to

maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct.

If a battery low indication is genera ted during the

24-hour interval check, this indicates that the bat-

tery is near end of life. However, data is not com-

promised due to the fact that a nominal VCC is

supplied.

The M48T513Y/V onl y monitors the battery when

a nominal VCC is applied to the device. Thus appli-

cations which require extensive durations in the

battery back- up mode should be powered-up peri-

odically (at least once every few mont hs) in order

for this technique to be beneficial. Additionally, i f a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

POWER-ON DEFAULTS

Upon application of power to the device, the fol-

lowing register bits are set to a '0' state: WDS,

BMB0 - BMB4, R B0 ,RB1, AF E, ABE, W, R a n d F T .

15/18

M48T513Y, M 48T513V

Table 13. Reset AC Characteristics

(TA = 0 to 70 °C, VCC = 3.0V to 3.6V or VCC = 4.5V to 5.5V)

Note: 1. CL = 5pF (see Fi gure 4)

Symbol Parameter Min Max Unit

tRRSTIN Low to RST Low 20 100 ms

tRHRZ (1) RSTIN High to RST Hi-Z 40 200 ms

Figure 14. RSTIN Timing Waveform

AI02585

tRHRZ

RSTIN

RST

Hi-Z Hi-Z

POWER SUPPLY DECOUPLING

and UNDERSHOO T PROTECTION

Note: ICC tr ansients , includi ng t hose produced by

output switching, can produce voltage fluctua-

tions, resulting in spikes on the VCC bus. These

transients can be reduced if capacitors are used to

store energy, which stabilizes the VCC bus. The

energy stored in the bypass c apacitors will be re-

leased as low going spikes are generat ed or ener-

gy will be absorbed when overshoots occur. A

ceramic by pass capacitor v alue of 0. 1 microfarad

is recommended in order to provide the needed fil-

tering. In addition t o transients that are c aused by

normal SRAM operation, power cycling can gener-

ate negative v ol tage s pikes on VCC that drive it to

values be low VSS by as m uch as one volt. These

negative spikes can cause data corruption in the

SRAM while in battery backup mode. To protect

from these voltage spikes, ST recommends con-

necting a schottky diode from VCC to VSS (cathode

connected to VCC, anode to VSS). (Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 i s recommended for surface mount).

M48T513Y, M48T513V

16/18

Table 14. Ordering Information Scheme

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, pleas e contact the ST Sales Office nearest to you.

Example: M48T513Y -70 PM 1

Device Type

M48T

Supply Voltage and Write Protect Voltage

513Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V

513V = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V

Speed

-70 = 70ns

-85 = 85 ns

Package

PM = PMLDIP36

Temperature Range

1 = 0 to 70 °C

Table 15. Revision History

Date Revision Details

July 1998 First Issue

12/01/99

M48T513Y: VPFD (Min) changed

Paragraph "SETTING ALARM CLOCK" changed

M48T513Y: ICC Max changed (Table 6A)

M48T513V: ICC Max changed (Table 6B)

Figure 4 changed

tFB changed (Figure 5, Table 8)

tREC added (Figure 5, Table 8)

Paragraph "WATCHDOG TIMER" changed

Paragraph "POWER-ON RESET" changed

Paragraph "BATTE RY LOW WAR NING " changed

Figure 12 change d

Table Title changed (Table 13)

17/18

M48T513Y, M 48T513V

Table 16. PMLDIP36 - 36 pin Long Plastic Module DIP, Package Me chanic al Data

Symb mm inches

Typ Min Max Typ Min Max

A 9.27 9.52 0.365 0.375

A1 0.38 – 0.015 –

B 0.43 0.59 0.017 0.023

C 0.20 0.33 0.008 0.013

D 52.58 53.34 2.070 2.100

E 18.03 18.80 0.710 0.740

e1 2.30 2.81 0.090 0.110

e3 38.86 47.50 1.530 1.870

eA 14.99 16.00 0.590 0.630

L 3.05 3.81 0.120 0.150

S 4.45 5.33 0.175 0.210

N36 36

Figure 15. PMLDIP36 - 36 pin Long Plas tic Module DIP, Packag e Outline

Drawing is not to scale.

PMDIP

Be1

M48T513Y, M48T513V

18/18

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