UL62H1616SK20G1 - Alliance Memory, Inc.

1 November 01, 2001

UL62H1616B

Preliminary

F65536 x 16 bit static CMOS RAM

F15 and 20 ns Access Time

FCommon data inputs and

data outputs

FThree-state outputs

FStandby curre nt < 50 µA at 1 25°C

FPower supply voltage 2.5 V

FOperating temperature range

K-Type:-40 °C to 85 °C

A-Type:-40 °C to 125 °C

FCECC 90000 Qua lity Standard

FESD protection > 2000 V

(MIL STD 883C M3015.7)

FLatch-up im mun ity >100 mA

FPackage: SOP44 (525 m il)

The UL62H1616B is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Lower / Upper Byte Read

- Word Read

- Lower / Upper Byte Write

- Word Write

- Standby

- Data Retention

The memory array is based on a

6-Transistor cell.

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simul taneously.

According to the information of W

and G, the data inputs, or outputs,

are active. During the active state

E = L and W = H each address

change lead s to a new Read cycle.

In a Read cycle, the data outputs

are activated by the falling edge of

G. If LB = L the data lower byte will

be available at the outputs DQ0-

DQ7, on UB = L the data upper

byte appear at the outputs DQ8-

DQ15. After the address change,

the data outputs go High-Z until the

new information is available. The

data outputs have no preferred

st ate. The Read cycle is finished by

the falling edge of W, or by the

rising edge of E, respecti ve ly.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

Lo w Voltage Autom o tive Fast 64K x 16 SRAM

Pin Confi gur a tion

Top View

Signal Name Signa l Description

A0 - A15 Address Inputs

DQ0 - DQ15 Data In/Out

EChip Enable

GOutpu t Enable

WWrite Enable

UB Upper Byte Enable

LB Lower Byte Enable

VCC Power Supply Volta ge

VSS Ground

n.c. not connecte d

Pin Description

VCC

2A3 A6

4A1 G

5A0 UB

3A2 A7

7DQ0 LB

8DQ1 DQ15

12VSS

9DQ2

DQ9

10DQ3

DQ8

11VCC

n.c.

13DQ4

14DQ5

A10

SOP

DQ7

A15

A14

A13

A12

n.c.

DQ6

DQ14

DQ13

DQ12

VSS

DQ11

DQ10

n.c.

A11

Features Description

2 November 01, 200 1

UL62H1616B Preliminary

Operating Mode E W G LB UB DQ0-DQ7 DQ8-DQ15

Standby/not selected H * * * * High-Z High-Z

Internal Read L

HHigh-Z High-Z

Lower Byte Read L H L L H Data Outputs Low-Z High-Z

Upper Byte Read L H L H L High-Z Data Outputs Low-Z

Word Read L H L L L Data Outputs Low-Z Data Outputs Low-Z

Lower Byte Write L L * L H Data Inputs High-Z High-Z

Upper Byte Write L L * H L High-Z Data Inputs High-Z

Word Write L L * L L Data Inputs High-Z Data Inp uts Hig h-Z

Truth Tabl e

Block Diagram

Maxim um Rati ngs Symb ol Min. Max. U nit

Power Supply Voltage VCC -0.3 3.6 V

Input Voltage VI-0.3 VCC + 0.3 V

Outp ut Voltage VO-0.3 VCC + 0.3 V

Power Dissipation PD-1W

Operating Temperature K-Type

A-Type Ta-40

-40 85

125 °C

Storage Temperature Tstg -65 150 °C

Outp ut Short-Circuit Current

at VCC = 2.5 V and VO = 0 V** | IOS | 100 mA

Characteristics

**Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

All vol tages are referenc ed to VSS = 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI,as well as

input levels of VIL = 0 V and VIH = 2.5 V. The timing re ference level of all input and output signal s is 1.2 V,

with the exception of the tdis-tim e s an d ten-times, in which cases transition is measured ±200 mV from steady-state voltage.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VCC VSS W GE

Row Address

Inputs

Column Address

Inputs

Address

Change

Detector

Column Decode r Row Decode r

Sense Ampl ifi er/

Write Control Logic

Clock

Generator

Common Data I/O

Memory Cell

Array

512 Rows x

128 x 16 Col um n s

A10

A11

A12

A13

A14

A15

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

UB LB

*H or L

3 November 01, 2001

UL62H1616B

Preliminary

Recommended

Operating Conditions Symbol Conditions Min. Max. Unit

Power Supply Voltage VCC 2.3 2.7 V

Input Low V ol t age*VIL -0.2 0.6 V

Input High V ol tage VIH 2.0 VCC + 0.2 V

Electrical Characteristic s Symbol Conditions Min. Max. Unit

Suppl y Current - Operating Mode

Suppl y Current - Standby Mode

(CMOS level)

Suppl y Current - Standby Mode

(LVTTL level)

ICC(OP)

ICC(SB)

ICC(SB)1

VCC

VIL

VIH

tcW

VCC

K-Type

A-Type

= 2.7 V

= 0.6 V

= 2.0 V

= 35 ns

= 55 ns

= 60 ns

= 2.7 V

= VCC - 0.2 V

= 2.7 V

= 2.0 V

µA

Outpu t High Vo ltage

Outpu t Low Vol tage

VOH

VOL

VCC

IOH

VCC

IOL

= 2.3 V

=-0.5 mA

= 2.3 V

= 0.5 mA

2.0

0.4

Input High Leakage Current

Input Low Leakage Current

IIH

IIL

VCC

VIH

VCC

VIL

= 2.7 V

= 0 V -2

2µA

µA

Outpu t High Current

Outpu t Low Current

IOH

IOL

VCC

VOH

VCC

VOL

= 2.3 V

= 2.0 V

= 2.3 V

= 0.4 V 0.5

-0.5 mA

Outpu t Leakage Current

High at Three-State Outputs

Low at Three-St ate Outputs

IOHZ

IOLZ

VCC

VOH

VCC

VOL

= 2.7 V

=0 V -2

2µA

µA

* -2 V at Pulse Width 10 ns

4 November 01, 200 1

UL62H1616B Preliminary

Switching Characteristics

Read Cycle Symbol 15 20 Unit

Alt. IEC Min. Max. Min. Max.

Read Cycle Time tRC tcR 15 20 ns

Address Access Time to Data Valid tAA ta(A) 15 20 ns

Chip Enable Access Time to Data Valid tACE ta(E) 15 20 ns

G LOW to Data Valid tOE ta(G) 79ns

LB, U B LOW to Data V alid tBta(B) 79ns

E HIGH to Output in High-Z tHZCE tdis(E) 78ns

G HIGH to Output in High-Z tHZOE tdis(G) 78ns

LB, U B HIGH to Output in High-Z tHZB tdis(B) 78ns

E LOW to Output in Low-Z tLZCE ten(E) 44ns

G LOW to Output in Low-Z tLZOE ten(G) 00ns

LB, U B LOW to Output in Low-Z tLZB ten(B) 00ns

Output Hold T i me from Address Change tOH tv(A) 33ns

E LOW to Power-Up Time tPU 00ns

E HIGH to Power-Down Time tPD 15 20 ns

Switching Characteristics

Write Cycle Symbol 15 20 Unit

Alt. IEC Min. Max. Min. Max.

Write Cycle Time tWC tcW 15 20 ns

Write Pulse Width tWP tw(W) 10 12 ns

Write Setup Time tWP tsu(W) 10 12 ns

Address Setup Time tAS tsu(A) 00ns

Address Valid to End of Wri te tAW tsu(A-WH) 10 12 ns

Chip Enable Setup Time tCW tsu(E) 10 12 ns

Byte Enable Set up Time tBW tsu(B) 10 12 ns

Pulse Width Chip Enable to End of Write tCW tw(E) 10 12 ns

Pulse Width Byte Enable to End of Write tBW tw(B) 10 12 ns

Da ta Se tu p Time tDS tsu(D) 79ns

Data Hold Time tDH th(D) 00ns

Address Hold from End of Write tAH th(A) 00ns

W LOW to Output in High-Z tHZWE tdis(W) 78ns

G HIGH to Output in High-Z tHZOE tdis(G) 78ns

W HIGH to Output in Low-Z tLZWE ten(W) 33ns

G LOW to Output in Low-Z t LZOE ten(G) 00ns

5 November 01, 2001

UL62H1616B

Preliminary

Data Retention Mode

E - controlled

Data Retention

2.3 V

tsu(DR) trec

VCC

VCC(DR) ≥ 1.5 V

0 V

2.0 V

VCC(DR) - 0.2 V ≤ VE(DR) ≤ VCC(DR) + 0.3 V

Data Retention

Characteristics Symbol Conditions Min. Typ. Max. Unit

Alt. IEC

Data Retention Supply Vol tage VCC(DR) 1.5 2.7 V

Data Retention Supply Current ICC(DR) VCC(DR) = 2 V

VE = VCC(DR) - 0.2 V 30 µA

Data Retention Setup Time tCDR tsu(DR) See Data Retention

Waveforms (above) 0ns

Operating Recovery Ti me tRtrec tcR ns

Tes t Co nfig urat io n f or Fu nc ti onal Chec k

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

VIH

VIL

VSS

VCC

2.5 V

481

255

30 pF1)

Inp ut leve l acco rding to t he

relev ant test me asurement

Simultaneous measure-

m ent of all 16 output pins

A10

A11

A12

A13

A14

A15

1) In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 p F.

6 November 01, 200 1

UL62H1616B Preliminary

Capacitance Conditions Symbol Min. Max. Unit

Input Capacitance VCC

= 2.5 V

= VSS

= 1 MHz

= 25 °C

CI7pF

Output Capacitance Co7pF

IC Code Numbers

UL62H1616 SA15

Type

Package

S = SOP44 525 mil

Oper ating Temp erature Range

K = -40 to 85 °C

A = -40 to 125 °C

Access Time

15 = 15 ns

20 = 20 ns

The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2

digits the calendar week.

All pins not under test must be connected with ground by capacitors.

7 November 01, 2001

UL62H1616B

Preliminary

tPU

tdis(G)

tdis(E)

tcR

Previous Data Valid Output Data Valid

Address Valid

tsu(A)

High-Z

ten(E)

ten(G)

ta(G)

ta(E)

Read Cycle 1: Ai-c ontrolle d (during Read Cycle : E = G = VIL, W = VIH)

Read Cycle 2: G-, E-, LB-, U B-controlled (during Read Cycle: W = VIH)

ta(A)

tcR

tv(A)

DQi

Output

DQi

Output tPD

ICC(OP)

ICC(SB) 50 % 50 %

Output Data Valid

tdis(B)

ten(B)

ta(B)

LB, UB

Write Cycl e1: W-controlled

th(D)

LB, UB

DQi

Output

tcW

tsu(E) th(A)

tw(W)

tsu(A) tsu(D)

tdis(W) ten(W)

Address Valid

High-Z

Input Input Data Valid

tsu(B)

tsu(A-WH)

8 November 01, 200 1

UL62H1616B Preliminary

Writ e Cy cle 2: E -controlled

Input Data Valid

tsu(A)

th(D)

DQi

Input

DQi

Output

tcW

tw(E) th(A)

tsu(W)

tsu(D)

tdis(W)

en(E)

High-Z

Addres s Vali d

tsu(B)

LB, UB

tdis(G)

Write Cycle 3: LB-, UB-controlled

Input Data Valid

tsu(A)

th(D)

DQi

Output

tcW

tw(B) th(A)

tsu(W)

tsu(D)

tdis(W)

en(B)

High-Z

Address Valid

tsu(E)

LB, UB

tdis(G)

L- to H-level undefined H- to L-leve l

The information describes the type of component and shall not be considered as assured characteristics.Terms of

delivery and rights to change design rese rved.

Input

Zentrum Mikroelektronik Dresden AG

Grenzstra ße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany

Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: sales@zmd.de • http://www.zmd.de

November 01, 2001

UL62H1616B

Preliminary

LIFE S U PP O R T POLI CY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or o ther application s intended to support or sustain life, or for any other application in which

the failure of the ZMD product could create a situation where personal injury or death may occur.

Componen ts used in life-s upport devices or systems must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However Zentrum

Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said in formation

and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.

The inform ation in this docum ent des cribes t he t ype of comp onent and sh all not be c onsidere d as ass ured charac-

teristics.

ZMD does not guarantee that the use of any information contained herei n will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This

document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and

condition s of sale.

ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,

presented in this publication at any time and without notice.