PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS84324 is a Crystal-to-3.3V LVPECL Frequency Synthesizer with Fanout Buffer and a memHiPerClockSTM ber of the HiPerClockSTM family of High Performance Clock Solutions from ICS. Output frequency can be programmed using the feedback and output frequency select pins. The low phase noise characteristics of the ICS84324 make it an ideal clock source for Fibre Channel 1 and Gigabit Ethernet applications. * 6 differential 3.3V LVPECL outputs FUNCTION TABLE ,&6 * Crystal oscillator interface * Output frequency range: 53.125MHz to 125MHz * Crystal input frequency: 25MHz * Cycle-to-cycle jitter: 25ps (typical) * RMS phase jitter at 106.25MHz, using a 25MHz crystal (637KHz to 10Mhz): 4.15ps 0 0 0 53.125MHz * Typical Phase noise at 106.25MHz Offset Noise Power 100Hz .................. -80dBc/Hz 1KHz ................ -105dBc/Hz 10KHz ................ -125dBc/Hz 100KHz ................ -125dBc/Hz 0 0 1 106.25MHz * 3.3V supply voltage 0 1 0 62.5MHz * 0C to 70C ambient operating temperature 0 1 1 125MHz * Industrial termperature information available upon request Inputs Output Frequency MR F_SEL1 F_SEL0 F_OUT 1 X X LOW BLOCK DIAGRAM PIN ASSIGNMENT XTAL1 0 OSC XTAL2 1 Output Divider PLL 6 Q0:Q5 6 nQ0:nQ5 / / Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Feedback Divider 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC F_SEL0 F_SEL1 MR XTAL1 XTAL2 VEE VCCA VCC PLL_SEL VEE VCC ICS84324 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View F_SEL1 MR PLL_SEL F_SEL0 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 84324DM www.icst.com/products/hiperclocks.html 1 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Type Description Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 11, 12 Q5, nQ5 Output Differential output pair. LVPECL interface levels. 13, 16, 24 VCC Power Core supply pins. 14, 18 VEE 15 PLL_SEL Input 17 VCCA Power Analog supply pin. 19, 20 XTAL2, XTAL1 Input Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Negative supply pins. Pullup Selects between the PLL and cr ystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels. 21 MR Input Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs Pulldown nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 22 F_SEL1 Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. 23 F_SEL0 Input Pullup Output frequency select pin. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum CIN Input Capacitance RPULLUP Input Pullup Resistor 51 K RPULLDOWN Input Pulldown Resistor 51 K 84324DM 4 Units www.icst.com/products/hiperclocks.html 2 pF REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VCC -0.5V to VCC + 0.5 V Outputs, VCC -0.5V to VCC + 0.5V Package Thermal Impedance, JA 50C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 135 mA ICCA Analog Supply Current 20 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V PLL_SEL, MR, F_SEL0, F_SEL1 PLL_SEL, MR, F_SEL0, F_SEL1 MR, F_SEL1 VCC = VIN = 3.465V 150 A PLL_SEL, F_SEL0 VCC = VIN = 3.465V 5 A MR, F_SEL1 VCC = 3.465V, VIN = 0V -5 A PLL_SEL, F_SEL0 VCC = 3.465V, VIN = 0V -150 A TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 1.0 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50 to VCC - 2V. 84324DM www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 70 Shunt Capacitance 7 pF TABLE 5. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C Symbol Parameter FOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter ; NOTE 2 tsk(o) Output Skew; NOTE 1, 2 Test Conditions Minimum Typical Maximum Units 125 MHz 53.125 25 ps TBD ps tR Output Rise Time 20% to 80% 200 650 ps tF Output Fall Time 20% to 80% 200 650 ps odc Output Duty Cycle tPW Output Pulse Width 50 tPERIOD/2 - TBD % tPERIOD/2 + TBD PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCC/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 84324DM www.icst.com/products/hiperclocks.html 4 1 ps ms REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TYPICAL PHASE NOISE AT 106.25MHZ USING A 25MHZ QUARTZ CRYSTAL 0 -10 -20 -30 -40 Process Result Source -50 -60 -70 Start Freq. 10.000 Hz Stop Freq. 40.000M Hz Freq. carrier 106.250M Hz Mode -80 Noise only sec. rms Integral 4.15p -90 Execute Plot -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1 100 1k 10k 100k 1M 10M 100M 637KHz to 10MHz, 4.15ps RMS 84324DM www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCC, VCCA = 2V Qx SCOPE nQx Qx LVPECL nQy nQx Qy tsk(o) VEE = -1.3V 0.165 OUTPUT SKEW 3.3V OUTPUT LOAD AC TEST CIRCUIT nQ0:nQ5 80% 80% Q0:Q5 tcycle n tcycle n+1 20% 20% Clock Outputs t R t F t jit(cc) = tcycle n -tcycle n+1 1000 Cycles OUTPUT RISE/FALL TIME CYCLE-TO-CYCLE JITTER nQ0:nQ5 Q0:Q5 Pulse Width t odc = PERIOD t PW t PERIOD odc & tPERIOD 84324DM www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84324 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01F 10 V CCA .01F 10 F FIGURE 2. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE A crystal can be characterized for either series or parallel mode operation. The ICS84324 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 3. 19 XTAL2 C1 18pF 25MHz X1 20 XTAL1 C2 22pF ICS84324 Figure 3. CRYSTAL INPUt INTERFACE 84324DM www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50 5 2 Zo FIN FOUT 5 2 Zo Zo = 50 Zo = 50 FOUT 50 RTT = 1 (VOH + VOL / VCC -2) -2 Zo = 50 VCC - 2V RTT 3 2 Zo Zo FIGURE 4A. LVPECL OUTPUT TERMINATION 84324DM FIN 50 3 2 Zo FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84324. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84324 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 468mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30.2mW = 181mW Total Power_MAX (3.465V, with all outputs switching) = 468mW + 181mW = 649mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.649W * 43C/W = 98C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE qJA FOR 24-PIN SOIC, FORCED CONVECTION qJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 50C/W 43C/W 38C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 84324DM www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CC * For logic high, VOUT = V OH_MAX (V CC_MAX * -V OH_MAX OL_MAX CC_MAX CC_MAX - 1.0V ) = 1.0V For logic low, VOUT = V (V =V =V CC_MAX - 1.7V ) = 1.7V -V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX - (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 1V)/50) * 1V = 20.0mW Pd_L = [(V OL_MAX - (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V ))/R ] * (V OL_MAX L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 84324DM www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 50C/W 43C/W 500 38C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84324 is: 2882 84324DM www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER PACKAGE OUTLINE - M SUFFIX TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum Maximum N A 24 -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 15.20 15.85 E 7.40 e H 7.60 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-013, MO-119 84324DM www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84324 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS84324DM ICS84324DM 24 Lead SOIC 30 per tube 0C to 70C ICS84324DMT ICS84324DM 24 Lead SOIC on Tape and Reel 1000 0C to 70C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84324DM www.icst.com/products/hiperclocks.html 13 REV. A JANUARY 30, 2003