MCP2021A/2A LIN Transceiver with Voltage Regulator Features Description * The MCP2021A/2A is compliant with: - LIN Bus Specifications Version 1.3, and 2.x. - SAE J2602-2 * Support Baud Rates up to 20 kBaud * 43V Load Dump Protected * Maximum Continuous Input Voltage of 30V * Wide LIN Compliant Supply Voltage, 6.0 - 18.0V * Extended Temperature Range: -40 to +125C * Interface to PIC(R) EUSART and Standard USARTs * Wake-up on LIN Bus Activity or Local Wake Input * LIN Bus Pin - Internal Pull-up Termination Resistor and Diode for Slave Node - Protected Against VBAT Shorts - Protected Against Loss of Ground - High Current Drive * TXD and LIN Bus Dominant Time-out Function * Two Low-Power Modes - TRANSMITTER OFF Mode: 9 A (typical) - POWER DOWN Mode: 4.5A (typical) * Output Indicating Internal RESET State (POR or SLEEP Wake) * MCP2021A/2A On-chip Voltage Regulator - Output Voltage of 5.0V or 3.3V 70 mA Capability withTolerances of 3% Over Temperature Range - Internal Short Circuit Current Limit - Only External Filter and Load Capacitors Needed * Automatic Thermal Shutdown * High Electromagnetic Immunity (EMI), Low Electromagnetic Emission (EME) * Robust ESD Performance: 15 kV for LBUS and VBB pin (IEC61000-4-2) * Transient Protection for LBUS and VBB Pins in Automotive Environment (ISO7637) * Meets Stringent Automotive Design Requirements Including "OEM Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications", Version 1.2, March 2011 * Multiple Package Options Including Small 4x4 mm DFN The MCP2021A/2A provides a bidirectional, halfduplex communication physical interface to meet the LIN bus specification Revision 2.1 and SAE J2602-2. The device incorporates a voltage regulator with 5V or 3.3V 70 mA regulated power supply output. The device has been designed to meet the stringent quiescent current requirements of the automotive industry and will survive +43V load dump transients, and double battery jumps. 2012 Microchip Technology Inc. Package Types (Top View) MCP2021A PDIP, SOIC FAULT/TXE RXD 1 8 CS/LWAKE 2 7 VBB VREG 3 6 LBUS TXD 4 5 VSS MCP2021A 4x4 DFN RXD 1 CS/LWAKE 2 VREG 3 TXD 4 8 FAULT/TXE EP 9 7 VBB 6 LBUS 5 VSS MCP2022A PDIP, SOIC, TSSOP RXD 1 14 CS/LWAKE 2 13 FAULT/TXE VBB VREG 3 12 LBUS TXD 4 11 VSS RESET 5 10 NC NC 6 9 NC NC 7 8 NC * Includes Exposed Thermal Pad (EP). DS22298A-page 1 MCP2021A/2A Block Diagram VREG RESET Thermal Protection Short Circuit Protection (MCP2022A ONLY) Voltage Regulator VREG Internal Circuits 4.2V VREG VBB Ratiometric Reference Wake-Up Logic and Power Control Bus Wakeup RXD CS/LWAKE Slope Control ~30 k LBUS TXD Bus Dominant Timer FAULT/TXE VSS Thermal and Short Circuit Protection MCP2021A/2A Family Members Device Package Regulator Output Voltage RESET Pin MCP2021A-500 8-PIN DFN, SOIC, PDIP 5.0V No MCP2021A-330 8-PIN DFN, SOIC, PDIP 3.3V No MCP2022A-500 14-PIN SOIC, TSSOP, PDIP 5.0V Yes MCP2022A-330 14-PIN SOIC, TSSOP, PDIP 3.3V Yes DS22298A-page 2 2012 Microchip Technology Inc. MCP2021A/2A 1.0 FUNCTION DESCRIPTION 1.1 The MCP2021A/2A provides a physical interface between a microcontroller and a LIN half-duplex bus. It is intended for automotive and industrial applications with serial bus baud rates up to 20 Kbaud. This device will translate the CMOS/TTL logic levels to LIN logic levels, and vice versa. The device offers optimum EMI and ESD performance; it can withstand high voltage on the LIN bus. The device supports two low-power modes to meet automotive industry power consumption requirements. The MCP2021A/2A also provides a +5V or 3.3V 70 mA regulated power output. FIGURE 1-1: Modes of Operation The MCP2021A/2A works in five modes: POWER-ONRESET mode, POWER-DOWN mode, READY mode, OPERATION mode, and TRANSMITTER OFF mode. For an overview of all operational modes, please refer to Table 1-1. For the operational mode transition, please refer to Figure 1-1. STATE DIAGRAM CS/LWAKE=0 POR(2) VREG OFF RX OFF TX OFF READY VREG ON RX ON TX OFF VBB>VON CS/LWAKE=1 & FAULT/TXE=1(3) & TXD=1& VREG_OK=1(1) CS/LWAKE=1& FAULT/TXE=0& VREG_OK=1(1) CS/LWAKE=1 OR Voltage Rising Edge on LBUS CS/LWAKE=1& FAULT/TXE=1(3)& TXD=1 TX OFF VREG ON RX ON TX OFF OPERATION VREG ON RX ON TX ON CS/LWAKE=1& FAULT/TXE=0 CS/LWAKE=0 POWER-DOWN VREG OFF RX OFF TX OFF CS/LWAKE=0 Note 1: VREG_OK : Regulator Output Voltage > 0.8VREG_NOM. 2: If the voltage on pin VBB falls below VOFF, the device will enter POWER ON RESET mode from all other modes, which is not shown in the figure. 3: FAULT/TXE = 1 represents input high and no fault conditions. FAULT/TXE = 0 represents input low or a fault condition, Refer to Table 1-3. 1.1.1 POWER-ON-RESET MODE Upon application of VBB, or whenever the voltage on VBB is below the threshold of regulator turn off voltage VOFF (typically 4.50V), the device enters POWER-ONRESET mode (POR). During this mode, the device maintains the digital section in a reset mode and waits 2012 Microchip Technology Inc. until the voltage on VBB pin rises above the threshold of regulator turn on voltage VON (typically 5.75V) to enter to the READY mode. In POWER-ON-RESET mode, the LIN physical layer and voltage regulator are disabled, and RESET output (MCP2022A only) is forced to LOW. DS22298A-page 3 MCP2021A/2A 1.1.2 READY MODE The transmitter may be re-enabled whenever the FAULT/TXE signal returns high, by removing the internal fault condition and the CPU returning the FAULT/ TXE high. The transmitter will not be enabled even if the FAULT/TXE pin is brought high externally, when the internal fault is still present. However, externally forcing the FAULT/TXE high while internal fault is still present should be avoided, since this will induce high current and power dissipation in the FAULT/TXE pin. The device enters READY mode from POR mode after the voltage on VBB rises above the threshold of regulator turn on voltage VON or from POWER-DOWN mode when a remote or local wake-up event happens. Upon entering READY mode, the voltage regulator and receiver section of the transceiver are powered up. The transmitter remains in an off state. The device is ready to receive data but not to transmit. In order to minimize the power consumption, the regulator operates in a reduced power mode. It has a lower GBW product and thus is slower. However, the 70 mA drive capability is unchanged. The transmitter is also turned off whenever the voltage regulator is unstable or recovering from a fault. This prevents unwanted disruption of the bus during times of uncertain operation. 1.1.5 The device stays in READY mode until the output of the voltage regulator has stabilized and the CS/LWAKE pin is HIGH (`1'). 1.1.3 In POWER-DOWN mode, the transceiver and the voltage regulator are both off. Only the Bus Wake-up section and the CS/LWAKE pin wake-up circuits are in operation. This is the lowest power mode. OPERATION MODE If VREG is OK (VREG>0.8VREG_NORM), and the CS/ LWAKE pin, FAULT/TXE pin and TXD pin are HIGH, the part enters OPERATION mode from either READY or TRANSMITTER OFF mode. If any bus activity (e.g. a BREAK character) occurs during POWER-DOWN mode, the device will immediately enter READY mode and enable the voltage regulator. Then, once the regulator output has stabilized (approximately 0.3 ms to 1.2 ms), it goes to OPERATION mode. Refer to Section 1.1.6 "Remote Wake-up". In this mode, all internal modules are operational. The internal pull-up resistor between LBUS and VBB is connected only in this mode. The part will also enter READY mode from POWERDOWN mode, followed by the OPERATION mode, if the CS/LWAKE pin becomes active HIGH (`1'). The device goes into POWER-DOWN mode at the falling edge on CS/LWAKE; or to the TRANSMITTER OFF mode at the falling on FAULT/TXE while CS/ LWAKE stays HIGH. 1.1.4 1.1.6 REMOTE WAKE-UP The remote wake-up sub module observes the LBUS in order to detect bus activity. In POWER DOWN mode, normal LIN recessive/dominant threshold is disabled, and the LIN bus Wake-Up Voltage Threshold VWK(LBUS) is used to detect bus activities. Bus activity is detected when the voltage on the LBUS falls below the LIN bus Wake-Up Voltage Threshold VWK(LBUS) (approximately 3.5V) for at least tBDB (a typical duration of 80 s ) followed by a rising edge. Such a condition causes the device to leave POWER-DOWN mode. TRANSMITTER OFF MODE In TRANSMITTER OFF mode, the receiver is enabled but the LBUS transmitter is off. It is a lower power mode. In order to minimize power consumption, the regulator operates in a reduced power mode. It has a lower GBW product and thus is slower. However the 70 mA drive capability is unchanged. TABLE 1-1: POWER-DOWN MODE OVERVIEW OF OPERATIONAL MODES Transmitter Receiver Internal Wake Module Voltage Regulator POR OFF OFF OFF OFF Transfer to READY mode after VBB>VON READY OFF ON OFF ON If CS/LWAKE high, then proceed to Bus Off state OPERATION or TRANSMITTER OFF mode. OPERATION ON ON OFF ON If CS/LWAKE low level, then Power down If FAULT/TXE low level, then TRANSMITTER-OFF mode Normal Operation mode POWER DOWN OFF OFF ON Activity Detect OFF On LIN bus rising edge or CS/LWAKE high level, go to READY mode. Lowest Power mode TRANSMITTER-OFF OFF ON OFF ON If CS/LWAKE low level, then Power down Bus Off state, If FAULT/TXE high, then OPERATION mode Lower Power mode State DS22298A-page 4 Operation Comments 2012 Microchip Technology Inc. MCP2021A/2A 1.2 Pin Descriptions Please refer to Table 1-2 for the pinout overview. 1.2.1 VBB Battery Positive Supply Voltage pin. An external diode is connected in series to prevent the device from being reversely powered (refer to FIGURE 1-9: "Typical Application Circuit"). 1.2.2 VREG Positive Supply Voltage Regulator Output pin. An onchip LDO gives +5.0 or +3.3V 70 mA regulated voltage on this pin. 1.2.3 VSS Ground pin. 1.2.4 TXD Transmit data input pin (TTL level, HV compliant, adaptive pull-up). The transmitter reads the data stream on TXD pin and sends it to LIN bus. The LBUS pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. The Transmit Data Input pin has an internal adaptive pull-up to an internally-generated 4.2V (approximately). When TXD is `0', a weak pull-up (~900 k) is used to reduce current. When TXD is `1', a stronger pull-up (~300 k) is used to maintain the logic level. A series reverse-blocking diode allows applying TXD input voltages greater than the internally generated 4.2V and renders TXD pin HV compliant up to 30V (see block diagram). 1.2.5 RXD Receive Data Output pin. The RXD pin is a standard CMOS output pin and it follows the state of the LBUS pin. 1.2.6 LBUS If CS/LWAKE = 1, the device can work in OPERATION mode (FAULT/TXE = 1) or TRANSMITTER OFF mode (FAULT/TXE = 0). If CS/LWAKE = 0, the device can work in POWERDOWN mode or READY mode. An internal pull-down resistor will keep the CS/LWAKE pin low to ensure that no disruptive data will be present on the bus while the microcontroller is executing a Power-on Reset and I/O initialization sequence. When CS/LWAKE is `1', a weak pull-down (~600 k) is used to reduce current. When CS/LWAKE is `0' a stronger pull-down (~300 k) is used to maintain the logic level. This pin may also be used as a local wake-up input (See FIGURE 1-9: "Typical Application Circuit"). The microcontroller will set the I/O pin to control the CS/LWAKE. An external switch, or other source, can then wake-up both the transceiver and the microcontroller. Note: 1.2.8 CS/LWAKE should NOT be tied directly to the VREG pin as this could force the MCP2021A/2A into Operation Mode before the microcontroller is initialized. FAULT/TXE Fault Detect Output/Transmitter Enable Input pin. The output section is HV tolerant open drain (up to 30V). The input section is identical with the TXD section (TTL level, HV compliant, adaptive pull-up). Internal adaptive pull-up maintains this input high '1' if the pin is floating. Its state is defined as shown in TABLE 1-3: "FAULT/TXE Truth Table". The device is placed in TRANSMITTER OFF mode whenever this pin is LOW (`0'), either from an internal fault condition or by external drive. If CS/LWAKE is HIGH (`1'), the FAULT/TXE signals a mismatch between the TXD input and the LBUS level. This can be used to detect a bus contention. Since the bus exhibits a propagation delay, the sampling of the internal compare is debounced to eliminate false faults. LIN Bus pin. LBUS is a bidirectional LIN bus Interface pin and is controlled by the signal TXD. It has an open collector output with a current limitation. To reduce ElectroMagnetic Emission, the slopes during signal changes are controlled, and the LBUS pin has cornerrounding control for both falling and rising edges. After the device wakes up, the FAULT/TXE indicates what wakes the device if CS/LWAKE remains LOW (`0') (refer Table 1-3). The internal LIN receiver observes the activities on the LIN bus, and generates the output signal RXD that follows the state of the LBUS. A 1st degree 160 kHz, low-pass input filter optimizes ElectroMagnetic immunity. 1.2.9 1.2.7 CS/LWAKE Chip Select and Local Wake-up Input pin (TTL level, high voltage tolerant). This pin controls the device state transition. Refer to FIGURE 1-1: "State Diagram". 2012 Microchip Technology Inc. The FAULT/TXE pin sampled at a rate faster than every 10 s. RESET (MCP2022A ONLY) RESET OUTPUT pin. This pin is open drain with ~90 k pull-up to VREG. It indicates the internal voltage has reached a valid, stable level. As long as the internal voltage is valid (above 0.8 VREG), this pin will remain HIGH (`1'); otherwise the RESET pin switches to LOW (`0'). DS22298A-page 5 MCP2021A/2A TABLE 1-2: PIN Name PINOUT OVERVIEW PIN Number MCP2021A PIN Type MCP2022A Function VREG 3 3 Output Voltage Regulator Output VSS 5 11 Power Ground VBB 7 13 Power TXD 4 4 Input, HV-tolerant RXD 1 1 Output Receive Data Output LBUS 6 12 I/O, HV LIN Bus Battery CS/LWAKE 2 2 FAULT/TXE 8 14 I/O, HV-tolerant RESET - 5 Output TABLE 1-3: Transmit Data Input TTL Input, HV-tolerant Chip Select and Local Wake-up Input Fault Detect Output/Transmitter Enable Input Reset Output FAULT/TXE TRUTH TABLE TXD In RXD Out LIN BUS I/O Thermal Override L H VBB OFF H H VBB OFF L L GND OFF H L GND OFF x x VBB ON x x VBB x FAULT/TXE External Input Definition Driven Output CS = 1 H L FAULT, TXD driven low, LIN BUS shorted to VBB (Note 1), or LBUS/TXD permanent dominant detected, and Transmit time-out shutdown. H H OK H H OK H H OK, data is being received from the LIN BUS H L FAULT, Transceiver in thermal shutdown L x NO FAULT, the CPU is commanding the transceiver to turn off the transmitter driver CS = 0 after a wake-up x x x x x L Wake-up from LIN bus activity x x x x x H Wake-up from POR Legend: x = don't care Note 1: The FAULT/TXE is valid after approximately 25 s after TXD falling edge. This is to eliminate false fault reporting during bus propagation delays. 1.3 1.3.1 Fail-Safe Features GENERAL FAIL-SAFE FEATURES * An internal pull-down resistor on CS/LWAKE pin disables the transmitter if the pin is floating. * An internal pull-up resistor on the TXD pin places TXD in HIGH thus the LBUS in recessive if TXD pin is floating. * High-impedance and low-leakage current on LBUS during loss of power or ground. * The current limit on LBUS protects the transceiver from being damaged if the pin is shorted to VBB. 1.3.2 THERMAL PROTECTION The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and voltage regulator. There are three causes for a thermal overload. A thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions. * Voltage regulator overload * LIN bus output overload * Increase in die temperature due to increase in environment temperature The recovery time from the thermal shutdown is equal to adequate cooling time. DS22298A-page 6 2012 Microchip Technology Inc. MCP2021A/2A Driving the TXD and checking the RXD pin make it possible to determine whether there is a bus contention (TXD = high, RXD = low) or a thermal overload condition (TXD = low, RXD = high). FIGURE 1-2: THERMAL SHUTDOWN STATE DIAGRAMS Voltage Regulator Shutdown Regarding the correlation between VBB, VREG and IDD, please refer to Figure 1-6 and Figure 1-7. When the input voltage (VBB) drops below the differential needed to provide stable regulation, the voltage regulator output VREG will track the input down to approximately VOFF. The regulator will turn off the output at this point. This will allow PIC(R) microcontrollers, with internal POR circuits, to generate a clean arming of the Power-on Reset trip point. The MCP2021A/2A will then monitor VBB and turn on the regulator when VBB is above the threshold of regulator turn on voltage VON. LIN bus shorted to VBB Output Overload Operation Mode Transmitter Shutdown Temp < SHUTDOWNTEMP Temp < SHUTDOWNTEMP 1.3.3 TXD/LBUS TIME-OUT TIMER The LIN bus can be driven to a dominant level either from the TXD pin or externally. An internal timer deactivates the LBUS transmitter if a dominant status (LOW) on the LIN bus lasts longer than Bus Dominant Time-out Time tTO(LIN) (approximately 20 milliseconds). At the same time, RXD output is put in recessive (HIGH), FAULT/TXE is also driven to LOW, and the internal LIN pull-up resistor is disconnected. The timer is reset on any recessive LBUS status or POR mode. The recessive status on LBUS can be caused either by the bus being externally pulled up or by the TXD pin being returned high. 1.4 With a load current of 70 mA, the minimum input to output voltage differential required for the output to remain in regulation is typically +0.5V (+1V maximum over the full operating temperature range). Quiescent current is less than 100 A with a full 70 mA load current when the input to output voltage differential is greater than +3.00V. In Power-down mode, the VBB monitor is turned off. Under specific ambient temperature and battery voltage range, the voltage regulator can output as high as 150mA current. For current load capability of the voltage regulator, refer Figure 1-4 and Figure 1-5. Note: Internal Voltage Regulator The MCP2021A/2A has a positive regulator capable of supplying +5.00 or +3.30 VDC 3% at up to 70 mA of load current over the entire operating temperature range of -40C to +125C. The regulator uses a LDO design, is short-circuit-protected and will turn the regulator output off if its output falls below the Shutdown Voltage Threshold VSD. FIGURE 1-3: The regulator overload current limit is approximately 250 mA. The regulator output voltage VREG is monitored. If output voltage VREG is lower than VSD, the voltage regulator will turn off. After a recovery time of about 3mS, the VREG will be checked again. If there is no short circuit (VREG > VSD), then the voltage regulator remains on. The regulator requires an external output bypass capacitor for stability. See Figure 2-1 for correct capacity and ESR for stable operation. VOLTAGE REGULATOR BLOCK DIAGRAM Pass Element VREG VBB Sampling Network Fast Transient Loop Buffer VSS VREF 2012 Microchip Technology Inc. DS22298A-page 7 MCP2021A/2A 5.0V VREG VS. IREG AT VBB = 12V FIGURE 1-5: 3.5 6 3 5 2.5 4 VREG (V) VREG (V) V) FIGURE 1-4: 2 40C 1.5 25C 3 40C 2 25C 90C 1 125C 90C 1 0.5 3.3V VREG VS. IREG AT VBB = 12V 125C 0 0 0 DS22298A-page 8 100 IREG (mA) 200 300 0 100 IREG (mA) 200 300 2012 Microchip Technology Inc. MCP2021A/2A FIGURE 1-6: VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET 8 6 VBB V Minimum VBB to maintain regulation VON VOFF 4 2 0 t VREG V 5 VREG-NOM 4 3 2 1 0 Note 1: 2: 3: 4: 2012 Microchip Technology Inc. t (4) (1) (2) (3) Start-up, VBB < VON, regulator off VBB > VON, regulator on. VBB Minimum VBB to maintain regulation VBB < VOFF, regulator will turn off DS22298A-page 9 MCP2021A/2A FIGURE 1-7: VOLTAGE REGULATOR OUTPUT ON OVER-CURRENT SITUATION IREG mA llim 0 6 5 t VREG V VREG-NOM 4 VSD 3 2 1 0 t (1) Note 1: 2: 1.5 1.5.1 IREG less than llim, regulator on After IREG exceeds llim, voltage regulator output will be reduced until voltage regulator shutdown voltage VSD is reached. Optional External Protection REVERSE BATTERY PROTECTION An external reverse-battery-blocking diode should be used to provide polarity protection (see Figure 1-9). 1.5.2 (2) TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) An external 43V transient suppressor (TVS) diode, between VBB and ground, with a transient protection resistor (RTP) in series with the battery supply and the VBB pin protects the device from power transients and ESD events greater than 43V (see Figure 1-9). The maximum value for the RTP protection resistor depends upon two parameters: the minimum voltage the part will start at, and the impacts of this RTP resistor on the VBB value, thus on the Bus recessive level and slopes. Equation 1-3 provides a max RTP value according to the maximum relative variation the user can accept on the slope when IREG varies. Since both Equation 1-1 and Equation 1-2 must be fulfilled, the maximum allowed value for RTP is thus the smaller of the two values found when solving Equation 1-1 and Equation 1-2. Usually Equation 1-1 gives the higher constraint (smaller value) for RTP as shown in the following example where VBATmin is 8V. However, the user needs to check that the value found with Equation 1-1 fulfills Equation 1-2 and Equation 13 as well. While this protection is optional, it should be considered as good engineering practice. This leads to a set of three equations to fullfil. Equation 1-1 provides a max RTP value according to the minimum battery voltage the user wants. Equation 1-2 provides a max RTP value according to the maximum error on the recessive level, thus VBB, since the part uses VBB as the reference value for the recessive level. DS22298A-page 10 2012 Microchip Technology Inc. MCP2021A/2A EQUATION 1-1: EQUATION 1-4: VBATmin - 5.5V R TP -------------------------------------250mA C BAT ------------- = C REG 5.5V = V OFF + 1.0V 250 mA is the peak current at power-on when VBB =5.5V Assume VBATMIN = 8V. Equation 1-1 shows 10 EQUATION 1-2: RTP <= VRECCESSIVE / IREGMAX. VRECCESSIVE is the maximum variation tolerated on the recessive level Assume VRECCESSIVE = 1V and IREGMAX = 50 mA Equation 1-2 shows 20. EQUATION 1-3: Slope V BATmin - 1V R TP -------------------------------------------------------------I regmax Slope is the maximum variation tolerated on the slope level and IREGMAX is the maximum current the regulator will provide to the load. VBATmin>VOFF + 1.0V. Assume Slope = 15%, VBATMIN = 8V and IREGMAX = 50 mA. Equation 1-2 shows 20. where L is in mH and Rtot in . Rtot = Rline + RTP. Equation 1-4 allows lower CBAT/CREG values than the 10* ratio we recommend. Let's assume that we have a good quality connection with RTOT = 0.1 and L = 0.1 mH. Solving the equation gives CBAT/CREG = 1. If we increase RTOT up to 1 the result becomes CBAT/ CREG = 1.4. But if the connection is highly resistive or highly inductive (poor connection), the CBAT/CREG ratio greatly increases. Highly inductive connection: Let's have RTOT = 0.1 and L = 1 mH: the CBAT/CREG ratio increases to 7! Highly resistive connection: Let's have RTOT = 10 and L = 0.1 mH: again the CBAT/CREG ratio increases to 7! Figure 1-8 shows the minimum recommended CBAT/ CREG ratio as a function of the impedance of the VBAT connection. FIGURE 1-8: Minimum Recommended CBAT/CREG Ratio 10 CBAT CAP Selecting CBAT = 10* CREG is recommended, however, this leads to a high value cap. Lower values for CBAT cap can be used with respect to some rules. In any case, the voltage at the VBB pin should remain above VOFF when the device is turned on. The current peak at start-up (due to the fast charge of the CREG and CBAT capacitors) may induce a significant drop on the VBB pin. This drop is proportional to the impedance of the VBAT connection (see Figure 1-9). CBAT/CREG 1.5.3 2 2 100L + R tot ------------------------------2 R 2 tot 1 + L + --------100 RBAT BAT=10 =0.1 R RBAT BAT=4 =0.3 R BAT=2 RBAT =1 R RBAT=1 RBAT=0.3 RBAT=0.1 1 0.1 VBAT Line Inductance [mH] 1 Assume that the VBAT connection is mainly inductive and resistive, and that the customer knows the resistive and inductive values of the connection. The following formula gives an indication of the minimum value the customer should use for CBAT: 2012 Microchip Technology Inc. DS22298A-page 11 MCP2021A/2A 1.6 Typical Applications FIGURE 1-9: TYPICAL APPLICATION CIRCUIT VBAT VBAT Rtp 10 k 43V (5) WAKE-UP VDD VREG TXD TXD RXD RXD I/O Master Node Only VBB VBB 1 K LIN Bus LBUS 43V (4) CS/LWAKE (3) FAULT/TXE I/O C CBAT CREG I/O RESET RESET VSS VSS Note 1: CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.022 F. See Figure 2-1 for selecting the correct ESR. 2: CBAT is the filter capacitor for the external voltage supply. Typically 10 * CREG, with no ESR restriction. See Figure 1-8 to select the minimum recommended value for CBAT. The RTP value is added to the line resistance. 3: This diode is only needed if CS/LWAKE is connected to VBAT supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: This component is for additional load dump protection. FIGURE 1-10: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus 1 k VBB LIN bus MCP202XA LIN bus MCP205X Slave 1 C LIN bus MCP202XA LIN bus MCP2003 Slave 2 C Slave n <16 C Master C DS22298A-page 12 2012 Microchip Technology Inc. MCP2021A/2A 1.7 ICSPTM Considerations The following should be considered when the MCP2021A/2A is connected to pins supporting in-circuit programming: * Power used for programming the microcontroller can be supplied from the programmer, or from the MCP2021A/2A. * The voltage on the pin VREG should not exceed the maximum value of VREG in Section 2.3 "DC Specifications" . 2012 Microchip Technology Inc. DS22298A-page 13 MCP2021A/2A NOTES: DS22298A-page 14 2012 Microchip Technology Inc. MCP2021A/2A 2.0 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings VIN DC Voltage on RXD, and RESET ................................................................................................. -0.3V to VREG+0.3 VIN DC Voltage on TXD, CS/LWAKE, FAULT/TXE .......................................................................................-0.3 to +40V VBB Battery Voltage, continuous, non-operating (Note 1)..............................................................................-0.3 to +40V VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) (Note 2) .......................-0.3 to +43V VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-100V VBB Battery Voltage, transient ISO 7637 Test 2a .....................................................................................................+75V VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-150V VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+100V VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V VLBUS Bus Voltage, transient (Note 3)............................................................................................................-27 to +43V ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA ESD protection on LIN, VBB (IEC 61000-4-2) (Note 4) ......................................................................................... 15 KV ESD protection on LIN, VBB (Human Body Model) (Note 5)................................................................................... 8 KV ESD protection on all other pins (Human Body Model) (Note 5) ............................................................................ 4 KV ESD protection on all pins (Charge Device Model) (Note 6) ................................................................................1500V ESD protection on all pins (Machine Model) (Note 7).............................................................................................200V Maximum Junction Temperature ............................................................................................................................. 150C Storage Temperature .................................................................................................................................. -65 to +150C Note 1: LIN 2.x compliant specification. 2: SAE J2602-2 compliant specification. 3: ISO 7637/1 load dump compliant (t < 500 ms). 4: According to IEC 61000-4-2, 330 ohm, 150 pF and Transceiver EMC Test Specifications [2] to [4]. 5: According to AEC-Q100-002 / JESD22-A114. 6: According to AEC-Q100-011B. 7: According to AEC-Q100-003 / JESD22-A115. NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2.2 Nomenclature Used in This Document Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent values are shown below. LIN 2.1 Name Term used in the following tables VBAT not used ECU operating voltage VSUP VBB Supply voltage at device pin VBUS_LIM ISC Current limit of Driver VBUSREC VIH(LBUS) Recessive state VBUSDOM VIL(LBUS) Dominant state 2012 Microchip Technology Inc. DS22298A-page 15 MCP2021A/2A 2.3 DC Specifications DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40C to +125C Sym. Min. Typ. Max. Units Conditions IBBQ -- -- 200 A IOUT = 0 mA, LBUS recessive VREG = 5.0V -- -- 200 A IOUT = 0 mA, LBUS recessive VREG = 3.3V -- -- 100 A IOUT = 0 mA, LBUS recessive VREG = 5.0V -- -- 100 A IOUT = 0 mA, LBUS recessive VREG = 3.3V -- -- 100 A With voltage regulator on, transmitter off, receiver on, FAULT/TXE = VIL, CS = VIH,VREG = 5.0V -- -- 100 A With voltage regulator on, transmitter off, receiver on, FAULT/TXE = VIL, CS = VIH,VREG = 3.3V IBBPD -- 4.5 8 A With voltage regulator powered-off, receiver on and transmitter off, FAULT/TXE = VIH, TXD = VIH, CS = VIL) IBBNOGND -1 -- 1 mA VBB = 12V, GND to VBB, VLIN = 0-18V High Level Input Voltage (TXD, FAULT/TXE) VIH 2.0 -- VREG +0.3 V Low Level Input Voltage (TXD, FAULT/TXE) VIL -0.3 -- 0.8 V High Level Input Current (TXD, FAULT/TXE) IIH -2.5 -- 0.4 A Input voltage = 4.0V. ~800 k internal adaptive pull-up Low Level Input Current (TXD, FAULT/TXE) IIL -10 -- -- A Input voltage = 0.5V. ~800 k internal adaptive pull-up High Level Input Voltage (CS/LWAKE) VIH 2.0 -- VBB V Through a current-limiting resistor Low Level Input Voltage (CS/LWAKE) VIL -0.3 -- 0.8 V High Level Input Current (CS/LWAKE) IIH -- -- 8.0 A Power VBB Quiescent Operating Current VBB READY Current VBB Transmitter-off Current VBB Power-down Current VBB Current with VSS Floating IBBRD IBBTO Microcontroller Interface DS22298A-page 16 Input voltage = 0.8VREG ~1.3 M internal pulldown to VSS 2012 Microchip Technology Inc. MCP2021A/2A 2.3 DC Specifications (Continued) DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40C to +125C Parameter Sym. Min. Typ. Max. Units IIL -- -- 5.0 A Input voltage = 0.2VREG ~1.3 M internal pulldown to VSS Low Level Output Voltage (RXD) VOLRXD -- -- 0.2VREG V IOL = 2 mA High Level Output Voltage (RXD) VOHRXD 0.8VREG -- -- V IOH = 2 mA Low Level Output Voltage (FAULT/TXE) VOLOD -- 1.0 V IOL = 4 mA Low Level Output Voltage (RESET) VOLRST -- 1.0 V IOL = 4 mA Low Level Input Current (CS/LWAKE) 2012 Microchip Technology Inc. -- Conditions DS22298A-page 17 MCP2021A/2A 2.3 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40C to +125C Sym. Min. Typ. Max. Units Conditions Bus Interface (DC specifications are for a VBB range of 6.0 to 18.0V) High Level Input Voltage VIH(LBUS) 0.6 VBB -- -- V Recessive state Low Level Input Voltage VIL(LBUS) -8 -- 0.4 VBB V Dominant state Input Hysteresis VHYS -- -- 0.175 VBB V Low Level Output Current IOL(LBUS) 40 -- 200 mA Output voltage = 0.1 VBB, VBB = 12V Pull-up Current on Input IPU(LBUS) -180 -- -72 A ~30 k internal pull-up @ VIH (LBUS) = 0.7 VBB, VBB=12V (Note 1) VIH(LBUS) - VIL(LBUS) Short Circuit Current Limit ISC 50 -- 200 mA High Level Output Voltage VOH(LBUS) 0.8 VBB -- VBB V Driver Dominant Voltage V_LOSUP -- -- 1.1 V VBB = 7.3V, RLOAD = 1000 Driver Dominant Voltage V_HISUP -- -- 1.2 V VBB = 18V, RLOAD = 1000 Input Leakage Current (at the receiver during dominant bus level) IBUS_PAS_DOM -1 -- -- mA Driver off, VBUS = 0V, VBB = 12V Input Leakage Current (at the receiver during recessive bus level) IBUS_PAS_REC -20 -- 20 A Driver off, 8V < VBB < 18V 8V < VBUs < 18V VBUS VBB Leakage Current (disconnected from ground) IBUS_NO_GND -10 -- +10 A GNDDEVICE = VBB, 0V < VBUS < 18V, VBB = 12V Leakage Current (disconnected from VBB) IBUS_NO_PWR -10 -- +10 A VBB = GND, 0 < VBUS < 18V Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5 VBB 0.525 VBB V VBUS_CNT = (VIL (LBUS) + VIH (LBUS))/2 RSLAVE 20 30 47 k 50 pF (Note 2) -- -- 3.4 V Wake up from POWERDOWN mode (Note 3) Slave Termination Capacitance of slave node CSLAVE Wake-Up Voltage Threshold on LIN Bus VWK(LBUS) Note 1: 2: 3: (Note 2) Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB). For design guidance only, not tested. In POWER DOWN mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect bus activities. DS22298A-page 18 2012 Microchip Technology Inc. MCP2021A/2A 2.3 DC Specification (Continued) DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40C to +125C CLOADREG = 10 F Parameter Sym. Min. Typ. Max. Units Conditions VREG 4.85 5.00 5.15 V Line Regulation VOUT1 -- 10 50 mV IOUT = 1 mA, 6.0V < VBB < 18V Load Regulation VOUT2 -- 10 50 mV 5 mA < IOUT <70 mA 6.0V < VBB < 12V Power Supply Ripple Reject PSRR -- -- 50 dB 1 VPP @10-20 kHz ILOAD = 20 mA Output Noise Voltage eN -- -- 100 Shutdown Voltage Threshold VSD 3.5 -- 4.0 V Input Voltage to Turn Off Output VOFF 3.9 -- 4.5 V Input Voltage to Turn On Output VON 5.25 -- 6.0 V Voltage Regulator - 5.0V Output Voltage Range 0 mA < IOUT < 70 mA VRMS 10 Hz - 40 MHz CFILTER = 10 f, CBP = 0.1 f, ILOAD = 20 mA See Figure 1-7 (Note 1) Voltage Regulator - 3.3V Output Voltage VREG 3.20 3.30 3.40 V Line Regulation VOUT1 -- 10 50 mV IOUT = 1 mA, 6.0V < VBB < 18V Load Regulation VOUT2 -- 10 50 mV 5 mA < IOUT < 70 mA, 6.0V < VBB < 12V Power Supply Ripple Reject PSRR -- -- 50 dB 1 VPP @10-20 kHz , ILOAD = 20 mA Output Noise Voltage eN -- -- 100 Shutdown Voltage VSD 2.5 -- 2.7 V Input Voltage to Turn Off Output VOFF 3.9 -- 4.5 V Input Voltage to Turn On Output VON 5.25 -- 6 V Note 1: 0 mA < IOUT < 70 mA VRMS 10 Hz - 40 MHz /Hz CFILTER = 10 f, CBP = 0.1 f, ILOAD = 20 mA See Figure 1-7 (Note 1) For design guidance only, not tested. 2012 Microchip Technology Inc. DS22298A-page 19 MCP2021A/2A FIGURE 2-1: ESR CURVES FOR LOAD CAPACITOR SELECTION ESR Curves 10 Unstable Instable Stable only ESR [ohm] 1 with Tantalum or Electrolytic cap. Stable with Tantalum, Electrolytic and Ceramic cap. Unstable Instable 0.1 0.01 Instable Unstable 0.001 0.1 1 10 100 1000 Load Capacitor [uF] DS22298A-page 20 2012 Microchip Technology Inc. MCP2021A/2A 2.4 AC Specification AC CHARACTERISTICS Parameter VBB = 6.0V to 18.0V; TA = -40C to +125C Sym. Min. Typ. Max. Units Test Conditions Bus Interface - Constant Slope Time Parameters (DC specifications are for a VBB range of 6.0 to 18.0V) tSLOPE 3.5 -- 22.5 s 7.3V <= VBB <= 18V Propagation Delay of Transmitter tTRANSPD -- -- 5.0 s tTRANSPD = max (tTRANSPDR or tTRANSPDF) Propagation Delay of Receiver tRECPD -- -- 6.0 s tRECPD = max (tRECPDR or tRECPDF) Symmetry of Propagation Delay of Receiver rising edge w.r.t. falling edge tRECSYM -2.0 -- 2.0 s tRECSYM = max (tRECPDF - tRECPDR) RRXD 2.4 kto VCC, CRXD 20 pF Symmetry of Propagation Delay of Transmitter rising edge w.r.t. falling edge tTRANSSYM -2.0 -- 2.0 s tTRANSSYM = max (tTRANSPDF tTRANSPDR) Bus dominant time-out time tTO(LIN) -- 25 -- mS Time to sample FAULT/TXE for bus conflict reporting tFAULT -- -- 32.5 s Duty Cycle 1 @20.0 kbit/sec .396 -- -- %tBIT CBUS;RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.744 x VBB, THDOM(MAX) = 0.581 x VBB, VBB =7.0V - 18V; tBIT = 50 s. D1 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 2 @20.0 kbit/sec -- -- .581 %tBIT CBUS;RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.284 x VBB, THDOM(MAX) = 0.422 x VBB, VBB =7.6V - 18V; tBIT = 50 s. D2 = tBUS_REC(MAX) / 2 x tBIT) Duty Cycle 3 @10.4 kbit/sec .417 -- -- %tBIT CBUS;RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.778 x VBB, THDOM(MAX) = 0.616 x VBB, VBB =7.0V - 18V; tBIT = 96 s. D3 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 4 @10.4 kbit/sec -- -- .590 %tBIT CBUS;RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.251 x VBB, THDOM(MAX) = 0.389 x VBB, VBB =7.6V - 18V; tBIT = 96 s. D4 = tBUS_REC(MAX) / 2 x tBIT) Slope rising and falling edges 2012 Microchip Technology Inc. tFAULT = max (tTRANSPD + tSLOPE + tRECPD) DS22298A-page 21 MCP2021A/2A 2.4 AC Specification (Continued) AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40C to +125C Parameter Sym. Min. Typ. Max. Units Test Conditions Voltage Regulator Bus Activity Debounce time tBDB 30 80 250 s tBACTIVE 35 -- 200 s Voltage Regulator Enabled to Ready tVEVR 300 -- 1200 s (Note 1) Chip Select to Ready Mode tCSR -- -- 230 s (Note 2) (Note 2) Bus Activity to Voltage Regulator Enabled Chip Select to Power-down tCSPD -- -- 330 s tSHUTDOWN 20 -- 100 s VREG OK detect to RESET inactive tRPU -- -- 60 s (Note 2) VREG not OK detect to RESET active tRPD -- -- 60 s (Note 2) Short circuit to shut-down RESET Timing Note 1: 2: 2.5 Time depends on external capacitance and load. Test condition: CREG = 4.7uF, no resistor load. For design guidance only, not tested. Thermal Specifications THERMAL CHARACTERISTICS Parameter Symbol Typ. Max. Units Recovery Temperature RECOVERY +140 -- C Shutdown Temperature SHUTDOWN +150 -- C tTHERM 1.5 5.0 ms Short Circuit Recovery Time Test Conditions Thermal Package Resistances Thermal Resistance, 8L-PDIP JA 89.3 -- C/W Thermal Resistance, 8L-SOIC JA 149.5 -- C/W Thermal Resistance, 8L-DFN JA 48 -- C/W Thermal Resistance, 14L-PDIP JA 70 -- C/W Thermal Resistance, 14L-SOIC JA 95.3 -- C/W Thermal Resistance, 14L-TSSOP JA 100 -- C/W Note 1: The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)JA. If this dissipation is exceeded, the die temperature will rise above 150C and the MCP2021A/2A will go into thermal shutdown. DS22298A-page 22 2012 Microchip Technology Inc. MCP2021A/2A 2.6 Timing Diagrams and Specifications FIGURE 2-2: BUS TIMING DIAGRAM TXD 50% 50% LBUS .95VLBUS .50VBB .05VLBUS tTRANSPDR tTRANSPDF tRECPDF 0.0V tRECPDR RXD 50% Internal TXD/RXD Compare Match 50% Match Match Match Match FAULT Sampling tFAULT tFAULT FAULT/TXE Output FIGURE 2-3: Stable Hold Value Stable Hold Value Stable REGULATOR BUS WAKE TIMING DIAGRAM LBUS VWK(LBUS) tBDB tVEVR tBACTIVE VREG-NOM VREG 2012 Microchip Technology Inc. DS22298A-page 23 MCP2021A/2A FIGURE 2-4: CS/LWAKE, REGULATOR AND RESET TIMING DIAGRAM CS/LWAKE tCSR tVEVR VREG-NOM VREG tRPD tRPU tCSPD RESET TYPICAL IBBQ VS. TEMPERATURE - 5.0V FIGURE 2-7: 200 5.2 180 5 160 4.8 IPD (A) A) IBBQ (A) A) FIGURE 2-5: 140 TYPICAL IPD VS. TEMPERATURE - 5.0V 4.6 44 4.4 120 VBB =6V VBB =12V VBB =18V 100 VBB =6V VBB =12V VBB =18V 4.2 4 80 -40 -25 -10 5 FIGURE 2-6: 20 35 50 65 80 95 110 125 TTemperature(C) (C) -40 40 -25 25 -10 10 5 20 35 50 65 80 95 110 125 Temperature(C) TYPICAL IBBTO VS. TEMPERATURE - 5.0V 90 IBBTO (A) A) 80 70 VBB =6V VBB =12V VBB =18V 60 50 -40 -25 -10 5 DS22298A-page 24 20 35 50 65 80 95 110 125 Temperature(C) 2012 Microchip Technology Inc. MCP2021A/2A TYPICAL IBBQVS. TEMPERATURE - 3.3V FIGURE 2-10: 200 5.2 180 5 160 4.8 140 VBB =6V VBB =12V VBB =18V 120 IPD (A) IBBQ (A) FIGURE 2-8: TYPICAL IPD VS. TEMPERATURE - 3.3V 4.6 4.4 VBB =6V VBB =12V VBB =18V 4.2 100 4 80 -40 -25 -10 5 -40 -25 -10 5 FIGURE 2-9: 20 35 50 65 80 95 110 125 Temperature(C) 20 35 50 65 80 95 110 125 Temperature(C) TYPICAL IBBTO VS. TEMPERATURE - 3.3V 100 IBBTO BTO (A) A) 90 80 70 VBB =6V VBB =12V = 12V VBB =18V 60 50 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature(C) 2012 Microchip Technology Inc. DS22298A-page 25 MCP2021A/2A NOTES: DS22298A-page 26 2012 Microchip Technology Inc. MCP2021A/2A 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 8-Lead DFN (4x4x0.9 mm) (MCP2021A) XXXXXX XXXXXX YYWW NNN PIN 1 Example 2021A 500EMD 1210 256 PIN 1 8-Lead SOIC (150 mil) (MCP2021A) NNN 8-Lead PDIP (300 mil) (MCP2021A) XXXXXXXX XXXXXNNN Example: 2021A50E e3 SN ^^1210 256 Example 2021A500 e3 E/P ^^256 1210 YYWW Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2012 Microchip Technology Inc. DS22298A-page 27 MCP2021A/2A Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP2022A) Example MCP2022A 3 500E/P e^^ 1210256 14-Lead SOIC (.150") (MC2022A) Example MCP2022A 3 500E/SL e^^ 1210256 14-Lead TSSOP (MCP2022A) XXXXXXXX YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS22298A-page 28 Example 2022A500 1210 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( can be found on the outer packaging for this package. ) In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2012 Microchip Technology Inc. MCP2021A/2A 8-Lead Plastic Dual Flat, No Lead Package (MD) 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 1 of 2 2012 Microchip Technology Inc. DS22298A-page 29 MCP2021A/2A 8-Lead Plastic Dual Flat, No Lead Package (MD) 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 2 of 2 DS22298A-page 30 2012 Microchip Technology Inc. MCP2021A/2A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc. DS22298A-page 31 MCP2021A/2A 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! '! 9'&! 7"') %! 7,8. 7 7 & ; < & & 7: 1, = = - 1!& & = = . - - ##4 "# & 4!! "# >#& ##4>#& . < : 9& -< -? 9 - < ) ? ) < 1 = = & & 9# 6 4!! 9#>#& 9 * 9#>#& : * + - !"#$%&" ' ()"&'"!&) &#*& & & # +%&, & !& - '! !#.# &"#' #%! & "! ! #%! & "! !! &$#/ !# '! #& .0 1,21!'! &$& "! **& "&& ! DS22298A-page 32 * ,<1 2012 Microchip Technology Inc. MCP2021A/2A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc. DS22298A-page 33 MCP2021A/2A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22298A-page 34 2012 Microchip Technology Inc. MCP2021A/2A ! ""#$%& !' 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 2012 Microchip Technology Inc. DS22298A-page 35 MCP2021A/2A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22298A-page 36 2012 Microchip Technology Inc. MCP2021A/2A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc. DS22298A-page 37 MCP2021A/2A 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 DS22298A-page 38 2012 Microchip Technology Inc. MCP2021A/2A () 3 & ' !&" & 4# *!( !!& 4 %& &#& && 255***' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 6&! '! 9'&! 7"') %! 7,8. 7 7 & ; & & 7: 1, = = - 1!& & = = . - - ##4 "# & 4!! "# >#& ##4>#& . < : 9& - 9 - < ) ? ) < 1 = = & & 9# 6 4!! 9#>#& 9 * 9#>#& : * + - !"#$%&" ' ()"&'"!&) &#*& & & # +%&, & !& - '! !#.# &"#' #%! & "! ! #%! & "! !! &$#/ !# '! #& .0 1,21!'! &$& "! **& "&& ! 2012 Microchip Technology Inc. * ,1 DS22298A-page 39 MCP2021A/2A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22298A-page 40 2012 Microchip Technology Inc. MCP2021A/2A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc. DS22298A-page 41 MCP2021A/2A Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22298A-page 42 2012 Microchip Technology Inc. MCP2021A/2A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X /XX Temperature Range Device: Package MCP2021A: LIN Transceiver with Voltage Regulator MCP2021AT: LIN Transceiver with Voltage Regulator (Tape and Reel) (SOIC only) Temperature Range: E = -40C to +125C Package: MD SN P SL ST = = = = = Plastic Dual Flat DFN, 8-lead Plastic Small Outline SOIC, 8-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC, (150 mil Body), 14-lead Plastic TSSOP, 14-lead 2012 Microchip Technology Inc. Examples: a) b) c) d) e) f) g) h) i) j) k) l) MCP2021A-330E/SL: MCP2021A-330E/P: MCP2021A-500E/SL: MCP2021A-500E/P: MCP2021AT-330E/SL: 3.3V, 8L-SOIC package 3.3V, 8L-PDIP package 5.0V, 8L-SOIC package 5.0V, 8L-PDIP package Tape and Reel, 3.3V, 8L-SOIC package MCP2021AT-500E/SL: Tape and Reel, 5.0V, 8L-SOIC package MCP2022A-330E/SL: 3.3V, 14L-SOIC package MCP2022A-330E/P: 3.3V, 14L-PDIP package MCP2022A-500E/SL: 5.0V, 14L-SOIC package MCP2022A-500E/P: 5.0V, 14L-PDIP package MCP2022AT-330E/SL: Tape and Reel, 3.3V, 14L-SOIC package MCP2022AT-500E/SL: Tape and Reel, 5.0V, 14L-SOIC package DS22298A-page 43 MCP2021A/2A NOTES: DS22298A-page 44 2012 Microchip Technology Inc. MCP2021A/2A APPENDIX A: REVISION HISTORY Revision A (March 2012) * Original Release of this Document. 2012 Microchip Technology Inc. DS22298A-page 45 MCP2021A/2A NOTES: DS22298A-page 46 2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-155-7 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS22298A-page 47 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-66-152-7160 Fax: 81-66-152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS22298A-page 48 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 11/29/11 2012 Microchip Technology Inc. Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: MCP2021AT-330E/MD MCP2021AT-330E/SN MCP2021AT-500E/MD MCP2022A-330E/ST MCP2022A-500E/SL MCP2022A-500E/ST MCP2022AT-330E/SL MCP2022AT-330E/ST MCP2022AT-500E/SL MCP2022AT-500E/ST MCP2021A-330E/MD MCP2021A-500E/SN MCP2021AT-500E/SN MCP2021A-500E/MD MCP2022A-330E/SL MCP2021A-330E/SN