2012 Microchip Technology Inc. DS22298A-page 1
MCP2021A/2A
Features
• The MCP2021A/2A is compliant with:
- LIN Bus Specifications Version 1.3, and 2.x.
- SAE J2602-2
• Support Baud Rates up to 20 kBaud
• 43V Load Dump Protected
• Maximum Continuous Input Voltage of 30V
• Wide LIN Compliant Supply Voltage, 6.0 - 18.0V
• Extended Temperature Range: -40 to +125°C
• Interface to PIC® EUSART and Standard USARTs
• Wake-up on LIN Bus Activity or Local Wake Input
• LIN Bus Pin
- Internal Pull-up Termination Resistor and
Diode for Slave Node
- Protected Against VBAT Shorts
- Protected Against Loss of Ground
- High Current Drive
• TXD and LIN Bus Dominant Time-out Function
• Two Low-Power Modes
- TRANSMITTER OFF Mode: 9µA (typical)
- POWER DOWN Mode: 4.5µA (typical)
• Output Indicating Internal RESET State (POR or
SLEEP Wake)
• MCP2021A/2A On-chip Voltage Regulator
- Output Voltage of 5.0V or 3.3V 70 mA
Capability withTolerances of ±3% Over
Temperature Range
- Internal Short Circuit Current Limit
- Only External Filter and Load Capacitors
Needed
• Automatic Thermal Shutdown
• High Electromagnetic Immunity (EMI), Low Elec-
tromagnetic Emission (EME)
• Robust ESD Performance: ±15 kV for LBUS and
VBB pin (IEC61000-4-2)
• Transient Protection for LBUS and VBB Pins in
Automotive Environment (ISO7637)
• Meets Stringent Automotive Design Requirements
Including “OEM Hardware Requirements for LIN,
CAN and FlexRay Interfaces in Automotive Appli-
cations”, Version 1.2, March 2011
• Multiple Package Options Including Small
4x4 mm DFN
Description
The MCP2021A/2A provides a bidirectional, half-
duplex communication physical interface to meet the
LIN bus specification Revision 2.1 and SAE J2602-2.
The device incorporates a voltage regulator with 5V or
3.3V 70 mA regulated power supply output. The device
has been designed to meet the stringent quiescent
current requirements of the automotive industry and
will survive +43V load dump transients, and double
battery jumps.
Package Types (Top View)
MCP2021A
PDIP, SOIC
VREG
CS/LWAKE
TXD
1
2
3
4
8
7
6
5
RXD FAULT/TXE
VBB
LBUS
VSS
MCP2021A
4x4 DFN
VREG
CS/LWAKE
TXD
RXD FAULT/TXE
VBB
LBUS
VSS
1
2
3
4
8
7
6
5
EP
9
MCP2022A
PDIP, SOIC, TSSOP
VREG
CS/LWAKE
TXD
1
2
3
4
14
13
12
11
RXD FAULT/TXE
VBB
LBUS
VSS
RESET 510 NC
NC 69
NC 78NC
NC
* Includes Exposed Thermal Pad (EP).
LIN Transceiver with Voltage Regulator
MCP2021A/2A
DS22298A-page 2 2012 Microchip Technology Inc.
Block Diagram
MCP2021A/2A Family Members
Device Package Regulator Output Voltage RESET Pin
MCP2021A-500 8-PIN DFN, SOIC, PDIP 5.0V No
MCP2021A-330 8-PIN DFN, SOIC, PDIP 3.3V No
MCP2022A-500 14-PIN SOIC, TSSOP, PDIP 5.0V Yes
MCP2022A-330 14-PIN SOIC, TSSOP, PDIP 3.3V Yes
Voltage
Regulator
Ratiometric
Reference
Thermal
Protection
Internal Circuits
VREG
FAULT/TXE
RXD
TXD
VBB
LBUS
VSS
~30
CS/LWAKE
Wake-Up
Logic and
Power Control
RESET
Short Circuit
Protection
Thermal
Protection
k
Bus Wakeup
and
Short Circuit
Slope Control
VREG
4.2V
Bus
Dominant
Timer
(MCP2022A ONLY)
VREG
2012 Microchip Technology Inc. DS22298A-page 3
MCP2021A/2A
1.0 FUNCTION DESCRIPTION
The MCP2021A/2A provides a physical interface
between a microcontroller and a LIN half-duplex bus. It
is intended for automotive and industrial applications
with serial bus baud rates up to 20 Kbaud. This device
will translate the CMOS/TTL logic levels to LIN logic
levels, and vice versa. The device offers optimum EMI
and ESD performance; it can withstand high voltage on
the LIN bus. The device supports two low-power
modes to meet automotive industry power consump-
tion requirements. The MCP2021A/2A also provides a
+5V or 3.3V 70 mA regulated power output.
1.1 Modes of Operation
The MCP2021A/2A works in five modes: POWER-ON-
RESET mode, POWER-DOWN mode, READY mode,
OPERATION mode, and TRANSMITTER OFF mode.
For an overview of all operational modes, please refer
to Table 1-1. For the operational mode transition,
please refer to Figure 1-1.
FIGURE 1-1: STATE DIAGRAM
1.1.1 POWER-ON-RESET MODE
Upon application of VBB, or whenever the voltage on
VBB is below the threshold of regulator turn off voltage
VOFF (typically 4.50V), the device enters POWER-ON-
RESET mode (POR). During this mode, the device
maintains the digital section in a reset mode and waits
until the voltage on VBB pin rises above the threshold of
regulator turn on voltage VON (typically 5.75V) to enter
to the READY mode. In POWER-ON-RESET mode,
the LIN physical layer and voltage regulator are dis-
abled, and RESET output (MCP2022A only) is forced
to LOW.
POR(2)
VREG OFF
RX OFF
TX OFF
READY
VREG ON
RX ON
TX OFF
TX OFF
VREG ON
RX ON
TX OFF
POWER-DOWN
VREG OFF
RX OFF
TX OFF
OPERATION
VREG ON
RX ON
TX ON
VBB>VON
CS/LWAKE=1&
FAULT/TXE=0&
VREG_OK=1(1)
CS/LWAKE=0
CS/LWAKE=1 &
FAULT/TXE=1(3) &
TXD=1&
VREG_OK=1(1)
CS/LWAKE=1&
FAULT/TXE=1(3)&
TXD=1
CS/LWAKE=1&
FAULT/TXE=0
CS/LWAKE=0
CS/LWAKE=1 OR
Voltage Rising Edge on LBUS
CS/LWAKE=0
Note 1: VREG_OK : Regulator Output Voltage > 0.8VREG_NOM.
2: If the voltage on pin VBB falls below VOFF, the device will enter POWER ON RESET mode from all other
modes, which is not shown in the figure.
3: FAULT/TXE = 1 represents input high and no fault conditions. FAULT/TXE = 0 represents input low or a
fault condition, Refer to Table 1-3.
MCP2021A/2A
DS22298A-page 4 2012 Microchip Technology Inc.
1.1.2 READY MODE
The device enters READY mode from POR mode after
the voltage on VBB rises above the threshold of
regulator turn on voltage VON or from POWER-DOWN
mode when a remote or local wake-up event happens.
Upon entering READY mode, the voltage regulator and
receiver section of the transceiver are powered up. The
transmitter remains in an off state. The device is ready
to receive data but not to transmit. In order to minimize
the power consumption, the regulator operates in a
reduced power mode. It has a lower GBW product and
thus is slower. However, the 70 mA drive capability is
unchanged.
The device stays in READY mode until the output of the
voltage regulator has stabilized and the CS/LWAKE pin
is HIGH (‘1’).
1.1.3 OPERATION MODE
If VREG is OK (VREG>0.8VREG_NORM), and the CS/
LWAKE pin, FAULT/TXE pin and TXD pin are HIGH,
the part enters OPERATION mode from either READY
or TRANSMITTER OFF mode.
In this mode, all internal modules are operational. The
internal pull-up resistor between LBUS and VBB is
connected only in this mode.
The device goes into POWER-DOWN mode at the
falling edge on CS/LWAKE; or to the TRANSMITTER
OFF mode at the falling on FAULT/TXE while CS/
LWAKE stays HIGH.
1.1.4 TRANSMITTER OFF MODE
In TRANSMITTER OFF mode, the receiver is enabled
but the LBUS transmitter is off. It is a lower power mode.
In order to minimize power consumption, the regulator
operates in a reduced power mode. It has a lower GBW
product and thus is slower. However the 70 mA drive
capability is unchanged.
The transmitter may be re-enabled whenever the
FAULT/TXE signal returns high, by removing the inter-
nal fault condition and the CPU returning the FAULT/
TXE high. The transmitter will not be enabled even if
the FAULT/TXE pin is brought high externally, when the
internal fault is still present. However, externally forcing
the FAULT/TXE high while internal fault is still present
should be avoided, since this will induce high current
and power dissipation in the FAULT/TXE pin.
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption of the bus during times of
uncertain operation.
1.1.5 POWER-DOWN MODE
In POWER-DOWN mode, the transceiver and the
voltage regulator are both off. Only the Bus Wake-up
section and the CS/LWAKE pin wake-up circuits are in
operation. This is the lowest power mode.
If any bus activity (e.g. a BREAK character) occurs dur-
ing POWER-DOWN mode, the device will immediately
enter READY mode and enable the voltage regulator.
Then, once the regulator output has stabilized (approx-
imately 0.3 ms to 1.2 ms), it goes to OPERATION
mode. Refer to Section 1.1.6 “Remote Wake-up”.
The part will also enter READY mode from POWER-
DOWN mode, followed by the OPERATION mode, if
the CS/LWAKE pin becomes active HIGH (‘1’).
1.1.6 REMOTE WAKE-UP
The remote wake-up sub module observes the LBUS in
order to detect bus activity. In POWER DOWN mode,
normal LIN recessive/dominant threshold is disabled,
and the LIN bus Wake-Up Voltage Threshold
VWK(LBUS) is used to detect bus activities. Bus activity
is detected when the voltage on the LBUS falls below
the LIN bus Wake-Up Voltage Threshold VWK(LBUS)
(approximately 3.5V) for at least tBDB (a typical duration
of 80 µs ) followed by a rising edge. Such a condition
causes the device to leave POWER-DOWN mode.
TABLE 1-1: OVERVIEW OF OPERATIONAL MODES
State Transmitter Receiver Internal Wake
Module
Voltage
Regulator Operation Comments
POR OFF OFF OFF OFF Transfer to READY mode after VBB>VON
READY OFF ON OFF ON If CS/LWAKE high, then proceed to
OPERATION or TRANSMITTER OFF mode.
Bus Off state
OPERATION ON ON OFF ON If CS/LWAKE low level, then Power down
If FAULT/TXE low level, then
TRANSMITTER-OFF mode
Normal
Operation
mode
POWER DOWN OFF OFF ON
Activity Detect
OFF On LIN bus rising edge or CS/LWAKE high
level, go to READY mode.
Lowest Power
mode
TRANSMITTER-OFF OFF ON OFF ON If CS/LWAKE low level, then Power down
If FAULT/TXE high, then OPERATION mode
Bus Off state,
Lower Power
mode
2012 Microchip Technology Inc. DS22298A-page 5
MCP2021A/2A
1.2 Pin Descriptions
Please refer to Ta b l e 1 - 2 for the pinout overview.
1.2.1 VBB
Battery Positive Supply Voltage pin. An external diode
is connected in series to prevent the device from being
reversely powered (refer to FIGURE 1-9: “Typical
Application Circuit”).
1.2.2 VREG
Positive Supply Voltage Regulator Output pin. An on-
chip LDO gives +5.0 or +3.3V 70 mA regulated voltage
on this pin.
1.2.3 VSS
Ground pin.
1.2.4 TXD
Transmit data input pin (TTL level, HV compliant,
adaptive pull-up). The transmitter reads the data
stream on TXD pin and sends it to LIN bus. The LBUS
pin is low (dominant) when TXD is low, and high
(recessive) when TXD is high.
The Transmit Data Input pin has an internal adaptive
pull-up to an internally-generated 4.2V (approxi-
mately). When TXD is ‘0’, a weak pull-up (~900 kΩ) is
used to reduce current. When TXD is ‘1’, a stronger
pull-up (~300 kΩ) is used to maintain the logic level. A
series reverse-blocking diode allows applying TXD
input voltages greater than the internally generated
4.2V and renders TXD pin HV compliant up to 30V (see
block diagram).
1.2.5 RXD
Receive Data Output pin. The RXD pin is a standard
CMOS output pin and it follows the state of the LBUS
pin.
1.2.6 LBUS
LIN Bus pin. LBUS is a bidirectional LIN bus Interface
pin and is controlled by the signal TXD. It has an open
collector output with a current limitation. To reduce
ElectroMagnetic Emission, the slopes during signal
changes are controlled, and the LBUS pin has corner-
rounding control for both falling and rising edges.
The internal LIN receiver observes the activities on the
LIN bus, and generates the output signal RXD that
follows the state of the LBUS. A 1st degree 160 kHz,
low-pass input filter optimizes ElectroMagnetic immu-
nity.
1.2.7 CS/LWAKE
Chip Select and Local Wake-up Input pin (TTL level,
high voltage tolerant). This pin controls the device state
transition. Refer to FIGURE 1-1: “State Diagram”.
If CS/LWAKE = 1, the device can work in OPERATION
mode (FAULT/TXE = 1) or TRANSMITTER OFF mode
(FAULT/TXE = 0).
If CS/LWAKE = 0, the device can work in POWER-
DOWN mode or READY mode.
An internal pull-down resistor will keep the CS/LWAKE
pin low to ensure that no disruptive data will be present
on the bus while the microcontroller is executing a
Power-on Reset and I/O initialization sequence. When
CS/LWAKE is ‘1’, a weak pull-down (~600 kΩ) is used
to reduce current. When CS/LWAKE is ‘0’ a stronger
pull-down (~300 kΩ) is used to maintain the logic level.
This pin may also be used as a local wake-up input
(See FIGURE 1-9: “Typical Application Circuit”).
The microcontroller will set the I/O pin to control the
CS/LWAKE. An external switch, or other source, can
then wake-up both the transceiver and the
microcontroller.
1.2.8 FAULT/TXE
Fault Detect Output/Transmitter Enable Input pin. The
output section is HV tolerant open drain (up to 30V).
The input section is identical with the TXD section (TTL
level, HV compliant, adaptive pull-up). Internal
adaptive pull-up maintains this input high '1' if the pin is
floating. Its state is defined as shown in TABLE 1-3:
“FAULT/TXE Truth Table”. The device is placed in
TRANSMITTER OFF mode whenever this pin is LOW
(‘0’), either from an internal fault condition or by
external drive.
If CS/LWAKE is HIGH (‘1’), the FAULT/TXE signals a
mismatch between the TXD input and the LBUS level.
This can be used to detect a bus contention. Since the
bus exhibits a propagation delay, the sampling of the
internal compare is debounced to eliminate false faults.
After the device wakes up, the FAULT/TXE indicates
what wakes the device if CS/LWAKE remains LOW (‘0’)
(refer Ta b l e 1 - 3 ).
The FAULT/TXE pin sampled at a rate faster than every
10 µs.
1.2.9 RESET (MCP2022A ONLY)
RESET OUTPUT pin. This pin is open drain with
~90 kΩ pull-up to VREG. It indicates the internal volt-
age has reached a valid, stable level. As long as the
internal voltage is valid (above 0.8 VREG), this pin will
remain HIGH (‘1’); otherwise the RESET pin switches
to LOW (‘0’).
Note: CS/LWAKE should NOT be tied directly to
the VREG pin as this could force the
MCP2021A/2A into Operation Mode
before the microcontroller is initialized.
MCP2021A/2A
DS22298A-page 6 2012 Microchip Technology Inc.
1.3 Fail-Safe Features
1.3.1 GENERAL FAIL-SAFE FEATURES
• An internal pull-down resistor on CS/LWAKE pin
disables the transmitter if the pin is floating.
• An internal pull-up resistor on the TXD pin places
TXD in HIGH thus the LBUS in recessive if TXD
pin is floating.
• High-impedance and low-leakage current on
LBUS during loss of power or ground.
• The current limit on LBUS protects the transceiver
from being damaged if the pin is shorted to VBB.
1.3.2 THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter and voltage regulator.
There are three causes for a thermal overload. A
thermal shut down can be triggered by any one, or a
combination of, the following thermal overload
conditions.
• Voltage regulator overload
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
The recovery time from the thermal shutdown is equal
to adequate cooling time.
TABLE 1-2: PINOUT OVERVIEW
PIN Name
PIN Number
PIN Type Function
MCP2021A MCP2022A
VREG 3 3 Output Voltage Regulator Output
VSS 5 11 Power Ground
VBB 7 13 Power Battery
TXD 4 4 Input, HV-tolerant Transmit Data Input
RXD 1 1 Output Receive Data Output
LBUS 6 12 I/O, HV LIN Bus
CS/LWAKE 2 2 TTL Input, HV-tolerant Chip Select and Local Wake-up Input
FAULT/TXE 8 14 I/O, HV-tolerant Fault Detect Output/Transmitter Enable Input
RESET - 5 Output Reset Output
TABLE 1-3: FAULT/TXE TRUTH TABLE
TXD
In
RXD
Out
LIN BUS
I/O
Thermal
Override
FAULT/TXE
Definition
External
Input
Driven
Output
CS = 1
LHVBB OFF H L FAULT, TXD driven low, LIN BUS shorted to
VBB (Note 1), or LBUS/TXD permanent
dominant detected, and Transmit time-out
shutdown.
HHV
BB OFF H H OK
LLGND OFF H HOK
HLGND OFF H HOK, data is being received from the LIN BUS
xxVBB ON H L FAULT, Transceiver in thermal shutdown
xxVBB xLxNO FAULT, the CPU is commanding the
transceiver to turn off the transmitter driver
CS = 0 after a wake-up
xx x x x LWake-up from LIN bus activity
xx x x x HWake-up from POR
Legend: x = don’t care
Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault
reporting during bus propagation delays.
2012 Microchip Technology Inc. DS22298A-page 7
MCP2021A/2A
Driving the TXD and checking the RXD pin make it
possible to determine whether there is a bus contention
(TXD = high, RXD = low) or a thermal overload
condition (TXD = low, RXD = high).
FIGURE 1-2: THERMAL SHUTDOWN
STATE DIAGRAMS
1.3.3 TXD/LBUS TIME-OUT TIMER
The LIN bus can be driven to a dominant level either
from the TXD pin or externally. An internal timer deac-
tivates the LBUS transmitter if a dominant status
(LOW) on the LIN bus lasts longer than Bus Dominant
Time-out Time tTO(LIN) (approximately 20 milliseconds).
At the same time, RXD output is put in recessive
(HIGH), FAULT/TXE is also driven to LOW, and the
internal LIN pull-up resistor is disconnected. The timer
is reset on any recessive LBUS status or POR mode.
The recessive status on LBUS can be caused either by
the bus being externally pulled up or by the TXD pin
being returned high.
1.4 Internal Voltage Regulator
The MCP2021A/2A has a positive regulator capable of
supplying +5.00 or +3.30 VDC ±3% at up to 70 mA of
load current over the entire operating temperature
range of -40°C to +125°C. The regulator uses a LDO
design, is short-circuit-protected and will turn the regu-
lator output off if its output falls below the Shutdown
Voltage Threshold VSD.
With a load current of 70 mA, the minimum input to out-
put voltage differential required for the output to remain
in regulation is typically +0.5V (+1V maximum over the
full operating temperature range). Quiescent current is
less than 100 µA with a full 70 mA load current when
the input to output voltage differential is greater than
+3.00V.
Regarding the correlation between VBB, VREG and IDD,
please refer to Figure 1-6 and Figure 1-7. When the
input voltage (VBB) drops below the differential needed
to provide stable regulation, the voltage regulator
output VREG will track the input down to approximately
VOFF. The regulator will turn off the output at this point.
This will allow PIC® microcontrollers, with internal POR
circuits, to generate a clean arming of the Power-on
Reset trip point. The MCP2021A/2A will then monitor
VBB and turn on the regulator when VBB is above the
threshold of regulator turn on voltage VON.
In Power-down mode, the VBB monitor is turned off.
Under specific ambient temperature and battery
voltage range, the voltage regulator can output as high
as 150mA current. For current load capability of the
voltage regulator, refer Figure 1-4 and Figure 1-5.
The regulator requires an external output bypass
capacitor for stability. See Figure 2-1 for correct
capacity and ESR for stable operation.
FIGURE 1-3: VOLTAGE REGULATOR BLOCK DIAGRAM
Operation
Mode
Transmitter
Shutdown
LIN bus
Voltage
Shutdown
Regulator
Output
Tem p < SHUTDOWNTEMP
shorted
to VBB
Overload
Temp < SHUTDOWNTEMP
Note: The regulator overload current limit is
approximately 250 mA. The regulator out-
put voltage VREG is monitored. If output
voltage VREG is lower than VSD, the volt-
age regulator will turn off. After a recovery
time of about 3mS, the VREG will be
checked again. If there is no short circuit
(VREG > VSD), then the voltage regulator
remains on.
Pass
Element
Sampling
Network
Buffer
VREG VBB
VSS
Fast
Transient
Loop
VREF
MCP2021A/2A
DS22298A-page 8 2012 Microchip Technology Inc.
FIGURE 1-4: 5.0V VREG VS. IREG AT
VBB = 12V
FIGURE 1-5: 3.3V VREG VS. IREG AT
VBB = 12V
3
3.5
2.5
3
3.5
V
)
2
2.5
3
3.5
V
REG
(V)
1
1.5
2
2.5
3
3.5
40C
25C
V
REG
(V)
0.5
1
1.5
2
2.5
3
3.5
40C
25C
90C
125C
V
REG
(V)
0
0.5
1
1.5
2
2.5
3
3.5
0 100 200 300
40C
25C
90C
125C
I
REG
(mA)
V
REG
(V)
0
0.5
1
1.5
2
2.5
3
3.5
0 100 200 300
40C
25C
90C
125C
I
REG
(mA)
V
REG
(V)
2
3
4
5
6
40C
VREG (V)
0
1
2
3
4
5
6
0 100 200 300
40C
25C
90C
125C
IREG (mA)
VREG (V)
2012 Microchip Technology Inc. DS22298A-page 9
MCP2021A/2A
FIGURE 1-6: VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET
Note 1: Start-up, VBB < VON, regulator off
2: VBB > VON, regulator on.
3: VBB 
4: VBB < VOFF, regulator will turn off
5
3
2
0
(1) (2) (3)
t
0t
6
2
8
4
VBB
V
VREG
V
1
4
VON
VOFF
Minimum VBB to maintain regulation
VREG-NOM
Minimum VBB to maintain regulation
(4)
MCP2021A/2A
DS22298A-page 10 2012 Microchip Technology Inc.
FIGURE 1-7: VOLTAGE REGULATOR OUTPUT ON OVER-CURRENT SITUATION
1.5 Optional External Protection
1.5.1 REVERSE BATTERY PROTECTION
An external reverse-battery-blocking diode should be
used to provide polarity protection (see Figure 1-9).
1.5.2 TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 43V transient suppressor (TVS) diode,
between VBB and ground, with a transient protection
resistor (RTP) in series with the battery supply and the
VBB pin protects the device from power transients and
ESD events greater than 43V (see Figure 1-9). The
maximum value for the RTP protection resistor depends
upon two parameters: the minimum voltage the part will
start at, and the impacts of this RTP resistor on the VBB
value, thus on the Bus recessive level and slopes.
This leads to a set of three equations to fullfil.
Equation 1-1 provides a max RTP value according to
the minimum battery voltage the user wants.
Equation 1-2 provides a max RTP value according to
the maximum error on the recessive level, thus VBB,
since the part uses VBB as the reference value for the
recessive level.
Equation 1-3 provides a max RTP value according to
the maximum relative variation the user can accept on
the slope when IREG varies.
Since both Equation 1-1 and Equation 1-2 must be
fulfilled, the maximum allowed value for RTP is thus the
smaller of the two values found when solving
Equation 1-1 and Equation 1-2.
Usually Equation 1-1 gives the higher constraint
(smaller value) for RTP as shown in the following exam-
ple where VBATmin is 8V.
However, the user needs to check that the value found
with Equation 1-1 fulfills Equation 1-2 and Equation 1-
3 as well.
While this protection is optional, it should be
considered as good engineering practice.
Note 1: IREG less than llim, regulator on
2: After IREG exceeds llim, voltage regulator output will be reduced until
voltage regulator shutdown voltage VSD is reached.
VSD
0
(1) (2)
t
0t
llim
IREG
mA
VREG
V
VREG-NOM
1
2
3
4
5
6
2012 Microchip Technology Inc. DS22298A-page 11
MCP2021A/2A
EQUATION 1-1:
Assume VBATMIN = 8V. Equation 1-1 shows 10
EQUATION 1-2:
Assume ΔVRECCESSIVE = 1V and IREGMAX = 50 mA
Equation 1-2 shows 20.
EQUATION 1-3:
Assume ΔSlope = 15%, VBATMIN = 8V and IREGMAX =
50 mA. Equation 1-2 shows 20.
1.5.3 CBAT CAP
Selecting CBAT = 10* CREG is recommended, however,
this leads to a high value cap. Lower values for CBAT
cap can be used with respect to some rules. In any
case, the voltage at the VBB pin should remain above
VOFF when the device is turned on.
The current peak at start-up (due to the fast charge of
the CREG and CBAT capacitors) may induce a
significant drop on the VBB pin. This drop is
proportional to the impedance of the VBAT connection
(see Figure 1-9).
Assume that the VBAT connection is mainly inductive
and resistive, and that the customer knows the resistive
and inductive values of the connection.
The following formula gives an indication of the
minimum value the customer should use for CBAT:
EQUATION 1-4:
Equation 1-4 allows lower CBAT/CREG values than the
10* ratio we recommend.
Let’s assume that we have a good quality connection
with RTOT = 0.1 and L = 0.1 mH.
Solving the equation gives CBAT/CREG = 1.
If we increase RTOT up to 1 the result becomes CBAT/
CREG = 1.4.
But if the connection is highly resistive or highly induc-
tive (poor connection), the CBAT/CREG ratio greatly
increases.
Highly inductive connection: Let’s have RTOT = 0.1
and L = 1 mH: the CBAT/CREG ratio increases to 7!
Highly resistive connection: Let’s have RTOT = 10 and
L = 0.1 mH: again the CBAT/CREG ratio increases to 7!
Figure 1-8 shows the minimum recommended CBAT/
CREG ratio as a function of the impedance of the VBAT
connection.
FIGURE 1-8: Minimum Recommended
CBAT/CREG Ratio
250 mA is the peak current at power-on when VBB
=5.5V
RTP <= ΔVRECCESSIVE / IREGMAX.
ΔVRECCESSIVE is the maximum variation tolerated on
the recessive level
ΔSlope is the maximum variation tolerated on the
slope level and IREGMAX is the maximum current the
regulator will provide to the load.
VBATmin>VOFF + 1.0V.
RTP
VBATmin 5.5V–
250mA
--------------------------------------
5.5VV
OFF 1.0V+=
RTP
Slope VBATmin 1V–
Iregmax
---------------------------------------------------------------
where L is in mH and Rtot in .
Rtot = Rline + RTP
.
CBAT
CREG
------------- 100L2Rtot
2
+
1L2Rtot
2
100
----------++
--------------------------------=
10
CBAT/CREG
RBAT=0.1
RBAT=0.3
R
BAT
=1
1
10
0.1 1
CBAT/CREG
VBAT Line Inductance [mH]
RBAT=0.1
RBAT=0.3
BAT
R=1
RBAT=2
RBAT=4
RBAT=10
MCP2021A/2A
DS22298A-page 12 2012 Microchip Technology Inc.
1.6 Typical Applications
FIGURE 1-9: TYPICAL APPLICATION CIRCUIT
FIGURE 1-10: TYPICAL LIN NETWORK CONFIGURATION
LIN Bus
43V (4)
VBB
LBUS
VREG
TXD
RXD
VSS
VDD
TXD
RXD
µC
VBAT
CBAT
CREG
CS/LWAKE
I/O
FAULT/TXE
I/O
43V (5)
1K
VBB
Master Node Only
VBAT
10 k
WAKE-UP
Note 1: CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0-
22 µF. See Figure 2-1 for selecting the correct ESR.
2: CBAT is the filter capacitor for the external voltage supply. Typically 10 * CREG, with no ESR
restriction. See Figure 1-8 to select the minimum recommended value for CBAT. The RTP value is
added to the line resistance.
3: This diode is only needed if CS/LWAKE is connected to VBAT supply.
4: Transient suppressor diode. Vclamp L = 43V.
5: This component is for additional load dump protection.
(3)
Rtp
RESET
RESET
VSS
I/O
LIN bus
MCP202XA
Master
µC
1k
VBB
Slave 1
µC
Slave 2
µC
Slave n <16
µC
40m
+ Return
LIN bus
LIN bus
MCP205X
LIN bus
MCP202XA
LIN bus
MCP2003
2012 Microchip Technology Inc. DS22298A-page 13
MCP2021A/2A
1.7 ICSP™ Considerations
The following should be considered when the
MCP2021A/2A is connected to pins supporting in-cir-
cuit programming:
• Power used for programming the microcontroller
can be supplied from the programmer, or from the
MCP2021A/2A.
• The voltage on the pin VREG should not exceed
the maximum value of VREG in Section 2.3 “DC
Specifications” .
MCP2021A/2A
DS22298A-page 14 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. DS22298A-page 15
MCP2021A/2A
2.0 ELECTRICAL
CHARACTERISTICS
2.1 Absolute Maximum Ratings†
VIN DC Voltage on RXD, and RESET ................................................................................................. -0.3V to VREG+0.3
VIN DC Voltage on TXD, CS/LWAKE, FAULT/TXE .......................................................................................-0.3 to +40V
VBB Battery Voltage, continuous, non-operating (Note 1)..............................................................................-0.3 to +40V
VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) (Note 2) .......................-0.3 to +43V
VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-100V
VBB Battery Voltage, transient ISO 7637 Test 2a .....................................................................................................+75V
VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-150V
VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+100V
VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V
VLBUS Bus Voltage, transient (Note 3)............................................................................................................-27 to +43V
ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA
ESD protection on LIN, VBB (IEC 61000-4-2) (Note 4)......................................................................................... ±15 KV
ESD protection on LIN, VBB (Human Body Model) (Note 5)................................................................................... ±8 KV
ESD protection on all other pins (Human Body Model) (Note 5) ............................................................................ ±4 KV
ESD protection on all pins (Charge Device Model) (Note 6) ................................................................................±1500V
ESD protection on all pins (Machine Model) (Note 7).............................................................................................±200V
Maximum Junction Temperature............................................................................................................................. 150C
Storage Temperature ..................................................................................................................................-65 to +150C
Note 1: LIN 2.x compliant specification.
2: SAE J2602-2 compliant specification.
3: ISO 7637/1 load dump compliant (t < 500 ms).
4: According to IEC 61000-4-2, 330 ohm, 150 pF and Transceiver EMC Test Specifications [2] to [4].
5: According to AEC-Q100-002 / JESD22-A114.
6: According to AEC-Q100-011B.
7: According to AEC-Q100-003 / JESD22-A115.
2.2 Nomenclature Used in This Document
Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent
values are shown below.
† NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
LIN 2.1 Name Term used in the following tables
VBAT not used ECU operating voltage
VSUP VBB Supply voltage at device pin
VBUS_LIM ISC Current limit of Driver
VBUSREC VIH(LBUS) Recessive state
VBUSDOM VIL(LBUS) Dominant state
MCP2021A/2A
DS22298A-page 16 2012 Microchip Technology Inc.
2.3 DC Specifications
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
T
A = -40°C to +125°C
Parameter Sym. Min. Typ. Max. Units Conditions
Power
VBB Quiescent Operating
Current
IBBQ ——200µAIOUT = 0 mA,
LBUS recessive
VREG = 5.0V
——200µAIOUT = 0 mA,
LBUS recessive
VREG = 3.3V
VBB READY Current IBBRD ——100µAIOUT = 0 mA,
LBUS recessive
VREG = 5.0V
——100µAIOUT = 0 mA,
LBUS recessive
VREG = 3.3V
VBB Transmitter-off Current IBBTO — — 100 µA With voltage regulator on,
transmitter off, receiver
on, FAULT/TXE = VIL, CS
= VIH,VREG = 5.0V
— — 100 µA With voltage regulator on,
transmitter off, receiver
on, FAULT/TXE = VIL, CS
= VIH,VREG = 3.3V
VBB Power-down Current IBBPD — 4.5 8 µA With voltage regulator
powered-off, receiver on
and transmitter off,
FAULT/TXE = VIH,
TXD = VIH, CS = VIL)
VBB Current with VSS
Floating
IBBNOGND -1 —1mAVBB = 12V, GND to VBB,
VLIN = 0-18V
Microcontroller Interface
High Level Input Voltage
(TXD, FAULT/TXE)
VIH 2.0 —VREG
+0.3
V
Low Level Input Voltage
(TXD, FAULT/TXE)
VIL-0.3 —0.8 V
High Level Input Current
(TXD, FAULT/TXE)
IIH -2.5 — 0.4 µA Input voltage = 4.0V.
~800 k internal
adaptive pull-up
Low Level Input Current
(TXD, FAULT/TXE)
IIL -10 — — µA Input voltage = 0.5V.
~800 k internal
adaptive pull-up
High Level Input Voltage
(CS/LWAKE)
VIH 2.0 —VBB V Through a current-limiting
resistor
Low Level Input Voltage
(CS/LWAKE)
VIL -0.3 —0.8 V
High Level Input Current
(CS/LWAKE)
IIH ——8.0 µA Input voltage = 0.8VREG
~1.3 M internal pull-
down to VSS
2012 Microchip Technology Inc. DS22298A-page 17
MCP2021A/2A
Low Level Input Current
(CS/LWAKE)
IIL ——5.0 µA Input voltage = 0.2VREG
~1.3 M internal pull-
down to VSS
Low Level Output Voltage
(RXD)
VOLRXD — — 0.2VREG VIOL = 2 mA
High Level Output Voltage
(RXD)
VOHRXD 0.8VREG —— VIOH = 2 mA
Low Level Output Voltage
(FAULT/TXE)
VOLOD —1.0V
IOL = 4 mA
Low Level Output Voltage
(RESET)
VOLRST ——1.0 V IOL = 4 mA
2.3 DC Specifications (Continued)
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
T
A = -40°C to +125°C
Parameter Sym. Min. Typ. Max. Units Conditions
MCP2021A/2A
DS22298A-page 18 2012 Microchip Technology Inc.
Bus Interface (DC specifications are for a VBB range of 6.0 to 18.0V)
High Level Input Voltage VIH(LBUS) 0.6 VBB — — V Recessive state
Low Level Input Voltage VIL(LBUS)-8—0.4 VBB V Dominant state
Input Hysteresis VHYS — — 0.175 VBB VVIH(LBUS) – VIL(LBUS)
Low Level Output Current IOL(LBUS) 40 — 200 mA Output voltage = 0.1 VBB,
VBB = 12V
Pull-up Current on Input IPU(LBUS)-180—-72µA~30k internal pull-up
@ VIH (LBUS) = 0.7 VBB,
VBB=12V
Short Circuit Current Limit ISC 50 — 200 mA (Note 1)
High Level Output Voltage VOH(LBUS) 0.8 VBB —VBB V
Driver Dominant Voltage V_LOSUP ——1.1VVBB = 7.3V, RLOAD =
1000
Driver Dominant Voltage V_HISUP ——1.2VVBB = 18V,
RLOAD = 1000
Input Leakage Current
(at the receiver during
dominant bus level)
IBUS_PAS_DOM -1 — — mA Driver off,
VBUS = 0V,
VBB = 12V
Input Leakage Current
(at the receiver during
recessive bus level)
IBUS_PAS_REC -20 — 20 µA Driver off,
8V < VBB < 18V
8V < VBUs < 18V
VBUS VBB
Leakage Current
(disconnected from ground)
IBUS_NO_GND -10 — +10 µA GNDDEVICE = VBB,
0V < VBUS < 18V,
VBB = 12V
Leakage Current
(disconnected from VBB)
IBUS_NO_PWR -10 — +10 µA VBB = GND,
0 < VBUS < 18V
Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5
VBB
0.525 VBB VVBUS_CNT = (VIL (LBUS) +
VIH (LBUS))/2
Slave Termination RSLAVE 20 30 47 k(Note 2)
Capacitance of slave node CSLAVE 50 pF (Note 2)
Wake-Up Voltage Thresh-
old on LIN Bus
VWK(LBUS) — — 3.4 V Wake up from POWER-
DOWN mode (Note 3)
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB).
2: For design guidance only, not tested.
3: In POWER DOWN mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to
detect bus activities.
2.3 DC Specifications (Continued)
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
T
A = -40°C to +125°C
Parameter Sym. Min. Typ. Max. Units Conditions
2012 Microchip Technology Inc. DS22298A-page 19
MCP2021A/2A
2.3 DC Specification (Continued)
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
T
A = -40°C to +125°C
CLOADREG = 10 µF
Parameter Sym. Min. Typ. Max. Units Conditions
Voltage Regulator - 5.0V
Output Voltage Range VREG 4.85 5.00 5.15 V 0 mA < IOUT < 70 mA
Line Regulation VOUT1—1050mVIOUT = 1 mA,
6.0V < VBB < 18V
Load Regulation VOUT2—1050mV5mA < IOUT <70 mA
6.0V < VBB < 12V
Power Supply Ripple
Reject
PSRR — — 50 dB 1 VPP @10-20 kHz
ILOAD = 20 mA
Output Noise Voltage eN — — 100 µVRMS 10 Hz – 40 MHz
CFILTER = 10 µf,
CBP = 0.1 µf, ILOAD = 20 mA
Shutdown Voltage
Threshold
VSD 3.5 — 4.0 V See Figure 1-7 (Note 1)
Input Voltage to Turn Off
Output
VOFF 3.9 — 4.5 V
Input Voltage to Turn On
Output
VON 5.25 — 6.0 V
Voltage Regulator - 3.3V
Output Voltage VREG 3.20 3.30 3.40 V 0 mA < IOUT < 70 mA
Line Regulation VOUT1—1050mVIOUT = 1 mA,
6.0V < VBB < 18V
Load Regulation VOUT2—1050mV5mA < IOUT < 70 mA,
6.0V < VBB < 12V
Power Supply Ripple
Reject
PSRR — — 50 dB 1 VPP @10-20 kHz ,
ILOAD = 20 mA
Output Noise Voltage eN — — 100 µVRMS
/Hz
10 Hz – 40 MHz
CFILTER = 10 µf,
CBP = 0.1 µf, ILOAD = 20 mA
Shutdown Voltage VSD 2.5 — 2.7 V See Figure 1-7 (Note 1)
Input Voltage to Turn Off
Output
VOFF 3.9 — 4.5 V
Input Voltage to Turn On
Output
VON 5.25 — 6 V
Note 1: For design guidance only, not tested.
MCP2021A/2A
DS22298A-page 20 2012 Microchip Technology Inc.
FIGURE 2-1: ESR CURVES FOR LOAD CAPACITOR SELECTION
Load Capacitor [uF]
ESR Curves
ESR [ohm]
10
1
0.1
0.01
0.001
10 100 1000
10.1
Instable
Instable
Instable
Stable only
with Tantalum or
Electrolytic cap.
Stable with
Tantalum,
Electrolytic and
Ceramic cap.
Unstable
U
nstable
Unstable
2012 Microchip Technology Inc. DS22298A-page 21
MCP2021A/2A
2.4 AC Specification
AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40°C to +125°C
Parameter Sym. Min. Typ. Max. Units Test Conditions
Bus Interface - Constant Slope Time Parameters (DC specifications are for a VBB range of 6.0 to 18.0V)
Slope rising and falling
edges
tSLOPE 3.5 — 22.5 µs 7.3V <= VBB <= 18V
Propagation Delay of
Transmitter
tTRANSPD ——5.0µstTRANSPD = max (tTRANSPDR or
tTRANSPDF)
Propagation Delay of
Receiver
tRECPD ——6.0µstRECPD = max (tRECPDR or
tRECPDF)
Symmetry of Propagation
Delay of Receiver rising
edge w.r.t. falling edge
tRECSYM -2.0 — 2.0 µs tRECSYM = max (tRECPDF –
tRECPDR)
RRXD 2.4 kto VCC, CRXD
20 pF
Symmetry of Propagation
Delay of Transmitter rising
edge w.r.t. falling edge
tTRANSSYM -2.0 — 2.0 µs tTRANSSYM = max (tTRANSPDF -
tTRANSPDR)
Bus dominant time-out time tTO(LIN) —25—mS
Time to sample FAULT/TXE
for bus conflict reporting
tFAULT ——32.5µstFAULT = max (tTRANSPD +
tSLOPE + tRECPD)
Duty Cycle 1 @20.0 kbit/sec .396 — — %tBIT CBUS;RBUS conditions:
1nF; 1k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.744 x VBB,
THDOM(MAX) = 0.581 x VBB,
VBB =7.0V - 18V; tBIT = 50 µs.
D1 = tBUS_REC(MIN) / 2 x tBIT)
Duty Cycle 2 @20.0 kbit/sec — — .581 %tBIT CBUS;RBUS conditions:
1nF; 1k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.284 x VBB,
THDOM(MAX) = 0.422 x VBB,
VBB =7.6V - 18V; tBIT = 50 µs.
D2 = tBUS_REC(MAX) / 2 x tBIT)
Duty Cycle 3 @10.4 kbit/sec .417 — — %tBIT CBUS;RBUS conditions:
1nF; 1k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.778 x VBB,
THDOM(MAX) = 0.616 x VBB,
VBB =7.0V - 18V; tBIT = 96 µs.
D3 = tBUS_REC(MIN) / 2 x tBIT)
Duty Cycle 4 @10.4 kbit/sec — — .590 %tBIT CBUS;RBUS conditions:
1nF; 1k | 6.8 nF; 660 |
10 nF; 500
THREC(MAX) = 0.251 x VBB,
THDOM(MAX) = 0.389 x VBB,
VBB =7.6V - 18V; tBIT = 96 µs.
D4 = tBUS_REC(MAX) / 2 x tBIT)
MCP2021A/2A
DS22298A-page 22 2012 Microchip Technology Inc.
2.5 Thermal Specifications
Voltage Regulator
Bus Activity Debounce time tBDB 30 80 250 µs
Bus Activity to Voltage
Regulator Enabled
tBACTIVE 35 — 200 µs
Voltage Regulator Enabled
to Ready
tVEVR 300 — 1200 µs (Note 1)
Chip Select to Ready Mode tCSR — — 230 µs (Note 2)
Chip Select to Power-down tCSPD — — 330 µs (Note 2)
Short circuit to shut-down tSHUTDOWN 20 — 100 µs
RESET Timing
VREG OK detect to RESET
inactive
tRPU ——60µs
(Note 2)
VREG not OK detect to
RESET active
tRPD ——60µs
(Note 2)
Note 1: Time depends on external capacitance and load. Test condition: CREG = 4.7uF, no resistor load.
2: For design guidance only, not tested.
THERMAL CHARACTERISTICS
Parameter Symbol Typ. Max. Units Test Conditions
Recovery Temperature RECOVERY +140 —C
Shutdown Temperature SHUTDOWN +150 —C
Short Circuit Recovery Time tTHERM 1.5 5.0 ms
Thermal Package Resistances
Thermal Resistance, 8L-PDIP JA 89.3 —C/W
Thermal Resistance, 8L-SOIC JA 149.5 —C/W
Thermal Resistance, 8L-DFN JA 48 —C/W
Thermal Resistance, 14L-PDIP JA 70 —C/W
Thermal Resistance, 14L-SOIC JA 95.3 —C/W
Thermal Resistance, 14L-TSSOP JA 100 —C/W
Note 1: The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum
allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)JA. If this dissipation is
exceeded, the die temperature will rise above 150C and the MCP2021A/2A will go into thermal
shutdown.
2.4 AC Specification (Continued)
AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40°C to +125°C
Parameter Sym. Min. Typ. Max. Units Test Conditions
2012 Microchip Technology Inc. DS22298A-page 23
MCP2021A/2A
2.6 Timing Diagrams and Specifications
FIGURE 2-2: BUS TIMING DIAGRAM
FIGURE 2-3: REGULATOR BUS WAKE TIMING DIAGRAM
.95VLBUS
.05VLBUS
tTRANSPDR
tRECPDR
tTRANSPDF
tRECPDF
TXD
LBUS
RXD
Internal TXD/RXD
Compare
FAULT Sampling
tFAULT tFAULT
FAULT/TXE Output Stable Stable
Stable
Match Match
Match Match Match
Hold
Value
Hold
Value
50%
50%
.50VBB
50%
50%
0.0V
VREG
LBUS
VWK(LBUS)
t
VEVR
VREG-NOM
tBDB tBACTIVE
MCP2021A/2A
DS22298A-page 24 2012 Microchip Technology Inc.
FIGURE 2-4: CS/LWAKE, REGULATOR AND RESET TIMING DIAGRAM
FIGURE 2-5: TYPICAL IBBQ VS.
TEMPERATURE - 5.0V
FIGURE 2-6: TYPICAL IBBTO VS.
TEMPERATURE - 5.0V
FIGURE 2-7: TYPICAL IPD VS.
TEMPERATURE - 5.0V
tCSPD
tCSR
CS/LWAKE
VREG
VREG-NOM
RESET
tRPU
tVEVR
tRPD
180
200
160
180
200
μ
A)
140
160
180
200
I
BBQ
(μA)
120
140
160
180
200
I
BBQ
(μA)
VBB =6V
100
120
140
160
180
200
I
BBQ
(μA)
VBB =6V
VBB =12V
VBB =18V
80
100
120
140
160
180
200
-40 -25 -10 5 20 35 50 65 80 95 110 125
I
BBQ
(μA)
T(C)
VBB =6V
VBB =12V
VBB =18V
80
100
120
140
160
180
200
-40 -25 -10 5 20 35 50 65 80 95 110 125
I
BBQ
(μA)
Temperature(C)
VBB =6V
VBB =12V
VBB =18V
90
80
90
μ
A)
70
80
90
BBTO (μA)
60
70
80
90
IBBTO (μA)
VBB =6V
VBB =12V
60
70
80
90
IBBTO (μA)
VBB =6V
VBB =12V
VBB =18V
50
60
70
80
90
-40 -25 -10 5 20 35 50 65 80 95 110 125
IBBTO (μA)
VBB =6V
VBB =12V
VBB =18V
50
60
70
80
90
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature(C)
IBBTO (μA)
VBB =6V
VBB =12V
VBB =18V
5
5.2
4.8
5
5.2
μA)
44
4.6
4.8
5
5.2
I
PD
(μA)
4.2
4.4
4.6
4.8
5
5.2
V
BB
=6V
V
BB
=12V
I
PD
(μA)
4
4.2
4.4
4.6
4.8
5
5.2
40
25
10
5
20
35
50
65
80
95
110
125
V
BB
=6V
V
BB
=12V
V
BB
=18V
I
PD
(μA)
4
4.2
4.4
4.6
4.8
5
5.2
-40 -25 -10 5 20 35 50 65 80 95 110 125
V
BB
=6V
V
BB
=12V
V
BB
=18V
Temperature(C)
I
PD
(μA)
4
4.2
4.4
4.6
4.8
5
5.2
-40 -25 -10 5 20 35 50 65 80 95 110 125
V
BB
=6V
V
BB
=12V
V
BB
=18V
Temperature(C)
I
PD
(μA)
2012 Microchip Technology Inc. DS22298A-page 25
MCP2021A/2A
FIGURE 2-8: TYPICAL IBBQVS.
TEMPERATURE - 3.3V
FIGURE 2-9: TYPICAL IBBTO VS.
TEMPERATURE - 3.3V
FIGURE 2-10: TYPICAL IPD VS.
TEMPERATURE - 3.3V
120
140
160
180
200
IBBQ (μA)
VBB =6V
VBB =12V
80
100
120
140
160
180
200
-40 -25 -10 5 20 35 50 65 80 95 110 125
IBBQ (μA)
Temperature(C)
VBB =6V
VBB =12V
VBB =18V
90
100
80
90
100
A
)
70
80
90
100
B
TO (μA)
60
70
80
90
100
IBBTO (μA)
VBB =6V
V
BB
= 12V
50
60
70
80
90
100
IBBTO (μA)
VBB =6V
VBB =12V
VBB =18V
50
60
70
80
90
100
-40 -25 -10 5 20 35 50 65 80 95 110 125
IBBTO (μA)
Temperature(
C)
VBB =6V
VBB =12V
VBB =18V
50
60
70
80
90
100
-40 -25 -10 5 20 35 50 65 80 95 110 125
IBBTO (μA)
Temperature(C)
VBB =6V
VBB =12V
VBB =18V
4.4
4.6
4.8
5
5.2
I
PD
(μA)
VBB =6V
VBB =12V
4
4.2
4.4
4.6
4.8
5
5.2
-40-25-105 203550658095110125
I
PD
(μA)
Temperature(C)
VBB =6V
VBB =12V
VBB =18V
MCP2021A/2A
DS22298A-page 26 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. DS22298A-page 27
MCP2021A/2A
3.0 PACKAGING INFORMATION
3.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
NNN
8-Lead SOIC (150 mil) (MCP2021A) Example:
2021A50E
SN ^^1210
256
3
e
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) (MCP2021A) Example
YYWW
NNN
XXXXXX
XXXXXX
PIN 1 PIN 1
2021A
500EMD
1210
256
8-Lead
DFN (4x4x0.9 mm)
(MCP2021A) Example
2021A500
E/P ^^256
1210
3
e
MCP2021A/2A
DS22298A-page 28 2012 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead SOIC (.150”) (MC2022A) Example
14-Lead TSSOP (MCP2022A)
MCP2022A
500E/SL ^^
1210256
3
e
YYWW
NNN
XXXXXXXX
2022A500
1210
256
14-Lead PDIP (300 mil) (MCP2022A) Example
Example
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
MCP2022A
500E/P ^^
1210256
3
e
3
e
2012 Microchip Technology Inc. DS22298A-page 29
MCP2021A/2A
8-Lead Plastic Dual Flat, No Lead Package (MD)  4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
MCP2021A/2A
DS22298A-page 30 2012 Microchip Technology Inc.
8-Lead Plastic Dual Flat, No Lead Package (MD)  4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
2012 Microchip Technology Inc. DS22298A-page 31
MCP2021A/2A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2021A/2A
DS22298A-page 32 2012 Microchip Technology Inc.


 
 
 
 

 

 
   

 
 
    
  
   
    
   
   
   
    
   
  
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
   
2012 Microchip Technology Inc. DS22298A-page 33
MCP2021A/2A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2021A/2A
DS22298A-page 34 2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012 Microchip Technology Inc. DS22298A-page 35
MCP2021A/2A
 ! ""#$%& !'
 

MCP2021A/2A
DS22298A-page 36 2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012 Microchip Technology Inc. DS22298A-page 37
MCP2021A/2A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2021A/2A
DS22298A-page 38 2012 Microchip Technology Inc.
 

2012 Microchip Technology Inc. DS22298A-page 39
MCP2021A/2A
()

 
 
 
 

 

 
   
 
 
 
   
  
   
    
   
   
   
    
   
  
N
E1
D
NOTE 1
123
E
c
eB
A2
L
A
A1 b1
be
   
MCP2021A/2A
DS22298A-page 40 2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012 Microchip Technology Inc. DS22298A-page 41
MCP2021A/2A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2021A/2A
DS22298A-page 42 2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012 Microchip Technology Inc. DS22298A-page 43
MCP2021A/2A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP2021A: LIN Transceiver with Voltage Regulator
MCP2021AT: LIN Transceiver with Voltage Regulator
(Tape and Reel) (SOIC only)
Temperature Range: E = -40°C to +125°C
Package: MD = Plastic Dual Flat DFN, 8-lead
SN = Plastic Small Outline SOIC, 8-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SL = Plastic SOIC, (150 mil Body), 14-lead
ST = Plastic TSSOP, 14-lead
PART NO. –X /XX
PackageTemperature
Range
Device
Examples:
a) MCP2021A-330E/SL: 3.3V, 8L-SOIC package
b) MCP2021A-330E/P: 3.3V, 8L-PDIP package
c) MCP2021A-500E/SL: 5.0V, 8L-SOIC package
d) MCP2021A-500E/P: 5.0V, 8L-PDIP package
e) MCP2021AT-330E/SL: Tape and Reel,
3.3V, 8L-SOIC package
f) MCP2021AT-500E/SL: Tape and Reel,
5.0V, 8L-SOIC package
g) MCP2022A-330E/SL: 3.3V, 14L-SOIC package
h) MCP2022A-330E/P: 3.3V, 14L-PDIP package
i) MCP2022A-500E/SL: 5.0V, 14L-SOIC package
j) MCP2022A-500E/P: 5.0V, 14L-PDIP package
k) MCP2022AT-330E/SL: Tape and Reel,
3.3V, 14L-SOIC package
l) MCP2022AT-500E/SL: Tape and Reel,
5.0V, 14L-SOIC package
MCP2021A/2A
DS22298A-page 44 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. DS22298A-page 45
MCP2021A/2A
APPENDIX A: REVISION HISTORY
Revision A (March 2012)
• Original Release of this Document.
MCP2021A/2A
DS22298A-page 46 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. DS22298A-page 47
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-155-7
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS22298A-page 48 2012 Microchip Technology Inc.
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MCP2021AT-330E/MD MCP2021AT-330E/SN MCP2021AT-500E/MD MCP2022A-330E/ST MCP2022A-500E/SL
MCP2022A-500E/ST MCP2022AT-330E/SL MCP2022AT-330E/ST MCP2022AT-500E/SL MCP2022AT-500E/ST
MCP2021A-330E/MD MCP2021A-500E/SN MCP2021AT-500E/SN MCP2021A-500E/MD MCP2022A-330E/SL
MCP2021A-330E/SN