AM79C976KD - AMD - Datasheet.Live

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 22929 Rev: EAmendment/0

Issue Date: September 2000

Refer to AMD’s Website (www.amd.com) for the latest information.

Am79C976

PCnet-PRO™

10/100 Mbps PCI Ethernet Controller

DISTINCTIVE CHARACTERISTICS

■Integrated Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) bus

—32-bit glueless PCI host interface

—Supports PCI clock frequency from DC to

33 MHz independent of network clock

—Supports network operation with PCI clock

from 15 MHz to 33 MHz

—High performance bus mastering

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization

—PCI specification revision 2.2 compliant

—Supports PCI Subsystem/Subvendor

ID/Vendor ID programming through the

EEPROM interface

—Supports both PCI 3.3-V and 5.0-V signaling

environments

—Plug and Play compatible

—Uses advanced PCI commands (MWI, MRL,

MRM)

—Optionally supports PCI bursts aligned to

cache line boundaries

—Supports big endian and little endian byte

alignments

—Implements optional PCI power management

event (PME) pin

—Supports 40-bit addressing (using PCI Dual

Address Cycles)

■Media Independent Interface (MII) for

connecting external 10/100 megabit per second

(Mbps) transceivers

—IEEE 802.3-compliant MII

—Intelligent Auto-Poll™ external PHY status

monitor and interrupt

—Supports both auto-negotiable and non auto-

negotiable external PHYs

—Supports 10BASE-T, 100BASE-TX/FX,

100BASE-T4, and 100BASE-T2 IEEE 802.3-

compliant MII PHYs at full- or half-duplex

■Full-duplex operation supported with

independent Transmit (TX) and Receive (RX)

channels

■Includes support for IEEE 802.1Q VLANs

—Automatically inserts, deletes, or modifies

VLAN tag

—Optionally filters untagged frames

■Provides optional flow control features

—Recognizes and transmits IEEE 802.3x MAC

flow control frames

—Asserts collision-based back pressure in

half-duplex mode

■Provides internal Management Information

Base (MIB) counters for network statistics

■Supports PC97, PC98, PC99, and Net PC

requirements

—Implements full OnNow features including

pattern matching and link status wake-up

—Implements Magic Packet™ mode

—Magic Packet mode and the physical address

loaded from EEPROM at power up without

requiring PCI clock

—Supports PCI Bus Power Management

Interface Specification Version 1.1

—Supports Advanced Configuration and

Power Interface (ACPI) Specification Version

1.0

—Supports Network Device Class Power

Management Specification Version 1.0

■Large independent external TX and RX FIFOs

—Supports up to 4 megabytes (Mbytes)

external SSRAM for RX and TX frame storage

—Programmable FIFO watermarks for both

transmit and receive operations

—Receive frame queuing for high latency PCI

bus host operation

—Programmable allocation of buffer space

between transmit and receive queues

2 Am79C976 9/14/00

PRELIMINARY

■Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with

IEEE/ANSI 802.3 and Blue Book Ethernet

standards

■Programmable internal/external loopback

capabilities

■Supports patented External Address Detection

Interface (EADI) with receive frame tagging

support for internetworking applications

■EEPROM interface supports jumperless design

and provides through-chip programming

—Supports full programmability of all internal

registers through EEPROM mapping

■Programmable PHY reset output pin capable of

resetting external PHY without needing

buffering

■Integrated oscillator circuit is controlled by

external crystal

■Extensive programmable LED status support

■Supports up to 16 Mbyte optional Boot PROM or

Flash for diskless node application

■Look-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead

by allowing protocol analysis to begin before

the end of a receive frame

■Programmable Inter Packet Gap (IPG) to

address less aggressive network MAC

controllers

■Offers the Modified Back-Off algorithm to

address the Ethernet Capture Effect

■Optionally sends and receives non-standard

frames of up to 64K octets in length

■IEEE 1149.1-compliant JTAG Boundary Scan

test access port interface for board-level

production connectivity test

■Provides built-in self test (MBIST) for the

external SSRAM

■Software compatible with AMD PCnet Family

and LANCE/C-LANCE register and descriptor

architecture

■Compatible with the existing PCnet Family

driver and diagnostic software (except for

statistics)

■Available in 208-pin PQFP package

■+3.3-V power supply with 5-V tolerant I/Os

enables broad system compatibility

■Support for operation in Industrial temperature

range (-40° C to +85° C) available.

9/14/00 Am79C976 3

PRELIMINARY

GENERAL DESCRIPTION

The Am79C976 controller is a highly-integrated 32-bit

full-duplex, 10/100-Megabit per second (Mbps) Ether-

net controller solution, designed to address high-

performance system application requirements. It is a

flexible bus mastering device that can be used in any

application, including network-ready PCs and bridge/

router designs. The bus master architecture provides

high data throughput and low CPU and system bus uti-

lization. The Am79C976 controller is fabricated with

advanced low-power 3.3-V CMOS process to provide

low operating current for power sensitive applications.

The Am79C976 controller also has several enhance-

ments over its predecessor, the Am79C971

PCnet-FAST device. In addition to providing access to

a larger SSRAM, it further reduces system implemen-

tation cost by the addition of a new EEPROM program-

mable pin (PHY_RST) and the integration of the PAL

function needed for Magic Packet application. The

PHY_RST pin is implemented to reset the external

PHY without increasing the load to the PCI bus and to

block RST to the PHY when PG input is LOW.

The 32-bit multiplexed bus interface unit provides a di-

rect interface to the PCI local bus, simplifying the de-

sign of an Ethernet node in a PC system. The

Am79C976 controller provides the complete interface

to an Expansion ROM or Flash device allowing add-on

card designs with only a single load per PCI bus inter-

face pin. With its built-in support for both little and big

endian byte alignment, this controller also addresses

non-PC applications. The Am79C976 controller’s

advanced CMOS design allows the bus interface to be

connected to either a +5-V or a +3.3-V signaling envi-

ronment. An IEEE 1149.1-compliant JTAG test inter-

face for board-level testing is also provided.

The Am79C976 controller is also compliant with the

PC97, PC98, PC99, and Network PC (Net PC) specifi-

cations. It includes the full implementation of the Mi-

crosoft OnNow and ACPI specifications, which are

backward compatible with the Magic Packet technol-

ogy, and it is compliant with the PCI Bus Power Man-

agement Interface Specification by supporting the four

power management states (D0, D1, D2, and D3), the

optional PME pin, and the necessary configuration and

data registers.

The Am79C976 controller is ideally suited for Net PC,

motherboard, network interface card (NIC), and em-

bedded designs. It is available in a 208-pin Plastic

Quad Flat Pack (PQFP) package.

The Am79C976 controller contains a bus interface unit,

a DMA Buffer Management Unit, an ISO/IEC 8802-3

(IEEE 802.3)-compliant Media Access Controller

(MAC), and an IEEE 802.3-compliant MII. An interface

to an external RAM of up to 4 Mbytes is provided for

frame storage. The MII supports IEEE 802.3-compliant

full-duplex and half-duplex operations at 10 Mbps or

100 Mbps. The MII TX and RX clock signals can be

stopped independently for home networking applica-

tions.

The Am79C976 controller is register compatible with

the LANCE™ (Am7990) and C-LANCE™ (Am79C90)

Ethernet controllers, and all Ethernet controllers in the

PCnet Family except ILACC™ (Am79C900), including

the PCnet™-ISA controller (Am79C960),

PCnet™-ISA+ (Am79C961), PCnet™-ISA II

(Am79C961A), PCnet™-32 (Am79C965), PCnet™-

PCI (Am79C970), PCnet™-PCI II (Am79C970A), and

the PCnet™-FAST (Am79C971).

The Buffer Management Unit supports the LANCE and

PCnet descriptor software models.

The Am79C976 controller supports auto-configuration

in the PCI configuration space. Additional Am79C976

controller configuration parameters, including the

unique IEEE physical address, can be read from an ex-

ternal nonvolatile memory (EEPROM) immediately fol-

lowing system reset.

In addition, the device provides programmable on-chip

LED drivers for transmit, receive, collision, link integrity,

Magic Packet status, activity, address match, full-

duplex, or 100 Mbps status. The Am79C976 controller

also provides an EADI to allow external hardware ad-

dress filtering in internetworking applications and a

receive frame tagging feature.

With the rise of embedded networking applications op-

erating in harsh environments where temperatures

may exceed the normal commercial temperature (0° C

to +70° C) window, an industrial temperature (-40° C to

+85° C) version is available. This industrial tempera-

ture version of the PCnet-PRO Ethernet controller is

characterized across the industrial temperature range

(-40° C to +85° C) within the published power supply

specification (2.97V to 3.63V; ±10% Vcc). Thus, con-

formance of the PCnet-PRO performance over this

temperature range is guaranteed by a design and

characterization monitor.

4 Am79C976 9/14/00

PRELIMINARY

BLOCK DIAGRAM

CLK

RST

AD[31:0]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT

PERR

SERR

INTA

PCI Bus

Interface

Unit

93CXX

EEPROM

Interface

Expansion Bus

Interface

MIB

Counters

JTAG

Port

Control

OnNow

Power

Management

Unit

802.3

MAC

Core

MII

Port

EADI

Port

ERADV/FLOE

ERADSP/ICEN

ERCLK

ERD[31:0]/FLD[7:0]/FLA[23.20]

ERA[19:0]/FLA[19:0]

ERCE

EROE

ERWE

FLCS

PME

RWU

WUMI

PHY_RST

TXD[3:0]

TX_EN

TX_CLK

COL

RXD[3:0]

RX_ER

RX_CLK

RX_DV

CRS

SFBD

EAR

RXFRTGD

RXFRTGE

EECS

EESK

EEDI

EEDO

LED0

LED1

LED2

LED3

Network Port

Manager

MDC

MDIO

Memory Control

Unit

and Status Unit

Descriptor

Management Unit

LED

Control

VAUX_SENSE

Clock

Generator

XTAL1

XTAL2

XCLK

CLKSEL0

CLKSEL1

CLKSEL2

TCK

TMS

TDI

TDO

TEST

22929B1

CEN

9/14/00 Am79C976 5
PRELIMINARY
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
BLOCK DIAGRAM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
LIST OF FIGURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LIST OF TABLES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CONNECTION DIAGRAM (PQR208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PIN DESIGNATIONS (PQR208)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Listed By Pin Number  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Board Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
EEPROM Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
External Address Detection Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Power Supply Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
BASIC FUNCTIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Network Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Slave Bus Interface Unit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Slave I/O Transfers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Expansion ROM Transfers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Disconnect When Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Disconnect Of Burst Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Master Bus Interface Unit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Basic Non-Burst Read Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Basic Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Basic Non-Burst Write Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Basic Burst Write Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
DMA Burst Alignment  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Disconnect Without Data Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Target Abort  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Master Initiated Termination  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Preemption During Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Initialization Block DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Descriptor Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
TABLE OF CONTENTS

6 Am79C976 9/14/00
PRELIMINARY
Re-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Run and Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Descriptor Management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Transmit Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Receive Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Look Ahead Packet Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Software Interrupt Timer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Media Access Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Destination Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Media Access Management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Medium Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Signal Quality Error (SQE) Test  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Transmit Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Automatic Pad Generation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Transmit Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Loss of Carrier  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Late Collision  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Transmit FIFO Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Receive Function Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Address Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Receive Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Receive Statistics Counters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Transmit Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
VLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
VLAN Frame Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Admit Only VLAN Frames Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
VLAN Tags in Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Loopback Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Miscellaneous Loopback Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Full-Duplex Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Full-Duplex Link Status LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MII Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MII Receive Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MII Network Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
MII Management Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
MII Management Frames  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Host CPU Access to External PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Auto-Poll State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Network Port Manager  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Auto-Negotiation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Auto-Negotiation With Multiple PHY Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Operation Without MMI Management Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Regulating Network Traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
MAC Control Pause Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Back Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9/14/00 Am79C976 7
PRELIMINARY
Enabling Traffic Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Hardware Control of Traffic Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Software Control of Traffic Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Programming the Pause Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
PAUSE Frame Reception  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
External Address Detection Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
External Address Detection Interface: Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . 93
External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Expansion ROM - Boot Device Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Direct Flash Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Flash/EPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
EEPROM Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Automatic EEPROM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
EEPROM Auto-Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Direct Access to the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EEPROM CRC Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LED Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Power Management Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
OnNow Wake-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
RWU Wake-Up Sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Link Change Detect  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Magic Packet Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
OnNow Pattern Match Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Pattern Match RAM (PMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Boundary Scan Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
TAP Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Supported Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Other Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
H_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
EE_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
S_RESET  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
STOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Power on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
External PHY Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Software Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Address PROM Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Reset Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Word I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Double Word I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PCI Configuration Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PCI Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PCI Command Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PCI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PCI Revision ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PCI Programming Interface Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PCI Sub-Class Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PCI Base-Class Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PCI Cache Line Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

8 Am79C976 9/14/00
PRELIMINARY
PCI Latency Timer Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PCI Header Type Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PCI I/O Base Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
PCI Memory Mapped I/O Base Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
PCI Subsystem Vendor ID Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
PCI Subsystem ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PCI Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PCI Capabilities Pointer Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
PCI Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PCI MIN_GNT Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PCI MAX_LAT Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PCI Capability Identifier Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PCI Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
PCI Power Management Capabilities Register (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PCI Power Management Control/Status Register (PMCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
PCI PMCSR Bridge Support Extensions Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
MIB Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
AP_VALUE0: Auto-Poll Value0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
AP_VALUE1: Auto-Poll Value1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
AP_VALUE2: Auto-Poll Value2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
AP_VALUE3: Auto-Poll Value3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
AP_VALUE4: Auto-Poll Value4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
AP_VALUE5: Auto-Poll Value5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
AUTOPOLL0: Auto-Poll0 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
AUTOPOLL1: Auto-Poll1 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
AUTOPOLL2: Auto-Poll2 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
AUTOPOLL3: Auto-Poll3 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
AUTOPOLL4: Auto-Poll4 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
AUTOPOLL5: Auto-Poll5 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
BADR: Receive Ring Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
BADX: Transmit Ring Base Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
CHIPID: Chip ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
CHPOLLTIME: Chain Poll Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
CMD0: Command0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
CMD2: Command2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
CMD3: Command3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
CMD7: Command7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
CTRL0: Control0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
CTRL1: Control1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
CTRL2: Control2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
CTRL3: Control3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
DATAMBIST: Memory Built-in Self-Test Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Reserved Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
EEPROM_ACC: EEPROM Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
FLASH_ADDR: Flash Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
FLASH_DATA: Flash Data Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
 FLOW: Flow Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
IFS1: Inter-Frame Spacing Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
INT0: Interrupt0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
INTEN0: Interrupt0 Enable  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
IPG: Inter-Packet Gap Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
LADRF: Logical Address Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
LED0 Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
LED1 Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
LED2 Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

9/14/00 Am79C976 9
PRELIMINARY
LED3 Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
MAX_LAT_A: PCI Maximum Latency Alias Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
MIN_GNT_A: PCI Minimum Grant Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
PADR: Physical Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Pause Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
PCIDATA0: PCI DATA Register Zero Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
PCIDATA1: PCI DATA Register One Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
PCIDATA2: PCI DATA Register Two Alias Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
PCIDATA3: PCI DATA Register Three Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
PCIDATA4: PCI DATA Register Four Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
PCIDATA5: PCI DATA Register Five Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
PCIDATA6: PCI DATA Register Six Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
PCIDATA7: PCI DATA Register Seven Alias Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
 PHY Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
PMAT0: OnNow Pattern Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
PMAT1: OnNow Pattern Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
PMC_A: PCI Power Management Capabilities Alias Register  . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Receive Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
RCV_RING_LEN: Receive Ring Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
ROM_CFG: ROM Base Address Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SID_A: PCI Subsystem ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
 SRAM Boundary Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
SRAM Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
STAT0: Status0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Software Timer Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
SVID_A: PCI Subsystem Vendor ID Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
VID_A: PCI Vendor ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
XMT_RING_LEN: Transmit Ring Length Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
XMTPOLLTIME: Transmit Poll Timer Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
RAP: Register Address Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
CSR0: Am79C976 Controller Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
CSR1: Initialization Block Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
CSR2: Initialization Block Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
CSR3: Interrupt Masks and Deferral Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
CSR5: Extended Control and Interrupt 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
CSR6: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
CSR7: Extended Control and Interrupt 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
CSR8: Logical Address Filter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
CSR9: Logical Address Filter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
CSR10: Logical Address Filter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
CSR11: Logical Address Filter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
CSR12: Physical Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
CSR13: Physical Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
CSR14: Physical Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
CSR15: Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
CSR16-23: Reserved  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
CSR25: Base Address of Receive Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
CSR26-29: Reserved  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
CSR30: Base Address of Transmit Ring Lower  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
CSR31: Base Address of Transmit Ring Upper  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
CSR32-46: Reserved  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
CSR47: Transmit Polling Interval  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
CSR48: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
CSR49: Chain Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

10 Am79C976 9/14/00
PRELIMINARY
CSR50-57: Reserved  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
CSR58: Software Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
CSR59-75: Reserved  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
CSR77: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
CSR78: Transmit Ring Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
CSR79: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
CSR80: DMA Transfer Counter and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
CSR81-87: Reserved  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR88: Chip ID Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR89: Chip ID Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR90-99: Reserved  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR100: Bus Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR101-111: Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR113: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR115: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
CSR116: OnNow Power Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
CSR117-121: Reserved  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
CSR122: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
CSR123: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
CSR124: Test Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
CSR125: MAC Enhanced Configuration Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Bus Configuration Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
BCR0: Master Mode Read Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
BCR1: Master Mode Write Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
BCR2: Miscellaneous Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
BCR4: LED0 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
BCR5: LED1 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
BCR6: LED2 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
BCR7: LED3 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
BCR9: Full-Duplex Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
BCR16: I/O Base Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
BCR17: I/O Base Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
BCR18: Burst and Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
BCR19: EEPROM Control and Status  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
BCR20: Software Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
BCR22: PCI Latency Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
BCR23: PCI Subsystem Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
BCR24: PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
BCR25: SRAM Size Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
BCR26: SRAM Boundary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
BCR27: SRAM Interface Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
BCR28: Expansion Bus Port Address Lower (Used for Flash/EPROM and SRAM Accesses)  . 218
BCR29: Expansion Port Address Upper (Used for Flash/EPROM Accesses)  . . . . . . . . . . . . . . 218
BCR30: Expansion Bus Data Port Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
BCR31: Software Timer Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
BCR32: MII Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
BCR33: MII Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
BCR34: MII Management Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
BCR35: PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
BCR36: PCI Power Management Capabilities (PMC) Alias Register . . . . . . . . . . . . . . . . . . . . . 222
BCR37: PCI DATA Register Zero (DATA0) Alias Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
BCR38: PCI DATA Register One (DATA1) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
BCR39: PCI DATA Register Two (DATA2) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
BCR40: PCI DATA Register Three (DATA3) Alias Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
BCR41: PCI DATA Register Four (DATA4) Alias Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

9/14/00 Am79C976 11
PRELIMINARY
BCR42: PCI DATA Register Five (DATA5) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
BCR43: PCI DATA Register Six (DATA6) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
BCR44: PCI DATA Register Seven (DATA7) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
BCR45: OnNow Pattern Matching Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
BCR46: OnNow Pattern Matching Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
BCR47: OnNow Pattern Matching Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Initialization Block  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
RDRA and TDRA  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
LADRF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
PADR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
PCI Configuration Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Bus Configuration Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
REGISTER BIT CROSS REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
REGISTER PROGRAMMING SUMMARY  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . 269
SWITCHING CHARACTERISTICS: BUS INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
SWITCHING WAVEFORMS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
SWITCHING CHARACTERISTICS: EEPROM INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
SWITCHING CHARACTERISTICS: JTAG TIMING  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . 280
SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . . . . . 283
SWITCHING WAVEFORMS: RECEIVE FRAME TAG  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
SWITCHING WAVEFORMS: EXTERNAL MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
PHYSICAL DIMENSIONS*  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
PQFP208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Plastic Quad Flat Pack Trimmed and Formed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
APPENDIX A: LOOK-AHEAD PACKET PROCESSING  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Outline of LAPP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
LAPP Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
LAPP Rules for Parsing Descriptors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
An Alternative LAPP Flow: Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

12 Am79C976 9/14/00

PRELIMINARY

APPENDIX B: MII MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Technology Ability Field Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .INDEX-1

10/17/00 Am79C976 13
PRELIMINARY
LIST OF FIGURES
 Figure 1:  Slave Configuration Read   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
 Figure 2:  Slave Configuration Write   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
 Figure 3:  Slave Read Using I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
 Figure 4:  Slave Write Using Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
 Figure 5:  Disconnect Of Slave Cycle When Busy  . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
 Figure 6:  Disconnect Of Slave Burst Transfer - No Host Wait States  . . . . . . . . . . . . 39
 Figure 7:  Disconnect Of Slave Burst Transfer - Host Inserts Wait States . . . . . . . . . 40
 Figure 8:  Address Parity Error Response  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
 Figure 9:  Slave Cycle Data Parity Error Response  . . . . . . . . . . . . . . . . . . . . . . . . . . 41
 Figure 10:  Bus Acquisition   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
 Figure 11:   Non-Burst Read Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
 Figure 12:   Burst Read Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
 Figure 13:  Non-Burst Write Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
 Figure 14:  Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
 Figure 15:  Disconnect With Data Transfer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
 Figure 16:  Disconnect Without Data Transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
 Figure 17:  Target Abort  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
 Figure 18:  Preemption During Non-Burst Transaction   . . . . . . . . . . . . . . . . . . . . . . . . 50
 Figure 19:  Preemption During Burst Transaction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
 Figure 20:  Master Abort   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
 Figure 21:  Master Cycle Data Parity Error Response  . . . . . . . . . . . . . . . . . . . . . . . . . 53
 Figure 22:  Descriptor Ring Read In Non-Burst Mode  . . . . . . . . . . . . . . . . . . . . . . . . . 54
 Figure 23:  Descriptor Ring Read In Burst Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
 Figure 24:  Descriptor Ring Write In Non-Burst Mode  . . . . . . . . . . . . . . . . . . . . . . . . . 57
 Figure 25:  Descriptor Ring Write In Burst Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
 Figure 26:  FIFO Burst Write At Start Of Unaligned Buffer   . . . . . . . . . . . . . . . . . . . . . 59
 Figure 27:  FIFO Burst Write At End Of Unaligned Buffer  . . . . . . . . . . . . . . . . . . . . . . 61
 Figure 28:  16-Bit Software Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
 Figure 29:  32-Bit Software Model  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
 Figure 30:  ISO 8802-3 (IEEE/ANSI 802.3) Data Frame  . . . . . . . . . . . . . . . . . . . . . . . 72
 Figure 31:  IEEE 802.3 Frame and Length Field Transmission Order  . . . . . . . . . . . . . 75
 Figure 32:  VLAN-Tagged Frame Format   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
 Figure 33:  Media Independent Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
 Figure 34:  Frame Format at the MII Interface Connection   . . . . . . . . . . . . . . . . . . . . . 85
 Figure 35:  MII Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
 Figure 36:  External SSRAM and Flash Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 94
 Figure 37:  Expansion ROM Bus Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
 Figure 38:  Flash Read from Expansion Bus Data Port  . . . . . . . . . . . . . . . . . . . . . . . . 97
 Figure 39:  Flash Write Sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
 Figure 40:  EEPROM Data Format   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
 Figure 41:  EEPROM Entry Positions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
 Figure 42:  CRC Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
 Figure 43:  LED Control Logic  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
 Figure 44:  OnNow Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
 Figure 45:  Pattern Match RAM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
 Figure 46:  PCI Expansion ROM Base Address Register   . . . . . . . . . . . . . . . . . . . . . 119
 Figure 47:  Address Match Logic  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
 Figure 48:  Normal and Tri-State Outputs   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

14 Am79C976 10/17/00
PRELIMINARY
 Figure 49:  CLK Waveform for 5 V Signaling  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
 Figure 50:  CLK Waveform for 3.3 V Signaling   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
 Figure 51:  Input Setup and Hold Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
 Figure 52:  Output Valid Delay Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
 Figure 53:  Output Tri-State Delay Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
 Figure 54:  EEPROM Read Functional Timing   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
 Figure 55:  Automatic PREAD EEPROM Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
 Figure 56:  JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling  . . . . . . . . . . . . . . 278
 Figure 57:  JTAG (IEEE 1149.1) Test Signal Timing  . . . . . . . . . . . . . . . . . . . . . . . . . 279
 Figure 58:  Transmit Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
 Figure 59:  Receive Timing   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
 Figure 60:  MDC Waveform  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
 Figure 61:  Management Data Setup and Hold Timing  . . . . . . . . . . . . . . . . . . . . . . . 282
 Figure 62:  Management Data Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . 282
 Figure 63:  Reject Timing - External PHY MII @ 25 MHz   . . . . . . . . . . . . . . . . . . . . . 283
 Figure 64:  Reject Timing - External PHY MII @ 2.5 MHz  . . . . . . . . . . . . . . . . . . . . . 284
 Figure 65:  Receive Frame Tag Timing with Media Independent Interface  . . . . . . . . 285
 Figure 66:  External Memory Timing   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
 Figure A-1:   LAPP Timeline A-4
 Figure A-2:   LAPP 3 Buffer Grouping A-5
 Figure A-3:   LAPP Timeline for Two-Interrupt Method A-9
 Figure A-4:   LAPP 3 Buffer Grouping for Two-Interrupt Method A-10

10/17/00 Am79C976 15
PRELIMINARY
LIST OF TABLES
 Table 1:   System Clock Selections   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
 Table 2:   Slave Commands  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
 Table 3:   PCI Commands   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
 Table 4:   Descriptor Read Sequence   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
 Table 5:   Descriptor Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
 Table 6:   Receive Address Match  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
 Table 7:   Receive Statistics Counters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
 Table 8:   Transmit Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
 Table 9:   VLAN Tag Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
 Table 10:   VLAN Tag Type   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
 Table 11:   Auto-Negotiation Capabilities  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
 Table 12:   MAC Control Pause Frame Format  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
 Table 13:   FC Pin Functions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
 Table 14:   FCCMD Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
 Table 15:   SRAM_TYPE Field Encoding  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
 Table 16:   LED Default Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
 Table 17:   IEEE 1149.1 Supported Instruction Summary  . . . . . . . . . . . . . . . . . . . . . 106
 Table 18:   BSR Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
 Table 19:   Device ID Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
 Table 20:    PCI Configuration Space Layout  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
 Table 21:   Address PROM Space Contents   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
 Table 22:   I/O Map In Word I/O Mode (DWIO = 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . 110
 Table 23:   Legal I/O Accesses in Word I/O Mode (DWIO = 0)   . . . . . . . . . . . . . . . . . 111
 Table 24:   I/O Map In DWord I/O Mode (DWIO = 1)  . . . . . . . . . . . . . . . . . . . . . . . . . 111
 Table 25:   Legal I/O Accesses in Double Word I/O Mode (DWIO =1) . . . . . . . . . . . . 111
 Table 26:   AP_VALUE0: Auto-Poll Value0 Register  . . . . . . . . . . . . . . . . . . . . . . . . . 124
 Table 27:   AP_VALUE1: Auto-Poll Value1 Register  . . . . . . . . . . . . . . . . . . . . . . . . . 125
 Table 28:   AP_VALUE2: Auto-Poll Value2 Register  . . . . . . . . . . . . . . . . . . . . . . . . . 125
 Table 29:   AP_VALUE3: Auto-Poll Value3 Register  . . . . . . . . . . . . . . . . . . . . . . . . . 125
 Table 30:   AP_VALUE4: Auto-Poll Value4 Register  . . . . . . . . . . . . . . . . . . . . . . . . . 125
 Table 31:   AP_VALUE5: Auto-Poll Value5 Register  . . . . . . . . . . . . . . . . . . . . . . . . . 125
 Table 32:   AUTOPOLL0: Auto-Poll0 Register    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
 Table 33:    AUTOPOLL1: Auto-Poll1 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
 Table 34:   AUTOPOLL2: Auto-Poll2 Register    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
 Table 35:   AUTOPOLL3: Auto-Poll3 Register    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
 Table 36:   AUTOPOLL4: Auto-Poll4 Register    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
 Table 37:    AUTOPOLL5: Auto-Poll5 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
 Table 38:   Receive Ring Base Address Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
 Table 39:   Transmit Ring Base Address Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
 Table 40:   CHIPID: Chip ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
 Table 41:   CHPOLLTIME: Chain Polling Interval Register   . . . . . . . . . . . . . . . . . . . . 131
 Table 42:   CMD0: Command0 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
 Table 43:   CMD2: Command2 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
 Table 44:   CMD3: Command3 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
 Table 45:   CMD7: Command7 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
 Table 46:   CTRL0: Control0 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
 Table 47:   CTRL1: Control1 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
 Table 48:   CTRL2: Control2 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

16 Am79C976 10/17/00
PRELIMINARY
 Table 49:   CTRL3: Control3 Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
 Table 50:   Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
 Table 51:   DATAMBIST: Memory Built-in Self-Test Access Register  . . . . . . . . . . . . 147
 Table 52:   Reserved Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
 Table 53:   EEPROM_ACC: EEPROM Access Register  . . . . . . . . . . . . . . . . . . . . . . 150
 Table 54:   Interface Pin Assignment  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
 Table 55:   FLASH_ADDR: Flash Address Register   . . . . . . . . . . . . . . . . . . . . . . . . . 152
 Table 56:   FLASH_DATA: Flash Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
 Table 57:    FLOW: Flow Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
 Table 58:   IFS1: Inter-Frame Spacing Part 1 Register   . . . . . . . . . . . . . . . . . . . . . . . 154
 Table 59:   INT0: Interrupt0 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
 Table 60:   INTEN0: Interrupt0 Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
 Table 61:   IPG: Inter-Packet Gap Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
 Table 62:   Logical Address Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
 Table 63:   LED0 Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
 Table 64:   MAX_LAT_A: PCI Maximum Latency Alias Register  . . . . . . . . . . . . . . . . 162
 Table 65:   MIN_GNT_A: PCI Minimum Grant Alias Register   . . . . . . . . . . . . . . . . . . 162
 Table 66:   PADR: Physical Address Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
 Table 67:   PAUSE_CNT: Pause Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
 Table 68:   PCIDATA0: PCI DATA Register Zero Alias Register  . . . . . . . . . . . . . . . . 163
 Table 69:   PHY_ACCESS: PHY Access Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
 Table 70:   PMAT0: OnNow Pattern Register 0  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
 Table 71:   PMAT1: OnNow Pattern Register 1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
 Table 72:   Receive Protect Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
 Table 73:   RCV_RING_LEN: Receive Ring Length Register   . . . . . . . . . . . . . . . . . . 167
 Table 74:   ROM_CFG: ROM Base Address Configuration Register  . . . . . . . . . . . . . 168
 Table 75:   SID_A: PCI Subsystem ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . 168
 Table 76:   SRAM Boundary Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
 Table 77:   SRAM Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
 Table 78:   STAT0: Status0 Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
 Table 79:   Software Timer Value Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
 Table 80:   SVID: PCI Subsystem Vendor ID Shadow Register . . . . . . . . . . . . . . . . . 172
 Table 81:   TEST0: Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
 Table 82:   VID_A: PCI Vendor ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
 Table 83:   XMT_RING_LEN: Transmit Ring Length Register  . . . . . . . . . . . . . . . . . . 173
 Table 84:   XMTPOLLTIME: Transmit Polling Interval Register  . . . . . . . . . . . . . . . . . 174
 Table 85:   Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
 Table 86:   Receive Watermark Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
 Table 87:   Transmit Start Point Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
 Table 88:   Transmit Watermark Programming   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
 Table 89:    BCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
 Table 90:   EEDET Setting  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
 Table 91:   Interface Pin Assignment  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
 Table 92:   Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
 Table 93:   SRAM_BND Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
 Table 94:   FMDC Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
 Table 95:   APDW Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
 Table 96:   Initialization Block (SSIZE32 = 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
 Table 97:   Initialization Block (SSIZE32 = 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

10/17/00 Am79C976 17
PRELIMINARY
 Table 98:   R/TLEN Decoding (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
 Table 99:   R/TLEN Decoding (SSIZE32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
 Table 100:   Receive Descriptor (SWSTYLE = 0)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
 Table 101:   Receive Descriptor (SWSTYLE = 2)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
 Table 102:   Receive Descriptor (SWSTYLE = 3)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
 Table 103:   Receive Descriptor (SWSTYLE = 4)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
 Table 104:   Receive Descriptor (SWSTYLE = 5)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
 Table 105:   Receive Descriptor, SWSTYLE = 0  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
 Table 106:   Receive Descriptor, SWSTYLE = 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
 Table 107:   Receive Descriptor, SWSTYLE = 3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
 Table 108:    Receive Descriptor, SWSTYLE = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
 Table 109:   Receive Descriptor, SWSTYLE = 5  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
 Table 110:   Transmit Descriptor (SWSTYLE = 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
 Table 111:   Transmit Descriptor (SWSTYLE = 2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
 Table 112:   Transmit Descriptor (SWSTYLE = 3)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
 Table 113:   Transmit Descriptor (SWSTYLE = 4)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
 Table 114:   Transmit Descriptor (SWSTYLE = 5)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
 Table 115:   Transmit Descriptor, SWSTYLE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
 Table 116:   Transmit Descriptor, SWSTYLE = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
 Table 117:   Transmit Descriptor, SWSTYLE = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
 Table 118:   Transmit Descriptor, SWSTYLE = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
 Table 119:   Transmit Descriptor, SWSTYLE = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
 Table 120:   Register Bit Cross Reference    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
 Table 121:   Control and Status Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
 Table 122:   Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

18 Am79C976 3/25/2009

P R E L I M i N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the elements below.

K C/D/I

Am79C976

DEVICE NUMBER/DESCRIPTION

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

D = Commercial Lead Free (0°C to +70°C)

I = Industrial (-40°C to +85°C)

PACKAGE TYPE

K = Plastic Quad Flat Pack (PQR208)

SPEED OPTION

Not Applicable

Am79C976

PCnet-PRO™ 10/100 Mbps PCI Ethernet Controller

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the local

AMD sales office to confirm availability of specific

valid combinations and to check on newly released

combinations.

Valid Combinations

Am79C976 KC/W

KD/W

KI/W

9/14/00 Am79C976 19

PRELIMINARY

CONNECTION DIAGRAM (PQR208)

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

171

170

169

168

167

166

165

164

163

162

161

172

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

127

126

125

124

123

122

121

120

119

118

117

128

100

ERD3/FLD3

ERD17

VDD

ERD18

ERD19

VSSB

TX_EN

TXD2

ERD0/FLD0

ERD1/FLD1

TXD1

TXD0

VSSB

CRS

VDD

ERD2/FLD2

VDD

ERD4/FLD4

ERD5/FLD5

ERD6/FLD6

VSS

ERD7/FLD7

VDD

ERD8/FLA20

ERD10/FLA22

ERD11/FLA23

VSSB

VDD

ERD13

ERD14

ERD15

ERD16

VSS

ERD12

ERD9/FLA21

VSSB

TXD3

COL

ERD20

VSSB

IRDY

VDD

TRDY

STOP

VSSB

PERR

VSS

SERR

PAR

VDD

C/BE1

AD15

AD14

AD30

AD29

VDD

AD28

AD27

AD26

VSSB

AD25

AD24

C/BE3

VDD

IDSEL

AD23

AD22

VSSB

AD21

AD20

AD19

VDD

AD18

AD17

AD16

VSSB

C/BE2

FRAME

DEVSEL

VSS

ERCE

VDD

EROE

VSSB

ERWE/FLWE

ERADV/FLOE

ERADSP/CEN

VSS

VSSB

ERA13/FLA13

ERA3/FLA3

ERA4/FLA4

VDD

ERA5/FLA5

ERA6/FLA6

ERA8/FLA8

ERA9/FLA9

VDD

VSS

VSSB

ERA11/FLA11

ERA12/FLA12

ERA14/FLA14

VDD

VSSB

ERA15/FLA15

VDD

ERA18/FLA18

ERA17/FLA17

VDD

FLCS

VSSB

ERA1/FLA1

ERA7/FLA7

ERA16/FLA16

ERD31

ERA0/FLA0

ERA10/FLA10

ERA2/FLA2

ERA19/FLA19

VDD

VSS

AVDD

VSSB

XTAL1

EAR

VDD

LED0/EEDI

LED2/RXFRTGE

XTAL2

LED3/EEDO/RXFRTGD

VSS

VSSB

CLKSEL0

TEST

VAUX_SENSE

PHY_RST

MDC

RXD3

VSSB

VDD

RXD0

EECS

PME

WUMI

RWU

TCK

TMS

TDO

VSSB

TDI

XCLK

CLKSEL1

MDIO

RXD2

RXD1

LED1/EESK

CLKSEL2

Am79C976

PCnet-PRO

INTA

RST

VDD

CLK

GNT

AD31

VSSB

REQ

VSSB

AD13

AD12

AD11

VDD

AD10

AD9

AD8

AD5

VDD

AD4

AD3

VSSB

AD2

AD1

AD0

116

115

114

113

112

111

110

109

VDD

ERD23

ERD24

ERD25

ERD22

ERD21

VSSB

ERCLK

VSSB

C/BE0

AD7

AD6

108

107

106

105

VSSB

ERD26

VDD

ERD27

101

102

103

104

ERD29

VSSB

ERD28

ERD30

160

159

158

157

RX_DV

RX_ER

TX_CLK

RX_CLK

208

207

206

205

204

203

202

201

22929B2

20 Am79C976 9/14/00

PRELIMINARY

PIN DESIGNATIONS (PQR208)

Listed By Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 AD30 53 AD5 105 ERD27 157 TX_CLK

2 AD29 54 VDD 106 VDD 158 RX_ER

3 VDD 55 AD4 107 ERD26 159 RX_CLK

4 AD28 56 AD3 108 VSSB 160 RX_DV

5 AD27 57 VSSB 109 ERCLK 161 RXD0

6 AD26 58 AD2 110 ERD25 162 VDD

7 VSSB 59 AD1 111 ERD24 163 RXD1

8 AD25 60 AD0 112 ERD23 164 VSSB

9 AD24 61 ERCE 113 VDD 165 RXD2

10 C/BE3 62 VDD 114 ERD22 166 RXD3

11 VDD 63 EROE 115 VSSB 167 MDC

12 IDSEL 64 VSSB 116 ERD21 168 MDIO

13 AD23 65 ERWE/FLWE 117 ERD20 169 PHY_RST

14 AD22 66 ERADV/FLOE 118 ERD19 170 VAUX_SENSE

15 VSSB 67 ERADSP/CEN 119 ERD18 171 TEST

16 AD21 68 VSS 120 VDD 172 CLKSEL0

17 VSS 69 FLCS 121 ERD17 173 CLKSEL1

18 AD20 70 VDD 122 VSSB 174 VSSB

19 AD19 71 ERA0/FLA0 123 VSS 175 CLKSEL2

20 VDD 72 VSSB 124 ERD16 176 VSS

21 AD18 73 ERA1/FLA1 125 ERD15 177 XTAL2

22 AD17 74 ERA2/FLA2 126 ERD14 178 XTAL1

23 AD16 75 ERA3/FLA3 127 ERD13 179 AVDD

24 VSSB 76 ERA4/FLA4 128 VDD 180 XCLK

25 C/BE2 77 VDD 129 ERD12 181 VDD

26 FRAME 78 ERA5/FLA5 130 VSSB 182 LED3/EEDO/

RXFRTGD

27 IRDY 79 VSSB 131 ERD11/FLA23 183 LED2/RXFRTGE

28 VDD 80 ERA6/FLA6 132 ERD10/FLA22 184 LED1/EESK

29 TRDY 81 ERA7/FLA7 133 ERD9/FLA21 185 LED0/EEDI

30 DEVSEL 82 ERA8/FLA8 134 ERD8/FLA20 186 EECS

31 STOP 83 ERA9/FLA9 135 VDD 187 EAR

32 VSSB 84 VDD 136 ERD7/FLD7 188 VSSB

33 PERR 85 ERA10/FLA10 137 VSSB 189 VSS

34 VSS 86 VSS 138 VSS 190 FC

9/14/00 Am79C976 21

PRELIMINARY

35 SERR 87 VSSB 139 ERD6/FLD6 191 VDD

36 PAR 88 ERA11/FLA11 140 ERD5/FLD5 192 PME

37 VDD 89 ERA12/FLA12 141 ERD4/FLD4 193 WUMI

38 C/BE1 90 ERA13/FLA13 142 ERD3/FLD3 194 RWU

39 AD15 91 ERA14/FLA14 143 VDD 195 TCK

40 AD14 92 VDD 144 ERD2/FLD2 196 TMS

41 VSSB 93 ERA15/FLA15 145 VSSB 197 TDO

42 AD13 94 VSSB 146 ERD1/FLD1 198 TDI

43 AD12 95 ERA16/FLA16 147 ERD0/FLD0 199 VSSB

44 AD11 96 ERA17/FLA17 148 CRS 200 PG

45 VDD 97 ERA18/FLA18 149 COL 201 INTA

46 AD10 98 ERA19/FLA19 150 VDD 202 RST

47 AD9 99 VDD 151 TXD3 203 VDD

48 AD8 100 ERD31 152 TXD2 204 CLK

49 VSSB 101 VSSB 153 VSSB 205 GNT

50 C/BE0 102 ERD30 154 TXD1 206 REQ

51 AD7 103 ERD29 155 TXD0 207 VSSB

52 AD6 104 ERD28 156 TX_EN 208 AD31

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

22 Am79C976 9/14/00

PRELIMINARY

PIN DESIGNATIONS

Listed By Group

Pin Name Pin Function Signal Type1Pin Type1No. of Pins

Clock Interface

XTAL1 Crystal I I 1

XTAL2 Crystal O O 1

XCLK External Clock I I 1

CLKSEL0 Clock Select I I 1

CLKSEL1 Clock Select I I 1

CLKSEL2 Clock Select I I 1

TEST Test Select I I 1

PCI Bus Interface

AD[31:0] Address/Data Bus IO IO 32

C/BE[3:0] Bus Command/Byte Enable IO IO 4

CLK Bus Clock I I 1

DEVSEL Device Select IO IO 1

FRAME Cycle Frame IO IO 1

GNT Bus Grant I I 1

IDSEL Initialization Device Select I I 1

INTA Interrupt O TSO 1

IRDY Initiator Ready IO IO 1

PAR Parity IO IO 1

PERR Parity Error IO IO 1

REQ Bus Request O TSO 1

RST Reset I I 1

SERR System Error IO IO 1

STOP Stop IO IO 1

TRDY Target Ready IO IO 1

Board Interface

LED0 LED0 O TSO 1

LED1 LED1 O TSO 1

LED2 LED2 O IO 1

LED3 LED3 O IO 1

PHY_RST Reset to PHY O O 1

FC Flow Control I I 1

EEPROM Interface

9/14/00 Am79C976 23

PRELIMINARY

EECS Serial EEPROM Chip Select O O 1

EEDI Serial EEPROM Data In O TSO 1

EEDO Serial EEPROM Data Out I IO 1

EESK Serial EEPROM Clock IO TSO 1

External Memory Interface

ERCLK External Memory Clock O O 1

ERA[19:0]/FLA[19:0] External Memory Address[19:0] O O 20

ERD[31:0] / FLA[23:20] / FLD[7:0] External Memory Data [31:0]/Flash

Address[23:20]/Flash Data[7:0] IO IO 32

ERADV/FLOE External Memory Advance O O 1

ERADSP/CEN External Memory Address Strobe O O 1

EROE External Memory Output Enable O O 1

ERWE/FLWE External Memory Write Enable O O 1

ERCE SSRAM Chip Enable O O 1

FLCS Flash Memory Chip Select O O 1

Media Independent Interface (MII)

COL Collision I I 1

CRS Carrier Sense I I 1

FC Hardware Flow Control I I 1

MDC Management Data Clock O O 1

MDIO Management Data I/O IO IO 1

RX_CLK Receive Clock I I 1

RXD[3:0] Receive Data I I 4

RX_DV Receive Data Valid I I 1

RX_ER Receive Error I I 1

TX_CLK Transmit Clock I I 1

TXD[3:0] Transmit Data O O 4

TX_EN Transmit Data Enable O O 1

External Address Detection Interface (EADI)

EAR External Address Reject I I 1

SFBD Start Frame Byte Delimiter Note 2 Note 2 1

RXFRTGD Receive Frame Tag Data I IO 1

RXFRTGE Receive Frame Tag Enable I IO 1

Power Management Interface

RWU Remote Wake Up O TSO 1

PME Power Management Event O OD 1

WUMI Wake-Up Mode Indicator O OD 1

PG Power Good I I 1

Pin Name Pin Function Signal Type1Pin Type1No. of Pins

24 Am79C976 9/14/00

PRELIMINARY

Notes:

1. Since some pins provide more than one signal, the pin type for a signal may differ from the signal type.

2. The SFBD signal can be programmed to appear on any of the LED pins.

Table Legend:

VAUX_SENSE Vaux Sense I I 1

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock I I 1

TDI Test Data In I I 1

TDO Test Data Out O O 1

TMS Test Mode Select I I 1

Power Supplies

VDD Digital and I/O Buffer Power P P 24

VSS Digital Ground P P 8

AVDD Analog VDD for PLL and OSC P P 1

VSSB I/O Buffer Ground P P 25

Pin Name Pin Function Signal Type1Pin Type1No. of Pins

Name Pin Type

IO Input/Output

I Input

O Output

TSO Three-State Output

OD Open Drain

9/14/00 Am79C976 25

PRELIMINARY

PIN DESCRIPTIONS

PCI Interface

AD[31:0]

Address and Data Input/Output

Address and data are multiplexed on the same bus in-

terface pins. During the first clock of a transaction,

AD[31:0] contain a physical address (32 bits). During

the subsequent clocks, AD[31:0] contain data. Byte or-

dering is Little Endian by default. AD[7:0] are defined

as the least significant byte (LSB) and AD[31:24] are

defined as the most significant byte (MSB). For FIFO

data transfers, the Am79C976 controller can be pro-

grammed for Big Endian byte ordering. See Control 0

During the address phase of the transaction, when the

Am79C976 controller is a bus master, AD[31:2] will

address the active Double Word (DWord). The

Am79C976 controller always drives AD[1:0] to “00”

during the address phase indicating linear burst order.

When the Am79C976 controller is not a bus master, the

AD[31:0] lines are continuously monitored to determine

if an address match exists for slave transfers.

During the data phase of the transaction, AD[31:0] are

driven by the Am79C976 controller when performing

bus master write and slave read operations. Data on

AD[31:0] is latched by the Am79C976 controller when

performing bus master read and slave write operations.

The Am79C976 device supports Dual Address Cycles

(DAC) for systems with 64-bit addressing. As a bus

master the Am79C976 device will generate addresses

of up to 40 bits in length. If the value of the C/BE[3:0]

bus during the PCI address phase is 1101b, the ad-

dress phase is extended to two clock cycles. The low

order address bits appear on the AD[31:0] bus during

the first clock cycle, and the high order bits appear dur-

ing the second clock cycle. In dual address cycles the

PCI bus command (memory read, I/O write, etc.) ap-

pears on the C/BE pins during the second clock cycle.

C/BE[3:0]

Bus Command and Byte Enables Input/Output

Bus command and byte enables are multiplexed on the

same bus interface pins. During the address phase of

the transaction, C/BE[3:0] define the bus command.

During the data phase, C/BE[3:0] are used as byte en-

ables. The byte enables define which physical byte

lanes carry meaningful data. C/BE0 applies to byte 0

(AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The

function of the byte enables is independent of the byte

ordering mode (BSWP, CSR3, bit 2).

CLK

Clock Input

This clock is used to drive the system bus interface. All

bus signals are sampled on the rising edge of CLK and

all parameters are defined with respect to this edge.

The Am79C976 controller normally operates over a fre-

quency range of 15 MHz to 33 MHz on the PCI bus due

to networking demands. The Am79C976 controller will

support a clock frequency of 0 MHz after certain pre-

cautions are taken to ensure data integrity. This clock

or a derivation is not used to drive any network func-

tions.

DEVSEL

Device Select Input/Output

The Am79C976 controller drives DEVSEL when it de-

tects a transaction that selects the device as a target.

The device samples DEVSEL to detect if a target

claims a transaction that the Am79C976 controller has

initiated.

FRAME

Cycle Frame Input/Output

FRAME is driven by the Am79C976 controller when it

is the bus master to indicate the beginning and duration

of a transaction. FRAME is asserted to indicate a bus

transaction is beginning. FRAME is asserted while data

transfers continue. FRAME is deasserted before the

final data phase of a transaction. When the Am79C976

controller is in slave mode, it samples FRAME to deter-

mine the address phase of a transaction.

GNT

Bus Grant Input

This signal indicates that the access to the bus has

been granted to the Am79C976 controller.

The Am79C976 controller supports bus parking. When

the PCI bus is idle and the system arbiter asserts GNT

without an active REQ from the Am79C976 controller,

the device will drive the AD[31:0], C/BE[3:0], and PAR

lines.

IDSEL

Initialization Device Select Input

This signal is used as a chip select for the Am79C976

controller during configuration read and write transac-

tions.

INTA

Interrupt Request Output

An attention signal which indicates that one or more

enabled interrupt flag bits are set. See the descriptions

of the INT and INTEN registers for details.

26 Am79C976 9/14/00

PRELIMINARY

By default INTA is an open-drain output. For applica-

tions that need an active-high edge-sensitive interrupt

signal, the INTA pin can be configured for this mode by

setting INTLEVEL (CMD3, bit 13 or BCR2, bit 7) to 1.

IRDY

Initiator Ready Input/Output

IRDY indicates the ability of the initiator of the transac-

tion to complete the current data phase. IRDY is used

in conjunction with TRDY

. Wait states are inserted until

both IRDY and TRDY are asserted simultaneously. A

data phase is completed on any clock when both IRDY

and TRDY are asserted.

When the Am79C976 controller is a bus master, it as-

serts IRDY during all write data phases to indicate that

valid data is present on AD[31:0]. During all read data

phases, the device asserts IRDY to indicate that it is

ready to accept the data.

When the Am79C976 controller is the target of a trans-

action, it checks IRDY during all write data phases to

determine if valid data is present on AD[31:0]. During

all read data phases, the device checks IRDY to deter-

mine if the initiator is ready to accept the data.

PAR

Parity Input/Output

Parity is even parity across AD[31:0] and C/BE[3:0].

When the Am79C976 controller is a bus master, it gen-

erates parity during the address and write data phases.

It checks parity during read data phases. When the

Am79C976 controller operates in slave mode, it checks

parity during every address phase. When it is the target

of a cycle, it checks parity during write data phases and

it generates parity during read data phases.

PERR

Parity Error Input/Output

During any slave write transaction and any master read

transaction, the Am79C976 controller asserts PERR

when it detects a data parity error and reporting of the

error is enabled by setting PERREN (PCI Command

the Am79C976 controller monitors PERR to see if the

target reports a data parity error.

REQ

Bus Request Input/Output

The Am79C976 controller asserts REQ pin as a signal

that it wishes to become a bus master. REQ is driven

high when the Am79C976 controller does not request

the bus.

RST

Reset Input

When RST is asserted LOW and the PG pin is HIGH,

then the Am79C976 controller performs an internal

system reset of the type H_RESET

(HARDWARE_RESET, see section on RESET). Imme-

diately after the initial power up, RST must be held low

for 26µs. At any other time RST must be held low for a

minimum of 30 clock periods to guarantee that the de-

vice is properly reset. While in the H_RESET state, the

Am79C976 controller will disable or deassert all out-

puts. RST may be asynchronous to clock when as-

serted or deasserted.

Asserting RST disables all of the PCI pins except the

PME pin.

SERR

System Error Output

During any slave transaction, the Am79C976 controller

asserts SERR when it detects an address parity error,

and reporting of the error is enabled by setting PER-

REN (PCI Command register, bit 6) and SERREN (PCI

Command register, bit 8) to 1.

By default SERR is an open-drain output. For compo-

nent test, it can be programmed to be an active-high

totem-pole output.

STOP

Stop Input/Output

In slave mode, the Am79C976 controller drives the

STOP signal to inform the bus master to stop the cur-

rent transaction. In bus master mode, the Am79C976

controller checks STOP to determine if the target wants

to disconnect the current transaction.

TRDY

Target Ready Input/Output

TRDY indicates the ability of the target of the transac-

tion to complete the current data phase. Wait states are

inserted until both IRDY and TRDY are asserted simul-

taneously. A data phase is completed on any clock

when both IRDY and TRDY are asserted.

When the Am79C976 controller is a bus master, it

checks TRDY during all read data phases to determine

if valid data is present on AD[31:0]. During all write data

phases, the device checks TRDY to determine if the

target is ready to accept the data.

When the Am79C976 controller is the target of a trans-

action, it asserts TRDY during all read data phases to

indicate that valid data is present on AD[31:0]. During

all write data phases, the device asserts TRDY to indi-

cate that it is ready to accept the data.

9/14/00 Am79C976 27

PRELIMINARY

PME

Power Management Event Output, Open Drain

PME is an output that can be used to indicate that a

power management event (a Magic Packet, an OnNow

pattern match, or a change in link state) has been de-

tected. The PME pin is asserted when either:

1. PME_STATUS and PME_EN are both 1,

2. PME_EN_OVR and MPMAT are both 1, or

3. PME_EN_OVR and LCDET are both 1.

The PME signal is asynchronous with respect to the

PCI clock.

Board Interface

Note: Before programming the LED pins, see the de-

scription of LEDPE in BCR2, bit 12.

LED0

LED0 Output

This output is designed to directly drive an LED. By de-

fault, LED0 indicates an active link connection. This pin

can also be programmed to indicate other network sta-

tus (see BCR4). The LED0 pin polarity is programma-

ble, but by default it is active LOW. When the LED0 pin

polarity is programmed to active LOW, the output is an

open drain driver. When the LED0 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

Note: The LED0 pin is multiplexed with the EEDI pin.

LED1

LED1 Output

This output is designed to directly drive an LED. By de-

fault, LED1 indicates receive or transmit activity on the

network. This pin can also be programmed to indicate

other network status (see BCR5). The LED1 pin polar-

ity is programmable, but by default, it is active LOW.

When the LED1 pin polarity is programmed to active

LOW, the output is an open drain driver. When the

LED1 pin polarity is programmed to active HIGH, the

output is a totem pole driver.

Note: The LED1 pin is multiplexed with the EESK pin.

LED2

L E D 2 O ut pu t

This output is designed to directly drive an LED. By de-

fault, LED2 indicates that the network bit rate is 100

Mb/s. This pin can also be programmed to indicate var-

ious network status (see BCR6). The LED2 pin polarity

is programmable, but by default it is active LOW. When

the LED2 pin polarity is programmed to active LOW,

the

output is an open drain driver. When the LED2 pin po-

larity is programmed to active HIGH, the output is a

totem pole driver.

Note: The LED2 pin is multiplexed with the RXFRTGE

pin.

LED3

LED3 Output

This output is designed to directly drive an LED. By de-

fault, LED3 indicates that a collision has occurred. This

pin can also be programmed to indicate other network

status (see BCR7). The LED3 pin polarity is program-

mable, but by default it is active LOW. When the LED3

pin polarity is programmed to active LOW, the output is

an open drain driver. When the LED3 pin polarity is pro-

grammed to active HIGH, the output is a totem pole

driver.

Special attention must be given to the external circuitry

attached to this pin. When this pin is used to drive an

LED while an EEPROM is used in the system, then

buffering may be required between the LED3 pin and

the LED circuit. If an LED circuit were directly attached

to this pin, it may create an IOL requirement that could

not be met by the serial EEPROM attached to this pin.

If no EEPROM is included in the system design or low

current LEDs are used, then the LED3 signal may be

directly connected to an LED without buffering. In any

case, if an EEPROM is present, there must be a pull-

up resistor connected to this pin (10 kΩ should be ad-

equate). For more details regarding LED connection,

see the section on LED Support.

Note: The LED3 pin is multiplexed with the EEDO and

RXFRTGD pins.

Power Good Input

The PG pin has two functions: (1) it puts the device into

Magic Packet mode, and (2) it blocks any resets when

the PCI bus power is off.

When PG is LOW and either MPPEN or MPMODE is

set to 1, the device enters the Magic Packet mode.

When PG is LOW, a LOW assertion of the PCI RST pin

will only cause the PCI interface pins (except for PME)

to be put in the high impedance state. The internal logic

will ignore the assertion of RST.

When PG is HIGH, assertion of the PCI RST pin

causes the controller logic to be reset and the configu-

ration information to be loaded from the EEPROM.

RWU

Remote Wake Up Output

RWU is an output that is asserted either when the con-

troller is in the Magic Packet mode and a Magic Packet

frame has been detected, or the controller is in the Link

28 Am79C976 9/14/00

PRELIMINARY

Change Detect mode and a Link Change has been de-

tected.

This pin can drive the external system management

logic that causes the CPU to get out of a low power

mode of operation. This pin is implemented for designs

that do not support the PME function.

Three bits that are loaded from the EEPROM into

CSR116 can program the characteristics of this pin:

1. RWU_POL determines the polarity of the RWU sig-

nal.

2. If RWU_GATE bit is set, RWU is forced to the high

impedance state when PG input is LOW.

3. RWU_DRIVER determines whether the output is

open drain or totem pole.

The internal power-on-reset signal forces this output

into the high impedance state until after the polarity and

drive type have been determined.

WUMI

Wa k e- U p M od e I ndic ator Out p u t ,

Open Drain

This output, which is capable of driving an LED, is as-

serted when the device is in Magic Packet mode. It can

be used to drive external logic that switches the device

power source from the main power supply to an auxil-

iary power supply.

VAUX_SENSE

3.3 Vaux Presence Sense Input

The signal on this pin is logically anded with bit 15 of

the PCI PMC register when the PMC register is read.

This pin should normally be connected to the PCI

3.3 Vaux pin. This allows the PMC register to indicate

that the device is capable of supporting PME from the

D3cold state only when the 3.3 Vaux pin is supplying

power.

CLKSEL0

Clock Select 0 Input

The Am79C976 system clock can either be driven by

an external clock generator connected to the XCLK pin

or by an internal clock generator timed by a 25-MHz

crystal connected between the XTAL1 and XTAL2 pins.

The CLKSEL0 and CLKSEL1 pins select the source of

the system clock and the frequency at which the exter-

nal clock generator must run. In addition, CLKSEL0

and CLKSEL1 determine the frequency of ERCLK, the

external SSRAM clock. Table 1 shows the possible

combinations.

CLKSEL1

Clock Select 1 Input

The Am79C976 system clock can either be driven by

an external clock generator connected to the XCLK pin

or by an internal clock generator timed by a 25-MHz

crystal connected between the XTAL1 and XTAL2 pins.

The CLKSEL0 and CLKSEL1 pins select the source of

the system clock and the frequency at which the exter-

nal clock generator must run. In addition CLKSEL0 and

CLKSEL1 determine the frequency of ERCLK, the ex-

ternal SSRAM clock. Table 1 shows the possible com-

binations.

CLKSEL2

Clock Se lect 2 I nput

The CLKSEL2 pin must be held low during normal op-

eration.

TEST

Test Reset Input

The TEST pin must be held low during normal opera-

tion.

XCLK

External Clock Input Input

The Am79C976 system clock can either be driven by

an external clock generator connected to this pin or by

a 25-MHz crystal connected between the XTAL1 and

XTAL2 pins, depending on the state of the CLKSEL0

and CLKSEL1 pins. When either CLKSEL0 or

CLKSEL1 or both are held high, a 20-, 25-, or

331/3-MHz clock signal must be applied to XCLK as

shown in Table 1. When CLKSEL0 and CLKSEL1 are

both held low, the XCLK pin should be connected to ei-

ther VSS or VDD.

Table 1. System Clock Selections

XTAL1

Cry stal I npu t

If the CLKSEL0 and CLKSEL1 pins are both held low,

a 25-MHz crystal should be connected between the

XTAL1 pin and the XTAL2 pin. This crystal controls the

frequency of the internal clock-generator circuit.

CLKSEL2 CLKSEL1 CLKSEL0

CLOCK

SOURCE

ERCLK

(MHz)

1XX

Design Factory

Test O nly.

000

25-MHz

Crystal,

XTAL1,XT

AL2

87.5

001

XCLK, 20

MHz 90

010

XCLK, 25

MHz 87.5

011

XCLK,

331/3 MHz 82.5

9/14/00 Am79C976 29

PRELIMINARY

If the CLKSEL0 and CLKSEL1 pins are not both held

low, a 20-, 25-, or 331/3-MHz clock source must be con-

nected to the XCLK pin, and the XTAL1 and XTAL2

pins should be connected to VSS.

XTAL1 and XTAL2 are not 5-volt tolerant pins.

XTAL2

Crystal Output

If the CLKSEL0 and CLKSEL1 pins are both held low,

a 25 MHz crystal should be connected between the

XTAL1 pin and the XTAL2 pin. This crystal controls the

frequency of the internal clock generator circuit.

If either the CLKSEL0 or the CLKSEL1 pin or both are

held high, a 20-, 25-, or 331/3-MHz clock source must be

connected to the XCLK pin, and the XTAL1 and XTAL2

pins should be connected to VSS.

XTAL1 and XTAL2 are not 5-volt tolerant pins.

PHY_RST

PHY Reset Output

PHY_RST is an output pin that is used to reset the ex-

ternal PHY. This output eliminates the need for a

fan-out buffer for the PCI RST signal, provides polarity

for the specific PHY used, and prevents the resetting of

the PHY when the PG input is LOW. The output polarity

is determined by the RST_POL bit (CMD3, bit0), which

can be loaded from the EEPROM.

The length of time for which the PHY_RST pin is as-

serted depends on the number of registers that are

loaded from the EEPROM and the order in which the

registers are loaded. Immediately after the RST_POL

bit is loaded from the EEPROM, the PHY_RST pin is

asserted. When the last register has been loaded from

the EEPROM, the PHY_RST pin is deasserted. Each

about 240 µs to the time that PHY_RST is asserted. If

the PHY_RST pin is used to reset an external PHY, the

user should program the EEPROM to make sure that

PHY_RST is asserted long enough to meet the require-

ments of the PHY. The user can insert dummy writes to

offset 28h to extend the reset period.

Flow Control Input

The Flow Control input signal controls when MAC Con-

trol Pause Frames are sent or when half-duplex back

pressure is asserted.

EEPROM Interface

EECS

EE P R OM C h i p S e l ect Outp u t

This pin is designed to directly interface to a serial EE-

PROM that uses the 93Cxx EEPROM interface proto-

col. EECS is connected to the EEPROM’s chip select

pin. It is controlled by either the Am79C976 controller

during command portions of a read of the entire EE-

PROM, or indirectly by the host system by writing to

BCR19, bit 2.

EEDI

EE P R OM D a t a In O utp u t

This pin is designed to directly interface to a serial EE-

PROM that uses the 93Cxx EEPROM interface proto-

col. EEDI is connected to the EEPROM’s data input

pin. It is controlled by either the Am79C976 controller

during command portions of a read of the entire EE-

PROM, or indirectly by the host system by writing to

BCR19, bit 0.

Note: The EEDI pin is multiplexed with the LED0 pin.

EEDO

EEP ROM Data Ou t I npu t

This pin is designed to directly interface to a serial EE-

PROM that uses the 93Cxx EEPROM interface proto-

col. EEDO is connected to the EEPROM’s data output

pin. It is controlled by either the Am79C976 controller

during command portions of a read of the entire EE-

PROM, or indirectly by the host system by reading from

BCR19, bit 0.

Note: The EEDO pin is multiplexed with the LED3 and

RXFRTGD pins.

EESK

EE P R OM S e r ia l C lock O u tp u t

This pin is designed to directly interface to a serial EE-

PROM that uses the 93Cxx EEPROM interface proto-

col. EESK is connected to the EEPROM’s clock pin. It

is controlled by either the Am79C976 controller directly

during a read of the entire EEPROM, or indirectly by

the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplexed with the LED1 pin.

External Memory Interface

ERA[19:0]/FLA[19:0]

Ex te rn al M em or y Ad dr es s [1 9: 0 ] O u tp ut

The ERA[19:0] pins provide addresses for both the ex-

ternal SSRAM and the external boot ROM device.

All ERA[19:0] pin outputs are forced to a constant level

to conserve power while no access on the External

Memory Bus is being performed.

FLA[23:20]

B o o t RO M (F la sh) A dd r es s [2 3: 20 ] O u tp ut

The FLA[23:20] pins provide the 4 most significant bits

of the address for the external boot ROM device.

30 Am79C976 9/14/00

PRELIMINARY

All FLA[23:20] pin outputs are forced to a constant level

to conserve power while no access on the External

Memory Bus is being performed.

Note: The FLA[23:20] pins are multiplexed with the

ERD[11:8] pins.

ERD[31:0]/FLD[7:0]

External Memory Data [31:0] Input/Output

The ERD[7:0] pins provide data bits [7:0] for boot ROM

accesses. The ERD[31:0] pins provide data bits [31:0]

for external SSRAM accesses. The ERD[31:0] signals

are forced to a constant level to conserve power while

no access on the External Memory Bus is being per-

formed.

Note: The FLA[23:20] pins are multiplexed with the

ERD[11:8] pins.

ERCE

Extern al SS RAM Chip En able Output

ERCE serves as the chip enable for the external SS-

RAM. It is asserted low when the SSRAM address on

the ERA[19:0] pins is valid.

FLCS

Boo t ROM Ch ip Select Output

FLCS serves as the chip select for the boot device. It is

asserted low when the boot ROM address on the

FLA[23:20] and ERA[19:0] pins is valid.

EROE

External SSRAM Output Enable Output

EROE is asserted active LOW during SSRAM device

read operations to allow the SSRAM device to drive the

ERD[31:0] data bus. It is deasserted at all other times.

FLOE

Expansion ROM Output Enable Output

FLOE is asserted active LOW during boot ROM read

operations to allow the boot ROM to drive the ERD[7:0]

data bus. It is deasserted at all other times.

Note: The FLOE pin is multiplexed with the ERADV

pin.

ERWE/FLWE

External Memory Write Enable Output

ERWE provides the write enable for write accesses to

the external SSRAM and the Flash (boot ROM) device.

ERADSP/CEN

Extern al Memor y Add re ss Strob e Ou tpu t

ERADSP provides the address strobe signal to load

the address into the external SSRAM.

ERADV

External Memory Address Advance Output

ERADV provides the address advance signal to the ex-

ternal SSRAM. This signal is asserted low during a

burst access to increment the address counter in the

SSRAM.

Note: The FLOE pin is multiplexed with the ERADV

pin.

ERCLK

Ex te rn al M em or y Cl oc k O u tp ut

ERCLK is the reference clock for all synchronous

SRAM accesses.

Media Independent Interface

TX_CLK

Transmit Cloc k Inp ut

TX_CLK is a continuous clock input that provides the

timing reference for the transfer of the TX_EN and

TXD[3:0] signals out of the Am79C976 device.

TX_CLK must provide a nibble rate clock (25% of the

network data rate). Hence, an MII transceiver operating

at 10 Mbps must provide a TX_CLK frequency of 2.5

MHz and an MII transceiver operating at 100 Mbps

must provide a TX_CLK frequency of 25 MHz.

TXD[3:0]

Tr ansm i t D a t a O u tp u t

TXD[3:0] is the nibble-wide MII transmit data bus. Valid

data is generated on TXD[3:0] on every TX_CLK rising

edge while TX_EN is asserted. While TX_EN is deas-

serted, TXD[3:0] values are driven to a 0. TXD[3:0]

transitions synchronous to TX_CLK rising edges.

TX_EN

Transmit Enable Output

TX_EN indicates when the Am79C976 device is pre-

senting valid transmit nibbles on the MII. While TX_EN

is asserted, the Am79C976 device generates TXD[3:0]

on TX_CLK rising edges. TX_EN is asserted with the

first nibble of preamble and remains asserted through-

out the duration of a packet until it is deasserted prior

to the first TX_CLK following the final nibble of the

frame. TX_EN transitions synchronous to TX_CLK ris-

ing edges.

COL

Collision Input

COL is an input that indicates that a collision has been

detected on the network medium.

9/14/00 Am79C976 31

PRELIMINARY

CRS

Carrier Sense Input

CRS is an input that indicates that a non-idle medium,

due either to transmit or receive activity, has been de-

tected.

RX_CLK

Receive Clock Input

RX_CLK is a clock input that provides the timing refer-

ence for the transfer of the RX_DV, RXD[3:0], and

RX_ER signals into the Am79C976 device. RX_CLK

must provide a nibble rate clock (25% of the network

data rate). Hence, an MII transceiver operating at 10

Mbps must provide an RX_CLK frequency of 2.5 MHz

and an MII transceiver operating at 100 Mbps must

provide an RX_CLK frequency of 25 MHz. When the

external PHY switches the RX_CLK and TX_CLK, it

must provide glitch-free clock pulses.

RXD[3:0]

Receive Data Input

RXD[3:0] is the nibble-wide MII receive data bus. Data

on RXD[3:0] is sampled on every rising edge of

RX_CLK while RX_DV is asserted. RXD[3:0] is ignored

while RX_DV is de-asserted.

RX_DV

Receive Data Valid Input

RX_DV is an input used to indicate that valid, received

data is being presented on the RXD[3:0] pins and

RX_CLK is synchronous to the receive data. In order

for a frame to be fully received by the Am79C976 de-

vice on the MII, RX_DV must be asserted prior to the

RX_CLK rising edge, when the first nibble of the Start-

of-Frame Delimiter is driven on RXD[3:0], and must re-

main asserted until after the rising edge of RX_CLK,

when the last nibble of the CRC is driven on RXD[3:0].

RX_DV must then be deasserted prior to the RX_CLK

rising edge which follows this final nibble. RX_DV tran-

sitions are synchronous to RX_CLK rising edges.

RX_ER

Receive Error Input

RX_ER is an input that indicates that the MII trans-

ceiver device has detected a coding error in the receive

frame currently being transferred on the RXD[3:0] pins.

When RX_ER is asserted while RX_DV is asserted, a

CRC error will be indicated in the receive descriptor for

the incoming receive frame. RX_ER is ignored while

RX_DV is deasserted. Special code groups generated

on RXD while RX_DV is deasserted are ignored (e.g.,

Bad SSD in TX and IDLE in T4). RX_ER transitions are

synchronous to RX_CLK rising edges.

MDC

Ma n a g eme n t Da ta C loc k O u tp u t

MDC is a non-continuous clock output that provides a

timing reference for bits on the MDIO pin. During MII

management port operations, MDC runs at a nominal

frequency of 2.5 MHz. When no management opera-

tions are in progress, MDC is driven LOW.

If the MII Management port is not used, the MDC pin

can be left floating.

MDIO

Management Data I/O Input/Output

MDIO is the bidirectional MII management port data

pin. MDIO is an output during the header portion of the

management frame transfers and during the data por-

tions of write transfers. MDIO is an input during the

data portions of read data transfers. When an opera-

tion is not in progress on the management port, MDIO

is not driven. MDIO transitions from the Am79C976

controller are synchronous to MDC falling edges.

If the PHY is attached through an MII physical connec-

tor, then the MDIO pin should be externally pulled down

to VSS with a 10-kΩ ±5% resistor. If the PHY is perma-

nently connected, then the MDIO pin should be exter-

nally pulled up to VCC with a 10-kΩ ±5% resistor.

External Address Detection Interface

EAR

Extern al Ad dress Re ject I npu t

The incoming frame will be checked against the inter-

nally active address detection mechanisms and the re-

sult of this check will be OR’d with the value on the EAR

pin. The EAR pin acts as an external address accept

function. The pin value is OR’d with the internal ad-

dress detection result to determine if the current frame

should be accepted. If EAR remains high while a frame

is being received, the frame will be accepted regard-

less of the state of the internal address matching logic.

The EAR pin must not be left unconnected. If it is not

used, it should be tied to VSS through a 10-kΩ ±5% re-

sistor.

SFBD

St a r t Fr a me -B y t e D e l i mit e r O utp u t

An initial rising edge on the SFBD signal indicates that

a start of valid data is present on the RXD[3:0] pins.

SFBD will go high for one nibble time (400 ns when op-

erating at 10 Mbps and 40 ns when operating at 100

Mbps) one RX_CLK period after RX_DV has been as-

serted and RX_ER is deasserted, and there is the de-

tection of the SFD (Start of Frame Delimiter) of a

received frame.

32 Am79C976 9/14/00

PRELIMINARY

Data on the RXD[3:0] will be the start of the destination

address field. SFBD will subsequently toggle every nib-

ble time (1.25 MHz frequency when operating at 10

Mbps and 12.5 MHz frequency when operating at 100

Mbps), indicating the first nibble of each subsequent

byte of the received nibble stream. The RX_CLK

should be used in conjunction with the SFBD to latch

the correct data for external address matching. SFBD

will be active only during frame reception.

Note: The SFBD signal can be programmed to appear

on any of the LED pins.

RXFRTGD

Receive Frame Tag Data Input

When the Receive Frame Tagging is enabled (RXFRT-

GEN, CMD3, bit 10), the RXFRTGD pin becomes a

data input pin for the Receive Frame Tag. See the Re-

ceive Frame Tagging section for details.

Note: The RXFRTGD pin is multiplexed with the LED3

and EEDO pins.

RXFRTGE

Receive Frame Tag Enable Input

When the Receive Frame Tagging is enabled (RXFRT-

GEN, CMD3, bit 10), the RXFRTGE pin becomes a

data input enable pin for the Receive Frame Tag. See

the Receive Frame Tagging section for details.

Note: The RXFRTGE pin is multiplexed with the LED2

pin.

IEEE 1149.1 (1990) Test Access Port

Interface

TCK

Test Clock Input

TCK is the clock input for the boundary scan test mode

operation. It can operate at a frequency of up to 10

MHz. TCK has an internal pull-up resistor.

TDI

Test Data In Input

TDI is the test data input path to the Am79C976 con-

troller. The pin has an internal pull-up resistor.

TDO

Test Data Out Output

TDO is the test data output path from the Am79C976

controller. The pin is tri-stated when the JTAG port is in-

active.

TMS

Test Mode Select Input

A serial input bit stream on the TMS pin is used to

define the specific boundary scan test to be executed.

The pin has an internal pull-up resistor.

Power Supply Pins

AVDD

Analog Power (1 Pin) Power

This power supply pin is used for the internal oscillator

and phase-locked loop circuits. This pin must be

connected to a +3.3-V supply.

VSSB

I/O Buffer Ground (25 Pins) Power

There are 25 ground pins that are used by the input/

output buffer drivers.

VDD

Digital and I/O Buffer Power (24 Pins)

Power

There are 24 power supply pins that are used by the in-

ternal digital circuitry and I/O buffers. All VDD pins must

be connected to a +3.3 V supply.

VSS

Digital Ground (8 Pins) Power

There are eight ground pins that are used by the inter-

nal digital circuitry.

9/14/00 Am79C976 33

PRELIMINARY

BASIC FUNCTIONS

System Bus Interface

The Am79C976 controller is designed to operate as a

bus master during normal operations. Some slave I/O

accesses to the Am79C976 controller are required in

normal operations as well. Initialization of the

Am79C976 controller is achieved through a combina-

tion of PCI Configuration Space accesses, bus slave

accesses, bus master accesses, and an optional read

of a serial EEPROM that is performed by the

Am79C976 controller. The EEPROM read operation is

performed through the 93Cxx EEPROM interface. The

ISO 8802-3 (IEEE/ANSI 802.3) Ethernet Address may

reside within the serial EEPROM. Some Am79C976

controller configuration registers may also be pro-

grammed by the EEPROM read operation.

The Am79C976 controller requires 4 Kbytes of memory

address space for access to all the various internal reg-

isters as well as access to some setup information

stored in an external serial EEPROM. For compatibility

with previous PCnet family devices, the lower 32 bytes

of the register space are also mapped into I/O space,

but some functions of the Am79C976 controller (such

as network statistics) are only available in memory

space. The location of the memory or I/O address

space claimed by this device is programmed through

the base address registers in PCI configuration space.

For diskless stations, the Am79C976 controller sup-

ports a ROM or Flash-based (both referred to as the

Expansion ROM throughout this specification) boot de-

vice of up to 16 Mbyte in size. The host can map the

boot device to any memory address that aligns to a de-

vice size boundary by modifying the Expansion ROM

Base Address register in the PCI configuration space.

The Expansion ROM device size is determined by the

value set in the ROM-CFG register.

Software Interface

The software interface to the Am79C976 controller is

divided into three parts. One part is the PCI configura-

tion registers used to identify the Am79C976 controller

and to setup the configuration of the device. The setup

information includes the I/O or memory mapped I/O

base address, mapping of the Expansion ROM, and

the routing of the Am79C976 controller interrupt chan-

nel. This allows for a jumperless implementation.

The second portion of the software interface is the

direct access to the I/O resources of the Am79C976

controller. The Am79C976 controller requires 4 Kbytes

of memory address space for access to all the various

internal registers as well as access to some setup infor-

mation stored in an external serial EEPROM. For com-

patibility with previous PCnet family devices, the lower

32 bytes of the register space are also mapped into I/O

space, but some functions of the Am79C976 controller

(such as network statistics) are only available in mem-

ory space.

The third portion of the software interface is the de-

scriptor and buffer areas that are shared between the

software and the Am79C976 controller during normal

network operations. The descriptor area boundaries

are set by the software and do not change during nor-

mal network operations. There is one descriptor area

for receive activity and there is a separate area for

transmit activity. The descriptor space contains relocat-

able pointers to the network frame data, and it is used

to transfer frame status from the Am79C976 controller

to the software. The buffer areas are locations that hold

frame data for transmission or that accept frame data

that has been received.

Network Interface

The Am79C976 controller can be connected to an

IEEE 802.3 or proprietary network through the IEEE

802.3-compliant Media Independent Interface (MII).

The MII is a nibble-wide interface to an external

100-Mbps and/or 10-Mbps transceiver device.

The Am79C976 controller supports both half-duplex

and full-duplex operation on the network interface.

34 Am79C976 9/14/00

PRELIMINARY

DETAILED FUNCTIONS

Slave Bus Interface Unit

The slave bus interface unit (BIU) controls all accesses

to the PCI configuration space, the Control and Status

Registers (CSR), the Bus Configuration Registers

(BCR), the Address PROM (APROM) locations, and

the Expansion ROM. Table 2 shows the response of

the Am79C976 controller to each of the PCI commands

in slave mode.

Table 2. Slave Commands

Slave Configuration Transfers

The host can access the Am79C976 PCI configuration

space with a configuration read or write command. The

Am79C976 controller will assert DEVSEL during the

address phase when IDSEL is asserted, AD[1:0] are

both 0, and the access is a configuration cycle. AD[7:2]

select the DWord location in the configuration space.

The Am79C976 controller requires AD[10:8] to be 0,

because it is a single function device. AD[31:11] are

“don't care.”

The active bytes within a DWord are determined by the

byte enable signals. Eight-bit, 16-bit, and 32-bit trans-

fers are supported. DEVSEL is asserted two clock cy-

cles after the host has asserted FRAME. All

configuration cycles are of fixed length. The

Am79C976 controller will assert TRDY on the third or

fourth clock of the data phase.

The Am79C976 controller does not support burst trans-

fers for access to configuration space. When the host

keeps FRAME asserted for a second data phase, the

Am79C976 controller will disconnect the transfer.

When the host tries to access the PCI configuration

space while the automatic read of the EEPROM after

H_RESET (see section on RESET) is on-going, the

Am79C976 controller will terminate the access on the

PCI bus with a disconnect/retry response.

The Am79C976 controller supports fast back-to-back

transactions to different targets. This is indicated by the

Fast Back-To-Back Capable bit (PCI Status register,

bit 7), which is hardwired to 1. The Am79C976 control-

ler is capable of detecting a configuration cycle even

when its address phase immediately follows the data

phase of a transaction to a different target without any

idle state in-between. There will be no contention on

the DEVSEL, TRDY, and STOP signals, since the

Am79C976 controller asserts DEVSEL on the second

clock after FRAME is asserted (medium timing).

Slave I/O Transfers

After the Am79C976 controller is configured as an I/O

device by setting IOEN (for regular I/O mode) or

MEMEN (for memory mapped I/O mode) in the PCI

Command register, it starts monitoring the PCI bus for

access to its address space. If configured for regular

I/O mode, the Am79C976 controller will look for an ad-

dress that falls within its 32 bytes of I/O address space

(starting from the I/O base address). The Am79C976

controller asserts DEVSEL if it detects an address

match and the access is an I/O cycle. If configured for

memory mapped I/O mode, the Am79C976 controller

will look for an address that falls within its 4096 bytes

of memory address space (starting from the memory

mapped I/O base address). The Am79C976 controller

asserts DEVSEL if it detects an address match and the

C[3:0] Command Use

0000 Interrupt

Acknowledge Not used

0001 Special Cycle Not used

0010 I/O Read Read of CSR, BCR, APROM,

and Reset registers

0011 I/O Write Write to CSR, BCR, and

APROM

0100 Reserved

0101 Reserved

0110 Memory Read

Memory mapped I/O read of

CSR, BCR, APROM, Reset

registers, and read of the

Expansion Bus

0111 Memory Write Memory mapped I/O write of

CSR, BCR, and APROM

1000 Reserved

1001 Reserved

1010 Configuration

Read

Read of the Configuration

Space

1011 Configuration

Write

Write to the Configuration

Space

1100 Memory Read

Multiple Aliased to Memory Read

1101 Dual Address

Cycle Not used

1110 Memory Read

Line Aliased to Memory Read

1111 Memory Write

Invalidate Aliased to Memory Write

AD 31 -

AD11

AD10 -

AD8

A D7 -

AD2 AD1 AD0

Don’t care 0 DWord

index 00

9/14/00 Am79C976 35

PRELIMINARY

access is a memory cycle. DEVSEL is asserted two

clock cycles after the host has asserted FRAME. See

Figure 1 and Figure 2.

Figure 1. Slave Configuration Read

Figure 2. Slave Configuration Write

For compatibility with older members of the PCnet fam-

ily of controllers, the 32 lowest addresses of the I/O or

memory space claimed by the Am79C976 device sup-

port indirect addressing of internal registers. The

Am79C976 controller does not support burst transfers

for access to these locations. When the host keeps

FRAME asserted for a second data phase in this ad-

dress range, the Am79C976 controller will disconnect

the transfer. However, the controller does support burst

accesses to locations at offsets 32 and above.

Because of the side effects of reading the Reset Reg-

ister at offset 14h or 18h (depending on the state of

DWIO (CMD2, bit 28)), locations at offsets less than

20h cannot be prefetched.

The Am79C976 controller supports fast back-to-back

transactions to different targets. This is indicated by the

Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardwired to 1. The Am79C976 controller

is capable of detecting an I/O or a memory-mapped

I/O cycle even when its address phase immediately fol-

lows the data phase of a transaction to a different target,

without any idle state in-between. There will be no con-

tention on the DEVSEL, TRDY, and STOP signals, since

the Am79C976 controller asserts DEVSEL on the sec-

ond clock after FRAME is asserted (medium timing).

See Figure 3 and Figure 4.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1010

PAR PAR PAR

DATA

ADDR

22929B3

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

IDSEL

1 23456

1011

PAR PAR PAR

DATA

ADDR

22929B4

The Am79C976 controller will not assert DEVSEL if it

detects an address match, but the PCI command is not

of the correct type. In memory mapped I/O mode, the

Am79C976 controller aliases all accesses to the I/O re-

sources of the command types Memory Read Multiple

and Memory Read Line to the basic Memory Read

command. All accesses of the type Memory Write and

Invalidate are aliased to the basic Memory Write com-

mand. Eight-bit, 16-bit, and 32-bit transactions are sup-

ported. The Am79C976 controller decodes all 32

address lines to determine which I/O resource is ac-

cessed.

The number of wait states added to slave transactions

varies. Typical values are shown in the table below:

Slave Transactions

Transaction Type

Read Write

Memory-mapped

transactions 90

I/O-mapped transactions 9 3

36 Am79C976 9/14/00

PRELIMINARY

Figure 3. Slave Read Using I/O Command

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0010

PAR

1 2345678 109 11

DATA

PAR

22929B5

9/14/00 Am79C976 37

PRELIMINARY

Figure 4. Slave Write Using Memory Command

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

PAR

ADDR

0111

PAR

1 2345678 109 11

DATA

PAR

22929B6

38 Am79C976 9/14/00

PRELIMINARY

Expansion ROM Transfers

The Am79C976 device includes an interface to an op-

tional expansion ROM. The amount of PCI address

space claimed by this ROM is determined by the con-

tents of the ROM Configuration Register, ROM_CFG,

which should normally be loaded from the serial EE-

PROM.

The host must initialize the Expansion ROM Base

Address register at offset 30H in the PCI configuration

space with a valid address before enabling the access

to the device. The Am79C976 controller will not react

to any access to the Expansion ROM until both

MEMEN (PCI Command register, bit 1) and ROMEN

(PCI Expansion ROM Base Address register, bit 0) are

set to 1. After the Expansion ROM is enabled, the

Am79C976 controller will assert DEVSEL on all mem-

ory read accesses to the memory space defined by the

contents of the Expansion ROM Base Address register.

The Am79C976 controller aliases all accesses to the

Expansion ROM of the command types Memory Read

Multiple and Memory Read Line to the basic Memory

Read command. Eight-bit, 16-bit, and 32-bit read trans-

fers are supported.

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given to

the PCI Memory Mapped I/O Base Address register

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base Ad-

dress register to a value that prevents the Am79C976

controller from claiming any memory cycles not in-

tended for it.

The Am79C976 controller will always read four bytes

for every host Expansion ROM read access. Since this

takes more than 16 PCI clock cycles, the Am79C976

device will assert STOP to force a PCI bus retry. Sub-

sequent accesses will be retried until all four bytes

have been read from the ROM and stored in an internal

temporary register. The timing of the access to the

ROM device is determined by the ROMTMG parameter

(CTRL0, bits 11-8).

Note: The Expansion ROM must not be read when the

Am79C976 controller is running (when the RUN bit in

CMD0 is set to 1). Any access to the Expansion ROM

clears the RUN bit and thereby abruptly stops all net-

work and DMA operations.

When the host tries to write to the Expansion ROM, the

Am79C976 controller will claim the cycle. The write op-

eration will have no effect. Writes to the Expansion

ROM are done through the BCR30 Expansion Bus

Data Port. See the section on the Expansion Bus Inter-

face for more details.

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55H (byte 0) and AAH (byte 1).

Slave Cycle Termination

In addition to the normal completion of a transaction,

there are three scenarios in which the Am79C976 con-

troller terminates a slave access for which it is the tar-

get.

Disconnect When Busy

If a slave access to the Am79C976 device takes more

than 16 PCI CLK cycles, the Am79C976 device will

generate a PCI disconnect/retry cycle by asserting

STOP and deasserting TRDY while keeping DEVSEL

asserted. This will free up the PCI bus so that it can be

used by other bus masters while the Am79C976 device

is busy. See Figure 5.

The Am79C976 controller cannot service any slave ac-

cess while it is reading the contents of the EEPROM.

Simultaneous access is not allowed in order to avoid

conflicts, since the EEPROM is used to initialize some

of the PCI configuration space locations and user-se-

lected BCRs and CSRs. The EEPROM read operation

will always happen automatically following H_RESET.

(See the H_RESET section for more details.) In addi-

tion, the host can start the read operation by setting the

PREAD bit (BCR19, bit 14). While the EEPROM read

is on-going, the Am79C976 controller will disconnect

any slave access where it is the target by asserting

STOP together with DEVSEL, while driving TRDY high.

STOP will stay asserted until the end of the cycle.

Note: The I/O and memory slave accesses will only be

disconnected if they are enabled by setting the IOEN or

MEMEN bit in the PCI Command register. Without the

enable bit set, the cycles will not be claimed at all.

Since H_RESET clears the IOEN and MEMEN bits for

the automatic EEPROM read after H_RESET, the dis-

connect only applies to configuration cycles.

The Am79C976 device will also generate PCI discon-

nect/retry cycles when it is executing a blocking read

access to an external PHY register.

9/14/00 Am79C976 39

PRELIMINARY

Figure 5. Disconnect Of Slave Cycle When Busy

Disconnect Of Burst Transfer

The Am79C976 controller does not support burst ac-

cess to the configuration space, the first 32 bytes of its

I/O or memory space, or to the Expansion Bus. The

host indicates a burst transaction by keeping FRAME

asserted during the data phase. When the Am79C976

controller sees FRAME and IRDY asserted in the clock

cycle before it wants to assert TRDY

, it also asserts

STOP at the same time. The transfer of the first data

phase is still successful, since IRDY and TRDY are

both asserted. See Figure 6.

Figure 6. Disconnect Of Slave Burst Transfer - No

Host Wait States

If the host is not yet ready when the Am79C976 control-

ler asserts TRDY, the device will wait for the host to as-

sert IRDY

. When the host asserts IRDY and FRAME is

still asserted, the Am79C976 controller will finish the

first data phase by deasserting TRDY one clock later.

At the same time, it will assert STOP to signal a discon-

nect to the host. STOP will stay asserted until the host

removes FRAME. See Figure 7.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

CMD

PAR PAR PAR

DATA

ADDR

22929B7

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 2345

PAR PAR PAR

DATA

1st DATA

22929B8

40 Am79C976 9/14/00

PRELIMINARY

Figure 7. Disconnect Of Slave Burst Transfer -

Host Inserts Wait States

Parity Error Response

When the Am79C976 controller is not the current bus

master, it samples the AD[31:0], C/BE[3:0], and the

PAR lines during the address phase of any PCI com-

mand for a parity error. When it detects an address par-

ity error, the controller sets PERR (PCI Status register,

bit 15) to 1. When reporting of that error is enabled by

setting SERREN (PCI Command register, bit 8) and

PERREN (PCI Command register, bit 6) to 1, the

Am79C976 controller also drives the SERR signal low

for one clock cycle and sets SERR (PCI Status register,

bit 14) to 1. The assertion of SERR follows the address

phase by two clock cycles. The Am79C976 controller

will not assert DEVSEL for a PCI transaction that has

an address parity error when PERREN and SERREN

are set to 1. See Figure 8.

Figure 8. Address Parity Error Response

During the data phase of an I/O write, memory-mapped

I/O write, or configuration write command that selects

the Am79C976 controller as target, the device samples

the AD[31:0] and C/BE[3:0] lines for parity on the clock

edge, and data is transferred as indicated by the asser-

tion of IRDY and TRDY. PAR is sampled in the follow-

ing clock cycle. If a parity error is detected and

reporting of that error is enabled by setting PERREN

(PCI Command register, bit 6) to 1, PERR is asserted

one clock later. The parity error will always set PERR

(PCI Status register, bit 15) to 1 even when PERREN

is cleared to 0. The Am79C976 controller will finish a

transaction that has a data parity error in the normal

way by asserting TRDY

. The corrupted data will be writ-

ten to the addressed location.

Figure 9 shows a transaction that suffered a parity error

at the time data was transferred (clock 7, IRDY and

TRDY are both asserted). PERR is driven high at the

beginning of the data phase and then drops low due to

the parity error on clock 9, two clock cycles after the

data was transferred. After PERR is driven low, the

Am79C976 controller drives PERR high for one clock

cycle, since PERR is a sustained tri-state signal.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 23456

PAR

PAR PAR

DATA

1st DATA

22929B9

FRAME

CLK

SERR

C/BE

DEVSEL

1 2345

PAR PAR

ADDR 1st DATA

CMD

PAR

22929B10

9/14/00 Am79C976 41

PRELIMINARY

Figure 9. Slave Cycle Data Parity Error Response

Master Bus Interface Unit

The master Bus Interface Unit (BIU) controls the acqui-

sition of the PCI bus and all accesses to the initializa-

tion block, descriptor rings, and the receive and

transmit buffer memory. Table 3 shows the usage of

PCI commands by the Am79C976 controller in master

mode.

Bus Acquisition

The Am79C976 logic will determine when a DMA

transfer should be initiated. The first step in any

Am79C976 bus master transfer is to acquire ownership

of the bus. This task is handled by synchronous logic

within the BIU. Bus ownership is requested with the

REQ signal and ownership is granted by the arbiter

through the GNT signal.

Figure 10 shows the Am79C976 controller bus acquisi-

tion. REQ is asserted and the arbiter returns GNT while

another bus master is transferring data. The

Am79C976 controller waits until the bus is idle

(FRAME and IRDY deasserted) before it starts driving

AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted

at clock 5 indicating a valid address and command on

AD[31:0] and C/BE[3:0]. The Am79C976 controller

does not use address stepping which is reflected by

ADSTEP (bit 7) in the PCI Command register being

hardwired to 0.

Bus Master DMA Transfers

There are four primary types of DMA transfers. The

Am79C976 controller uses non-burst as well as burst

cycles for read and write access to the main memory.

Basic Non-Burst Read Transfer

The Am79C976 controller uses non-burst cycles to ac-

cess descriptors when SWSTYLE (BCR20, bits 7-0) is

0 or 2. All Am79C976 controller non-burst read ac-

cesses are of the PCI command type Memory Read

(type 6). Note that during a non-burst read operation,

all byte lanes will always be active. The Am79C976

controller will internally discard unneeded bytes.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

ADDR

CMD

PAR

1 2345678 109

DATA

PAR

PERR

22929B11

42 Am79C976 9/14/00

PRELIMINARY

Table 3. PCI Commands

Figure 10. Bus Acquisition

The Am79C976 controller typically performs more than

one non-burst read transaction within a single bus

mastership period. FRAME is dropped between con-

secutive non-burst read cycles. REQ, however, stays

asserted until FRAME is asserted for the last transac-

tion. The Am79C976 controller supports zero wait-

state read cycles. It asserts IRDY immediately after the

address phase and at the same time starts sampling

DEVSEL. Figure 11 shows two non-burst read transac-

tions. The first transaction has zero wait states. In the

second transaction, the target extends the cycle by as-

serting TRDY one clock later.

Basic Burst Read Transfer

The Am79C976 controller supports burst mode for all

bus master read operations. To allow burst transfers in

descriptor read operations, the Am79C976 controller

must be programmed to use SWSTYLE 3, 4, or 5

(BCR20, bits 7-0).

The BIU chooses which PCI command to use as fol-

lows:

■When reading one DWord, use Memory Read.

■When reading a block of more than one DWord that

does not cross a cache line, use Memory Read

Line.

■When reading a block that crosses a cache line

boundary, use Memory Read Multiple.

C[3:0] Command Use

0000 Interrupt Acknowledge Not used

0001 Special Cycle Not used

0010 I/O Read Not used

0011 I/O Write Not used

0100 Reserved

0101 Reserved

0110 Memory Read Read of the initialization block and descriptor rings

Read of the transmit buffer in non-burst mode

0111 Memory Write Write to the descriptor rings and to the receive buffer

1000 Reserved

1001 Reserved

1010 Configuration Read Not used

1011 Configuration Write Not used

1100 Memory Read Multiple Read of descriptor or transmit buffer in burst mode

1101 Dual Address Cycle Used when required

1110 Memory Read Line Read of descriptor or transmit buffer in burst mode

1111 Memory Write Invalidate Burst write of 1 or more complete cache lines to the receive buffer

22929B12

FRAME

CLK

IRDY

C/BE

REQ

GNT

1 2345

CMD

ADDR

9/14/00 Am79C976 43

PRELIMINARY

Figure 11. Non-Burst Read Transfer

The FIFO thresholds should be greater than or equal to

the cache line size to maximize the use of the MRL and

MRM commands. If the PCI bridge stops a transfer, the

Am79C976 device waits until the FIFO threshold con-

ditions are met before resuming the transfer.

During the address phase of a burst access, AD[1:0]

will both be 0 indicating a linear burst order. Note that

during a burst read operation, all byte lanes will always

be active. The Am79C976 controller will internally dis-

card unneeded bytes.

The Am79C976 controller will always perform only a

single burst read transaction per bus mastership pe-

riod, where transaction is defined as one address

phase and one or multiple data phases. The

Am79C976 controller supports zero wait state read cy-

cles. It asserts IRDY immediately after the address

phase and at the same time starts sampling DEVSEL.

FRAME is deasserted when the next-to-last data

phase is completed.

The device may insert IRDY wait states in the middle of

a burst read transaction.

Figure 12 shows a typical burst read access. The

Am79C976 controller arbitrates for the bus, is granted

access, reads three 32-bit words (DWord) from the sys-

tem memory, and then releases the bus. In the exam-

ple, the memory system extends the data phase of

each access by one wait state.

Basic Non-Burst Write Transfer

The Am79C976 controller uses non-burst cycles to

write descriptors when SWSTYLE (BCR20, bits 7-0) is

0 or 2. All Am79C976 controller non-burst write ac-

cesses are of the PCI command type Memory Write

(type 7). The byte enable signals indicate the byte

lanes that have valid data.The Am79C976 controller

may perform more than one non-burst write transaction

within a single bus mastership period. FRAME is

dropped between consecutive non-burst write cycles.

REQ, however, stays asserted until FRAME is asserted

for the last transaction. The Am79C976 supports zero

wait state write cycles. (See the section Descriptor

DMA Transfers for the only exception.) It asserts IRDY

immediately after the address phase.

Figure 13 shows two non-burst write transactions. The

first transaction has two wait states. The Am79C976

device supports zero wait state non-burst write cycles.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0110

PAR

1 2345678 109 11

DATA

ADDR

DATA

PAR PAR PAR

0000 0110 0000

22929B13

44 Am79C976 9/14/00

PRELIMINARY

Figure 12. Burst Read Transfer

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

00001110

PAR

1 2345678 109 11

DATA

PAR PAR PAR

22929B14

9/14/00 Am79C976 45

PRELIMINARY

Figure 13. Non-Burst Write Transfer

Basic Burst Write Transfer

The Am79C976 controller supports burst mode for all

bus master write operations. To allow burst transfers in

descriptor write operations, the Am79C976 controller

must be programmed to use SWSTYLE 3, 4, or 5

(BCR20, bits 7-0).

The controller uses the following rules to determine

whether to use the PCI Memory Write (MW) command

or the Memory Write and Invalidate (MWI) command

for burst write transfers.

—When a transfer starts on a cache line boundary,

and there is at least a cache line of data to trans-

fer, use MWI.

—When a transfer does not start on a cache line

boundary, use MW. (The external PCI bridge

should stop the transfer at the cache line bound-

ary if it can make good use of the MWI com-

mand.)

—Stop the MWI transfer at a cache line boundary

if there is less than 1 cache line of data left to

transfer.

The Receive FIFO threshold should be greater than or

equal to the cache line size to maximize the use of the

MWI command. If the PCI bridge stops a transfer, the

Am79C976 device waits until the FIFO threshold con-

ditions are met before resuming the transfer.

During the address phase of a burst write transfer

AD[1:0] will both be 0 indicating a linear burst order.

The byte enable signals indicate which byte lanes have

valid data.

The Am79C976 controller will always perform a single

burst write transaction per bus mastership period,

where transaction is defined as one address phase and

one or multiple data phases. The Am79C976 controller

supports zero wait state write cycles when using the

Memory Write command. When using Memory Write

and Invalidate commands, the device may insert IRDY

wait states anywhere in the transaction.

The device asserts IRDY immediately after the address

phase and at the same time starts sampling DEVSEL.

FRAME is deasserted when the next-to-last data

phase is completed.

Figure 14 shows a typical burst write access. The

Am79C976 controller arbitrates for the bus, is granted

access, and writes four 32-bit words (DWords) to the

system memory and then releases the bus. In this ex-

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 2345678 109

DATA

ADDR

DATA

PAR PAR PAR

BE 0111 BE

22929B15

46 Am79C976 9/14/00

PRELIMINARY

ample, the memory system extends the data phase of

the first access by one wait state. The following three

data phases take one clock cycle each, which is deter-

mined by the timing of TRDY

DMA Burst Alignment

The BIU has two programmable features that can im-

prove the DMA performance with PCI bridges that do

not automatically stop burst transfers to align them with

cache line boundaries:

1. The Burst Alignment (BA) bit (CTRL0, bit 4). When

this bit is set, if a burst transfer starts in the middle

of a cache line, the transfer will stop at the first

cache line boundary.

2. The Burst Limit Register (CTRL0, bits 3:0). This 4-

bit register limits the maximum length of a burst

transfer. If the contents of this register are 0, the

burst length is limited by the amount of data avail-

able or by the amount of FIFO space available.

If the contents of this register are not zero, a burst

transfer will end when the transfer has crossed the

number of cache line boundaries equal to the con-

tents of this register.

Target Initiated Termination

When the Am79C976 controller is a bus master, the cy-

cles it produces on the PCI bus may be terminated by

the target in one of three different ways: disconnect

with data transfer, disconnect without data transfer, and

target abort.

Disconnect With Data Transfer

Figure 15 shows a disconnection in which one last data

transfer occurs after the target asserted STOP

. STOP

is asserted on clock 4 to start the termination se-

quence. Data is still transferred during this cycle, since

both IRDY and TRDY are asserted. The Am79C976

controller terminates the current transfer with the deas-

sertion of FRAME on clock 5 and of IRDY one clock

later. It finally releases the bus on clock 7. The

Am79C976 controller will again request the bus after

two clock cycles, if it wants to transfer more data. The

starting address of the new transfer will be the address

of the next non-transferred data.

Figure 14. Burst Write Transfer

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

12345678

ADDR DATA DATA DATA

0111

PAR PAR PAR PAR PAR

DATA

PAR

DEVSEL is sampled

22929B16

9/14/00 Am79C976 47

PRELIMINARY

Figure 15. Disconnect With Data Transfer

Disconnect Without Data Transfer

Figure 16 shows a target disconnect sequence during

which no data is transferred. STOP is asserted on clock

4 without TRDY being asserted at the same time. The

Am79C976 controller terminates the access with the

deassertion of FRAME on clock 5 and of IRDY one

clock cycle later. It finally releases the bus on clock 7.

The Am79C976 controller will again request the bus

after two clock cycles to retry the last transfer. The

starting address of the new transfer will be the address

of the last non-transferred data.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

ADDRi

00000111

PAR

0111

23456789 11

PAR

DATA

STOP

ADDRi+8

DATA

22929B17

48 Am79C976 9/14/00

PRELIMINARY

Figure 16. Disconnect Without Data Transfer

Target Abort

Figure 17 shows a target abort sequence. The target

asserts DEVSEL for one clock. It then deasserts

DEVSEL and asserts STOP on clock 4. A target can

use the target abort sequence to indicate that it can-

not service the data transfer and that it does not want

the transaction to be retried. Additionally, the

Am79C976 controller cannot make any assumption

about the success of the previous data transfers in the

current transaction. The Am79C976 controller termi-

nates the current transfer with the deassertion of

FRAME on clock 5 and of IRDY one clock cycle later.

It finally releases the bus on clock 7.

Since data integrity is not guaranteed, the Am79C976

controller cannot recover from a target abort event. The

Am79C976 controller will reset all CSR locations to their

STOP_RESET values. The BCR and PCI configuration

registers will not be cleared. Any on-going network

transmission is terminated with the current FCS inverted

and appended at the next byte boundary. This guaran-

tees that the receiving station will drop the truncated

frame.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

STOP

ADDRi

00000111

PAR

0111

23456789 11

ADDRi

DATA

PAR

22929B18

9/14/00 Am79C976 49

PRELIMINARY

Figure 17. Target Abort

RTABORT (PCI Status register, bit 12) will be set to

indicate that the Am79C976 controller has received a

target abort. In addition, SINT (CSR5, bit 11) will be set

to 1. When SINT is set, INTA is asserted if the enable

bit SINTE (CSR5, bit 10) is set to 1. This mechanism

can be used to inform the driver of the system error. The

host can read the PCI Status register to determine the

exact cause of the interrupt.

Master Initiated Termination

There are three scenarios besides normal completion

of a transaction where the Am79C976 controller will

terminate the cycles it produces on the PCI bus.

Preemption During Non-Burst Transaction

When the Am79C976 controller performs multiple non-

burst transactions, it keeps REQ asserted until the as-

sertion of FRAME for the last transaction. When GNT

is removed, the Am79C976 controller will finish the cur-

rent transaction and then release the bus. If it is not the

last transaction, REQ will remain asserted to regain

bus ownership as soon as possible. See Figure 18.

Preemption During Burst Transaction

When the Am79C976 controller operates in burst

mode, it only performs a single transaction per bus

mastership period, where transaction is defined as one

address phase and one or multiple data phases. The

central arbiter can remove GNT at any time during the

transaction. The Am79C976 controller will ignore the

deassertion of GNT and continue with data transfers,

as long as the PCI Latency Timer is not expired. When

the Latency Timer is 0 and GNT is deasserted, the

Am79C976 controller will finish the current data phase,

deassert FRAME, finish the last data phase, and re-

lease the bus. It will immediately assert REQ to regain

bus ownership as soon as possible.

When the preemption occurs after the counter has

counted down to 0, the Am79C976 controller will finish

the current data phase, deassert FRAME, finish the

last data phase, and release the bus. Note that it is im-

portant for the host to program the PCI Latency Timer

according to the bus bandwidth requirement of the

Am79C976 controller. The host can determine this bus

bandwidth requirement by reading the PCI MAX_LAT

and MIN_GNT registers.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

234567

ADDR

0000

0111

PAR PAR

DATA

STOP

22929B19

50 Am79C976 9/14/00

PRELIMINARY

Figure 18. Preemption During Non-Burst Transaction

If the controller is executing a Memory Write and Inval-

idate instruction when preemption occurs, the control-

ler will finish writing the current cache line before it

releases the bus.

Figure 19 assumes that the PCI Latency Timer has

counted down to 0 on clock 7.

Master Abort

The Am79C976 controller will terminate its cycle with a

Master Abort sequence if DEVSEL is not asserted

within 4 clocks after FRAME is asserted. Master Abort

is treated as a fatal error by the Am79C976 controller.

The Am79C976 controller will reset all CSR locations

to their STOP_RESET values. The BCR and PCI con-

figuration registers will not be cleared. Any on-going

network transmission is terminated in an orderly se-

quence. The message will have the current FCS in-

verted and appended at the next byte boundary to

guarantee that the receiving station will treat the trans-

mission either as a runt or as a corrupted frame.

RMABORT (in the PCI Status register, bit 13) will be set

to indicate that the Am79C976 controller has termi-

nated its transaction with a master abort. In addition,

SINT (CSR5, bit 11) will be set to 1. When SINT is set,

INTA is asserted if the enable bit SINTE (CSR5, bit 10)

is set to 1. This mechanism can be used to inform the

driver of the system error. The host can read the PCI

Status register to determine the exact cause of the in-

terrupt. See Figure 20.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

BE0111

PAR PAR

DEVSEL is sampled

PAR

DATA

ADDR

22929B20

9/14/00 Am79C976 51

PRELIMINARY

Figure 19. Preemption During Burst Transaction

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

BE0111

PAR

1 23456789

DATA

PAR

REQ

DATA

PAR PAR PAR PAR

GNT

22929B21

52 Am79C976 9/14/00

PRELIMINARY

Figure 20. Master Abort

Parity Error Response

During every data phase of a DMA read operation,

when the target indicates that the data is valid by as-

serting TRDY

, the Am79C976 controller samples the

AD[31:0], C/BE[3:0] and the PAR lines for a data parity

error. When it detects a data parity error, the controller

sets PERR (PCI Status register, bit 15) to 1. When re-

porting of that error is enabled by setting PERREN

(PCI Command register, bit 6) to 1, the Am79C976

controller also drives the PERR signal low and sets

DATAPERR (PCI Status register, bit 8) to 1. The asser-

tion of PERR follows the corrupted data/byte enables

by two clock cycles and PAR by one clock cycle.

Figure 21 shows a transaction that has a parity error in

the data phase. The Am79C976 controller asserts

PERR on clock 8, two clock cycles after data is valid.

The data on clock 5 is not checked for parity, since on

a read access PAR is only required to be valid one

clock after the target has asserted TRDY. The

Am79C976 controller then drives PERR high for one

clock cycle, since PERR is a sustained tri-state signal.

During every data phase of a DMA write operation, the

Am79C976 controller checks the PERR input to see if

the target reports a parity error. When it sees the PERR

input asserted, the controller sets PERR (PCI Status

sets DATAPERR (PCI Status register, bit 8) to 1.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 23456789

DATA

PAR

REQ

GNT

0000

22929B22

9/14/00 Am79C976 53

PRELIMINARY

Figure 21. Master Cycle Data Parity Error Response

Whenever the Am79C976 controller is the current bus

master and a data parity error occurs, SINT (CSR5, bit

11) will be set to 1. When SINT is set, INTA is asserted

if the enable bit SINTE (CSR5, bit 10) is set to 1. This

mechanism can be used to inform the driver of the sys-

tem error. The host can read the PCI Status register to

determine the exact cause of the interrupt. The setting

of SINT due to a data parity error is not dependent on

the setting of PERREN (PCI Command register, bit 6).

By default, a data parity error does not affect the state

of the MAC engine. The Am79C976 controller treats the

data in all bus master transfers that have a parity error

as if nothing has happened. All network activity contin-

ues.

Initialization Block DMA Transfers

During execution of the Am79C976 controller bus mas-

ter initialization procedure, the Am79C976 controller

will use a burst transfer of seven Dwords to read the ini-

tialization block. AD[1:0] is 0 during the address phase

indicating a linear burst order.

Descriptor DMA Transfers

During descriptor read accesses, the byte enable sig-

nals will indicate that all byte lanes are active. Should

some of the bytes not be needed, then the Am79C976

controller will internally discard the extraneous informa-

tion that was gathered during such a read.

The settings of SWSTYLE (BCR20, bits 7-0) affect the

way the Am79C976 controller performs descriptor read

operations.

Because of the order in which the descriptor data must

be read or written when SWSTYLE is set to 0 or 2, all

descriptor read operations are performed in non-burst

mode. See Figure 22.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

DEVSEL is sampled

ADDR

0111

PAR

1 23456789

DATA

PAR

PERR

22929B23

54 Am79C976 9/14/00

PRELIMINARY

Figure 22. Descriptor Ring Read In Non-Burst Mode

When SWSTYLE is set to 3, 4, or 5 the descriptor en-

tries are ordered to allow burst transfers, and the

Am79C976 controller will perform all descriptor read

operations in burst mode. The device may read more

than one descriptor in a single burst. See Figure 23.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD1

00000110

PAR PAR

DATA DATA

MD0

00000110

PAR PAR

1 2345678 109

22929B24

9/14/00 Am79C976 55

PRELIMINARY

Figure 23. Descriptor Ring Read In Burst Mode

Table 4 shows the descriptor read sequence. During

descriptor write accesses, only the byte lanes which

need to be written are enabled.

The settings of SWSTYLE (BCR20, bits 7-0) affect the

way the Am79C976 controller performs descriptor write

operations.

When SWSTYLE is set to 0 or 2, all descriptor write op-

erations are performed in non-burst mode.

When SWSTYLE is set to 3, 4, or 5, the descriptor en-

tries are ordered to allow burst transfers. The

Am79C976 controller will perform all descriptor write

operations in burst mode. See Table 5 for the descrip-

tor write sequence.

Table 4. Descriptor Read Sequence

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

MD1

00000110

PAR PAR PAR

DATA DATA

PAR

DEVSEL is sampled

22929B25

SWSTYLE

BCR20

[7:0]

AD Bus Sequence

for Rx Descriptors

AD Bus Sequence

for Tx Descriptors

Address = XXXX

XX00h

Turn around cycle

Data

Idle

Address = XXXX

XX04h

Turn around cycle

Data

Address = XXXX

XX00h

Turn around cycle

Data

Idle

Address = XXXX

XX04h

Turn around cycle

Data

Address = XXXX

XX04h

Turn around cycle

Data

Idle

Address = XXXX

XX00h

Turn around cycle

Data

Address = XXXX

XX04h

Turn around cycle

Data

Idle

Address = XXXX

XX00h

Turn around cycle

Data

Address = XXXX

XX04h

Turn around cycle

Data

Address = XXXX

XX04h

Turn around cycle

Data

Address = XXXX

XX04h

Turn around cycle

Data

Address = XXXX

XX00h

Turn around cycle

Data

Address = XXXX

XX08h

Turn around cycle

Data

Address = XXXX

XX00h

Turn around cycle

Data

56 Am79C976 9/14/00

PRELIMINARY

Table 5. Descriptor Write Sequence

Note: Figure 24 assumes that the Am79C976 control-

ler is programmed to use 32-bit software structures

(SWSTYLE = 2, 3, 4, or 5). The byte enable signals for

the second data transfer would be 0111b, if the device

was programmed to use 16-bit software structures

(SWSTYLE = 0).

SWSTYLE

BCR20[7:

AD Bus Sequence

for Rx Descriptor

AD Bus Sequence

for Tx Descriptor

Address = XXXX

XX04h

Data

Idle

Address = XXXX

XX00h

Data

Address = XXXX

XX04h

Data

Idle

Address = XXXX

XX00h

Data

Address = XXXX

XX08h

Data

Idle

Address = XXXX

XX04h

Data

Address = XXXX

XX08h

Data

Idle

Address = XXXX

XX04h

Data

Address = XXXX

XX00h

Data

Address = XXXX

XX00h

Data

Address = XXXX

XX00h

Data

Address = XXXX

XX00h

Data

Address = XXXX

XX00h

Data

Address = XXXX

XX00h

Data

9/14/00 Am79C976 57

PRELIMINARY

Figure 24. Descriptor Ring Write In Non-Burst Mode

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

PAR

DEVSEL is sampled

MD2

00000111

PAR

MD1

00110111

PAR

1 2345678 109

DATA

PAR

DATA

22929B26

58 Am79C976 9/14/00

PRELIMINARY

Figure 25. Descriptor Ring Write In Burst Mode

FIFO DMA Transfers

Am79C976 logic will determine when a FIFO DMA

transfer is required. This transfer mode will be used for

transfers of data to and from the Am79C976 FIFOs.

Once the Am79C976 BIU has been granted bus mas-

tership, it will perform a series of consecutive transfer

cycles before relinquishing the bus. All transfers within

the master cycle will be either read or write cycles, and

all transfers will be transferred to contiguous, ascend-

ing addresses. Burst cycles are used whenever possi-

ble.

A burst transaction will start with an address phase, fol-

lowed by one or more data phases. AD[1:0] will always

be 0 during the address phase indicating a linear burst

order.

During FIFO DMA read operations, all byte lanes will

always be active. The Am79C976 controller will inter-

nally discard unused bytes. During the first and the last

data phases of a FIFO DMA burst write operation, one

or more of the byte enable signals may be inactive. All

other data phases will always write a complete DWord.

Figure 26 shows the beginning of a FIFO DMA write

with the beginning of the buffer not aligned to a DWord

boundary. The Am79C976 controller starts off by writ-

ing only three bytes during the first data phase. This op-

eration aligns the address for all other data transfers to

a 32-bit boundary so that the Am79C976 controller can

continue bursting full DWords.

GNT

REQ

DEVSEL

TRDY

PAR

C/BE

FRAME

CLK

PAR

IRDY

DEVSEL is sampled

DATA

1 2 4 6 7 8

0110 0000 0011

MD2

PAR

DATA

PAR

22929B27

9/14/00 Am79C976 59

PRELIMINARY

Figure 26. FIFO Burst Write At Start Of Unaligned

Buffer

If a receive buffer does not end on a DWord boundary,

the Am79C976 controller will perform a non-DWord

write on the last transfer to the buffer. Figure 27 shows

the final three FIFO DMA transfers to a receive buffer.

Since there were only 9 bytes of space left in the re-

ceive buffer, the Am79C976 controller bursts three

data phases. The first two data phases write a full

DWord, the last one only writes a single byte.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 23456

00000111

PAR PAR PAR

DEVSEL is sampled

0001

PAR

DATA DATA

DATA

ADD

22929B28

60 Am79C976 9/14/00

PRELIMINARY

9/14/00 Am79C976 61

PRELIMINARY

Figure 27. FIFO Burst Write At End Of Unaligned

Buffer

Note that the Am79C976 controller will always perform

a DWord transfer as long as it owns the buffer space,

even when there are less than four bytes to write. For

example, if there is only one byte left for the current re-

ceive frame, the Am79C976 controller will write a full

DWord, containing the last byte of the receive frame in

the least significant byte position (BSWP is cleared to

0, CSR3, bit 2). The content of the other three bytes is

undefined. The message byte count in the receive

descriptor always reflects the exact length of the re-

ceived frame.

In the normal DMA mode (when the Burst Alignment bit

= 0 and the Burst Limit register contents = 0) the

Am79C976 controller will continue transferring FIFO

data until the transmit FIFO is filled to its high threshold

(for read transfers) or the receive FIFO is emptied to its

low threshold (for write transfers), or until the

Am79C976 controller is preempted and the PCI La-

tency Timer is expired. The host should use the values

in the PCI MIN_GNT and MAX_LAT registers to deter-

mine the value for the PCI Latency Timer.

In the burst alignment mode (when the Burst Alignment

bit = 1) if a burst transfer starts in the middle of a cache

line, the transfer will stop at the first cache line

boundary.

If the contents of the Burst Limit register are not zero, a

burst transfer will end when the transfer has crossed

the number of cache line boundaries equal to the con-

tents of this register.

The exact number of total transfer cycles in the bus

mastership period is dependent on all of the following

variables: the settings of the FIFO watermarks, the

conditions of the FIFOs, the latency of the system bus

to the Am79C976 controller’s bus request, and the

speed of bus operation. The TRDY response time of

the memory device will also affect the number of trans-

fers, since the speed of the accesses will affect the

state of the FIFO. The general rule is that the longer the

Bus Grant latency, the slower the bus transfer opera-

tions; the slower the clock speed, the higher the trans-

mit watermark; or the lower the receive watermark, the

longer the total burst length will be.

When a FIFO DMA burst operation is preempted, the

Am79C976 controller will not relinquish bus ownership

until the PCI Latency Timer expires.

Descriptor Management Unit

The Descriptor Management Unit (DMU) implements

the automatic initialization procedure and manages the

descriptors and buffers.

Initialization

The Am79C976 controller is initialized by a combina-

tion of EEPROM register writes, direct register writes

from the PCI bus and, for compatibility with older PCnet

family products, DMA reads from an initialization block

in memory. The registers that must be programmed de-

pend on the features that are required in a particular

application. See USER ACCESSIBLE REGISTERS on

page 113 for more details.

The format of the legacy initialization block depends on

the programming of the SWSTYLE register, as de-

scribed in the Initialization Block section.

The initialization block is read when the INIT bit in

CSR0 is set. The INIT bit should be set before or con-

current with the STRT bit to ensure correct operation.

Once the initialization block has been completely read

in and internal registers have been updated, IDON will

be set in CSR0, generating an interrupt (if IENA is set).

The Am79C976 controller obtains the start address of

the initialization block from the contents of CSR1 (least

significant 16 bits of address) and CSR2 (most signifi-

cant 16 bits of address). The host must write CSR1 and

CSR2 before setting the INIT bit. The initialization block

contains the user defined conditions for Am79C976 op-

eration, together with the base addresses and length

information of the transmit and receive descriptor rings.

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000111

PAR PAR PAR PAR

DEVSEL is sampled

1110

PAR

DATA DATA

DATA

ADD

62 Am79C976 9/14/00

PRELIMINARY

Re-Initialization

Earlier members of the PCnet family of controllers had

to be re-initialized if the transmitter and/or the receiver

were not turned on during the original initialization, and

it was subsequently required to activate them, or if ei-

ther section was shut off due to the detection of a mem-

ory error, transmitter underflow, or transmit buffer error

condition. This restriction does not apply to the

Am79C976 device. The memory error and transmit

buffer error conditions cannot occur in the Am79C976

controller and the transmit underflow condition does

not stop the Am79C976 controller’s transmitter.

For compatibility with other PCnet family devices, re-

initialization may be done via the initialization block or

by setting the STOP bit in CSR0, followed by writing to

CSR15, and then setting the STRT bit in CSR0. Note

that this form of restart will not perform the same in the

Am79C976 controller as in the C-LANCE device. In

particular, setting the STRT bit causes the Am79C976

controller to reload the transmit and receive descriptor

pointers with their respective base addresses. This

means that the software must clear the descriptor

OWN bits and reset its descriptor ring pointers before

restarting the Am79C976 controller. The reload of de-

scriptor base addresses is performed in the C-LANCE

device only after initialization, so that a restart of the

C-LANCE without initialization leaves the C-LANCE

pointing at the same descriptor locations as before the

restart.

Run and Suspend

Following reset, the transmitter and receiver of the

Am79C976 controller are disabled, so no descriptor or

data DMA activity will occur. The receiver will process

incoming frames to detect address matches, which are

counted in the RcvMissPkts register. No transmits will

occur except that pause frames may be sent (see flow

control section).

Setting the RUN bit in CMD0 (equivalent to setting

STRT in CSR0) causes the Am79C976 controller to

begin descriptor polling and normal transmit and re-

ceive activity. Clearing the RUN bit (equivalent to set-

ting STOP in CSR0) causes the Am79C976 controller

to halt all transmit, receive, and DMA transfer activities

abruptly.

The Am79C976 controller offers suspend modes that

allow stopping the device with orderly termination of all

network activity. Transmit and receive are controlled

separately.

Setting the RX_FAST_SPND bit in CMD0 suspends re-

ceiver activity after the current frame being received by

the MAC is complete. If no frame is being received

when RX_FAST_SPND is set, the receiver is sus-

pended immediately. After the receiver is suspended,

the RX_SUSPENDED bit in STAT0 is set and SPND-

INT interrupt bit in INT0 is set. Receive data and de-

scriptor DMA activity continues normally while the

receiver is fast suspended.

Setting the RX_SPND bit in CMD0 suspends the re-

ceiver in the same way as RX_FAST_SPND, but the

RX_SUSPENED bit and SPNDINT interrupt bit are

only set after any frames in the receive FIFO have been

completely transferred into system memory and the

corresponding descriptors updated. No receive data or

descriptor DMA activity will occur while the receiver is

suspended.

When the receiver is suspended, no frames will be re-

ceived into the receive FIFO, but frames will be

checked for address match and the RcvMissPkts

counter incremented appropriately, and frames will be

checked for Magic Packet match if Magic Packet mode

is enabled.

Setting the TX_FAST_SPND bit in CMD0 suspends

transmitter activity after the current frame being trans-

mitted by the MAC is complete. If no frame is being

transmitted when TX_FAST_SPND is set, the transmit-

ter is suspended immediately. After the transmitter is

suspended, the TX_SUSPENDED bit in STAT0 is set

and SPNDINT interrupt bit in INT0 is set. Transmit de-

scriptor and data DMA activity continues normally while

the transmitter is fast suspended.

Setting the TX_SPND bit in CMD0 suspends the trans-

mitter in the same way as TX_FAST_SPND, but the

TX_SUSPENDED bit and SPNDINT interrupt bit are

only set after any frames in the transmit FIFO have

been completely transmitted. No transmit descriptor or

data DMA activity will occur while the transmitter is sus-

pended.

When the transmitter is suspended, no frames will be

transmitted except for flow control frames (see Flow

Control section).

It is not meaningful to set both TX_SPND and

TX_FAST_SPND at the same time, nor is it meaningful

to set both RX_SPND and RX_FAST_SPND at the

same time. Doing so will cause unpredictable results.

However, transmit and receive are independent of

each other, so one may be suspended or fast sus-

pended while the other is running, suspended or fast

suspended.

For compatibility with other PCnet family devices, set-

ting the SPND bit in CSR5 with FASTSPNDE in CSR7

cleared is equivalent to setting both TX_SPND and

RX_SPND and clearing SPND with FASTSPNDE

cleared is equivalent to clearing both TX_SPND and

RX_SPND. Similarly, setting SPND with FASTSPNDE

set is equivalent to setting both TX_FAST_SPND and

RX_FAST_SPND and clearing SPND with

FASTSPNDE set is equivalent to clearing both

TX_FAST_SPND and RX_FAST_SPND. While equiv-

alent, these methods are not identical, so software

9/14/00 Am79C976 63

PRELIMINARY

should not mix the CSR5/CSR7 method with the CMD0

method.

For compatibility with other PCnet family devices, after

the SPND bit in CSR5 is set, it will read back a one only

after the suspend operation is complete, that is, after

both TX_SUSPENDED and RX_SUSPENDED in

STAT0 have been set. It is recommended that when

software polls this register that a delay be inserted be-

tween polls. Continuous polling will reduce the bus

bandwidth available to the Am79C976 controller and

will delay the completion of the suspend operation.

It is recommended that software use the SPNDINT in-

terrupt to determine when the Am79C976 controller

has suspended after one or more suspend bits have

been set. This results in the least competition for the

PCI bus and thus the shortest time from setting of a

suspend bit until completion of the suspend operation.

Clearing the RUN bit in CMD0 will generate a pulse that

will clear all the suspend command and status bits

(TX_SPND, RX_SPND, TX_FAST_SPND and

RX_FAST_SPND in CMD0, TX_SUSPENDED and

RX_SUSPENDED in STAT0, SPND in CSR5 and DRX

and DTX in CSR15). The RX_SPND or TX_SPND bits

may then be set while RUN is cleared. When RUN is

subsequently set, the suspend bit will remain set and

the corresponding operation (transmit or receive) will

be disabled. Since the suspend bit will be cleared when

RUN is cleared, this must be done each time RUN is

set. Since the suspend bits and RUN are in the same

same time that RUN is set.

For compatibility with other PCnet family devices, set-

ting the STOP bit in CSR0 will also clear the SPND bit

in CSR5. While STOP is set, the DRX or DTX bits in

CSR15 may be set. When the STRT bit in CSR0 is sub-

sequently set, the corresponding operation will be dis-

abled. Since the bits are all cleared when STOP is set,

CSR15 must be written (either directly or indirectly via

the DMA initialization) each time before STRT is set

again.

The suspend bits in CMD0 and STAT0 are equivalent

but not identical to the suspend bits in CSR5, CSR7

and CSR15. Software should use one set of bits or the

other and not mix them. The SPNDINT bit in INT0 has

no equivalent in the CSR registers, so this bit may be

used to detect the completion of a suspend operation

initiated by the SPND bit in CSR5.

Descriptor Management

Descriptor management is accomplished through mes-

sage descriptor entries organized as ring structures in

memory. There are two descriptor rings, one for trans-

mit and one for receive. Each descriptor describes a

single buffer. A frame may occupy one or more buffers.

If multiple buffers are used, this is referred to as buffer

chaining.

Descriptor Rings

Each descriptor ring must occupy a contiguous area of

memory. During initialization, the user-defined base

address for the transmit and receive descriptor rings,

as well as the number of entries contained in the de-

scriptor rings are set up. The programming of the soft-

ware style (SWSTYLE, BCR20, bits 7-0) affects the

way the descriptor rings and their entries are arranged.

When SWSTYLE is at its default value of 0, the de-

scriptor rings are backwards compatible with the

Am79C90 C-LANCE and the Am79C96x PCnet-ISA

family. The descriptor ring base addresses must be

aligned to 8-byte boundaries. Each ring entry contains

a subset of the three 32-bit transmit or receive mes-

sage descriptors that are organized as four 16-bit

structures (SSIZE32 (BCR20, bit 8) is set to 0). Note

that even though the Am79C976 controller treats the

descriptor entries as 16-bit structures, it will always

perform 32-bit bus transfers to access the descriptor

entries. The value of CSR2, bits 15-8, is used as the

upper 8-bits for all memory addresses during bus mas-

ter transfers.

When SWSTYLE is set to 2, 3, or 4, the descriptor ring

base addresses must be aligned to 16-byte bound-

aries. Each ring entry is organized as three 32-bit mes-

sage descriptors (SSIZE32 (BCR20, bit 8) is set to 1).

The fourth DWord is reserved for user software pur-

poses. When SWSTYLE is set to 3, 4, or 5, the order of

the message descriptors is optimized to allow read and

write access in burst mode.

When SWSTYLE is set to 5, the descriptor ring base

addresses must be aligned to a 32-byte boundary.

Each ring entry is organized as eight 32-bit message

descriptors (SSIZE32 (BCR20, bit 8) is set to 1).

Descriptor ring lengths can be set up either by writing

directly to the transmit and receive ring length registers

(CSR76, CSR78) or by using the initialization block. If

the initialization block is used to set up ring lengths, the

ring lengths are restricted to powers of two that are less

than or equal to 128 if SWSTYLE is 0 or 512 if SW-

STYLE is 2 or 3. However, ring lengths of any size up

to 65535 descriptors can be set up by writing directly to

the transmit and receive ring length registers.

The initialization block can not be used if SWSTYLE is

4 or 5. The descriptor ring lengths must be initialized by

writing directly to the appropriate registers.

Each ring entry contains the following information:

■The address of the actual message data buffer in

user or host memory

64 Am79C976 9/14/00

PRELIMINARY

■The length of the message buffer

■Status information indicating the condition of the

buffer

To permit the queuing and de-queuing of message

buffers, ownership of each buffer is allocated to either

the Am79C976 controller or the host. The OWN bit

within the descriptor status information, either TMD or

RMD, is used for this purpose.

Setting the OWN to 1 signifies that the Am79C976 con-

troller currently has ownership of this ring descriptor

and its associated buffer. Only the owner is permitted

to relinquish ownership or to write to any field in the de-

scriptor entry. A device that is not the current owner of

a descriptor entry cannot assume ownership or change

any field in the entry. A device may, however, read from

a descriptor that it does not currently own. Software

should always read descriptor entries in sequential or-

der. When software finds that the current descriptor is

owned by the Am79C976 controller, then the software

must not read ahead to the next descriptor. The soft-

ware should wait at a descriptor it does not own until

the Am79C976 controller sets OWN to 0 to release

ownership to the software. (When LAPPEN (CSR3, bit

5) is set to 1, this rule is modified. See the LAPPEN de-

scription.

At initialization, the base address of the receive de-

scriptor ring is written to CSR24 (lower 16 bits) and

CSR25 (upper 16 bits), and the base address of the

transmit descriptor ring is written to CSR30 and

CSR31.

Figure 28 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is cleared to 0.

Figure 28. 16-Bit Software Model

Initialization

Block

IADR[15:0]IADR[31:16]

CSR1

CSR2

TDRA[15:0]

MOD

PADR[15:0]

PADR[31:16]

PADR[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLE RES RDRA[23:16]

TLE RES TDRA[23:16]

Rcv

Buffers

RMDO RMD1 RMD2 RMD3

Rcv Descriptor

Ring

NNNN•••

1st

desc. 2nd

desc.

RMD0

Xmt

Buffers

TMD0 TMD1 TMD2 TMD3

Xmt Descriptor

Ring

MMMM•••

1st

desc.

2nd

desc.

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

RLEN

TLEN

9/14/00 Am79C976 65

PRELIMINARY

Note that in this mode the value of CSR2, bits 15-8, is

used as the upper 8-bits for all memory addresses dur-

ing bus master transfers.

Figure 29 illustrates the relationship between the initial-

ization base address, the initialization block, the re-

ceive and transmit descriptor ring base addresses, the

receive and transmit descriptors, and the receive and

transmit data buffers, when SSIZE32 is set to 1.

Figure 29. 32-Bit Software Model

Polling

If there is no network channel activity and there is no

pre- or post-receive or pre- or post-transmit activity

being performed by the Am79C976 controller, then the

Am79C976 controller will periodically poll the current

receive and transmit descriptor entries in order to as-

certain their ownership. If the TXDPOLL bit in CSR4 is

set, then the transmit polling function is disabled. The

Descriptor Management Unit (DMU) is responsible for

these operations.

The Am79C976 controller stores internally the informa-

tion from two or more receive descriptors and two or

more transmit descriptors. Polling operations depend

on the ownership of the current and next receive and

transmit descriptors.

When the poll time has elapsed, if the current receive

descriptor is not owned by the Am79C976 controller or

if the current receive descriptor is owned and the next

receive descriptor is not owned, the unowned descrip-

tor will be polled. Depending on the software style,

more than one descriptor may be read in a burst.

If the TXDPOLL bit is not set and the poll time has

elapsed, or whenever the TDMD bit is set, if the current

transmit descriptor is not owned by the Am79C976

controller, it will be polled. Depending on the software

style, more than one descriptor may be read in a burst.

If either transmit or receive or both are suspended or

disabled due to the setting of TX_SPND, RX_SPND,

SPND, DRX or DTX, the corresponding descriptors will

not be polled. Polling is not affected by fast suspend.

Initialization

Block

CSR1CSR2

RMD0 RMD1 RMD2 RMD3

Rcv Descriptor

Ring

NNNN

•

1st

desc.

start

2nd

desc.

start

RMD0

TMD0 TMD1 TMD2 TMD3

Xmt Descriptor

Ring

MMMM

••

•

1st

desc.

start

2nd

desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

PADR[31:0]

IADR[31:16] IADR[15:0]

TLE

RES

RLE

RES

MODE

PADR[47:32]

RES

LADRF[31:0]

LADRF[63:32]

RDRA[31:0]

TDRA[31:0]

Rcv

Buffers

Xmt

Buffers

RLEN

TLEN

66 Am79C976 9/14/00

PRELIMINARY

Receive descriptor polling will continue even if transmit

polling is disabled by setting TXDPOLL. If at least two

receive descriptors are owned by the Am79C976 con-

troller there will be no descriptor polling if there is no

network activity.

The user may change the poll time value from the de-

fault value by modifying the value in the Transmit Poll-

ing Interval register (CSR47). The default value is

0000h, which corresponds to a polling interval of

65,536 X 3 ERCLK clock periods or 2.185 ms when

ERCLK = 90 MHz.

When the Am79C976 controller is in the process of re-

ceiving a frame and it does not own the next descriptor

or if it is in the process of transmitting a frame that does

not end in the current descriptor and it does not own the

next descriptor, it switches to the chain polling mode in

which the polling interval is determined by the Chain

Polling Interval register (CSR49). Thus, the device can

be programmed to poll at a faster rate when it is about

to run out of buffers.

Transmit Polling

If, after a transmit descriptor access, the Am79C976

controller finds that the OWN bit of that descriptor is not

set, the Am79C976 controller resumes the poll time

count and re-examines the same descriptor at the next

expiration of the poll time count.

If the OWN bit of the descriptor is set, but the Start of

Packet (STP) bit is not set, the Am79C976 controller

will immediately request the bus in order to clear the

OWN bit of this descriptor. After resetting the OWN bit

of this descriptor, the Am79C976 controller will again

immediately request the bus in order to access the next

descriptor in the ring.

If the OWN bit is set and the buffer length is 0, the OWN

bit will be cleared. The Am79C976 controller skips buff-

ers with length of 0, which differs from the C-LANCE

device, which interprets a buffer length of 0 to mean a

4096-byte buffer. For the Am79C976 device a zero

length buffer is acceptable anywhere in the buffer

chain.

If the OWN bit and STP are set, the DMA controller will

start reading data from the current transmit buffer. If the

next transmit descriptor is not already known to be

owned, the Am79C976 controller will interleave a read

of this descriptor into the sequence of data DMA oper-

ations.

If the next transmit descriptor has the OWN bit set, the

Am79C976 controller will complete reading the data

from the current transmit buffer, clear the OWN bit in

the current descriptor and advance the internal ring

pointer to make the next transmit descriptor the new

current transmit descriptor.

The Am79C976 controller returns ownership of trans-

mit descriptors to the software when the DMA transfer

of data from system memory to the Am79C976 control-

ler’s memory is complete. This is different from older

devices in the PCnet family, which will not return the

last transmit descriptor of a frame (the one with

ENP=1) until transmission of the frame is complete.

The Am79C976 controller does not return any status

information in the transmit descriptor, it will only write to

the OWN bit to clear it.

Normally, the driver will set all the OWN bits of a frame

in reverse order so that the Am79C976 controller will

never encounter the situation where the current trans-

mit descriptor has OWN=1 and ENP=0 and the next

transmit descriptor has OWN=0. Older devices in the

PCnet family treat this condition as a fatal error. The

Am79C976 controller allows this mode of operation to

permit DMA of the beginning of a frame before pro-

cessing of the entire frame is complete. The number of

bytes in the first buffer(s) should be less than the trans-

mit start point or the REX_UFLO bit in CMD3 should be

set.

When the Am79C976 controller encounters the condi-

tion of the current transmit descriptor’s OWN=1 and

ENP=0 and the next transmit descriptor’s OWN=0, it

enters the chain polling mode. In this mode, polling of

the descriptor will occur at intervals determined by the

Chain Polling Interval register (CSR49). Setting the

TDMD bit will also cause a poll. Chain polling may be

disabled by setting the CHDPOLL bit in CSR7 or

CMD2. Note that this will also disable chain polling for

receive descriptors.

If underflow occurs due to delays in setting the OWN

bits or excessive bus latency, the transmitter will ap-

pend an inverted FCS field to the frame and will incre-

ment the XmtUnderrunPkts counter. The frame may be

retransmitted (if the REX_UFLO bit in CMD3 is set) or

discarded.

If an error occurs in the transmission that causes the

frame to be discarded (late collision, underflow or retry

failure with the corresponding retry or retransmit option

not enabled) before the entire frame has been trans-

ferred or if the current transmit descriptor has its KILL

bit set, and if current transmit descriptor does not have

its ENP bit set, the Am79C976 controller will skip over

the rest of the frame which experienced the error. The

Am79C976 controller will clear the OWN bit for all de-

scriptors with OWN = 1 and STP = 0 and continue in

like manner until a descriptor with OWN = 0 (no more

transmit frames in the ring) or OWN = 1 and STP = 1

(the first buffer of a new frame) is reached.

At the end of any transmit operation, whether success-

ful or with errors, the Am79C976 controller will always

perform another polling operation, unless the next

transmit descriptor is already known to be owned.

9/14/00 Am79C976 67

PRELIMINARY

By default, whenever the DMA controller finishes copy-

ing a transmit frame from system memory, it sets the

TINT bit of CSR0 to indicate that the buffers are no

longer needed. This causes an interrupt signal if the

IENA bit of CSR0 has been set and the TINTM bit of

CSR3 is cleared.

The Am79C976 controller provides a mode to reduce

the number of transmit interrupts. Setting LTINTEN

(CSR5, bit14) to 1 suppresses interrupts for transmis-

sion of all but the last frame in a sequence.

Receive Polling

If the Am79C976 controller does not own both the cur-

rent and the next receive descriptor, then the

Am79C976 controller will continue to poll according to

the polling sequence described in the Transmit Polling

section. If the receive descriptor ring length is one, then

there is no next descriptor to be polled.

If a poll operation has revealed that the current and the

next receive descriptors belong to the Am79C976 con-

troller, then additional poll accesses are not necessary.

Future poll operations will not include receive descrip-

tor accesses as long as the Am79C976 controller re-

tains ownership of the current and the next receive

descriptors.

When receive activity is present on the channel, the

Am79C976 controller waits until the number of bytes

specified in the RCV_PROTECT register (default 64)

have been received. If the frame is accepted based on

all active addressing schemes at that time, the DMU is

notified that a frame has been received.

As receive buffers become available in system mem-

ory, the DMA controller will copy frame data from the

receive FIFO into system memory. The Am79C976

controller will set the STP bit in the first descriptor of a

frame. If the frame length exceeds the length of the cur-

rent buffer, the Am79C976 controller will pass owner-

ship back to the system by writing 0s to the OWN and

ENP bits of the descriptor when the first buffer is full.

This activity continues until the Am79C976 controller

recognizes the completion of the frame (the last byte of

this receive message has been removed from the

FIFO). The Am79C976 controller will subsequently up-

date the current receive descriptor with the frame sta-

tus (message byte count, VLAN info, frame tag, error

flags, etc.) and will set the ENP bit to 1. The Am79C976

controller will then advance the internal ring pointer to

make the next receive descriptor the new current re-

ceive descriptor.

When the Am79C976 controller has receive data in the

FIFO ready to write to system memory, either at the be-

ginning of a new frame or in the middle of a frame that

does not fit in the previous buffer, and it does not own

the current receive descriptor, it will immediately poll it.

If the OWN bit is still zero, polling of this descriptor will

continue at a rate determined by the contents of the

CHPOLLINT register (CSR49). Polling will occur imme-

diately if the RDMD bit is set.

If the driver does not provide the Am79C976 controller

with a descriptor in a timely fashion, the receive FIFO

will eventually overflow. Subsequent frames will be dis-

carded and the RcvMissPkts MIB counter will be incre-

mented. Normal receive operation will resume when a

descriptor is provided to the Am79C976 controller and

sufficient data has been DMA’ed from the Am79C976

controller’s receive FIFO into the system memory.

When the receive FIFO is empty and the Am79C976

device does not own two descriptors (current and

next), the Receive Descriptor Ring is polled at an inter-

val by the contents of the TXPOLLINT register

(CSR47). When the Am79C976 device owns two de-

scriptors, the Receive Descriptor Ring is not polled at

all.

Look Ahead Packet Processing

Setting LAPPEN (CMD2, bit 2 or CSR3, bit 5) to a 1

modifies the way the controller processes receive de-

scriptors. The Am79C976 controller will use the STP

information to determine where it should begin writing

a receive packet’s data. Note that while in this mode,

the Am79C976 controller can write intermediate packet

data to buffers whose descriptors do not contain STP

bits set to 1. Following the write to the last descriptor

used by a packet, the Am79C976 controller will scan

through the next descriptor entries to locate the next

STP bit that is set to a 1. The Am79C976 controller will

begin writing the next packet’s data to the buffer

pointed to by that descriptor.

Note that because several descriptors may be allo-

cated by the host for each packet and not all messages

may need all of the descriptors that are allocated be-

tween descriptors containing STP = 1, then some de-

scriptors/buffers may be skipped in the ring. While

performing the search for the next STP bit that is set to

1, the Am79C976 controller will advance through the

receive descriptor ring regardless of the state of own-

ership bits. If any of the entries that are examined dur-

ing this search indicate Am79C976 controller

ownership of the descriptor but also indicate STP = 0,

then the Am79C976 controller will reset the OWN bit to

0 in these entries. If a scanned entry indicates host

ownership with STP = 0, then the Am79C976 controller

will not alter the entry, but will advance to the next entry.

When the STP bit is found to be true, but the descriptor

that contains this setting is not owned by the

Am79C976 controller, then the Am79C976 controller

will stop advancing through the ring entries and begin

periodic polling of this entry. When the STP bit is found

to be true, and the descriptor that contains this setting

is owned by the Am79C976 controller, then the

Am79C976 controller will stop advancing through the

68 Am79C976 9/14/00

PRELIMINARY

ring entries, store the descriptor information that it has

just read, and wait for the next receive to arrive.

This behavior allows the host software to pre-assign

buffer space in such a manner that the header portion

of a receive packet will always be written to a particular

memory area, and the data portion of a receive packet

will always be written to a separate memory area. The

interrupt is generated when the header bytes have

been written to the header memory area.

Software Interrupt Timer

The Am79C976 controller is equipped with a software

programmable free-running interrupt timer. The timer is

constantly running and will generate an interrupt STINT

(CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to

1. After generating the interrupt, the software timer will

load the value stored in STVAL and restart. The timer

value STVAL (BCR31, bits 15-0) is interpreted as an

unsigned number with a resolution of 10.24µs. For in-

stance, a value of 98 (62h) corresponds to 1.0 ms. The

default value of STVAL is FFFFh which corresponds to

0.671 seconds. A write to STVAL restarts the timer with

the new contents of STVAL.

Media Access Control

The Media Access Control (MAC) engine incorporates

the essential protocol requirements for operation of an

Ethernet/IEEE 802.3-compliant node and provides the

interface between the FIFO subsystem and the MII.

This section describes operation of the MAC engine

when operating in half-duplex mode. The operation of

the device in full-duplex mode is described in the sec-

tion titled Full-Duplex Operation.

The MAC engine is fully compliant to Section 4 of IEEE

Std 802.3, 1998 Edition.

The MAC engine provides programmable enhanced

features designed to minimize host supervision, bus

utilization, and pre- or post-message processing.

These features include the ability to disable retries after

a collision, dynamic FCS generation on a frame-by-

frame basis, automatic pad field insertion and deletion

to enforce minimum frame size attributes, automatic re-

transmission without reloading the FIFO, and auto-

matic deletion of collision fragments. The MAC also

provides a mechanism for automatically inserting, de-

leting, and modifying IEEE 802.3ac VLAN tags.

The two primary attributes of the MAC engine are:

■Transmit and receive message data encapsulation

—Framing (frame boundary delimitation, frame

synchronization)

—Addressing (source and destination address

handling)

—Error detection (physical medium transmission

errors)

■Media access management

—Medium allocation (collision avoidance, except

in full-duplex operation)

—Contention resolution (collision handling, except

in full-duplex operation)

Transmit and Receive Message Data Encapsulation

The MAC engine provides minimum frame size en-

forcement for transmit and receive frames. When

APAD_XMT (CSR4, bit 11) is set to 1, transmit mes-

sages will be padded with sufficient bytes (containing

00h) to ensure that the receiving station will observe an

information field (destination address, source address,

length/type, data, and FCS) of 64 bytes. When

ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will

automatically strip pad bytes from the received mes-

sage by observing the value in the length field and by

stripping excess bytes if this value is below the mini-

mum data size (46 bytes). Both features can be inde-

pendently over-ridden to allow illegally short (less than

64 bytes of frame data) messages to be transmitted

and/or received. The use of this feature reduces bus

utilization because the pad bytes are not transferred

into or out of main memory.

Framing

The MAC engine will autonomously handle the con-

struction of the transmit frame. Once the transmit FIFO

has been filled to the predetermined threshold (set by

XMTSP in CSR80) and access to the channel is cur-

rently permitted, the MAC engine will commence the

7-byte preamble sequence (10101010b, where first bit

transmitted is a 1). The MAC engine will subsequently

append the Start Frame Delimiter (SFD) byte

(10101011b) followed by the serialized data from the

transmit FIFO. Once the data has been transmitted, the

MAC engine will append the FCS (most significant bit

first) which was computed on the entire data portion of

the frame. The data portion of the frame consists of

destination address, source address, length/type, and

frame data. The user is responsible for the correct or-

dering and content in each of these fields in the frame.

The MAC does not use the content in the length/type

field unless APAD_XMT (CSR4, bit 11) is set and the

data portion of the frame is shorter than 60 bytes.

The receiver section of the MAC engine will detect the

incoming preamble sequence when the RX_DV signal

is activated by the external PHY. The MAC will discard

the preamble and begin searching for the SFD except

in the case of 100BASE-T4, for which there is no pre-

9/14/00 Am79C976 69

PRELIMINARY

amble. In that case, the SFD will be the first two nibbles

received. Once the SFD is detected, all subsequent

nibbles are treated as part of the frame. The MAC en-

gine will inspect the length field to ensure minimum

frame size, strip unnecessary pad characters (if auto-

matic pad stripping is enabled), and pass the remaining

bytes through the receive FIFO to the host. If pad strip-

ping is performed, the MAC engine will also strip the re-

ceived FCS bytes, although normal FCS computation

and checking will occur. Note that apart from pad strip-

ping, the frame will be passed unmodified to the host.

If the length field has a value of 46 or greater, all frame

bytes including FCS will be passed unmodified to the

receive buffer, regardless of the actual frame length.

If the frame terminates or suffers a collision before 64

bytes of information (after SFD) have been received,

the MAC engine will automatically delete the frame

from the receive FIFO, without host intervention. The

Am79C976 controller has the ability to accept runt

packets for diagnostic purposes and proprietary net-

works.

Destination Address Handling

The first 6 bytes of information after SFD will be inter-

preted as the destination address field. The MAC en-

gine provides facilities for physical (unicast), logical

(multicast), and broadcast address reception.

Error Detection

The MAC engine provides several facilities which count

and recover from errors on the medium. In addition, it

protects the network from gross errors due to inability

of the host to keep pace with the MAC engine activity.

On completion of transmission, the MAC engine up-

dates various counters that are described in the Statis-

tics Counters section. The host CPU can read these

counters at any time for network management pur-

poses.

The MAC engine also attempts to prevent the creation

of any network error due to the inability of the host to

service the MAC engine. During transmission, if the

host fails to keep the transmit FIFO filled sufficiently,

causing an underflow, the MAC engine will guarantee

the message is sent with an invalid FCS, which will

cause the receiver to reject the message.

The MAC engine can be programmed to try to transmit

the same frame again after a FIFO underflow or exces-

sive collision error.

The status of each receive message is available in the

appropriate Receive Message Descriptor (RMD). All

received frames are passed to the host regardless of

any error.

During the reception, the FCS is generated on every

nibble (including the dribbling bits) coming from the MII,

although the internally saved FCS value is only up-

dated on each byte boundary. The MAC engine will ig-

nore an extra nibble at the end of a message, which

corresponds to dribbling bits on the network medium. A

framing or alignment error is reported to the user if an

FCS error is detected and there is an extra nibble in the

message. If there is an extra nibble but no FCS error,

no framing error is reported.

Media Access Management

The basic requirement for all stations on the network is

to provide fairness of channel allocation. The IEEE

802.3/Ethernet protocols define a media access mech-

anism which permits all stations to access the channel

with equality. Any node can attempt to contend for the

channel by waiting for a predetermined time (Inter

Packet Gap) after the last activity, before transmitting

on the media. The channel is a multidrop communica-

tions media (with various topological configurations

permitted), which allows a single station to transmit and

all other stations to receive. If two nodes simulta-

neously contend for the channel, their signals will inter-

act causing loss of data, defined as a collision. It is the

responsibility of the MAC to attempt to avoid and to re-

cover from collisions.

Medium Allocation

The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990)

requires that the CSMA/CD MAC monitor the medium

for traffic by watching for carrier activity. When carrier

is detected, the media is considered busy, and the

MAC should defer to the existing message.

The ISO 8802-3 (IEEE/ANSI 802.3) standard allows an

optional two-part deferral after a receive message.

See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:

Note: It is possible for the PLS carrier sense indication

to fail to be asserted during a collision on the media. If

the deference process simply times the inter-Frame

gap based on this indication, it is possible for a short in-

terFrame gap to be generated, leading to a potential re-

ception failure of a subsequent frame. To enhance

system robustness, the following optional measures,

as specified in 4.2.8, are recommended when Inter-

Frame-SpacingPart1 is other than 0:

1. Upon completing a transmission, start timing the in-

terrupted gap, as soon as transmitting and carrier

sense are both false.

2. When timing an inter-frame gap following reception,

reset the inter-frame gap timing if carrier sense be-

comes true during the first 2/3 of the inter-frame gap

timing interval. During the final 1/3 of the interval,

the timer shall not be reset to ensure fair access to

the medium. An initial period shorter than 2/3 of the

interval is permissible including 0.

The MAC engine implements the optional receive two

part deferral algorithm, with an InterFrameSpacing-

70 Am79C976 9/14/00

PRELIMINARY

Part1 (IFS1) time of 60 bit times and an Inter-

FrameSpacingPart 2 time of 36 bit times.

The Am79C976 controller will perform the two-part de-

ferral algorithm as specified in Clause 4.2.8 of IEEE

Std 802.3 (Process Deference). The Inter Packet Gap

(IPG) timer will start timing the 96-bit InterFrameSpac-

ing after the receive carrier is deasserted.

During the first part deferral (InterFrameSpacingPart1 -

IFS1), the Am79C976 controller will defer any pending

transmit frame and respond to the receive message. If

carrier sense or collision is detected during the first part

of the gap, the IPG counter will be cleared to 0 contin-

uously until carrier sense and collision are both deas-

serted, at which point the IPG counter will resume the

96-bit time count once again. Once the IPG counter

reaches the IFS1 count (60-bit times), the Am79C976

controller will not defer to a receive frame if a transmit

frame is pending. Instead, when the IPG count reaches

96-bit times, the transmitter will start transmitting,

which will cause a collision. The Am79C976 controller

will complete the preamble (64-bit) and jam (32-bit) se-

quence before ceasing transmission and invoking the

random backoff algorithm.

The Am79C976 controller allows the user to program

both the IPG and the first part deferral (InterFrame-

SpacingPart1 - IFS1) through CSR125. The user can

change the IPG value from its default of 96-bit times to

compensate for delays through the external PHY de-

vice. Changing IFS1 will alter the period for which the

Am79C976 MAC engine will defer to incoming receive

frames.

CAUTION: Care must be exercised when altering

these parameters. Undesirable network activity

could result!

This transmit two-part deferral algorithm is imple-

mented as an option which can be disabled using the

DXMT2PD bit in CSR3. When DXMT2PD is set to 1,

the IFS1 register is ignored, and the value 0 is used for

the Inter FrameSpacingPart1 parameter. However, the

IPG value is still valid.

When the Am79C976 device operates in full-duplex

mode, the IPG timer starts counting when TX_EN is

de-asserted. CRS is ignored in full-duplex mode.

Signal Quality Error (SQE) Test

During the time period immediately after a transmission

has been completed, an external transceiver operating

in the 10 Mb/s half-duplex mode should generate an

SQE Test signal on the COL pin within 0.6 µs to 1.6 µs

after the transmission ceases. Therefore, when the

Am79C976 controller is operating in half-duplex mode,

the IPG counter ignores the COL signal during the first

40-bit times of the inter-packet gap. This 40-bit times is

the time period in which the SQE Test message is ex-

pected.

The SQE Test was originally designed to check the in-

tegrity of the Collision Detection mechanism indepen-

dently of the Transmit and Receive capabilities of the

Physical Layer. However, MII-based PHY devices de-

tect collisions by sensing receptions that occur during

transmissions, a process that does not require a sepa-

rate level-sensing collision detection mechanism. Col-

lision detection is therefore dependent on the health of

the receive channel. Since the Link Monitor function

checks the health of the receive channel, the SQE test

is not very useful for MII-based devices. Therefore, the

Am79C976 device does not report or count SQE Test

failures.

Collision Handling

Collision detection is performed and reported to the

MAC engine via the COL input pin. Since the COL sig-

nal is not required to be synchronized with TX_CLK,

the COL signal must be asserted for at least three

TX_CLK cycles in order to be detected reliably.

If a collision is detected before the complete preamble/

SFD sequence has been transmitted, the MAC engine

will complete the preamble/SFD before appending the

jam sequence. If a collision is detected after the pream-

ble/SFD has been completed, but prior to 512 bits

being transmitted, the MAC engine will abort the trans-

mission and append the jam sequence immediately.

The jam sequence is a 32-bit all zeros pattern.

The MAC engine will attempt to transmit a frame a total

of 16 times (initial attempt plus 15 retries) due to normal

collisions (those within the slot time). Detection of colli-

sion will cause the transmission to be rescheduled to a

time determined by the random backoff algorithm. If a

single retry was required, the XmtOneCollision counter

will be incremented. If more than one retry was re-

quired, the XmtMultipleCollision counter will be incre-

mented. If all 16 attempts experienced collisions, the

XmtExcessiveCollision counter will be incremented.

After an excessive collision error, if REX_RTRY

(CMD3, bit 18) is cleared to 0, the transmit message

will be flushed from the FIFO. If the REX_RTRY bit is

set to 1, the transmitter will not flush the transmit mes-

sage from the FIFO. Instead, it will clear the back-off

logic and will restart the transmission process, treating

the data in the FIFO as a new frame.

If retries have been disabled by setting the DRTY bit in

CSR15, the MAC engine will abandon transmission of

the frame on detection of the first collision. In this case,

XmtExcessiveCollision counter will be incremented,

and the transmit message will be flushed from the

FIFO.

If a collision is detected after 512-bit times have been

transmitted, the collision is termed a late collision. The

MAC engine will abort the transmission, append the

jam sequence, and increment the XmtLateCollision

counter. If RTRY_LCOL (CMD3, bit 16) is set to 1, the

9/14/00 Am79C976 71

PRELIMINARY

retry logic treats late collisions just like normal colli-

sions. However, if the RTRY_LCOL bit is cleared to 0,

no retry attempt will be scheduled on detection of a late

collision. In this case, the transmit message will be

flushed from the FIFO.

The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires

use of a “truncated binary exponential backoff” algo-

rithm, which provides a controlled pseudo random

mechanism to enforce the collision backoff interval, be-

fore retransmission is attempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming), the

CSMA/CD sublayer delays before attempting to re-

transmit the frame. The delay is an integer multiple

of slot time. The number of slot times to delay be-

fore the nth retransmission attempt is chosen as a

uniformly distributed random integer r in the range:

0 < r < 2k where k = min (n,10).”

The Am79C976 controller provides an alternative algo-

rithm, which suspends the counting of the slot time/IPG

during the time that receive carrier sense is detected.

This aids in networks where large numbers of nodes

are present, and numerous nodes can be in collision. It

effectively accelerates the increase in the backoff time

in busy networks and allows nodes not involved in the

collision to access the channel, while the colliding

nodes await a reduction in channel activity. Once chan-

nel activity is reduced, the nodes resolving the collision

time-out their slot time counters as normal.

This modified backoff algorithm is enabled when EMBA

(CSR3, bit 3) is set to 1.

Transmit Operation

The transmit operation and features of the Am79C976

controller are controlled by programmable options. The

Am79C976 controller provides a large transmit FIFO to

provide frame buffering for increased system latency,

automatic retransmission with no FIFO reload, and au-

tomatic transmit padding.

Transmit Function Programming

Automatic transmit features such as retry on collision,

FCS generation/transmission, and pad field insertion

can all be programmed to provide flexibility in the (re-)

transmission of messages.

Disable retry on collision (DRTY) is controlled by the

DRTY bit of the Mode register (CSR15) in the initializa-

tion block.

Automatic pad field insertion is controlled by the

APAD_XMT bit in CSR4.

The disable FCS generation/transmission feature can

be programmed as a static feature or dynamically on a

frame-by-frame basis.

REX_RTRY (CMD3, bit 18) and REX_UFLO (CMD3,

bit 17) can be programmed to cause the transmitter to

automatically restart the transmission process instead

of discarding a frame that experiences an excessive

collisions or underflow error. In this case the retrans-

mission will not begin until the entire frame has been

loaded into the transmit FIFO. The RTRY_LCOL bit

(CMD3, bit 16) can be programmed either to drop a

frame after a late collision or to treat late collisions just

like normal collisions.

Transmit FIFO Watermark (XMTFW) in CSR80 sets

the point at which the controller requests more data

from the transmit buffers for the FIFO. A minimum of

XMTFW empty spaces must be available in the trans-

mit FIFO before the controller will request the system

bus in order to transfer transmit frame data into the

transmit FIFO.

Transmit Start Point (XMTSP) in CSR80 sets the point

when the transmitter actually attempts to transmit a

frame onto the media. A minimum of XMTSP bytes

must be written to the transmit FIFO for the current

frame before transmission of the current frame will be-

gin. (When automatically padded packets are being

sent, it is conceivable that the XMTSP is not reached

when all of the data has been transferred to the FIFO.

In this case, the transmission will begin when all of the

frame data has been placed into the transmit FIFO.)

The default value of XMTSP is 01b, meaning there has

to be 64 bytes in the transmit FIFO to start a transmis-

sion.

In order to ensure that collisions occurring within 512-

bit times from the start of transmission (including pre-

amble) will be automatically retried with no host inter-

vention, the transmit FIFO ensures that data contained

within the FIFO will not be overwritten until at least 64

bytes (512 bits) of preamble plus address, length, and

data fields have been transmitted onto the network

without encountering a collision. If the REX_RTRY bit

or the REX_UFLO bit is set, the transmit data will not

be overwritten until the frame has been either transmit-

ted or discarded.

Automatic Pad Generation

Transmit frames can be automatically padded to ex-

tend them to 64 data bytes (excluding preamble). This

allows the minimum frame size of 64 bytes (512 bits)

for IEEE 802.3/Ethernet to be guaranteed with no soft-

ware intervention from the host/controlling process.

Setting the APAD_XMT bit in CSR4 enables the auto-

matic padding feature. The pad is placed between the

LLC data field and FCS field in the IEEE 802.3 frame.

FCS is always added if the frame is padded, regardless

of the state of DXMTFCS (CSR15, bit 3) or ADD_FCS

72 Am79C976 9/14/00

PRELIMINARY

(TMD1, bit 29). The transmit frame will be padded by

bytes with the value of 00H. The default value of

APAD_XMT is 0 after H_RESET, which will disable au-

tomatic pad generation.

If automatic pad generation is disabled, the software is

responsible for insuring that the minimum frame size

requirement is met. The hardware can reliably transmit

frames ranging in size from 16 to 65536 octets.

It is the responsibility of upper layer software to cor-

rectly define the actual length/type field contained in

the message to correspond to the total number of LLC

Data bytes encapsulated in the frame (length/type field

as defined in the IEEE 802.3 standard). The length

value contained in the message is not used by the

Am79C976 controller to compute the actual number of

pad bytes to be inserted. The Am79C976 controller will

append pad bytes dependent on the actual number of

bits transmitted onto the network. Once the last data

byte of the frame has completed, prior to appending the

FCS, the Am79C976 controller will check to ensure

that 544 bits have been transmitted. If not, pad bytes

are added to extend the frame size to this value, and

the FCS is then added. See Figure 30.

Figure 30. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame

The 544 bit count is derived from the following:

Minimum frame size (excluding preamble/SFD,

including FCS) 64 bytes 512 bits

Preamble/SFD size 8 bytes 64 bits

FCS size 4 bytes 32 bits

At the point that FCS is to be appended, the transmitted

frame should contain:

Preamble/SFD + (Min Frame Size - FCS)

64 + (512-32) = 544 bits

A minimum length transmit frame from the Am79C976

controller, therefore, will be 576 bits, after the FCS is

appended.

Transmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame depends on the value of DXMTFCS

(CSR15, bit 3). If DXMTFCS is cleared to 0, the trans-

mitter will generate and append the FCS to the trans-

mitted frame. If the transmitter modifies the frame data

because of automatic padding or VLAN tag manipula-

tion, the FCS will be appended by the Am79C976 con-

troller regardless of the state of DXMTFCS or

ADD_FCS (TMD1, bit 29). Note that the calculated

FCS is transmitted most significant bit first. The default

value of DXMTFCS is 0 after H_RESET.

When DXMTFCS is set to 1, the ADD_FCS (TMD1, bit

29) allows the automatic generation and transmission

of FCS on a frame-by-frame basis. When DXMTFCS is

set to 1, a valid FCS field is appended only to those

frames whose TX descriptors have their ADD_FCS bits

set to 1. If a frame is split into more than one buffer, the

ADD_FCS bit is ignored in all descriptors except for the

first.

Transmit Error Conditions

The Am79C976 transmitter detects the following error

conditions and increments the appropriate error

counters when they occur:

■Loss of carrier

■Late collision

■Transmit FIFO Underflow

Late collision errors can only occur when the device is

operating in half-duplex mode. Loss of carrier and

transmit FIFO underflow errors are possible when the

device is operating in half- or full-duplex mode.

When an error occurs in the middle of a multi-buffer

frame transmission, the appropriate error counter will

be incremented, and the transmission will be aborted

with an inverted FCS field appended to the frame. The

OWN bit(s) in the current and subsequent descriptor(s)

will be cleared until the STP (the next frame) is found.

If REX_UFLO (CMD3, bit 17) is set, the transmitter will

not flush the frame data from the transmit FIFO after a

Preamble

1010....1010

SFD

10101011

Destination

Address

Source

Address

Length/

Type

LLC

Data Pad FCS

Bytes

46 – 1500

Bytes

Bits

9/14/00 Am79C976 73

PRELIMINARY

transmit FIFO underflow error occurs. Instead, it will

wait until the entire frame has been copied into the

transmit FIFO, and then it will restart the transmission

process.

Loss of Carrier

The XmtLossCarrier counter is incremented if transmit

is attempted when the LINK_STAT bit in the STAT0 reg-

ister is 0.

Late Collision

A late collision will be detected when the device is op-

erating in half-duplex mode and a collision condition

occurs after one slot time (512 bit times) after the trans-

mit process was initiated (first bit of preamble com-

menced). When it detects a late collision, the

Am79C976 controller will increment the XmtLateColli-

sion counter. If RTRY_LCOL (CMD3, bit 16) is cleared

to 0, the controller will abandon the transmit process for

that frame, and process the next transmit frame in the

ring. If the RTRY_LCOL bit is set to 1, transmission at-

tempts that incur late collisions will be retried up to a

maximum of 16 attempts.

Transmit FIFO Underflow

An underflow error occurs when the transmitter runs

out of data from the transmit FIFO in the middle of a

transmission. When this happens, an inverted FCS is

appended to the frame so that the intended receiver

will ignore the frame, and the XmtUnderrunPkts

counter is incremented. If REX_UFLO (CMD3, bit 17)

is set to 1, the transmitter will then wait until the entire

frame has been loaded into the transmit FIFO, and

then it will restart the transmission of the same frame.

If the REX_UFLO is cleared to 0, the transmitter will not

attempt to retransmit the aborted frame.

Receive Operation

The receive operation and features of the Am79C976

controller are controlled by programmable options. The

Am79C976 controller uses a large receive FIFO to pro-

vide frame buffering for increased system latency, au-

tomatic flushing of collision fragments (runt packets),

automatic receive pad stripping, and a variety of ad-

dress match options.

Receive Function Programming

Automatic pad field stripping is enabled by setting the

ASTRP_RCV bit in CSR4. This can provide flexibility in

the reception of messages using the IEEE 802.3 frame

format.

The device can be programmed to accept all receive

frames regardless of destination address by setting the

PROM bit in CSR15. Acceptance of unicast and broad-

cast frames can be individually turned off by setting the

DRCVPA or DRCVBC bits in CSR15. The Physical Ad-

dress register (CSR12 to CSR14) stores the address

that the Am79C976 controller compares to the destina-

tion address of the incoming frame for a unicast ad-

dress match. The Logical Address Filter register

(CSR8 to CSR11) serves as a hash filter for multicast

address match.

The point at which the controller will start to transfer

data from the receive FIFO to buffer memory is con-

trolled by the RCVFW bits in CSR80. The default es-

tablished during H_RESET is 01b, which sets the

watermark flag at 64 bytes filled.

For test purposes, the Am79C976 controller can be

programmed to accept runt packets of 12 bytes or

larger by setting RPA in CSR124.

Address Matching

The Am79C976 controller supports three types of ad-

dress matching: unicast, multicast, and broadcast. The

normal address matching procedure can be modified

by programming three bits in CSR15, the mode register

(PROM, DRCVPA, and DRCVBC).

If the first bit received after the SFD (the least signifi-

cant bit of the first byte of the destination address field)

is 0, the frame is unicast, which indicates that the frame

is meant to be received by a single node. If the first bit

received is 1, the frame is multicast, which indicates

that the frame is meant to be received by a group of

nodes. If the destination address field contains all 1s,

the frame is broadcast, which is a special type of multi-

cast. Frames with the broadcast address in the desti-

nation address field are meant to be received by all

nodes on the local area network.

When a unicast frame arrives at the Am79C976 con-

troller, the controller will accept the frame if the destina-

tion address field of the incoming frame exactly

matches the 6-byte station address stored in the Phys-

ical Address registers (PADR, CSR12 to CSR14). The

byte ordering is such that the first byte received from

the network (after the SFD) must match the least signif-

icant byte of CSR12 (PADR[7:0]), and the sixth byte re-

ceived must match the most significant byte of CSR14

(PADR[47:40]).

When DRCVPA (CSR15, bit 13) is set to 1, the

Am79C976 controller will not accept unicast frames.

If the incoming frame is multicast, the Am79C976 con-

troller performs a calculation on the contents of the

destination address field to determine whether or not to

accept the frame. This calculation is explained in the

section that describes the Logical Address Filter

(LADRF).

When all bits of the LADRF registers are 0, no multicast

frames are accepted, except for broadcast frames.

Although broadcast frames are classified as special

multicast frames, they are treated differently by the

Am79C976 controller hardware. Broadcast frames are

74 Am79C976 9/14/00

PRELIMINARY

always accepted, except when DRCVBC (CSR15, bit

14) is set. DRCVBC overrides a logical address match.

If DRCVBC is set to 1, broadcast frames are not ac-

cepted even if the Logical Address Filter is pro-

grammed in such a way that a Broadcast frame would

pass the hash filter.

None of the address filtering described above applies

when the Am79C976 controller is operating in the pro-

miscuous mode. In the promiscuous mode, all properly

formed packets are received, regardless of the con-

tents of their destination address fields. The promiscu-

ous mode overrides the Disable Receive Broadcast bit

(DRCVBC bit Am79C976 in the MODE register) and

the Disable Receive Physical Address bit (DRCVPA,

CSR15, bit 13).

The Am79C976 controller operates in promiscuous

mode when PROM (CSR15, bit 15) is set.

In addition, the Am79C976 controller provides the Ex-

ternal Address Detection Interface (EADI) to allow ex-

ternal address filtering. See the External Address

Detection Interface section for further details.

The receive descriptor entry RMD1 contains three bits

that indicate which method of address matching

caused the Am79C976 controller to accept the frame.

Note that these indicator bits are not available when

the Am79C976 controller is programmed to use 16-bit

structures for the descriptor entries (BCR20, bit 7-0,

SWSTYLE is set to 0).

PAM (RMD1, bit 22) is set by the Am79C976 controller

when it accepts the received frame due to a match of

the frame’s destination address with the content of the

physical address register.

LAFM (RMD1, bit 21) is set by the Am79C976 control-

ler when it accepts the received frame based on the

value in the logical address filter register.

BAM (RMD1, bit 20) is set by the Am79C976 controller

when it accepts the received frame because the

frame’s destination address is of the type ’Broadcast’.

Only BAM, but not LAFM, will be set when a Broadcast

frame is received, even if the Logical Address Filter is

programmed in such a way that a Broadcast frame

would pass the hash filter.

When the Am79C976 controller operates in promiscu-

ous mode and none of the three match bits is set, it is

an indication that the Am79C976 controller only ac-

cepted the frame because it was in promiscuous mode.

When the Am79C976 controller is not programmed to

be in promiscuous mode, but the EADI interface is

used and when none of the three match bits is set, it is

an indication that the Am79C976 controller only ac-

cepted the frame because it was not rejected by driving

the EAR pin LOW during the receive protect time. The

length of receive protect period can be programmed in

the Receive Protect Register.

See Table 6 for receive address matches.

Table 6. Receive Address Match

Automatic Pad Stripping

During reception of an IEEE 802.3 frame, the pad field

can be stripped automatically. Setting ASTRP_RCV

(CSR4, bit 10) to 1 enables the automatic pad stripping

feature. The pad field will be stripped before the frame

is passed to the FIFO, thus preserving FIFO space for

additional frames. The FCS field will also be stripped,

since it is computed at the transmitting station based on

the data and pad field characters, and will be invalid for

a receive frame that has had the pad characters

stripped.

The number of bytes to be stripped is calculated from

the embedded length field (as defined in the ISO 8802-

3 (IEEE/ANSI 802.3) definition) contained in the frame.

The length indicates the actual number of LLC data

bytes contained in the message. Any received frame

which contains a length field less than 46 bytes will have

the pad field stripped (if ASTRP_RCV is set). Receive

frames which have a length field of 46 bytes or greater

will be passed to the host unmodified.

Figure 31 shows the byte/bit ordering of the received

length field for an IEEE 802.3-compatible frame format.

PAM LAFM BAM Comment

000

Frame accepted due to

PROM = 1 or no EADI

reject

1 0 0 Physical address match

010

Logical address filter

match;

frame is not of type

broadcast

0 0 1 Broadcast frame

9/14/00 Am79C976 75

PRELIMINARY

Figure 31. IEEE 802.3 Frame and Length Field Transmission Order

Since any valid Ethernet Type field value will always be

greater than a normal IEEE 802.3 Length field (>46),

the Am79C976 controller will not attempt to strip valid

Ethernet frames. Note that for some network protocols,

the value passed in the Ethernet Type and/or IEEE

802.3 Length field is not compliant with either standard

and may cause problems if pad stripping is enabled.

Receive FCS Checking

Reception and checking of the received FCS is per-

formed automatically by the Am79C976 controller.

Note that if the Automatic Pad Stripping feature is en-

abled, the FCS for padded frames will be verified

against the value computed for the incoming bit stream

including pad characters, but the FCS value for a pad-

ded frame will not be passed to the host. If an FCS

error is detected in any frame, the error will be reported

in the CRC bit in the Receive Descriptor.

Receive Exception Conditions

Exception conditions for frame reception fall into two

categories, i.e., those conditions which are the result of

normal network operation, and those which occur due

to abnormal network and/or host related events.

Normal exception events are caused by collisions,

which can distort and truncate received frames.

Frames shorter than 64 bytes will, by default, be dis-

carded. These fragments will be discarded regardless

of whether the receive frame was the first (or only)

frame in the FIFO or if the receive frame was queued

behind a previously received message.

There are two control bits that can be used to cause the

MAC to override normal behavior and accept all frames

that pass address match, regardless of the frame

length. Setting the Runt Packet Accept (RPA) bit

(CMD2, bit 19) causes the MAC to accept runt packets

when the device is operating in either half- or full-du-

plex mode. Setting Full-Duplex Runt Packet Accept

(FDRPA, CMD2, bit 20) causes the MAC to accept runt

packets when the device is operating in full-duplex

mode. (When the value of RPA is 1, runt packets are

accepted regardless of the duplex mode or the value of

FDRPA.) In either case, there is a minimum frame size

of 16 bytes. Frames shorter than this may not be ac-

cepted, regardless of the value of RPA or FDRPA.

Abnormal network conditions include:

■FCS errors

■Framing errors

■Receiver overflow events

These error conditions are reported in the correspond-

ing receive descriptors. The RcvFCSErrors, RcvAlign-

mentErrors, or RcvMissPkts counter is also

incremented when one of these events occurs.

Statistics Counters

In order to provide network management information

with minimum host CPU overhead, the Am79C976 de-

vice automatically maintains a set of 32-bit controller

statistics counters. These counters are mapped di-

Preamble

1010....1010

SFD

10101011

Destination

Address

Source

Address Length LLC

Data Pad FCS

Bytes

46 – 1500

Bytes

Bits

Start of Frame

at Time = 0

Increasing Time

Bit

Most

Significant

Byte

Least

Significant

Byte

1 – 1500

Bytes

45 – 0

Bytes

76 Am79C976 9/14/00

PRELIMINARY

rectly into PCI memory space and can not be accessed

indirectly through the RAP and RDP registers.

To simplify the use of software debuggers, the counter

logic is designed so that the statistics counters can be

accessed one, two, or four bytes at a time. When a por-

tion of a statistics counter is read, the entire 32 bits of

the counter is loaded into an internal holding register in

a single atomic operation. When the CPU reads one or

more bytes from the same counter, the data are read

from the holding register rather than from the counter.

The holding register is updated when either a read ac-

cess is made to a different counter or a byte of the

same counter is read for a second time.

Write access to statistics counters is provided for de-

bugging purposes only. No holding register is used for

write accesses. Writing one or two bytes at a time to a

statistics counter while the network is active can cause

unpredictable results.

The contents of the entire set of statistics counters can

be cleared to zero by setting the INIT_MIB bit (CMD3,

bit 25). The counters will be cleared within approxi-

mately 55 ERCLK cycles after the INIT_MIB bit is set.

Receive Statistics Counters

The receive statistics counters are defined and the

Management Information Base (MIB) objects that they

support are listed in Table 7.

For these counters, the definition of a valid frame de-

pends on the state of the JUMBO and VSIZE bits

(CMD3, bits 21 and 20) as follows:

If JUMBO = 1, valid frames are frames that are be-

tween 64 and 65536 bytes in length and have a correct

FCS value. Frames longer than 65536 bytes may not

be handled properly.

If JUMBO = 0 and VSIZE = 0, valid frames are frames

that are between 64 and 1518 bytes in length and have

a correct FCS value.

If JUMBO = 0 and VSIZE = 1, valid frames are frames

that are between 64 and 1522 bytes in length and have

a correct FCS value.

In Table 7, the Offset column gives the offset with re-

spect to the value stored in the read-only MIB Offset

address space allocated to the Am79C976 device. The

actual address of a particular counter is the sum of the

following quantities:

■The contents of the PCI Memory-Mapped I/O Base

Address Register.

■The contents of the MIB Offset Register.

■The offset given in Table 7.

Table 7. Receive Statistics Counters

Offset (hex) Receive Counter Name MIB Object Supported Description of Counter/Comments

00 RcvMissPkts

RMON etherStatsDropEvents

RMON etherHistoryDropEvents

MIB-II ifInDiscards

E-like

dot3StatsInternalMacReceiveErrors

The number of times a receive packet was

dropped due to lack of resources. This is

the number of times a packet was dropped

due to receive FIFO overflow. This count

does not include undersize, oversize,

misaligned or bad FCS packets.

04 RcvOctets

RMON etherStatsOctets

RMON etherHistoryOctets

MIB-II IfInOctets

The total number of octets of data

received including octets from invalid

frames. This does not include the

preamble but does include the FCS bits.

The RcvOctets counter is incremented

whenever the receiver receives an octet.

08 RcvBroadCastPkts

RMON etherStatsBroadcastPkts

RMON etherHistoryBroadcastPkts

EXT-MIB-II ifInBroadcastPkts

The total number of valid frames received

that are addressed to a broadcast

address. This counter does not include

errored broadcast packets or valid

multicast packets.

0C RcvMultiCastPkts

RMON etherStatsMulticastPkts

RMON etherHistoryMulticastPkts

EXT-MIB-II ifInMulticastPkts

The total number of valid frames received

that are addressed to a multicast address.

This counter does not include errored

multicast packets or valid broadcast

packets.

9/14/00 Am79C976 77

PRELIMINARY

10 RcvUndersizePkts RMON etherStatsUndersizePkts

RMON etherHistoryUndersizePkts

The total number of valid frames received

that are less than 64 bytes long (including

the FCS) and do not have any error. SFD

must be received so that the FCS can be

calculated.

14 RcvOversizePkts

RMON etherStatsOversizePkts

RMON etherHistoryOversizePkts

E-like MIB dot3StatsFrameTooLongs

The total number of packets received that

are greater than 1518 (1522 when VLAN

set) bytes long (including the FCS) and do

not have any error. SFD must be received

so that the FCS can be calculated.

18 RcvFragments RMON etherStatsFragments

RMON etherHistoryFragments

The number of packets received that are

less than 64 bytes (not including the

preamble or SFD) and have either an FCS

error or an alignment error.

1C RcvJabbers RMON etherStatsJabbers

RMON etherHistoryJabbers

The number of packets received that are

greater than 1518 (1522 when VLAN set)

bytes long and have either an FCS error or

an alignment error.

20 RcvUnicastPkts MIB-II ifInUcastPkts

The number of valid frames received that

are not addressed to a multicast address

or a broadcast address. This counter does

not include errored unicast packets.

24 RcvAlignmentErrors E-like MIB dot3StatsAlignmentErrors

The number of packets received that are

between 64 and 1518 (1522 when VLAN

set) bytes (excluding preamble/SFD but

including FCS), inclusive, and have a bad

FCS with non-integral number of bytes.

28 RcvFCSErrors E-like MIB dot3StatsFCSErrors

The total number of packets received that

are between 64 and 1518 (1522 when

VLAN set) bytes (excluding preamble/

SFD but including FCS), inclusive, and

have a bad FCS with an integral number of

bytes. This counter will also count packets

with a correct FCS if RX_ER occurs when

valid carrier RX_DV is present.

2C RcvGoodOctets RMON hostInOctets

RMON hostTimeInOctets

The total number of bytes received by a

port. Bytes are 8-bit quantities received

after the SFD. This does not include

preamble or bytes from erroneous

packets, but does include the FCS.

30 RcvMACCtrl 802.3x aMACControlFramesReceived

The total number of valid frames received

with a lengthOrType field value equal to

8808h.

34 RcvFlowCtrl 802.3x

aPAUSEMACCtrlFramesReceived

The total number of valid frames received

with (1) a lengthOrType field value equal

to 8808h and (2) an opcode equal to 1.

40 RcvPkts64Octets RMON etherStatsPkts64Octets The total number of packets (including

error packets) that are 64 bytes long.

44 RcvPkts65to127Octets RMON etherStatsPkts65to127Octets

The total number of packets (including

error packets) that are 65 bytes to 127

bytes long, inclusive.

Offset (hex) Receive Counter Name MIB Object Supported Description of Counter/Comments

78 Am79C976 9/14/00

PRELIMINARY

Transmit Statistics Counters

Table 8 describes the statistics counters associated

with the transmitter and lists the MIB objects that these

counters support.

In this table the Offset column gives the offset with re-

spect to the value stored in the read-only MIB Offset

address space allocated to the Am79C976 device. The

actual address of a particular counter is the sum of the

following quantities:

■The contents of the PCI Memory-Mapped I/O Base

Address Register

■The contents of the MIB Offset Register

■The offset given in Table 8.

Table 8. Transmit Statistics Counters

48 RcvPkts128to255Octets RMON etherStatsPkts128to255Octets

The total number of packets (including

error packets) that are 128 bytes to 255

bytes long, inclusive.

4C RcvPkts256to511Octets RMON etherStatsPkts256to511Octets

The total number of packets (including

error packets) that are 256 bytes to 511

bytes long, inclusive.

50 RcvPkts512to1023Octets RMON etherStatsPkts512to1023Octets

The total number of packets (including

error packets) that are 512 bytes to 1023

bytes long, inclusive

54 RcvPkts1024to1518Octets RMON

etherStatsPkts1024to1518Octets

The total number of packets (including

error packets) that are 1024 bytes to 1518

(1522 when VLAN set) bytes long,

inclusive.

58 RcvUnsupportedOpcodes 802.3x an

UnsupportedOpcodesReceived

The total number of valid frames received

with (1) a lengthOrType field value equal

to 8808h and (2) an opcode not equal to 1.

5C RcvSymbolErrors

The number of times when valid carrier

(CRS) was present and there was at least

one occurrence of an invalid data symbol

(RX_ER). This counter is incremented

only once per valid carrier event (once per

frame), and if a collision is present, this

counter must not be incremented.

Offset (hex) Receive Counter Name MIB Object Supported Description of Counter/Comments

Offset

(hex) Transmit Counter Name MIB Object Supported Description of Counter/Comments

60 XmtUnderrunPkts

RMON etherStatsDropEvents

RMON etherHistoryDropEvents

MIB-II ifOutDiscards

E-like

dot3StatsInternalMacTranmsitErrors

The number of times a packet was dropped

due to transmit FIFO underrun.

64 XmtOctets

RMON etherStatsOctets

RMON etherHistoryOctets

RMON hostOutOctets

RMON hostTimeOutOctets

MIB-II IfOutOctets

The total number of octets of data

transmitted. This does not include the

preamble but does include the FCS bits. The

XmtOctets counter is incremented whenever

the transmitter transmits an octet.

9/14/00 Am79C976 79

PRELIMINARY

68 XmtPackets

RMON etherStatsPkts

RMON etherHistoryPkts

RMON hostOutPkts

RMON hostTimeOutPkts

BRIDGE-MIB dot1dTpPortOutFrames

The number of packets transmitted. This

does not include packets transmitted with

errors (i.e., collision fragments and partial

packets due to transmit FIFO under runs).

6C XmtBroadCastPkts

RMON etherStatsBroadcastPkts

RMON etherHistoryBroadcastPkts

RMON hostOutBroadcastPkts

RMON hostTimeOutBroadcastPkts

EXT-MIB-II ifOutBroadcastPkts

The number of valid frames transmitted that

are addressed to a broadcast address. This

counter does not include errored broadcast

packets or valid multicast packets.

70 XmtMultiCastPkts

RMON etherStatsMulticastPkts

RMON etherHistoryMulticastPkts

RMON hostOutMulticastPkts

RMON hostTimeOutMulticastPkts

EXT-MIB-II ifOutMulticastPkts

The number of valid frames transmitted that

are addressed to a multicast address. This

counter does not include errored multicast

packets or valid broadcast packets.

74 XmtCollisions RMON etherStatsCollisions

RMON etherHistoryCollisions

The number of collisions that occur during

transmission attempts. Collisions that occur

while the device is not transmitting (i.e.,

receive collisions) are not identifiable and

therefore not counted.

78 XmtUnicastPkts MIB-II ifOutUcastPkts

The number of valid frames transmitted that

are not addressed to a multicast or a

broadcast address. This counter does not

include errored unicast packets.

7C XmtOneCollision E-like dot3StatsSingleCollisionFrames The number of packets successfully

transmitted after experiencing one collision.

80 XmtMultipleCollision E-like dot3StatsMultipleCollsionFrames

The number of packets successfully

transmitted after experiencing more than one

collision.

84 XmtDeferredTransmit E-like dot3StatsDeferredTransmissions

The number of packets for which the first

transmission attempt on the network is

delayed because the medium is busy.

88 XmtLateCollision E-like dot3StatsLateCollisions

The number of late collisions that occur. A

late collision is defined as a collision that

occurs more than 512 bit times after the

transmission starts. The 512- bit interval is

measured from the start of preamble.

8C XmtExcessiveDefer

The number of excessive deferrals that occur.

An excessive deferral occurs when a

transmission is deferred for more than 3036

byte times in normal mode or 3044 byte times

in VLAN mode.

90 XmtLossCarrier The number of transmit attempts made when

the LINK_STAT bit in the STAT0 register is 0.

94 XmtExcessiveCollision E-like dot3StatsExcessiveCollisions

The number of packets that are not

transmitted because the packet experienced

16 unsuccessful transmission attempts (the

first attempt plus 15 retries).

Offset

(hex) Transmit Counter Name MIB Object Supported Description of Counter/Comments

80 Am79C976 9/14/00

PRELIMINARY

VLAN Support

Virtual Bridged Local Area Network (VLAN) tags are

defined in IEEE Std 802.3ac-1998. A VLAN tag is a

4-byte quantity that is inserted between the Source

Address field and the Length/Type field of a basic

802.3 MAC frame. The VLAN tag consists of a Length/

Type field that contains the value 8100h and a 16-bit

Tag Control Information (TCI) field. The TCI field is fur-

ther divided into a 3-bit User Priority field, a 1-bit Ca-

nonical Format Indicator (CFI), and a 12-bit VLAN

Identifier.

A frame that has no VLAN tag is said to be untagged.

A frame with a VLAN tag whose VLAN Identifier field

contains the value 0 is said to be priority-tagged. A

frame with a VLAN tag with a non-zero VLAN Identifier

field is said to be VLAN-tagged.

The format of a VLAN-tagged frame is shown in

Figure 32.

98 XmtBackPressure The total number of back pressure collisions

generated.

9C XmtFlowCtrl PAUSEMACCtrlFramesTransmitted

The total number of PAUSE packets

generated and transmitted by the controller

hardware.

A0 XmtPkts64Octets RMON etherStatsPkts64Octets The total number of packets (excluding error

packets) that are 64 bytes long.

A4 XmtPkts65to127Octets RMON etherStatsPkts65to127Octets

The total number of packets transmitted

(excluding error packets) that are 65 bytes to

127 bytes long, inclusive.

A8 XmtPkts128to255Octets RMON etherStatsPkts128to255Octets

The total number of packets transmitted

(excluding error packets) that are 128 bytes to

255 bytes long, inclusive.

AC XmtPkts256to511Octets RMON etherStatsPkts256to511Octets

The total number of packets transmitted

(excluding error packets) that are 256 bytes to

511 bytes long, inclusive.

B0 XmtPkts512to1023Octets RMON etherStatsPkts512to1023Octets

The total number of packets transmitted

(excluding error packets) that are 512 bytes to

1023 bytes long, inclusive

B4 XmtPkts1024to1518Octets RMON etherStatsPkts1024to1518Octets

The total number of packets transmitted

(excluding error packets) that are 1024 bytes

to 1518 (1522 when VLAN set) bytes long,

inclusive.

B8 XmtOversizePkts

The total number of packets transmitted

(excluding error packets) that are longer than

1518 (1522 when VLAN set) bytes.

Offset

(hex) Transmit Counter Name MIB Object Supported Description of Counter/Comments

9/14/00 Am79C976 81

PRELIMINARY

Figure 32. VLAN-Tagged Frame Format

The Am79C976 device includes several features that

can simplify the processing of IEEE 802.3ac VLAN-

tagged frames.

VLAN Frame Size

While the maximum frame size for IEEE 802.3 frames

without VLAN tags is 1518 bytes, the maximum frame

size for VLAN-tagged frames is 1522 bytes. The VLAN

frame size bit (VSIZE, CMD3, bit 20) determines the

maximum frame size. When VSIZE is set to 1 the max-

imum frame size is 1522 bytes. Otherwise, the maxi-

mum frame size is 1518 bytes.

The maximum frame size is used for determining

when to increment the XmtOversizePkts,

XmtPkts1024to1518Octets, XmtExcessiveDefer,

RcvPkts1024to1518Octets, and RcvOversizePkts

MIB counters.

Admit Only VLAN Frames Option

The Admit Only VLAN (VLONLY) bit in CMD3, bit19

can be programmed to reject any frame that is not

VLAN-tagged. When VLONLY is set, untagged or pri-

ority-tagged frames will be flushed from the receive

FIFO and will not be copied into system memory. Only

frames with a Length/Type field equal to 8100h and a

non-zero VLAN ID field will be received. The VLAN ID

field consists of bits [11:0] of the 15th and 16th bytes of

the frame.

VLAN Tags in Descriptors

When the SWSTYLE field in CSR58 contains the value

4 or 5, VLAN tag information can be passed between

the host CPU and the network medium through Trans-

mit or Receive Descriptors. The transmitter can be pro-

grammed to insert or delete a VLAN tag or to modify

the TCI field of a VLAN tag. This feature allows VLAN

software to control the VLAN tag of a frame without

modifying data in transmit buffers. The receiver can de-

termine whether a frame is untagged, priority-tagged,

or VLAN-tagged, and it can copy the TCI field of the

VLAN tag into the Receive Descriptor

The Tag Control Command (TCC) is a 2-bit field in the

Transmit Descriptor that determines whether the trans-

mitter will insert, delete, or modify a VLAN tag or trans-

mit the data from the transmit buffers unaltered. The

encoding of the TCC field is shown in Table 9.

If the transmitter adds, deletes, or modifies a VLAN tag,

it will append a valid FCS field to the frame, regardless

of the state of the Disable Transmit FCS (DXMTFCS)

bit in CSR15.

When SWSTYLE is 4 or 5, the receiver examines each

incoming frame and writes the frame’s VLAN classifica-

tion into the Tag Type (TT) field of the Receive Descrip-

tor. If the frame contains a VLAN tag, the receiver will

copy the TCI field of tag into the TCI field of the Receive

Descriptor. The encoding of the TT field is shown in

Table 10.

PREAMBLE

SFD

DESTINATION ADDRESS

SOURCE ADDRESS

LENGTH/TYPE = 8100h

TAG CONTROL INFORMATION

MAC CLIENT LENGTH/TYPE

MAC CLIENT DATA

FRAME CHECK SEQUENCE

7 OCTETS

1 OCTET

6 OCTETS

2 OCTETS

42-1500 OCTETS

4 OCTETS

VLAN ID

CANONICAL FMT INDICATOR

USER PRIORITY

111315

82 Am79C976 9/14/00

PRELIMINARY

Table 9. VLAN Tag Control Command

Table 10. VLAN Tag Type

Loopback Operation

Loopback is a mode of operation intended for system

diagnostics. In this mode, the transmitter and receiver

are both operating at the same time so that the control-

ler receives its own transmissions. The controller pro-

vides two basic types of loopback. In internal loopback

mode, the transmitted data is looped back to the re-

ceiver inside the controller. The receiver will move the

received data to the next receive buffer, where it can be

examined by software. Alternatively, in external loop-

back mode, data can be transmitted to and received

from the external network.

The external loopback through the MII requires a two-

step operation. The external PHY must be placed into

a loop-back mode by writing to the PHY Access Regis-

ter. Then the Am79C976 controller must be placed into

an external loopback mode by setting EXLOOP

(CMD2, bit 3).

The internal loopback through the MII is controlled by

INLOOP (CMD2, bit 4). When set to 1, this bit will

cause the internal portion of the MII data port to loop-

back on itself. The MII management port (MDC, MDIO)

is unaffected by the INLOOP bit.

The internal MII interface is mapped in the following

way:

■The TXD[3:0] nibble data path is looped back onto

the RXD[3:0] nibble data path

■TX_CLK is looped back as RX_CLK

■TX_EN is looped back as RX_DV

■TX_EN is OR’d with the CRS pin and is looped back

as CRS

■The COL input is driven low

■TX_ER is not driven by the Am79C976 and there-

fore not looped back.

During the internal loopback, the TX_EN and TXD pins

will be active. Internal loopback should not be used on

a live network because collisions will not be handled

correctly. The wire should be disconnected or the PHY

isolated before using internal loopback.

Miscellaneous Loopback Features

All transmit and receive function programming, such as

automatic transmit padding and receive pad stripping,

operates identically in loopback as in normal operation.

Runt Packet Accept is internally enabled regardless of

the state of the RPA bit in CSR124 when any loopback

mode is invoked. This is for backwards compatibility

with the C-LANCE (Am79C90) software.

The C-LANCE controller and the half-duplex members

of the PCnet family of devices place certain restrictions

on FCS generation and checking, and on testing multi-

cast address detection. Since the Am79C976 controller

has two FCS generators, these restrictions do not

apply to the Am79C976 controller. On receive, the

Am79C976 controller provides true FCS status. The

descriptor for a frame with an FCS error will have the

CRC bit (RMD1, bit 27) set to 1. The FCS generator on

the transmit side can still be disabled by setting DXMT-

FCS (CSR15, bit 3) to 1.

In internal loopback operation, the Am79C976 control-

ler provides a special mode to test the collision logic.

When FCOLL (CSR15, bit 4) is set to 1, a collision is

forced during every transmission attempt. This will re-

sult in a Retry error.

Full-Duplex Operation

The Am79C976 controller supports full-duplex opera-

tion on both network interfaces. Full-duplex operation

allows simultaneous transmit and receive activity on the

TXD[3:0] and RXD[3:0] pins of the MII port. Full-duplex

operation is enabled by the FDEN bit located in BCR9

for all ports. Full-duplex operation is also enabled

through Auto-Negotiation when DISPM (BCR 32, bit 7)

is not enabled on the MII port and the ASEL bit is set,

and both the external PHY and its link partner are ca-

pable of Auto-Negotiation and full-duplex operation.

When operating in full-duplex mode, the following

changes to the device operation are made:

The MAC engine changes for full-duplex operation are

as follows:

■Changes to the Transmit Deferral mechanism:

TCC

(TMD2[17:16]) Action

00 Transmit data in buffer unaltered

01 Delete Tag Header

10 Insert Tag Header containing TCI

field from descriptor.

11 Replace TCI field from buffer with TCI

data from descriptor.

(RMD1[19:18]) Description

00 Reserved

01 Frame is untagged

10 Frame is priority-tagged

11 Frame is VLAN-tagged

9/14/00 Am79C976 83

PRELIMINARY

—Transmission is not deferred while receive is

active.

—The IPG counter which governs transmit deferral

during the IPG between back-to-back transmits

is started when transmit activity for the first

packet ends, instead of when transmit and car-

rier activity ends.

■The collision indication input to the MAC engine is

ignored.

Full-Duplex Link Status LED Support

The Am79C976 controller provides bits in each of the

LED Status registers (BCR4, BCR5, BCR6, BCR7) to

display the Full-Duplex Link Status. If the FDLSE bit

(bit 8) is set, a value of 1 will be sent to the associated

LEDOUT bit when in Full-Duplex.

Media Independent Interface

The Am79C976 controller fully supports the MII

according to the IEEE 802.3 standard. This Reconcili-

ation Sublayer interface allows a variety of PHYs

(100BASE-TX, 100BASE-FX, 100BASE-T4,

100BASE-T2, 10BASE-T, etc.) to be attached to the

Am79C976 MAC engine without future upgrade prob-

lems. The MII interface is a 4-bit (nibble) wide data path

interface that runs at 25 MHz for 100-Mbps networks or

2.5 MHz for 10-Mbps networks. The interface consists

of two independent data paths, receive (RXD(3:0)) and

transmit (TXD(3:0)), control signals for each data path

(RX_ER, RX_DV, TX_EN), network status signals

(COL, CRS), clocks (RX_CLK, TX_CLK) for each data

path, and a two-wire management interface (MDC and

MDIO). See Figure 33.

The transmit and receive paths in the Am79C976 con-

troller's MAC are independent. The TX_CLK and

RX_CLK need not run at the same frequency. TX_CLK

can slow down or stop without affecting receive and

vice versa. It is only necessary to respect the minimum

clock high and low time specifications when switching

TX_CLK or RX_CLK. This facilitates operation with

PHYs that use MII signaling but do not adhere to 802.3

MII specifications.

MII Transmit Interface

The MII transmit clock is generated by the external

PHY and is sent to the Am79C976 controller on the

TX_CLK input pin. The clock can run at 25 MHz or 2.5

MHz, depending on the speed of the network to which

the external PHY is attached. The data is a nibble-wide

(4 bits) data path, TXD(3:0), from the Am79C976 con-

troller to the external PHY and is synchronous with the

rising edge of TX_CLK. The transmit process starts

when the Am79C976 controller asserts TX_EN, which

indicates to the external PHY that the data on TXD(3:0)

is valid.

IEEE Std 802.3 provides a mechanism for signaling un-

recoverable errors through the MII to the external PHY

with the TX_ER output pin. The external PHY will re-

spond to this error by generating a TX coding error on

the current transmitted frame. The Am79C976 control-

ler does not use this method of signaling errors on the

transmit side. Instead if the Am79C976 controller de-

tects a transmit error, it will invert the FCS to generate

an invalid FCS. Since the Am79C976 controller does

not implement the TX_ER function, the TX_ER pin on

the external PHY device should be connected to VSS.

MII Receive Interface

The MII receive clock is also generated by the external

PHY and is sent to the Am79C976 controller on the

RX_CLK input pin. The clock will be the same fre-

quency as the TX_CLK but will be out of phase and can

run at 25 MHz or 2.5 MHz, depending on the speed of

the network to which the external PHY is attached.

84 Am79C976 9/14/00

PRELIMINARY

Figure 33. Media Independent Interface

The receive process starts when RX_DV is asserted.

RX_DV must remain asserted until the end of the re-

ceive frame. If the external PHY device detects errors

in the currently received frame, it asserts the RX_ER

signal. RX_ER can be used to signal special conditions

out of band when RX_DV is not asserted. Two defined

out-of-band conditions for this are the 100BASE-TX

signaling of bad Start of Frame Delimiter and the

100BASE-T4 indication of illegal code group before the

receiver has synchronized with the incoming data. The

Am79C976 controller will not respond to these condi-

tions. All out of band conditions are currently treated as

NULL events. Certain in-band non-IEEE 802.3-compli-

ant flow control sequences may cause erratic behavior

for the Am79C976 controller. Consult the switch/

bridge/router/hub manual to disable the in-band flow

control sequences if they are being used.

MII Network Status Interface

The MII also provides the CRS (Carrier Sense) and

COL (Collision Sense) signals that are required for

IEEE 802.3 operation. Carrier Sense is used to detect

non-idle activity on the network for the purpose of inter-

frame spacing timing in half-duplex mode. Collision

Sense is used to indicate that simultaneous transmis-

sion has occurred in a half-duplex network.

MII Management Interface

The MII provides a two-wire management interface so

that the Am79C976 controller can control external PHY

devices and receive status from them.

The Am79C976 controller offers direct hardware sup-

port of the external PHY device without software inter-

vention. The device automatically uses the MII

Management Interface to read auto-negotiation infor-

mation from the external PHY device and configures

the MAC accordingly. The controller also provides the

host CPU indirect access to the external PHY through

the MII Control, Address, and Data registers (BCR32,

33, 34).

With software support the Am79C976 controller can

support up to 31 external PHYs attached to the MII

Management Interface.

Two independent state machines use the MII Manage-

ment Interface to poll external PHY devices: the Net-

work Port Manager and the Auto-poll State Machine.

The Network Port Manager coordinates the auto-nego-

tiation process, while the Auto-poll State Machine inter-

rupts the host CPU when it detects changes in user-

selected PHY registers.

The Network Port Manager sends a management

frame to the default PHY about once every 900 ms to

determine auto-negotiation results and the current link

status. The Network Port Manager uses the auto-nego-

tiation results to set the MAC’s speed, duplex mode,

and flow control ability. Changes detected by the Net-

work Port Manager affect the operation of the MAC and

MIB counters. For example, if link failure is detected,

the transmitter will increment the XmtLossCarrier

counter each time it attempts to transmit a frame.

The Auto-poll State Machine periodically sends man-

agement frames to poll the status register of the default

PHY device plus up to 5 user-selected PHY registers

and interrupts the host processor if it detects a change

in any of these registers. The Auto-poll State Machine

does not change the state of the MAC engine.

MII Management Frames

The format of an MII Management Frame is defined in

Clause 22 of IEEE Std 802.3. The start of an MII Man-

RXD(3:0)

RX_DV

RX_ER

RX_CLK

TXD(3:0)

TX_EN

Am79C976

MII Interface

COL

CRS

Receive Signals

Transmit Signals

Management Port Signals

Network Status Signals

TX_CLK

MDIO

MDC

9/14/00 Am79C976 85

PRELIMINARY

agement Frame is a preamble of 32 ones that guaran-

tees that all of the external PHYs are synchronized on

the same interface. (See Figure 34.) Loss of synchro-

nization is possible due to the hot-plugging capability of

the exposed MII. The preamble can be suppressed as

described below if the external PHY is designed to ac-

cept frames with no preamble.

Figure 34. Frame Format at the MII Interface Connection

The preamble (if present) is followed by a start field

(ST) and an operation field (OP). The operation field

(OP) indicates whether the Am79C976 controller is ini-

tiating a read or write operation. This field is followed by

the external PHY address (PHYAD) and the register

address (REGAD). The PHY address of 1Fh is re-

served and should not be used.

The register address field is followed by a bus turn-

around field. During a read operation, the bus turn-

around field is used to determine if the external PHY is

responding correctly to the read request or not. The

Am79C976 controller will tri-state the MDIO for both

MDC cycles.

During the second cycle of a read operation, if the ex-

ternal PHY is synchronized to the Am79C976 control-

ler, the external PHY will drive a 0. If the external PHY

does not drive a 0, the Am79C976 controller will signal

a MREINT (CSR7, bit 9) interrupt, if MREINTE (CSR7,

bit 8) is set to a 1. This interrupt indicates that the

Am79C976 controller had an MII management frame

read error and that the data read is not valid.

During a write access the Am79C976 controller drives

a 1 for the first bit time of the turnaround field and a 0

for the second bit time.

After the Turn Around field comes the data field. For a

write access the Am79C976 controller fills this field

with data to be written to the PHY device. For a read

access the external PHY device fills this field with data

from the selected register.

The last field of the MII Management Frame is an IDLE

field that is necessary to give ample time for drivers to

turn off before the next access.

MII management frames transmitted through the MDIO

pin are synchronized with the rising edge of the Man-

agement Data Clock (MDC). The Am79C976 controller

will drive the MDC to 0 and tri-state the MDIO anytime

the MII Management Port is not active.

To help to speed up the reading and writing of the MII

management frames to the external PHY, the MDC can

be sped up to 10 MHz by setting the FMDC bits in

BCR32. The IEEE 802.3 specification requires use of

the 2.5-MHz clock rate, but 5 MHz and 10 MHz are

available for the user. The intended applications are

that the 10-MHz clock rate can be used for a single ex-

ternal PHY on an adapter card or motherboard. The

5-MHz clock rate can be used for an exposed MII with

one external PHY attached. The 2.5-MHz clock rate is

intended to be used when multiple external PHYs are

connected to the MII Management Port or if compli-

ance to the IEEE 802.3u standard is required.

Host CPU Access to External PHY

The host CPU can indirectly read and write external

PHY registers through the PHY Access Register or, for

compatibility with other PCnet family devices, through

BCR33 and BCR34.

PHY register accesses must be done using either

BCR33 and BCR34 registers or the PHY_ACCESS

BCR34 are used, the PHY_ACCESS register should

be at the default value of all zeros.

To write to a PHY register the host CPU puts the regis-

ter data into the PHY_DATA field of the PHY Access

vice in the PHY_ADDR field and the PHY register num-

ber in the PHY_REG_ADDR field, and sets the

PHY_WR_CMD bit.

The Am79C976 device provides two types of read ac-

cess to external PHY registers, blocking and non-

blocking. If a blocking read access is used, the device

will generate PCI disconnect/retry cycles if the host

CPU attempts to read the PHY Access Register while

the MII Management Frame is being processed. If a

Preamble

1111....1111

10 Rd

01 Wr

PHY

Address

Z0 Rd

10 Wr

Data

Bits

Bit

Idle

86 Am79C976 9/14/00

PRELIMINARY

non-blocking read is used, the PHY Access Register

can be read at any time, and the PHY_CMD_DONE bit

in that register indicates whether or not PHY_DATA

field contains valid data.

To generate a non-blocking read from a PHY register

the host CPU specifies the address of the external PHY

device in the PHY_ADDR field and the PHY register

number in the PHY_REG_ADDR field of the PHY Ac-

cess Register and sets the PHY_NBLK_RD_CMD bit.

The host CPU can then poll the register until the

PHY_CMD_DONE bit is 1, or it can wait for the MII

Management Command Complete Interrupt (MCCINT

in the Int0 Register). When the PHY_CMD_DONE bit

is 1, the PHY_DATA field contains the data read from

the specified external PHY register. If an error occurs in

the read operation, the MII Management Read Error In-

terrupt (MREINT) bit in the Interrupt0 Register is set,

and if the corresponding enable bit is set (MREINTE in

the Interrupt Enable Register), the host CPU is inter-

rupted.

To generate a blocking read, the host CPU uses the

same procedure as it does for a non-blocking read, ex-

cept that it sets the PHY_BLK_RD_CMD bit rather than

the PHY_NBLK_RD_CMD bit, and it can poll the PHY

Access Register until the PHY_CMD_DONE bit is set.

When any one of the PHY register access command

bits (PHY_WR_CMD, PHY_BLK_RD_CMD or

PHY_NBLK_RD_CMD) is set, the PHY_CMD_DONE

bit must be cleared by writing a 1 to it in the same

PHY_ACCESS register write.

The host CPU must not set both the

PHY_BLK_RD_CMD bit and the PHY_NBLK_RD_CMD

bit at the same time.

The host CPU must not attempt a second PHY register

access until the first access is complete. When the ac-

cess is complete, the PHY_CMD_DONE bit in the PHY

Access Register and the MII Management Command

Complete Interrupt (MCCINT) bit in the Interrupt Regis-

ter will be set to 1, and if the corresponding enable bit

is set, the host CPU will be interrupted. The host can ei-

ther wait for this interrupt, or it can use some other

method to guarantee that it waits for a long enough

time. Note that with a 2.5 MHz MDC clock it takes about

27 µs to transmit a management frame with a pream-

ble. However, if the Auto-Poll or Port Manager ma-

chines are active, there may be a delay in sending a

host generated management frame while other frames

are sent. Under these conditions, the host should al-

ways check for command completion.

For an MII Management Frame transmitted as the re-

sult of a host CPU access to the PHY Access Register,

preamble suppression is controlled by the Preamble

Suppression bit (PRE_SUP) in the PHY Access Regis-

ter. If this bit is set to 1 the preamble will be sup-

pressed. Otherwise, the frame will include a preamble.

The host CPU should only set the Preamble Suppres-

sion bit when accessing a register in a PHY device that

is known to be able to accept management frames

without preambles. For PHY devices that comply with

Clause 22 of IEEE Std 802.3, bit 6 of PHY Register 1 is

fixed at 1 if the PHY will accept management frames

with the preamble suppressed.

The PHY_PRE_SUP bit in the PHY_ACCESS register

controls preamble suppression for PHY register ac-

cesses initiated either from the PHY_ACCESS register

or from the BCR33 and BCR34 registers. When using

BCR33 and BCR34 to access PHY registers,

PHY_PRE_SUP must be 0 unless all connected PHY’s

support preamble suppression.

See Appendix B, MII Management Registers, for de-

scriptions of the standard registers that are found in

IEEE 802.3 compatible devices.

Auto-Poll State Machine

As defined in the IEEE 802.3 standard, the external

PHY attached to the Am79C976 controller’s MII has no

way of communicating important timely status informa-

tion back to the Am79C976 controller. Unless it polls

the external PHY’s status register, the Am79C976 con-

troller has no way of knowing that an external PHY has

undergone a change in status. Although it is possible

for the host CPU to poll registers in external PHY de-

vices, the Am79C976 controller simplifies this process

by implementing an automatic polling function that pe-

riodically polls up to 6 user-selected PHY registers and

interrupts the host CPU if the contents of any of these

registers change.

The automatic polling of PHY registers is controlled by

six 16-bit Auto-Poll registers, AUTOPOLL0 to

AUTOPOLL5. By writing to the Auto-Poll registers, the

user can independently define the PHY addresses and

registers are not restricted to a single PHY device. In

the Auto-Poll registers there is an enable bit for each of

the selected PHY registers. When the host CPU sets

one of these enable bits, the Auto-Poll logic reads the

corresponding PHY register and stores the result in the

corresponding Auto-Poll Data Register. (There is one

Auto-Poll Data register for each of the six PHY regis-

ters.) Thereafter, at each polling interval, the Auto-Poll

logic compares the current contents of the selected

PHY register with the corresponding Auto-Poll Data

ment Auto-Poll Interrupt (MAPINT) in the Interrupt Reg-

ister, which causes an interrupt to the host CPU (if that

interrupt is enabled).

Note that when the host CPU writes to one of the Auto-

Poll Registers the contents of the associated Auto-Poll

Data Register are considered to be invalid during the

next polling cycle so that the next polling cycle updates

9/14/00 Am79C976 87

PRELIMINARY

the appropriate Auto-Poll Data Register without caus-

ing an interrupt.

When the contents of one of the selected PHY regis-

ters changes, the corresponding Auto-Poll Data Regis-

ter is updated so that another interrupt will occur when

the data changes again.

Auto-Poll Register 0 differs from the other Auto-Poll

Registers in several ways. The PHY address

(AP_PHY0_ADDR) field of this register defines the de-

fault PHY address that is used by both the Auto-Poll

State Machine and the Network Port Manager. The

the external PHY status register), and the register is al-

ways enabled. This means that if the Auto-Poll State

Machine is enabled, it will always poll register 1 of the

default PHY and will interrupt the host CPU when it de-

tects a change in that register.

In addition to the PHY address, register number, and

enable bit, the Auto-Poll Registers contain two other

control bits for each of the 5 user-selected registers.

These bits are the Preamble Suppression

(AP_PRE_SUP) and Default PHY (AP_DFLT_PHY)

bits.

If the Preamble Suppression bit is set, the Auto-Poll

sends management frames to the corresponding regis-

ter with no preamble field. The host CPU should only

set the Preamble Suppression bit for registers in PHY

devices that are known to be able to accept manage-

ment frames without preambles. For PHY devices that

comply with Clause 22 of IEEE Std 802.3, bit 6 of PHY

ment frames with the preamble suppressed.

If the Default PHY bit (AP_DFLT_PHY) is set, the cor-

responding Preamble Suppression bit and PHY ad-

dress field are ignored. In this case the Auto-Poll State

Machine uses the default PHY address from the

AP_PHY0_ADDR field, and suppresses the preamble

if the Network Port Manager logic has determined that

the default PHY device accepts management frames

with no preamble. If the Network Port Manager logic

has not determined that the default PHY device ac-

cepts management frames with no preamble, the Auto-

Poll State Machine does not suppress the preamble

when accessing the selected register.

The Auto-Poll State Machine is enabled when the

Auto-Poll External PHY (APEP) bit (CMD3, bit 24) is

set to 1. If APEP is cleared to 0, the Auto-Poll machine

does not poll any PHY registers regardless of the state

of the enable bits in the Auto-Poll registers. The APEP

bit has no effect on the Network Port Manager, which

may poll the default PHY even when the state of the

APEP bit is 0.

The Auto-Poll’s frequency of generating MII manage-

ment frames can be adjusted by setting of the APDW

bits (BCR32, bits 10-8). The delay can be adjusted

from 0 MDC periods to 2048 MDC periods.

Network Port Manager

The Am79C976 controller is unique in that it does not

require software intervention to control and configure

an external PHY attached to the MII. This feature was

included to ensure backwards compatibility with exist-

ing software drivers. The Am79C976 controller will op-

erate with existing PCnet drivers from revision 2.5

upward (although older drivers will report incorrect sta-

tistics for the Am79C976 device). The heart of this au-

tomatic configuration system is the Network Port

Manager.

The Network Port Manager initiates auto-negotiation in

the external PHY when necessary and monitors the re-

sults. When auto-negotiation is complete, the Network

Port Manager sets up the MAC to be consistent with

the negotiated configuration. The Network Port Man-

ager auto-negotiation sequence requires that the exter-

nal PHY respond to the auto-negotiation request within

4 seconds. Otherwise, system software will be required

to properly control and configure the external PHY at-

tached to the MII. After auto negotiation is complete,

the Network Port Manager generates MII management

frames about once every 900 ms to monitor the status

of the external PHY.

The Network Port Manager is enabled when the Dis-

able Port Manager (DISPM) bit (CMD3, bit 14) is

cleared to 0.

Auto-Negotiation

The external PHY and its link partner may have one or

more of the following capabilities: 100BASE-T4,

100BASE-TX Full-/Half-Duplex, 10BASE-T Full-/Half-

Duplex, and MAC Control PAUSE frame processing.

During the auto-negotiation process the two PHY de-

vices exchange information about their capabilities and

then select the best mode of operation that is common

to both devices. The modes of operation are prioritized

according to the order shown in Table 11 (with the high-

est priority shown at the top of the table).

Table 11. Auto-Negotiation Capabilities

Network Speed Physical Network Type

200 Mbps 100BASE-X, Full Duplex

100 Mbps 100BASE-T4, Half Duplex

100 Mbps 100BASE-X, Half Duplex

20 Mbps 10BASE-T, Full Duplex

10 Mbps 10BASE-T, Half Duplex

88 Am79C976 9/14/00

PRELIMINARY

Auto-Negotiation goes further by providing a message-

based communication scheme called, Next Pages, be-

fore connecting to the Link Partner. The Network Port

Manager does not support this feature. However, the

host CPU can disable the Network Port Manager and

manage Next Pages by accessing the PHY device

through the PHY Access Register. The host CPU can

disable the Network Port Manager by setting the Dis-

able Port Manager (DISPM) bit (CMD3, bit 14) to 1.

(The DISPM bit corresponds to the Disable Auto-Nego-

tiation Auto Setup (DANAS) bit in BCR32 of older

PCnet family devices.)

To control the auto-negotiation process, the Network

Port Manager generates MII Management Frames to

execute the procedure described below. (See Appen-

dix B, MII Management Registers, for the MII register

bit descriptions.)

The Network Port Manager is held in the IDLE state

while H_RESET is asserted, while the EEPROM is

being read and while the DISPM bit is set. When none

of these conditions are true, the Network Port Manager

proceeds through the following steps:

1. If XPHYRST is set, write to the PHY’s Control Reg-

ister (R0) to set the Soft Reset bit and cause the

PHY to reset. The Network Port Manager then peri-

odically reads the PHY’s Control Register (R0) until

the reset is complete.

2. If XPHYRST is not set or after the PHY reset is com-

plete, the PHY’s Status Register (R1) is read.

3. If the PHY’s Auto-Negotiation Ability bit (R1, bit 3) is

0 or if the XPHYANE bit in the Control2 Register is

0, write to the PHY’s Control Register (R0) to dis-

able auto-negotiation and set the speed and duplex

mode to the values specified by the XPHYSP and

XPHYFD bits in the Control2 Register “and”ed with

the appropriate bits from the PHY's Technology

Ability Field. Then proceed to step 8.

4. Otherwise write to the Auto-Negotiation Advertise-

ment Register (R4). Bits A0 to A5 of Technology

Ability field of R4 are taken from bits 15 to 11 in R1.

Bit A6 of the Technology Ability field indicates the

MAC's ability to respond to MAC Control Pause

frames. This bit is set equal to the value of the Ne-

gotiate Pause Ability (NPA) bit in the Flow Control

mote Fault bits are set to 0, and the Selector Field

is set to 00001 to indicate IEEE Std 802.3.

5. Write to the Control Register (R0) to restart Auto-

negotiation.

6. Poll R1 until the Auto-Negotiation Complete bit is

set to 1.

7. Read the Auto-Negotiation Link Partner Ability Reg-

ister (R5). Set the MAC's speed, duplex mode, and

pause ability to the highest priority mode that is

common to both PHY devices.

8. Poll R1 until the Link Status bit is 1. If Link Status is

not found to be 1 after two polls at 900 ms intervals,

go back to step 1.

9. Poll R1 at intervals of about 900 ms until the Link

Status bit is 0. Go to step 8.

When Auto-Negotiation is complete, the Network Port

Manager examines the MF Preamble Suppression bit

in PHY register 1. If this bit is set, the Network Port

Manager suppresses preambles on all frames that it

sends until one of the following events occurs:

■A Software or hardware reset occurs.

■The DISPM bit (in CMD3.bit 14 Register) is set.

■Management frame read error occurs.

■The external PHY is disconnected.

A complete bit description of the MII and Auto-

Negotiation registers can be found in Appendix B.

The Network Port Manager is not disabled when the

MDIO pin is held low when the MII Management Inter-

face is idle. If no PHY is connected, reads of the exter-

nal PHY's registers will result in read errors, causing

the MREINT interrupt to be asserted.

Auto-Negotiation With Multiple PHY Devices

The MII Management Interface (MDC and MDIO) can

be used to manage more than one external PHY de-

vice. The external PHY devices may or may not be con-

nected to the Am79C976 controller’s MII bus. For

example, two PHY devices can be connected to the

Am79C976 controller’s MII bus so that the MAC can

communicate over either a twisted-pair cable or a fiber-

optic link. Conversely, several Am79C976 controllers

may share a single integrated circuit that contains sev-

eral PHY devices with separate MII busses but with

only one MII Management bus. In this case, the MII

Management Interface of one Am79C976 controller

could be used to manage PHY devices connected to

different Am79C976 controllers.

If more than one PHY device is connected to the MII

bus, only one PHY device is allowed to be enabled at

any one time. Since the Network Port Manager can not

detect the presence of more than one PHY on the MII

bus, the host CPU is responsible for making sure that

only one PHY is enabled. The host CPU can use the

PHY Access Register to set the Isolate bit in the Con-

trol Register (Register 0, bit 10) of any PHY that needs

to be disabled.

Operation Without MMI Management Interface

The Port Manager normally sets up the speed, duplex

mode, and flow control (pause) ability of the MAC

based on the results of auto-negotiation. However, it is

possible to operate the Am79C976 device with no MII

9/14/00 Am79C976 89

PRELIMINARY

Management Interface connection, in which case the

Port Manager is not able to start the auto-negotiation

process or set up the MAC-based on auto-negotiation

results. This may happen if the Am79C976 controller is

connected to a multi-PHY device that has only one MII

Management Interface that is shared among several

PHYs.

If the Am79C976 controller is operating without a MII

Management Interface connection to its external PHY,

the host CPU can force the MAC into the desired state

by setting the DISPM bit in CMD3 Register to 1 to dis-

able the Port Manager, then writing to the following bits:

1. FORCE_FD (CMD3, bit 12),

2. FORCE_SPEED (CTRL2, bits 18-16),

3. FORCE_LINK_STAT (CMD3, bit 11), and

4. Force Pause Ability (FPA, FLOW_CONTROL, bit

20).

These bits set up the duplex mode, speed, and flow

control ability in the MAC and put the MAC into the Link

Pass state.

Regulating Network Traffic

The Am79C976 device provides two hardware mecha-

nisms for regulating network traffic: 802.3x Flow Con-

trol and collision-based back pressure. 802.3x Flow

Control applies to full-duplex operation only, while back

pressure applies to half-duplex operation only. 802.3x

Flow Control works by sending and receiving MAC

Control PAUSE frames, which cause the receiving sta-

tion to postpone transmissions for a time determined

by the contents of the PAUSE frame. Back pressure

forces collisions to occur when other nodes attempt to

transmit, thereby preventing other nodes from transmit-

ting for periods of times determined by the back-off al-

gorithm.

MAC Control Pause Frames

The format of a MAC Control Pause frame is shown in

Table 12.

When a network station that supports IEEE 802.3x

Flow Control receives a pause frame, it must suspend

transmissions after the end of any frame that was being

transmitted when the pause frame arrived. The length

of time for which the station must suspend transmis-

sions is given in the request_operand field of the pause

frame. This pause time is given in units of slot times.

For 10-Mbps and 100-Mbps 802.3 networks, one slot

time is 512 bit times. The request_operand field is in-

terpreted as Big-Endian data. Octet 17 is the most sig-

nificant byte and octet 18 is the least significant byte.

Back Pressure

The Am79C976 device supports collision-based back

pressure for congestion control when the device is op-

erating in half-duplex mode. Back pressure is enabled

when the device is operating in half duplex mode and

either the Flow Control Command bit (FCCMD,

FLOW_CONTROL, bit 16) is set or the FC Pin Enable

bit (FCPEN, FLOW_CONTROL, bit 17) is set and the

FC pin is asserted.

When the MAC begins receiving a frame that passes

the address matching criteria and if back pressure is

enabled, the MAC will intentionally cause a collision by

transmitting a “phantom” frame consisting of a continu-

ous stream of alternating 1s and 0s. The length of the

phantom frame is 568 bits so that it will be interpreted

as a runt frame.

Back pressure does not affect the transmission of a

frame. The MAC will only force a collision when it be-

gins to receive a new frame.

The generation of a Back-Pressure collision causes the

XmtBackPressure MIB Counter to increment.

Enabling Traffic Regulation

Traffic regulation can be controlled either by external

hardware or by CPU commands. Traffic regulation is

affected by the following:

■Duplex mode

■Flow Control (FC) pin

■FC Pin Enable (FCPEN) bit

■Flow Control Command (FCCMD) bit

■Fixed Length Pause (FIXP) bit

■16-bit PAUSE Length Register

Table 12. MAC Control Pause Frame Format

Octet

Numbers Field Name Value

1-6 Destination

Address 01-80-C2-00-00-01

7-12 Source Address Sender’s physical

address

13-14 Length/Type 88-08

15-16 MAC Control

Opcode 00-01

17-18 Request_operand Pause time measured in

slot times

19-60 Pad Zeros

61-64 FCS FCS

Table 12. MAC Control Pause Frame Format

90 Am79C976 9/14/00

PRELIMINARY

■Negotiate Pause Ability (NPA) bit

■Force Pause Ability (FPA) bit.

The duplex mode affects the type of traffic regulation

that is used. In full-duplex mode the FC pin and the

FCPEN, FCCMD, and FIXP bits control the transmis-

sion of pause frames. In half-duplex mode the same

pin and bits control the assertion of back pressure.

Also, in half-duplex mode the Am79C976 device does

not respond to received pause frames.

The Am79C976 device includes support for two styles

of full-duplex flow control. In one style, which is similar

to an XON-XOFF protocol, a pause frame whose

request_operand field (bytes 17 and 18) contains

0FFFFh is sent to prevent the link partner from transmit-

ting. Later, a pause frame whose request_operand field

contains 0 is sent to allow the link partner to resume

transmissions. This style of flow control is selected by

clearing the Fixed Length Pause bit (FIXP) to 0.

For the other style of flow control, a single pause frame

is sent to halt transmissions for a predetermined period

of time. The contents of the request_operand field of

this frame are taken from the Pause Length register.

This style of flow control is selected by setting the Fixed

Length Pause bit (FIXP) to 1.

Hardware Control of Traffic Regulation

The Flow Control pin (FC) allows external hardware to

cause pause frames to be transmitted or back pressure

to be asserted. The use of the FC pin for traffic regula-

tion is enabled by the FC Pin Enable bit (ENFC). When

FCPEN is cleared to 0, the signal on the FC pin is ig-

nored. Otherwise, back pressure is enabled when FC

is high and the device is operating in half-duplex mode,

and pause frames are sent at FC pin signal transitions

when the device is operating in full-duplex mode.

In full-duplex mode with the FC Pin Enable bit (FCPEN)

=1, the actions that occur at low-to-high and high-to-

low transitions of the FC pin depend on the value of the

Fixed Length Pause bit (FIXP). If FIXP is 1, a low-to-

high transition causes a pause frame to be sent with its

request_operand field contents taken from the Pause

Length register. In this case high-to-low transitions of

the FC pin are ignored.

If FIXP is 0, a low-to-high transition sends a pause

frame whose request_operand field contains 0FFFFh,

while a high-to-low transition sends a pause frame

whose request_operand field contains 0.

The effects of the FC pin are summarized in Table 13.

Software Control of Traffic Regulation

For software control of traffic regulation the Flow Con-

trol Command bit (FCCMD) mimics the FC pin.

In half-duplex mode, back pressure is enabled when

FCCMD is set to 1, and it is disabled when FCCMD is

cleared to 0.

In full-duplex mode, the act of setting FCCMD to 1

causes a pause frame to be sent. The contents of the

request_operand field of the frame depend on the state

of the FIXP bit. If FIXP is 1, the contents of the

request_operand field are copied from the Pause

Length register. If FIXP is 0, the contents of the

request_operand field are set to 0FFFFh.

In full-duplex mode, if FIXP is 0, the act of clearing

FCCMD to 0 causes a pause frame to be sent with its

request_operand field cleared to 0.

If FIXP is set to 1, the FCCMD bit is self-clearing--the

CPU does not have to write to the Am79C976 device to

clear the FCCMD bit. This allows the CPU to use a sin-

gle write access to cause a pause frame to be sent with

a predetermined request_operand field.

Table 13. FC Pin Functions

FC Pin

Transition FCPEN FIXP

Duplex

Mode Action

X 0 X X No Action

0 to 1 1 X Half Enable back

pressure

1 to 0 1 X Half Disable back

pressure

0 to 1 1 1 Full

Send pause frame

with request

operand equal to

the contents of the

Pause Length

1 to 0 1 1 Full No action

0 to 1 1 0 Full

Send pause frame

with request

operand equal to

0FFFFh.

1 to 0 1 0 Full

Send pause frame

with request

operand equal to

0000h.

9/14/00 Am79C976 91

PRELIMINARY

The effects of the FCCMD bit are summarized in

Table 14.

Programming the Pause Length Register

When the host CPU changes the contents of the Pause

Length Register, it must make sure that no Pause

frame is transmitted while the register is being updated.

If the host CPU can not control the state of the FC pin,

it can clear the FCPEN pin so that the FC pin will be ig-

nored. It can then poll the PAUSE_PENDING bit in the

Status0 Register until that bit is 0. When FCPEN and

PAUSE_PENDING are both 0, it is safe to write to the

Pause Length Register.

PAUSE Frame Reception

The ability to respond to received pause frames, or

pause ability, is controlled independently from the

transmission of pause frames. When pause ability is

enabled, the receipt of a pause frame causes the de-

vice to stop transmitting for a time period that is deter-

mined by the contents of the pause frame.

Pause ability is enabled by Negotiate Pause Ability

(NPA, FLOW_CONTROL, bit 19) and Force Pause

Ability (FPA, FLOW_CONTROL, bit 20). If the FPA bit

is set, pause ability is enabled regardless of the Pause

Ability state of the link partner. If the NPA bit is set and

the FPA bit is not set, pause ability is enabled only if the

auto-negotiation process determines that the link part-

ner also supports 802.3x flow control.

The auto-polling state machine is extended to read the

external PHY Status registers at register locations 1, 4,

and 5. (The contents of these registers are defined in

the IEEE P802.3u specification.) From Register 1 the

state machine obtains the link status and auto-negotia-

tion status as well as Jabber and Remote Fault indica-

tions. If auto negotiation is complete, the logic uses the

Technology Ability fields of the Auto-Negotiation Adver-

tisement register (Register 4) and the Auto-Negotiation

Link Partner Ability register (Register 5) to determine

the network speed and duplex mode and the flow con-

trol status. The MAC device will be put into the speed

and duplex mode for the highest common ability that

the PHY and its link partner share. If full-duplex mode

is selected and the PAUSE bits are set in both Register

4 and Register 5, pause ability will be enabled so that

the MAC will be able to respond to MAC Control

PAUSE frames as described in the IEEE P802.3x

specification.

A MAC Control PAUSE frame is any valid frame with

the following:

■A destination address field value equal to the MAC’s

physical address or equal to the reserved multicast

address 01-80-C2-00-00-01,

■A Length/Type field value equal to 88-08, and

■A MAC Control Opcode field value equal to 0001.

If such a frame is received while pause ability is en-

abled, the MAC device will wait until the end of the

frame currently being transmitted (if any) and then stop

transmitting for a time equal to the value of the

request_operand field (octets 17 and 18) multiplied by

512-bit times.

If another MAC Control PAUSE frame is received

before the Pause timer has timed out, the Pause timer

will be reloaded from the request_operand field of the

new frame so that the new frame overrides the earlier

one.

Received MAC Control PAUSE frames are handled

completely by the Am79C976 hardware. They are not

passed on to the host computer. However, MAC Con-

trol frames with opcodes not equal to 0001h are treated

as normal frames, except that their reception causes

the Unsupported Opcodes counter to be incremented.

Since the host computer does not receive MAC Control

PAUSE frames, 32-bit MIB counters have been added

to record the following:

■MAC Control Frames received

■Unsupported Opcodes received

■PAUSE frames received

Table 14. FCCMD Bit Functions

FCCMD

Transition FIXP

Duplex

Mode Action

0 to 1 X Half Enable back pressure

1 to 0 X Half Disable back pressure

0 to 1 1 Full

Send pause frame with

request operand equal to

the contents of the Pause

Length register.

Automatically clear

FCCMD to 0.

1 to 0 1 Full

No action. (FCCMD is

cleared automatically

when FIXP = 1.)

0 to 1 0 Full

Send pause frame with

request operand equal to

0FFFFh.

1 to 0 0 Full

Send pause frame with

request operand equal to

0000h.

92 Am79C976 9/14/00

PRELIMINARY

External Address Detection Interface

The EADI is provided to allow external address filtering

and to provide a Receive Frame Tag word for propri-

etary routing information. This feature is typically uti-

lized by terminal servers, switches and/or router

products. The EADI interface can be used in conjunc-

tion with external logic to capture the packet destina-

tion address from the MII input data stream as it arrives

at the Am79C976 controller, to compare the captured

address with a table of stored addresses or identifiers,

and then to determine whether or not the Am79C976

controller should accept the packet.

The EADI consists of the External Address Reject

(EAR), Start Frame-Byte Delimiter (SFBD), Receive

Frame Tag Data (RXFRTGD), and Receive Frame Tag

Enable (RXFRTGE) pins.

The SFBD pin indicates two types of information to the

external logic--the start of the frame and byte bound-

aries. The first low-to-high transition on the SFBD pin

after the assertion of the RX_DV signal indicates that

the first nibble of the Destination Address field of the in-

coming frame is available on the RXD[3:0] pins. There-

after, SFBD toggles with each RX_CLK pulse so that

SFBD is high when the least significant nibble of frame

date is present on the RXD[3:0] lines and low when the

most significant nibble is present. SFBD stays low

when RX_DV is not asserted (which indicates that the

receiver is idle).

Note that the SFBD signal is available on any LED pin.

To direct the SFBD signal to one of the LED pins, the

SFBDE and LEDPOL bits should be set to 1 and the

PSE bit should be cleared to 0 in the appropriate LED

pin, the LEDPOL bit sets the polarity to active high and

enables the totem-pole driver, and the PSE bit disables

the LED pulse stretcher logic.

If the system needs all four LEDs as well as the EADI

function, the Am79C976 controller can be programmed

to use the shared pin for the LED function, and the ex-

ternal logic can be designed to generate the SFBD sig-

nal by searching for the 11010101b Start Frame

Delimiter (SFD) pattern in the RCD[3:0] data.

The external address detection logic can use the EAR

input to indicate whether or not the incoming frame

should be accepted. If the EAR signal remains high

during the receive protect time, the frame will be ac-

cepted and copied into host system memory. The re-

ceive protect time is a period of time measured from the

receipt of the SFD field of a frame. The length of the re-

ceive protect time is programmable through the Re-

ceive Protect Register.

A frame is accepted if it passes either the internal ad-

dress match criteria or the external address match cri-

teria. If the internal address logic is disabled, the

acceptance of a frame depends entirely on the external

address match logic. If the external address match

logic is disabled, the acceptance of a frame depends

entirely on the internal address match logic.

Internal address match is disabled when PROM

(CSR15, bit 15) is cleared to 0, DRCVBC (CSR15, bit

14) and DRCVPA (CSR15, bit 13) are set to 1, and the

Logical Address Filter registers (CSR8 to CSR11) are

programmed to all zeros.

External address matching can be disabled by holding

the EAR pin low. There is no programmable bit that

causes the Am79C976 device to ignore the state of the

EAR pin.

The EADI logic only samples EAR from 2 nibble times

after SFD until the end of the receive protect time. (See

the Receive Protect Register section.) The frame will

be accepted if EAR has not been asserted during this

window. EAR must have a pulse width of at least two

bit times plus 10 ns.

External Address Detection Interface: Receive

Frame Tagging

Receive Frame Tagging is a feature that allows the ex-

ternal address detection logic to pass an identification

code or tag to the Am79C976 controller to be placed in

the RX descriptor corresponding to a received frame.

The external logic can shift this tag in as a serial bit

stream on the Receive Frame Tag Data (RXFRTGD)

pin. It uses the Receive Frame Tag Enable (RX-

FRTGE) pin to indicate when the tag data is valid. The

clock signal for shifting in the tag data is RX_CLK. See

Figure 35.

If the Software Style (SWSTYLE) field in BCR20 con-

tains the value 2 or 3, the Receive Frame Tag can be

up to 15 bits long. In this case the tag data is sampled

on the low-to-high transition of RX_CLK whenever RX-

FRTGE is high. If SWSTLYE = 5, the Receive Frame

Tag can be up to 32 bits long. In this case, the tag data

is sampled on both edges of RX_CLK so that the entire

tag can be shifted in 16 RX_CLK cycles or less, de-

pending on the length of the tag. If SWSTYLE is 0 or 4,

Receive Frame Tagging is not supported. In those

cases the descriptor space is allocated to other func-

tions.

If SWSTYLE = 5, tag bits are shifted in the order B31,

B15, B30, B14, … , B0, where B0 is the least significant

bit of the tag. This sequence allows the external logic

to be simplified slightly if the system design requires a

frame tag of fewer than 17 bits. In this case the external

logic can use only one clock edge to shift in the data.

Since the Am79C976 device samples the RXFRTGD

pin on both edges of RX_CLK, the same data will ap-

pear in the upper and lower halves of the frame tag field

in the descriptor.

9/14/00 Am79C976 93

PRELIMINARY

If SWSTYLE = 2 or 3, tag bits are shifted in the order

B14, B13, ... , B0.

Because of the order in which frame tag bits are shifted

in, if the tag is shorter than 15 bits, the tag data will be

placed in the least significant portion of the Receive

Frame Tag field of the RX descriptor, and the most sig-

nificant bits of the field will be cleared to zeros.

RXFRTGE need not be a continuous signal. It can tog-

gle on and off so that the tag data can be shifted in at a

slower rate than the frequency of RX_CLK. The length

of the frame tag is determined by the number of

RX_CLK cycles during which RXFRTGE is asserted

before the end of the frame arrives (with a maximum of

15 bits for SWSTYLE 2 or 3 or a maximum of 32 bits for

SWSTYLE 5). The last bit of the Receive Frame Tag

must be shifted into the RXFRTGD input at least one

RX_CLK cycle before RX_DV is de-asserted.

The Receive Frame Tagging feature is enabled by the

RXFRTGEN bit in CMD3 Register. When this bit is

cleared to 0, the Receive Frame Tag field of the RX de-

scriptor will be filled with zeros.

Figure 35. MII Receive Frame Tagging

External Memory Interface

The Am79C976 controller contains an External Mem-

ory Interface that supports Flash (or EPROM) devices

as boot devices, as well as SSRAM for frame data stor-

age. The controller provides read and write access to

Flash or EPROM. No glue logic is required for the

memory interface.

The Am79C976 device contains a built-in self test sys-

tem (MBIST) that can be programmed to run a diag-

nostics test on the external SSRAM.

The external SSRAM is organized around a 32-bit data

bus. The memory can be as large as 1M X 32 bits. The

memory devices can be either JEDEC standard Pipe-

line Burst Synchronous Static RAM devices (PB-SS-

RAM) or ZBT™ Synchronous Static RAM (ZBT-

SSRAM) with pipelined outputs. The SRAM_TYPE

field of the CTRL0 Register must be initialized to in-

dicate which type of SSRAM is actually used.

The contents of the SRAM_TYPE field are defined in

Table 15.

The width of the Flash memory (or EPROM) is 8 bits.

The memory can be as large as 16M X 8 bits.

The external memory bus uses the same address,

data, and control pins to access both Flash and

SSRAM memory, but it has separate chip select (or

chip enable) pins so that only one device can be se-

lected at a time. FLCS selects the Flash memory, while

ERCE selects the SSRAM. The Flash memory must

not be accessed when the Am79C976 controller is run-

ning (when the RUN bit in CMD0 is set to 1). Any ac-

cess to the Flash memory clears the RUN bit and

thereby abruptly stops all network and DMA opera-

tions.

ERA[19:0] provides 20 bits of address for the SSRAM

and the lower 20 bits of address for the Flash memory.

RX_CLK

RX_DV

MIIRXFRTGE

MIIRXFRTGD

SF/BD

Table 15. SRAM_TYPE Field Encoding

SRAM_TYPE[1:0] External Memory Type

00 Reserved

01 ZBT

10 Reserved

11 Pipelined Burst

94 Am79C976 9/14/00

PRELIMINARY

The higher 4 bits of address for the Flash memory are

shared with bits [11:8] of the SSRAM data bus

(ERD[11:8]). The lower 8 bits of the external memory

data bus ERD[7:0] are used by both the SSRAM and

the Flash. The high order 20 bits of the external mem-

ory data bus ERD[31:12] are used only by the SSRAM.

The output enable signal for the Flash (FLOE) shares

a pin with the SSRAM Address Advance signal

(ERADV).

Figure 36 shows how the SSRAM and Flash can be

connected to the Am79C976 controller.

Expansion ROM - Boot Device Access

The Am79C976 controller supports EPROM or Flash

as an Expansion ROM boot device. Both are config-

ured using the same methods and operate the same.

See Figure 36. See the previous section on Expansion

ROM transfers for the PCI timing and functional de-

scription of the transfer method.

Figure 36. External SSRAM and Flash Configuration

The Am79C976 controller will always read four bytes

for every host Expansion ROM read access. The inter-

face to the Expansion Bus is timed by an internal signal

called ROMCLK, which runs at one fourth of the fre-

quency of the external memory interface clock (ER-

CLK). Thus, when the clock select pins are configured

so that ERCLK runs at 90 MHz; ROMCLK runs at 22.5

MHz.

The time that the Am79C976 controller waits for data to

be valid is programmable. ROMTMG (CTRL0, bits 8-11

or BCR18, bits 15-12) defines the time from when the

Am79C976 controller drives ERA[19:0] with the Expan-

sion ROM address to when the Am79C976 controller

latches in the data on the ERD[7:0] inputs. The register

value specifies the time in number of ROMCLK cycles.

When ROMTMG is set to nine (the default value),

ERD[7:0] is sampled with the next rising edge of ROM-

CLK ten cycles after ERA[19:0] was driven with a new

address value. The clock edge that is used to sample

the data is also the clock edge that generates the next

Expansion ROM address. All four bytes of Expansion

ROM data are stored in holding registers.

Because Expansion ROM accesses take longer than

16 PCI bus clock cycles, the PCI access will be discon-

nected with no data transfer after 15 clocks. Subse-

quent accesses will be retried until all four bytes have

been read from the Expansion ROM.

ERCLK

EROE

A[19:0]

DQ[7:0]

L4 Controller

FLASH

A[23:20]

SSRAM

CLK

A[16:0]

CE1 OR CE2

D[31:0]

GW OR R/W

ADV

ADSP OR CEN

ERA[19:0]

ERD[31:0]

ERWE/FLWE

ERADV/FLOE

ERADSP/CEN

ERCE

FLCS

1720

[11:8]

[7:0]

A17

9/14/00 Am79C976 95

PRELIMINARY

The timing diagram in Figure 37 assumes the default

programming of ROMTMG (1001b = 9 CLK). After

reading the first byte, the Am79C976 controller reads in

three more bytes by incrementing the lower portion of

the ROM address. The PCI bus logic generates discon-

nect/retry cycles until all 32 bits are ready to be trans-

ferred over the PCI bus. When the host tries to perform

a burst read of the Expansion ROM, the Am79C976

controller will disconnect the access at the second data

phase.

Figure 37. Expansion ROM Bus Read Sequence

The host must program the Expansion ROM Base Ad-

dress register (ROMBASE) in the PCI configuration

space before the first access to the Expansion ROM.

The Am79C976 controller will not react to any access

to the Expansion ROM until both MEMEN (PCI Com-

mand register, bit 1) and ROMEN (PCI Expansion ROM

Base Address register, bit 0) are set to 1.

The amount of memory space that the Am79C976 de-

vice will claim for the Expansion ROM depends on the

contents of the Expansion ROM Configuration Register

(ROM_CFG), which should be loaded from the EE-

PROM. This register is included in the Am79C976 de-

vice so that the controller can accommodate ROMs of

different sizes without wasting memory space. The

ROM occupies a block of memory space that is some

power of two between 2K and 16M in size. If the ROM

requires 2n bytes of address space, bits 1 through n-1

of the Expansion ROM Base Address Register in PCI

configuration space (ROMBASE) should appear to be

wired to 0. The contents of the Expansion ROM Config-

uration Register (ROM_CFG) determine how many bits

of the configuration space register are forced to 0.

Bits [15:1] of ROM_CFG correspond to bits [23:9] of

ROMBASE and bit 0 of ROM_CFG corresponds to bit

0 of ROMBASE. If a bit in ROM_CFG is set to 0, the

corresponding bit in ROMBASE is fixed at zero. If a bit

in ROM_CFG is set to 1, the corresponding bit in ROM-

BASE can be programmed to 0 or 1 through PCI con-

figuration space accesses to ROMBASE.

Bit 0 of ROM_CFG controls bit 0 of ROMBASE. If bit 0

of ROM_CFG is 0, the host CPU cannot write to bit 0 of

ROMBASE. This bit is the address decode enable bit.

When this bit is fixed at 0, it will appear to the host CPU

that the ROM Base Address Register and, therefore,

the expansion ROM does not exist.

If bit 0 of ROM_CFG is set to 1, the host CPU is able to

read and write bit 0 of ROMBASE.

As an example, if the Expansion ROM occupies 216

(65536) bytes, bits 15:9 of ROMBASE should be fixed

at 0. Since bits 15:9 of ROMBASE are controlled by bits

7:1 of ROM_CFG, bits 7:1 of ROM_CFG should be

cleared to 0 and bits 15:8 should be set to 1. To make

ROMBASE accessible to the host CPU, bit 0 of

ROM_CFG should be set to 1. Therefore, ROM_CFG

should be set to FF01h. If the host CPU writes all 1s to

the ROMBASE register and then reads back the con-

tents of ROMBASE, the result would be FFFF0001h.

After the host CPU has written to the Expansion ROM

Base Address Register in PCI configuration space to

map the ROM into PCI memory space and to enable

accesses to the ROM, the address output to the Ex-

pansion ROM will be the offset from the address on the

PCI bus to ROMBASE.

ROMCLK

ERA[19:0]

ERD[7:0]

FLCS

FLOE

FLWE

96 Am79C976 9/14/00

PRELIMINARY

The Am79C976 controller aliases all accesses to the

Expansion ROM of the command types Memory Read

Multiple and Memory Read Line to the basic Memory

Read command.

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given to

the PCI Memory Mapped I/O Base Address register,

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base Ad-

dress register to a value that prevents the Am79C976

controller from claiming any memory cycles not in-

tended for it.

During the boot procedure, the system will try to find an

Expansion ROM. A PCI system assumes that an Ex-

pansion ROM is present when it reads the ROM signa-

ture 55h (byte 0) and AAh (byte 1).

Direct Flash Access

In addition to mapping the Flash memory into PCI ad-

dress space, the Am79C976 controller provides an in-

direct read/write data path for programming the Flash

memory. The Flash is accessed by first writing the

memory address to the Flash Address Register, and

then reading or writing the Flash Data Register.

For software compatibility with older PCnet devices,

the Flash device can also be accessed by a read or

write to the Expansion Bus Data port (BCR30). The

user must load the upper address EPADDRU (BCR 29,

bits 3-0). EPADDRU is not needed if the Flash size is

64K or less, but still must be programmed. The user will

then load the lower 16 bits of address, EPADDRL (BCR

28, bits 15-0).

Flash/EPROM Read

A read to the Flash Data Register will start a read cycle

on the External Memory Interface. The Am79C976

controller will drive ERD[11:8] with the 4 most signifi-

cant address bits at the same time that it drives

ERA[19:0] with the 20 least significant bits.

The FLCS pin is driven low for the value ROMTMG + 1.

Figure 38 assumes that ROMTMG is set to nine.

ERD[7:0] is sampled with the next rising edge of CLK

ten clock cycles after ERA[19:0] was driven with a new

address value. This PCI slave access to the Flash/

EPROM will result in a retry for the very first access.

Subsequent accesses may give a retry or not, depend-

ing on whether or not the data is present and valid. The

access time is dependent on the ROMTMG bits

(CTRL0, bits 11-8, or BCR18, bits 15-12) and can be

tuned for the particular memory device used.

This access mechanism using BCR28, 29, and 30 dif-

fers from the Expansion ROM access mechanism

since only one byte is read in this manner, instead of

the 4 bytes in an Expansion ROM access.

If the Lower Address Auto Increment (LAAINC) bit

(FLASH_ADDR, bit 31 or BCR29, bit 14) is set, the

EBADDRL address will be incremented and a continu-

ous series of reads from the Expansion Data Port

(FLASH_DATA or EBDATA, BCR30) is possible. The

upper address field, EBADDRU, is not automatically

incremented when the lower address field, EBADDRL

rolls over.

The Flash write procedure is almost identical to the

read access, except that the Am79C976 controller will

not drive FLOE low. The FLCS and FLWE signals are

driven low for the value ROMTMG again. The write to

the FLASH port is a posted write and will not result in a

retry to the PCI, unless the host tries to write a new

value before the previous write is complete. Then the

host will experience a retry. See Figure 39.

Figure 38. Flash Read from Expansion Bus Data Port

ROMCLK

ERA[19:0]

FLCS

FLOE

ERD[7:0]

FLWE

9/14/00 Am79C976 97

PRELIMINARY

Figure 39. Flash Write Sequence

SRAM Configuration

The Am79C976 controller uses external SSRAM for re-

ceive and transmit FIFOs. The size of the SSRAM can

be up to 4 Mbytes, organized as 1M X 32 bits. The size

of the SSRAM is indicated by the contents of the

SSRAM Size Register (or BCR25). SRAM_SIZE

should be loaded from the EEPROM.

The SSRAM is programmed in units of 512-byte pages.

To specify how much of the SSRAM is allocated to

transmit and how much is allocated to receive, the user

should program SRAM_BND Register (or BCR26, bits

15-0) with the page boundary where the receive buffer

begins. The SRAM_BND is also programmed in units

of 512-byte pages. The transmit buffer space starts at

0000h. It is up to the user or the software driver to split

up the memory for transmit or receive; there is no de-

faulted value. The minimum SSRAM size required is

four 512-byte pages for each transmit and receive

queue, which limits the SSRAM size to be at least 4

Kbytes.

The SRAM_BND upon H_RESET will be reset to

0000h. SRAM_BND must be programmed to a non-

zero value if the transmitter is enabled. SRAM_BND

should be programmed to a value larger than the max-

imum frame size to use the automatic retransmission

options, REX_UFLO, REX_RTRY, and RTRY_LCOL,

or if the transmit FIFO start point, XMTSP, is set to Full

Frame. (XMTSP is CTRL1, bits 17-16, or CSR80, bits

11-10.)

The Am79C976 controller does not allow software di-

agnostic access to the SRAM as do older devices in the

PCnet family. The Am79C976 controller provides soft-

ware access to an internal memory built-in self-test

(MBIST) controller which runs extensive, at-speed

tests on the external SRAM, internal SRAM access

logic, and the PC board interconnect.

The MBIST controller can determine the size of the ex-

ternal SRAM and verify its operation using the following

procedure:

1. Program SRAM_SIZE to the minimum allowed

value of 4.

2. Write DM_START and DM_FAIL_STOP (write

DATAMBIST bits 63:56 with 0x28). The remainder

of the DATAMBIST register ignores writes so it may

be written with arbitrary data or not written at all.

3. Read DM_DONE (DATAMBIST bit 63) and

DM_ERROR (DATAMBIST bit 62) until DM_DONE

is set.

4. If DM_ERROR is set, the memory is defective; re-

port the error and exit.

5. Program SRAM_SIZE to the maximum value of

0x8000 and repeat steps 2 and 3.

6. If DM_ERROR is zero, report the current value of

SRAM_SIZE as the SSRAM size.

7. If DM_ERROR is set, program SRAM_SIZE to one-

half the maximum (0x4000) and repeat steps 2

and 3.

8. Repeat, using the binary search algorithm, until the

SRAM size has been determined.

EEPROM Interface

The Am79C976 device includes an interface to an op-

tional 16-bit word-oriented 93Cxx-compatible serial

EEPROM that supports automatic address increment-

ing (sequential read). This EEPROM can be used for

storing initial values for Am79C976 registers. The con-

tents of this EEPROM are automatically loaded into the

ROMCLK

ERA[19:0]

FLCS

FLOE

ERD[7:0]

FLWE

98 Am79C976 9/14/00

PRELIMINARY

selected registers after a reset operation or whenever

the host CPU requests an EEPROM read operation.

Note that if the EEPROM is not included in the system,

the MAC address (and Magic Packet information, if

needed) must be initialized by the host CPU.

The Am79C976 device automatically detects the size

of the EEPROM. When the EEPROM decodes a read

command, it drives its DO pin low when the A0 address

bit is written to the DI pin. The Am79C976 device uses

this fact to detect the number of bits in the EEPROM

address and from this determines the EEPROM size.

Data in the EEPROM are interpreted as three-byte

entries that contain register address and register data

so that the system designer can choose which regis-

ters will automatically be loaded. In a typical system,

the EEPROM would be used to initialize the device’s

IEEE 802 physical address, the PCI Subsystem Ven-

dor ID, LED configuration, SSRAM configuration, and

other hardware configuration information. For compat-

ibility with older PCnet family software the Address

PROM Space should be loaded from the EEPROM.

See the Address PROM Space section for details.

Only the memory-mapped registers can be loaded

from the EEPROM. While the CSRs and BCRs are not

memory-mapped, all useful bits in the CSRs and BCRs

are aliased into memory-mapped registers so that all

useful bits can be loaded from the EEPROM.

Most of the memory-mapped registers are 32 bits wide

and occupy 4 bytes of memory space each. For exam-

ple, the CMD2 Register is located at offset 50h from the

memory base address. Its least significant 16 bits can

be accessed at offset 50h, and its most significant 16

bits can be accessed at offset 52h. Register data are

loaded from the EEPROM 16 bits at a time, so that the

high order bits of a register are loaded independently

from the low order bits.

The EEPROM Access Register gives the host CPU di-

rect access to the interface pins so that it can read from

or write to the EEPROM.

Automatic EEPROM Read Operation

After the trailing edge of the RESET signal or after the

PREAD bit in BCR19 is set, the Am79C976 device be-

gins to read data from the EEPROM. Data from the EE-

PROM are interpreted as a string of 3-byte entries.

Each entry contains a 1-byte register address and a

2-byte register data field. The register address field

contains the offset of the target register divided by 2.

The initialization logic writes the contents of the register

data field into the register selected by the register ad-

dress byte.

Since EEPROM data are loaded two bytes at a time,

the least significant bit of the target register offset is

omitted from the address field. Only bits 8:1 are in-

cluded. Therefore, the register address byte contains

the offset of the target register divided by two. For ex-

ample, the Control2 Register (CTRL2) is a 32-bit regis-

ter located at offset 70h (relative to the contents of the

Memory-Mapped I/O Base Address Register). There-

fore, the byte stream 38h, 02h, 05h would cause the

value 0205h to be loaded into bits [15:0] of CTRL2, and

39h, 00h, 03h would cause the value 0003h to be

loaded into bits [31:16] of the same register.

If the value of the address byte is 0FFh, the following

2-byte field is interpreted as a 16-bit CRC code rather

than as register data. The CRC code covers all

EEPROM data up to and including the address byte of

the entry containing the CRC. All EEPROM data after

the CRC code word are ignored.

The CRC code used is CRC-16, which is based on the

generator polynomial x16 + x15 + x2 + 1.

The EEPROM must contain data for an odd number of

registers so that the CRC is aligned on a 16-bit word

boundary in the EEPROM. If an even number of regis-

ters need to be loaded from the EEPROM, two dupli-

cate entries for the same register can be included so

that the CRC is aligned properly.

For full compatibility with legacy Magic Packet soft-

ware, the EEPROM should initialize both the APROM

area (offset 0-0Fh) and the PADR Register.

Data are shifted into or out of the EEPROM most sig-

nificant bit first.

Figure 41 shows the mapping of the 3-byte entries into

the 16-bit word-oriented EEPROM.

If the Am79C976 device detects a CRC error in the EE-

PROM or fails to detect the presence of an EEPROM,

it restores all registers to their default values and clears

the PVALID bit in BCR19 to indicate the error.

9/14/00 Am79C976 99

PRELIMINARY

Figure 40. EEPROM Data Format

Figure 41. EEPROM Entry Positions

Note: All registers are restored to their default values,

not just those registers that were altered by the EE-

PROM read operation.

If the Am79C976 device detects a correct CRC code, it

sets the PVALID bit to 1 to indicate that the registers

have been successfully initialized.

The CPU can initiate an automatic EEPROM read op-

eration at any time by setting the PREAD bit in BCR19

to 1.

The CPU cannot access any Am79C976 register while

an automatic EEPROM read operation is in progress. If

the CPU attempts to access a register during this time,

the Am79C976 controller will terminate the access at-

tempt by asserting DEVSEL and STOP while TRDY is

not asserted, a combination that indicates that the initi-

DATA[15:8]

DATA[7:0]

Entry for 1 register Data covered

by CRC

Byte 127

DATA[15:8]

DATA[7:0]

0FFh

CRC[15:8]

CRC[7:0]

Byte 0

ADR1 DATA[15:8]

DATA[7:0]Word 1 ADR2

DATA[15:8] DATA[7:0]

Word 0

ADR3 DATA[15:8]

DATA[7:0] ADR4

DATA[15:8] DATA[7:0]

Shaded area

represents 1 entry.

578

Bit:

100 Am79C976 9/14/00

PRELIMINARY

ator must disconnect and retry the access at a later

time. The automatic read operation takes about 180 µs

for each 16-bit register that is initialized plus 180 µs for

the CRC code word.

EEPROM Auto-Detection

When the address field of an EEPROM instruction is

shifted in through the DI pin of the EEPROM, the

EEPROM drives its DO pin low when the A0 bit ap-

pears on the DI pin. The Am79C976 controller makes

use of this feature to detect the presence of an

EEPROM. When the device attempts to read the first

word from the EEPROM and if the EEDO pin is not

driven low before the 15th EESK clock cycle, the de-

vice assumes that there is no EEPROM present.

Direct Access to the Interface

The user can directly access the port through the

EEPROM Access Register (BCR19). This register con-

tains bits that can be used to control the interface pins.

By performing an appropriate sequence of accesses to

BCR19, the user can effectively write to and read from

the EEPROM. This feature may be used by a system

configuration utility to program hardware configuration

information into the EEPROM.

EEPROM CRC Calculation

The EEPROM interface logic first shifts each 16-bit

word from the EEPROM most significant bit first into an

internal holding register. Then it shifts the word through

the CRC logic least significant bit first, effectively swap-

ping the bytes. Therefore, the data shown in Figure 42

are processed by the CRC logic in the following order:

DATA[15:8], ADR1, ADR2, DATA[7:0], DATA[7:0],

DATA[15:8], ... .

Figure 42. CRC Flow

LED Support

The Am79C976 controller can support up to four LEDs.

LED outputs LED0, LED1, and LED2 allow for direct

connection of an LED and its supporting pull-up device.

In applications that want to use the pin to drive an LED

and also have an EEPROM, it might be necessary to

buffer the LED3 circuit from the EEPROM connection.

When an LED circuit is directly connected to the

EEDO/LED3/RXFRTGD pin, then it is not possible for

most EEPROM devices to sink enough IOL to maintain

a valid low level on the EEDO input to the Am79C976

controller. Use of buffering can be avoided if a low

power LED is used.

Each LED can be programmed through a BCR register

to indicate one or more of the following network

statuses or activities: Collision Status, Full-Duplex Link

Status, Receive Match, Receive Status, Magic Packet,

Transmit Status, and Start Frame/Byte Delimiter.

The LED pins can be configured to operate in either

open-drain mode (active low) or in totem-pole mode

(active high). The output can be stretched to allow the

human eye to recognize even short events that last

only several microseconds. After H_RESET, the four

LED outputs are configured as shown in Table 16.

For each LED register, each of the status signals is

AND’d with its enable signal, and these signals are all

OR’d together to form a combined status signal. Each

LED pin combined status signal can be programmed to

run to a pulse stretcher, which consists of a 3-bit shift

each shift register is normally at logic 0. The OR gate

DATA[15:8]ADR1

ADR2DATA[7:0]

DATA[7:0]DATA[15:8]

DATA[15:8]ADR3

DATA[15:8]ADR1

CRC LOGIC

15 0 15 0

Holding Register

+ +

...

x15

x16

EEPROMAm79C976 Controller

9/14/00 Am79C976 101

PRELIMINARY

output for each LED register asynchronously sets all

three bits of its shift register when the output becomes

asserted. The inverted output of each shift register is

used to control an LED pin. Thus, the pulse stretcher

provides 2 to 3 clocks of stretched LED output, or 52

ms to 78 ms. See Figure 43.

Figure 43. LED Control Logic

Power Savings Mode

Power Management Support

The Am79C976 controller supports power manage-

ment as defined in the PCI Bus Power Management In-

terface Specification V1.1 and Network Device Class

Power Management Reference Specification V1.0.

These specifications define the network device power

states, PCI power management interface including the

Capabilities Data Structure and power management

registers block definitions, power management events,

and OnNow network Wake-up events. In addition, the

Am79C976 controller supports legacy power manage-

ment schemes, such as Remote Wake-Up (RWU)

mode. The RWU mode can accommodate systems

that sleep with PCI bus power off or on and the PCI

clock running or stopped. The RWU pin can drive the

CPU’s System Management Interrupt (SMI) line or a

system power controller.

The general scheme for the Am79C976 controller

power management is that when a wake-up event is

detected, a signal is generated to cause hardware ex-

ternal to the Am79C976 device to put the computer into

the working (S0) mode. The Am79C976 device sup-

ports three types of wake-up events:

■Magic Packet Detect

■Link State Change

■Pattern Match Detect

The Am79C976 device supports two types of wake-up

control mechanisms:

Table 16. LED Default Configuration

LED

Output Indication Driver Mode Pulse Stretch

LED0 Link Status Open Drain -

Active Low Enabled

LED1 Activity Open Drain -

Active Low Enabled

LED2 Speed Open Drain -

Active Low Enabled

LED3 Coll Open Drain -

Active Low Enabled

COL

COLE

FDLS

FDLSE

LNKS

LNKSE

RCV

RCVE

RCVM

RCVME

XMT

XMTE

Pulse

Stretcher

MR_SPEED_SEL

100E

MPS

MPSE

22929B-45

102 Am79C976 9/14/00

PRELIMINARY

■PCI Bus Power Management Interface Specifica-

tion (OnNow) wake-up

■RWU (hardware controlled) wake-up

All three wake-up events and both control mechanisms

support wake-up from any power state including D3cold

(PCI bus power off and clock stopped). Figure 44

shows the relationship between these Wake-up events

and the various outputs used to signal to the external

hardware.

Figure 44. OnNow Functional Diagram

OnNow Wake-Up Sequence

The system software enables the PME pin by setting

the PME_EN bit in the PMCSR register (PCI configura-

tion registers, offset 48h, bit 8) to 1. When a Wake-up

event is detected, the Am79C976 device sets the

PME_STATUS bit in the PMCSR register (PCI configu-

ration registers, offset 48h, bit 15). Setting this bit

causes the PME signal to be asserted.

Assertion of the PME signal causes external hardware

to wake up the CPU. The system software then reads

the PMCSR register of every PCI device in the system

to determine which device asserted the PME signal.

When the software determines that the signal came

from the Am79C976 device, it writes to the device’s

PMCSR to put the device into power state D0. The soft-

ware then writes a 0 to the PME_STATUS bit to clear

the bit and turn off the PME signal, and it calls the de-

vice’s software driver to tell it that the device is now in

state D0. The system software can clear the

PME_STATUS bit either before, after, or at the same

time that it puts the device back into the D0 state.

MPDETECT

MPPEN_EE

MPEN_EE

MPINT

LED

WUMI

Magic Packet

Link Change

LCMODE_EE Link Change

MPMAT

LCDET

SET

CLR

PMAT1

SET

CLR

SET

CLR

SET

CLR

PMAT

Pattern Match

Input

Pattern

PME_STATUS

PME Status

PME_EN

MPMAT

PME_EN_OVR

LCEVENT

PME

RWU

SET

CLR

POR

H_RESET

POR

Data from PCI Bus

MPPEN_SW

MPEN_SW

PMAT0

Pattern Match RAM (PMR)

PMAT_MODE

LCMODE_SW

9/14/00 Am79C976 103

PRELIMINARY

The type of wake-up is configured by software using

the bits LCMODE_SW, PMAT_MODE, MPEN_SW and

MPPEN_SW in the CMD7 register. These bits are only

reset by the power-on reset (POR) and are not loaded

from the EEPROM so that they will maintain value

across PCI bus resets and EEPROM read operations.

RWU Wake-Up Sequence

The RWU wake-up mechanism is used by systems that

do not have software support for the PCI Bus Power

Management Interface. The wake-up may be config-

ured and controlled completely in hardware, using the

EEPROM to load Am79C976 controller registers and

using the PG pin to enable wake-up. Alternatively, if the

PCI bus power is never removed, wake-up may be

configured and enabled by software.

To accommodate systems with hardware that connects

PME to the system power control logic running soft-

ware that is not aware of the PCI Bus Power Manage-

ment Interface, the RWU signal may be routed to the

PME pin by setting the PME_EN_OVR bit (CMD3, bit

4). This is typically set by the EEPROM.

The RWU wake-up is configured by using the bits

LCMODE_EE, MPEN_EE, MPPEN_EE,

PME_EN_OVR, RWU_POL, RWU_DRIVER and

RWU_GATE in the CMD3 register. These bits are reset

by H_RESET and may be loaded from the EEPROM.

Do not use LCMODE_SW, MPEN_SW or MPPEN_SW

to enable the RWU wake-up mechanism. These bits

are intended for OnNow wake-up operation only.

The Pattern Match wake-up event is not supported by

the RWU wake-up mechanism.

For legacy system support, the Magic Packet wake-up

event may be routed to the INTA pin or to any of the

four LED pins.

Link Change Detect

Link change detect is one of the Wake-up events that

is defined by the OnNow specification and is supported

by the RWU mode. Link Change Detect mode is set

when the LCMODE_EE bit (CMD3, bit 5) is set either

by software or loaded through the EEPROM or when

the LCMODE_SW bit (CMD7, bit 0) is set by software.

When this bit is set, any change in the Link status will

cause the LC_DET bit (STAT0, bit 10) to be set. When

the LC_DET bit is set, the RWU pin will be asserted

and the PME_STATUS bit (PMCSR register, bit 15) will

be set. If either the PME_EN bit (PMCSR, bit 8) or the

PME_EN_OVR bit (CMD3, bit 4) are set, then the PME

signal will also be asserted.

The Am79C976 controller may be configured to enter

link change detect mode immediately upon initial

power-up, regardless of the presence or absence of

PCI bus power. This is accomplished by setting the

LCMODE_EE bit from the EEPROM.

Magic Packet Mode

A Magic Packet is a frame that is addressed to the

Am79C976 controller and contains a data sequence

made up of 16 consecutive copies of the device’s phys-

ical address (PADR[47:0]) anywhere in its data field.

The frame must also cause an address match. By de-

fault, it must be a physical address match, but if the

MPPLBA bit (CMD3, bit 9) is set, logical and broadcast

address matches are also accepted. Regardless of the

setting of MPPLBA, the sequence in the data field of

the frame must be 16 repetitions of the Am79C976 de-

vice’s physical address (PADR[47:0]).

Magic Packet mode is enabled by setting the

MPEN_SW bit (CMD7, bit 1) or the MPEN_EE bit

(CMD3, bit 6). Alternatively, Magic Packet mode may

be enabled by setting the MPPEN_SW bit (CMD7, bit

2) or the MPPEN_EE bit (CMD3, bit 8) and deasserting

the PG pin. Magic Packet mode is disabled by clearing

the enable bit(s) or, if only MPPEN_EE and/or

MPPEN_SW are set, by asserting PG.

The Am79C976 controller may be configured to enter

Magic Packet mode immediately upon initial power-up

if PCI bus power is off. This is accomplished by setting

the MPPEN_EE bit from the EEPROM and enabling

Magic Packet mode by the deassertion of PG.

Enabling Magic Packet mode has a similar effect to that

of suspending both transmit and receive. After the

FIFOs have emptied, no frames will be transmitted or

received until Magic Packet mode is disabled.

The WUMI output will be asserted when Magic Packet

mode is enabled.

When the Am79C976 controller detects a Magic

Packet frame, it sets the MP_DET bit (STAT0, bit 11),

the MPINT bit (INT0, bit 13), and the PME_STATUS bit

(PMCSR, bit 15). The RWU pin will also be asserted

and if the PME_EN or the PME_EN_OVR bits are set,

then the PME signal will be asserted as well. If INTREN

(CMD0, bit 1) and MPINTEN (INTEN0, bit 13) are set

to 1, INTA will be asserted. Any one of the four LED

pins can be programmed to indicate that a Magic

Packet frame has been received. MPSE (LED0-3, bit 9)

must be set to 1 to enable that function.

Note: The polarity of the LED pin can be programmed

to be active HIGH by setting LEDPOL (LED0-3, bit 14)

to 1.

Once a Magic Packet frame is detected, the

Am79C976 controller will discard the frame internally,

but will not resume normal transmit and receive opera-

tions until Magic Packet mode is disabled. Once both

of these events has occurred, indicating that the sys-

tem has detected the Magic Packet and is awake, the

controller will continue polling receive and transmit de-

scriptor rings where it left off. It is not necessary to

re-initialize the device. If the part is re-initialized, the in-

104 Am79C976 9/14/00

PRELIMINARY

ternal pointers to the current descriptors will be lost,

and the Am79C976 controller will not start where it left

off.

If Magic Packet mode is disabled by the assertion of

PG, then in order to immediately re-enable Magic

Packet mode, the PG pin must remain asserted for at

least 200 ns before it is deasserted. If Magic Packet

mode is disabled by clearing the register bits, then it

may be immediately re-enabled by setting MPEN_EE

or MPEN_SW back to 1.

The PCI bus interface clock (CLK) is not required to be

running while the device is operating in Magic Packet

mode. Either of the INTA, the LED pins, RWU, or the

PME signal may be used to indicate the receipt of a

Magic Packet frame when the CLK is stopped.

OnNow Pattern Match Mode

In the OnNow Pattern Match Mode, the Am79C976

controller compares the incoming packets with up to

eight patterns stored in the Pattern Match RAM (PMR).

The stored patterns can be compared with part or all of

incoming packets, depending on the pattern length and

the way the PMR is programmed. When a pattern

match has been detected, then PMAT_DET bit (STAT0,

bit 12) is set. This causes the PME_STATUS bit

(PMCSR, bit 15) to be set, which in turn will assert the

PME pin if the PME_EN bit (PMCSR, bit 8) is set.

Pattern Match mode is enabled by setting the

PMAT_MODE bit (CMD7,bit 3).The RUN bit (CMD0, bit

0) and RX_SPND bit (CMD0, bit 3) must also be set. If

using the legacy registers, STRT (CSR0, bit 1) and

SPND (CSR5, bit 0) must be set. Because Pattern

Match mode must be configured by software, it is not

possible to enable Pattern Match mode directly from

the EEPROM.

Pattern Match RAM (PMR)

The PMR is organized as an array of 64 words by 40

bits as shown in Figure 45. The PMR is programmed

indirectly through the PMAT0 and PMAT1 registers. For

compatibility with legacy controllers, the PMR may also

be programmed through BCR45, BCR46, and BCR47.

Pattern Match mode must be disabled (PMAT_MODE

bit cleared) to allow reading or writing the PMR.

A write access to the PMR begins with a write to the

PMAT0 register. Bits 6:0 of PMAT0 specify the address

in the PMR and bits 31:8 contain the data to be written

to bits 23:0 of the specified address in the PMR. This is

followed by a write to the PMAT1 register, with bits 15:0

of PMAT1 containing the data to be written to bits 39:24

of the specified address in the PMR. The actual write to

the PMR occurs when PMAT1 is written.

A read access to the PMR also begins with a write to

the PMAT0 register. Bits 6:0 of PMAT0 specify the ad-

dress in the PMR to be read and the remaining bits of

PMAT0 are ignored. This write is followed by a read of

PMAT0, which returns bits 23:0 of PMR in bit positions

31:8 and a read of PMAT1, which returns bits 39:24 of

PMR in bit positions 15:0. These reads may be done in

any order.

The first two 40-bit words in the PMR serve as pointers

and contain enable bits for the eight possible match

patterns. The remainder of the RAM contains the

match patterns and associated match pattern control

bits. Byte 0 of the first word contains the Pattern Enable

bits. Any bit position set in this byte enables the corre-

sponding match pattern in the PMR. As an example, if

bit 3 is set, then Pattern 3 is enabled for matching.

Bytes 1 to 4 in the first word are pointers to the begin-

ning of the patterns 0 to 3, and bytes 1 to 4 in the sec-

ond word are pointers to the beginning of the patterns

4 to 7, respectively. Byte 0 of the second word has no

function associated with it. Byte 0 of words 2 to 63 is

the Control Field of the PMR. Bit 7 of this field is the

End of Pattern (EOP) bit. When this bit is set, it indi-

cates the end of a pattern in the PMR.

Bits 6-4 of the Control Field byte are the SKIP bits. The

value of the SKIP field indicates the number of the

Dwords to be skipped before the pattern in this PMR

word is compared with data from the incoming frame. A

maximum of seven Dwords may be skipped. Bits 3-0 of

the Control Field byte are the MASK bits. These bits

correspond to the pattern match bytes 3-0 of the same

PMR word (PMR bytes 4-1). If bit n of this field is 0,

then byte n of the corresponding pattern word is ig-

nored. If this field is programmed to 3, then bytes 0 and

1 of the pattern match field (bytes 2 and 1 of the word)

are used and bytes 3 and 2 are ignored in the pattern

matching operation.

The contents of the PMR are not affected by any reset.

The contents are undefined after a power-up reset

(POR).

9/14/00 Am79C976 105

PRELIMINARY

Figure 45. Pattern Match RAM

IEEE 1149.1 (1990) Test Access Port

Interface

An IEEE 1149.1-compatible boundary scan Test Ac-

cess Port is provided for board-level continuity test and

diagnostics. All digital input, output, and input/output

pins are tested. The following paragraphs summarize

the IEEE 1149.1-compatible test functions imple-

mented in the Am79C976 controller.

Boundary Scan Circuit

The boundary scan test circuit requires four pins (TCK,

TMS, TDI and TDO), defined as the Test Access Port

(TAP). It includes a finite state machine (FSM), an in-

struction register, a data register array. Internal pull-up

resistors are provided for the TDI, TCK, and TMS pins.

TAP Finite State Machine

The TAP engine is a 16-state finite state machine

(FSM), driven by the Test Clock (TCK), and the Test

Mode Select (TMS) pins. The FSM is reset when TMS

and TDI are high for five TCK periods.

Supported Instructions

In addition to the minimum IEEE 1149.1 requirements

(BYPASS, EXTEST, and SAMPLE instructions), three

additional instructions (IDCODE, TRIBYP, and SET-

BYP) are provided to further ease board-level testing.

All unused instruction codes are reserved. See Table

17 for a summary of supported instructions.

BCR Bit Number

BCR 47 BCR 46 BCR45

15 8 7 0 15 8 7 0 15 8

PMAT1 PMAT0

15 8 7 0 31 24 23 16 15 8

PMR_B4 PMR_B3 PMR_B2 PMR_B1 PMR_B0

Pattern Match

RAM Address

Pattern Match RAM Bit Number

39 32 31 24 23 16 15 8 7 0 Comments

0P3 pointer P2 pointer P1 pointer P0 pointer Pattern Enable

bits First Address

1P7 pointer P6 pointer P5 pointer P4 pointer X Second

Address

2Data Byte 3 Data Byte 2 Data Byte1 Data Byte 0 Pattern Control Start Pattern

2+n Data Byte 4n+3 Date Byte 4n+2 Data Byte 4n+1 Data Byte 4n+0 Pattern Control End Pattern P1

JData Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 Pattern Control Start Pattern Pk

J+m Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern Pk

7 6 5 4 3 2 1 0

EOP SKIP MASK

106 Am79C976 9/14/00

PRELIMINARY

Instruction Register and Decoding Logic

After the TAP FSM is reset, the IDCODE instruction is

always invoked. The decoding logic gives signals to

control the data flow in the Data registers according to

the current instruction.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two

stages. A flip-flop and a latch are used for the Serial

Shift Stage and the Parallel Output Stage, respectively.

There are four possible operation modes in the BSR

cell shown in Table 18.

Other Data Registers

Other data registers are the following:

1. Bypass Register (1 bit)

2. Device ID register (32 bits) (Table 19).

Note: The content of the Device ID register is the

same as the content of CSR88.

Reset

There are five different types of RESET operations that

may be performed on the Am79C976 device,

H_RESET, EE_RESET, S_RESET, STOP, and POR.

The following is a description of each type of RESET

operation.

H_RESET

Hardware Reset (H_RESET) is an Am79C976 reset

operation that has been created by the proper asser-

tion of the RST pin of the Am79C976 device while the

PG pin is HIGH. When the minimum pulse width timing

as specified in the RST pin description has been satis-

fied, then an internal reset operation will be performed.

H_RESET will program most of the CSR and BCR reg-

isters to their default value. Note that there are several

CSR and BCR registers that are undefined after

H_RESET. See the sections on the individual registers

for details.

H_RESET will clear most of the registers in the PCI

configuration space. H_RESET will reset the internal

state machines. Following the end of the H_RESET op-

eration, the Am79C976 controller will attempt to read

the EEPROM device through the EEPROM interface.

H_RESET will clear DWIO (BCR18, bit 7) and the

Am79C976 controller will be in 16-bit I/O mode after

the reset operation. A DWord write operation to the

RDP (I/O offset 10h) must be performed to set the

device into 32-bit I/O mode.

EE_RESET

Prior to starting a read of the serial EEPROM, the

Am79C976 controller resets all the registers that can

be programmed from the EEPROM. This provides a

consistent starting point for register programming.

EE_RESET is also generated following EEPROM read

if the EEPROM CRC check fails.

Table 17. IEEE 1149.1 Supported Instruction

Summary

Instruction

Name

Instruc-

tion

Code Description Mode

Selected

Data

EXTEST 0000 External

Test Test BSR

IDCODE 0001 ID Code

Inspection Normal ID REG

SAMPLE 0010 Sample

Boundary Normal BSR

TRIBYP 0011 Force Float Normal Bypass

SETBYP 0100

Control

Boundary To

1/0

Test Bypass

BYPASS 1111 Bypass

Scan Normal Bypass

Table 18. BSR Mode Of Operation

1Capture

2Shift

3 Update

4 System Function

Table 19. Device ID Register

Bits 31-28 Version

Bits 27-12 Part Number: 0010 0110 0010 1000b

(2628h)

Bits 11-1

Manufacturer ID. The 11 bit manufacturer ID

code for AMD is 00000000001 in

accordance with JEDEC publication 106-A.

Bit 0 Always a logic 1

9/14/00 Am79C976 107

PRELIMINARY

S_RESET

S_RESET is provided for compatibility with previous

PCnet family devices. S_RESET occurs when the host

CPU reads the Reset register, which is located at offset

14h if the device is operating in Word I/O mode or at off-

set 18h in DWord I/O mode.

S_RESET has the same effect as setting STOP except

that S_RESET resets some Control and Status Regis-

ter (CSR) bits that STOP does not change. See the de-

scriptions of individual Control and Status Registers for

details about which bits are affected. S_RESET does

not trigger an automatic EEPROM read sequence.

New software should not use S_RESET. It should be

replaced by a combination of clearing the RUN bit in

the CMD0 register followed by explicit setting or clear-

ing of control bits as required.

STOP

A STOP reset is generated by the assertion of the

STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0,

when the stop bit currently has a value of 0, will initiate

a STOP reset. If the STOP bit is already a 1, then writ-

ing a 1 to the STOP bit will not generate a STOP reset.

STOP will reset all or some portions of CSR0, 3, and 4

to default values. For the identity of individual CSRs

and bit locations that are affected by STOP, see the in-

dividual CSR register descriptions. STOP will not affect

any of the BCR and PCI configuration space locations.

STOP will reset the internal state machines. Following

the end of the STOP operation, the Am79C976 control-

ler will not attempt to read the EEPROM device.

STOP terminates all network activity abruptly. The host

can use the suspend mode (SPND, CSR5, bit 0) to ter-

minate all network activity in an orderly sequence be-

fore setting the STOP bit.

Power on Reset

Power on Reset (POR) is generated when the

Am79C976 controller is powered up. POR generates a

hardware reset (H_RESET). In addition, it clears some

bits that H_RESET does not affect.

External PHY Reset

The Am79C976 controller provides the PHY_RST pin

which may be connected to the reset input of an exter-

nal PHY. The polarity of PHY_RST is determined by the

RST_POL bit in CMD3 (RST_POL in CSR116). The

PHY_RST pin will assert at the start of the read of the

serial EEPROM and will deassert at least 240µs (the

duration of the read of two bytes from the EEPROM)

before the end of the serial EEPROM read, providing

time for the PHY to recover from the reset.

The RST_POL bit may be programmed from the serial

EEPROM. The default value is zero, corresponding to

an active high PHY_RST signal. If an active low

PHY_RST is required, the CMD3 register should be the

first register programmed from the serial EEPROM.

The duration of the assertion of PHY_RST depends on

the number of registers programmed by the serial

EEPROM. Each register requires at least 240 µs. The

time to program the CMD3 register and any registers

programmed before CMD3 should be ignored in the

calculation of PHY_RST duration if the RST_POL bit is

programmed to 1.

If the number of registers programmed from the serial

EEPROM results in PHY_RST being too short, the

read-only register at offset 0x28 may be used for pad-

ding. Specify the address as 0x14 with arbitrary data

and repeat as many times as necessary to achieve the

required PHY_RST duration.

If the serial EEPROM is not used, the PHY may be

reset by BIOS or driver software by programming the

correct RST_POL value, disabling the internal port

manager by setting the DISPM bit, disabling the auto-

poll logic by clearing the APEP bit and then setting the

RESET_PHY bit. All these bits are in the CMD3 regis-

ter.

The PHY_RST will be asserted as long as

RESET_PHY remains set. If the PHY requires a recov-

ery time after reset, the software must provide the

delay after clearing the RESET_PHY bit before ac-

cessing the PHY’s registers or enabling the Am79C976

controller's port manager and/or auto-poll logic.

108 Am79C976 9/14/00

PRELIMINARY

Software Access

PCI Configuration Registers

The Am79C976 controller implements the 256-byte

configuration space as defined by the PCI specification

revision 2.1. The 64-byte header includes all registers

required to identify the Am79C976 controller and its

function. Additionally, the optional PCI Power Manage-

ment Interface registers are implemented at location

44h - 4Bh. The layout of the Am79C976 PCI configura-

tion space is shown in Table 20.

The PCI configuration registers are accessible only by

configuration cycles. All multi-byte numeric fields follow

Little Endian byte ordering. All write accesses to Re-

served locations have no effect; reads from these loca-

tions will return a data value of 0.

I/O Resources

The Am79C976 controller requires 4K bytes of memory

address space for access to all the various internal reg-

isters as well as access to some setup information

stored in an external serial EEPROM. For compatibility

with previous PCnet family devices, the lower 32 bytes

of the register space are also mapped into I/O space,

but some functions of the Am79C976 controller (such

as network statistics) are only available in memory

space.

The Am79C976 controller supports mapping the ad-

dress space to both I/O and memory space. The value

in the PCI I/O Base Address register determines the

start address of the I/O address space. The register is

typically programmed by the PCI configuration utility

after system power-up. The PCI configuration utility

must also set the IOEN bit in the PCI Command register

to enable I/O accesses to the Am79C976 controller.

For memory mapped I/O access, the PCI Memory

Mapped I/O Base Address register controls the start

Table 20. PCI Configuration Space Layout

31 24 23 16 15 8 7 0 Offset

Device ID Vendor ID 00h

Status Command 04h

Base-Class Sub-Class Programming IF Revision ID 08h

Reserved Header Type Latency Timer Cache Line Size 0Ch

I/O Base Address 10h

Memory-Mapped I/O Base Address 14h

Reserved 18h

Reserved 1Ch

Reserved 20h

Reserved 24h

Reserved 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address 30h

Reserved CAP-PTR 34h

Reserved 38h

MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3Ch

Reserved 40h

PMC NXT_ITM_PTR CAP_ID 44h

DATA_REG PMCSR_BSE PMCSR 48h

Reserved .

Reserved FCh

9/14/00 Am79C976 109

PRELIMINARY

address of the memory space. The MEMEN bit in the

PCI Command register must also be set to enable the

mode. Both base address registers can be active at the

same time.

The Am79C976 controller requires that the memory

space that it claims must be within the 32-bit address

space.

The Am79C976 controller supports two modes for ac-

cessing the I/O resources. For backwards compatibility

with AMD’s 16-bit Ethernet controllers, Word I/O is the

default mode after power up. The device can be config-

ured to DWord I/O mode by software.

I/O Registers

The Am79C976 controller registers are divided into

three groups: memory-mapped registers, Control and

Status Registers (CSRs), and Bus Control Registers

(BCRs). The CSRs and BCRs are included in the

Am79C976 device for software compatibility with older

PCnet family controllers that do not have the memory-

mapped register group. The CSRs and BCRs are ad-

dressed indirectly through the Register Address Port

(RAP), Register Data Port (RDP), and BCR Data Port

(BDP) so that a large number of functions can be con-

trolled through a small amount of I/O space.

All CSR and BCR functions can be accessed more ef-

ficiently through the memory-mapped registers. The

memory-mapped registers are directly addressed as

offsets from the address stored in the Memory Mapped

I/O Base Address Register, which is located in PCI

Configuration Space.

The Control and Status Registers (CSR) are used to

configure the Ethernet MAC engine and to obtain sta-

tus information. The Bus Control Registers (BCR) are

used to configure the bus interface unit and the LEDs.

Both sets of registers are accessed using indirect ad-

dressing.

The CSR and BCR share a common Register Address

Port (RAP). There are, however, separate data ports.

The Register Data Port (RDP) is used to access a

CSR. The BCR Data Port (BDP) is used to access a

BCR.

In order to access a particular CSR location, the RAP

should first be written with the appropriate CSR ad-

dress. The RDP will then point to the selected CSR. A

read of the RDP will yield the selected CSR data. A

write to the RDP will write to the selected CSR. In order

to access a particular BCR location, the RAP should

first be written with the appropriate BCR address. The

BDP will then point to the selected BCR. A read of the

BDP will yield the selected BCR data. A write to the

BDP will write to the selected BCR.

Once the RAP has been written with a value, the RAP

value remains unchanged until another RAP write oc-

curs, or until an H_RESET or S_RESET occurs. RAP

is cleared to all 0s when an H_RESET or S_RESET oc-

curs. RAP is unaffected by setting the STOP bit.

Address PROM Space

Software written for early PCnet family products ex-

pects the 48-bit IEEE MAC address to be found in a

small external PROM that occupies the first 16 bytes of

the controller’s I/O address space. The software copies

this address from the PROM into the Initialization Block

in host memory. For compatibility with this software the

Am79C976 controller contains 16-bytes of read/write

memory starting at offset 0 in the device’s I/O or mem-

ory address space. This 16 bytes of space is known as

the Address PROM Space (APROM). If compatibility

with this software is required, the EEPROM should

load the data shown in Table 21 into the Address

PROM Space. The order of bytes in the MAC address

is such that the first byte transmitted is located at offset

CPU access to the APROM space is controlled by the

APROM Write Enable (APROMWE) bit (BCR2, bit 8). If

this bit is cleared to 0, the host CPU can not write to the

APROM space. However, the APROM space can be

loaded from the EEPROM regardless of the state of

APROMWE.

Reset Register

A read of the Reset register creates an internal soft-

ware reset (S_RESET) pulse in the Am79C976 control-

ler. The effect of this reset is the same as that of setting

the STOP bit, except that S_RESET clears some bits

that are not affected by setting STOP.

This register exists for backward compatibility with ear-

lier PCnet family devices. It should not be used in new

software.

The NE2100 LANCE-based family of Ethernet cards

requires that a write access to the Reset register fol-

lows each read access to the Reset register. The

Am79C976 controller does not have a similar require-

ment. The write access is not required and does not

have any effect.

Table 21. Address PROM Space Contents

Offset Contents

00h-05h MAC Address

06h-0Bh 00 00 00 00 00 00h

0Ch-0Dh Check sum of bytes 0-11 and

bytes 14-15

0Eh-0Fh ASCII “W” (57h)

110 Am79C976 9/14/00

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Word I/O Mode

After H_RESET, the Am79C976 controller is pro-

grammed to operate in Word I/O mode. DWIO (BCR18,

bit 7) will be cleared to 0. Table 22 shows how the 32

bytes of address space are used in Word I/O mode.

All I/O resources must be accessed in word quantities

and on word addresses. The Address PROM locations

can also be read in byte quantities. The only allowed

DWord operation is a write access to the RDP, which

switches the device to DWord I/O mode. A read access

other than those listed in Table 22 will yield undefined

data, and a write operation may cause unexpected re-

programming of the Am79C976 control registers.

Table 23 shows legal I/O accesses in Word I/O mode.

Note: * The offset of a MIB counter is the value con-

tained in the MIB Offset Register plus the offset shown

in Table 7 or Table 8.

Double Word I/O Mode

The Am79C976 controller can be configured to operate

in DWord (32-bit) I/O mode. The software can invoke

the DWIO mode by performing a DWord write access

to the I/O location at offset 10h (RDP). The data of the

write access must be such that it does not affect the in-

tended operation of the Am79C976 controller. Setting

the device into 32-bit I/O mode is usually the first oper-

ation after H_RESET or S_RESET. The RAP register

will point to CSR0 at that time. Writing a value of 0 to

CSR0 is a safe operation. DWIO (BCR18, bit 7) will be

set to 1 as an indication that the Am79C976 controller

operates in 32-bit I/O mode.

Note: Even though the I/O resource mapping changes

when the I/O mode setting changes, the RDP location

offset is the same for both modes. Once the DWIO bit

has been set to 1, only H_RESET can clear it to 0. The

DWIO mode setting is unaffected by S_RESET or set-

ting of the STOP bit. Table 24 shows how the 32 bytes

of address space are used in DWord I/O mode.

All I/O resources must be accessed in DWord quanti-

ties and on DWord addresses. A read access other

than listed in Table 25 will yield undefined data, and a

write operation may cause unexpected reprogramming

of the Am79C976 control registers.

DWIO mode applies to both I/O- and memory-mapped

accesses. Either a 32-bit I/O write to offset 10h relative

to the contents of the I/O Base Address Register (BAR)

or a 32-bit memory write to offset 10h relative to the

contents of the Memory BAR puts the device into

DWIO mode. Once in DWIO mode, the offsets of the

RAP, Reset, and BDP registers are 14h, 18h, and 1Ch

relative to the contents of either the I/O BAR or the

Memory BAR.

For example, in DWIO mode the BDP Register can be

read either by an I/O read from offset 1Ch relative to

the contents of the I/O BAR or by a memory read from

offset 1Ch relative to the contents of the Memory BAR.

DWIO mode affects only the locations between 0 and

1Fh, which include the RAP, Reset, and BDP registers.

Registers at offset 20h and above are directly ac-

cessed in memory space by byte address and are un-

affected by DWIO.

The DWIO bit is also located at bit 28 of the CMD2 reg-

ister and can be set or cleared by software regardless

of its current setting.

Table 22. I/O Map In Word I/O Mode (DWIO = 0)

Offset

No. of

Bytes Register

00h - 0Fh 16 APROM

10h 2 RDP

12h 2 RAP (shared by RDP and BDP)

14h 2 Reset Register

16h 2 BDP

18h - 1Fh 8 Reserved

20h-1FFh 224 Memory-mapped Registers

* 256 MIB Counters

9/14/00 Am79C976 111

PRELIMINARY

Table 23. Legal I/O Accesses in Word I/O Mode (DWIO = 0)

AD[4:0] BE[3:0] Type Comment

0XX00 1110 RD Byte read of APROM location 0h, 4h, 8h or Ch

0XX01 1101 RD Byte read of APROM location 1h, 5h, 9h or Dh

0XX10 1011 RD Byte read of APROM location 2h, 6h, Ah or Eh

0XX11 0111 RD Byte read of APROM location 3h, 7h, Bh or Fh

0XX00 1100 RD Word read of APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or

Ch and Dh

0XX10 0011 RD Word read of APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or

Fh and Eh

10000 1100 RD Word read of RDP

10010 0011 RD Word read of RAP

10100 1100 RD Word read of Reset Register

10110 0011 RD Word read of BDP

0XX00 1100 WR Word write to APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or

Ch and Dh

0XX10 0011 WR Word write to APROM locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh and Ah or

Fh and Eh

10000 1100 WR Word write to RDP

10010 0011 WR Word write to RAP

10100 1100 WR Word write to Reset Register

10110 0011 WR Word write to BDP

10000 0000 WR DWord write to RDP,

switches device to DWord I/O mode

Table 24. I/O Map In DWord I/O Mode (DWIO = 1)

Offset No. of Bytes Register

00h - 0Fh 16 APROM

10h 4 RDP

14h 4 RAP (shared by RDP and

BDP)

18h 4 Reset Register

1Ch 4 BDP

20h-1FFh 224 Memory-mapped Registers

200h-2FFh 256 MIB Counters

Table 25. Legal I/O Accesses in Double Word I/O

Mode (DWIO =1)

AD[4:0] BE[3:0] Type Comment

0XX00 0000 RD

DWord read of APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8h or Fh to

0XX00 0000 WR

DWord write to APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8h or Fh to

10000 0000 WR DWord write to RDP

10100 0000 WR DWord write to RAP

11000 0000 WR DWord write to Reset

10000 0000 RD DWord read of RDP

112 Am79C976 9/14/00

PRELIMINARY

10100 0000 RD DWord read of RAP

11000 0000 RD DWord read of Reset

Table 25. Legal I/O Accesses in Double Word I/O

Mode (DWIO =1)

9/14/00 Am79C976 113

PRELIMINARY

USER ACCESSIBLE REGISTERS

The Am79C976 controller has four types of user regis-

ters: the PCI configuration registers, the memory-

mapped registers, the Control and Status registers

(CSRs), and the Bus Control registers (BCRs). The

CSRs and BCRs are included for software compatibility

with older PCnet family devices. However, all CSR and

BCR functions can be accessed more efficiently

through the memory-mapped registers. Software writ-

ten for the Am79C976 device and future PCnet family

devices does not have to access any CSR or BCR.

The Am79C976 controller implements all PCnet-ISA

(Am79C960) registers, all C-LANCE (Am79C90) regis-

ters, all PCnet-FAST (Am79C971) registers, plus a

number of additional registers. The Am79C976 CSRs

are compatible upon power up with both the PCnet-ISA

CSRs and all of the C-LANCE CSRs.

The PCI configuration registers and the memory-

mapped registers can be accessed in any data width.

The CSRs and BCRs must be accessed according to

the I/O mode that is currently selected. When WIO

mode is selected, all CSR and BCR locations are de-

fined to be 16 bits in width. When DWIO mode is se-

lected, all these register locations are defined to be 32

bits in width, with the upper 16 bits of most register lo-

cations marked as reserved locations with undefined

values. When performing register write operations in

DWIO mode, the upper 16 bits should always be writ-

ten as zeros. When performing register read opera-

tions in DWIO mode, the upper 16 bits of I/O resources

should always be regarded as having undefined val-

ues, except for CSR88.

The Am79C976 controller’s registers can be divided

into several functional groups: PCI Configuration Alias

registers, PCI Configuration registers, Setup registers,

Running registers, and Test registers.

The PCI Configuration Alias registers are typically pro-

grammed through the EEPROM read operation. In this

way, they are initialized before the BIOS accesses the

PCI Configuration registers. This group includes the

MAX_LAT_A, MIN_GNT_A, PCIDATA0 - 7, PMC_A,

SID_A, SVID_A and VID_A registers and the

ROM_CFG register.

The PCI Configuration registers are accessed by the

system BIOS software to configure the Am79C976

controller. These registers include the Memory Base

Address register, the Expansion ROM Base Address

Typically, device information will also be read from the

SID, SVID and VID registers.

The Setup registers include most of the remaining

memory mapped registers. The programming of these

is typically divided between the EEPROM and the

driver software. Many of these registers are optional

and need not be initialized unless the associated func-

tion is used.

Typically, the SRAM_SIZE, SRAM_BND and PADR

registers are initialized from the EEPROM. The driver

initializes the BADR, BADX, RCV_RING_LEN,

XMT_RING_LEN and LADRF registers. The CMD2,

CMD3, CTRL0, CTRL1 and CTRL2 registers are typi-

cally partially initialized from the EEPROM and partially

by the driver. The CMD7 and CTRL3 registers are ini-

tialized by the driver. The driver reads the

MIB_OFFSET and CHIPID registers at initialization

time. The PHY_ACCESS register may be used at this

time to initialize the external PHY.

Running registers are accessed by the driver software.

These include the CMD0, INT0, INTEN0, STAT0,

LADRF and MIB registers. The driver may access

other registers during operation depending on the fea-

tures being used.

PCI Configuration Registers

PCI Vendor ID Register

Offset 00h

The PCI Vendor ID register is a 16-bit register that iden-

tifies the manufacturer of the Am79C976 controller.

AMD’s Vendor ID is 1022h. Note that this vendor ID is

not the same as the Manufacturer ID in CSR88 and

CSR89. The vendor ID is assigned by the PCI Special

Interest Group.

The PCI Vendor ID register is read only.

This register is the same as BCR35, which can be writ-

ten by the EEPROM.

PCI Device ID Register

Offset 02h

The PCI Device ID register is a 16-bit register that

uniquely identifies the Am79C976 controller within

AMD's product line. The Am79C976 Device ID is

2000h. Note that this Device ID is not the same as the

Part number in CSR88 and CSR89. The Device ID is

assigned by AMD. The Device ID is the same as the

PCnet-PCI II (Am79C970A) and PCnet-FAST

(Am79C971) devices.

The PCI Device ID register is read only.

PCI Command Register

Offset 04h

The PCI Command register is a 16-bit register used to

control the gross functionality of the Am79C976 con-

troller. It controls the Am79C976 controller's ability to

generate and respond to PCI bus cycles. To logically

disconnect the Am79C976 device from all PCI bus cy-

cles except configuration cycles, a value of 0 should be

written to this register.

114 Am79C976 9/14/00

PRELIMINARY

The PCI Command register is read and written by the

host.

Bit Name Description

15-10 RES Reserved locations. Read as ze-

ros; write operations have no ef-

fect.

9 FBTBEN Fast Back-to-Back Enable. When

this bit is set to 1, the Am79C976

controller will generate Fast

Back-to-Back cycles. When this

bit is cleared to 0, the Am79C976

controller will not generate Fast

Back-to-Back cycles.

FBTBEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

8 SERREN SERR Enable. Controls the as-

sertion of the SERR pin. SERR is

disabled when SERREN is

cleared. SERR will be asserted

on detection of an address parity

error and if both SERREN and

PERREN (bit 6 of this register)

are set.

SERREN is cleared by

H_RESET and is not effected by

S_RESET or by setting the STOP

bit.

7 RES Reserved location. Read as ze-

ros; write operations have no ef-

fect.

6 PERREN Parity Error Response Enable.

Enables the parity error response

functions. When PERREN is 0

and the Am79C976 controller de-

tects a parity error, it only sets the

Detected Parity Error bit in the

PCI Status register. When PER-

REN is 1, the Am79C976 control-

ler asserts PERR on the

detection of a data parity error. It

also sets the DATAPERR bit (PCI

Status register, bit 8), when the

data parity error occurred during

a master cycle. PERREN also

enables reporting address parity

errors through the SERR pin and

the SERR bit in the PCI Status

PERREN is cleared by

H_RESET and is not affected by

S_RESET or by setting the STOP

bit.

5 VGASNOOP VGA Palette Snoop. Read as ze-

ro; write operations have no ef-

fect.

4 MWIEN Memory Write and Invalidate Cy-

cle Enable. When this bit is set to

1, the Am79C976 controller will

generate Memory Write and In-

validate (MWI) cycles when ap-

propriate. When the bit is cleared

to 0, the device will generate

Memory Write cycles instead of

MWI cycles.

MWIEN is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

3 SCYCEN Special Cycle Enable. Read as

zero; write operations have no ef-

fect. The Am79C976 controller

ignores all Special Cycle opera-

tions.

2 BMEN Bus Master Enable. Setting

BMEN enables the Am79C976

controller to become a bus mas-

ter on the PCI bus. The host must

set BMEN before setting the INIT

or STRT bit in CSR0 of the

Am79C976 controller.

BMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

1 MEMEN Memory Space Access Enable.

The Am79C976 controller will ig-

nore all memory accesses when

MEMEN is cleared. The host

must set MEMEN before the first

memory access to the device.

For memory mapped I/O, the

host must program the PCI Mem-

ory Mapped I/O Base Address

dress before setting MEMEN.

For accesses to the Expansion

ROM, the host must program the

PCI Expansion ROM Base Ad-

dress register at offset 30h with a

valid memory address before set-

9/14/00 Am79C976 115

PRELIMINARY

ting MEMEN. The Am79C976

controller will only respond to ac-

cesses to the Expansion ROM

when both ROMEN (PCI Expan-

sion ROM Base Address register,

bit 0) and MEMEN are set to 1.

Since MEMEN also enables the

memory mapped access to the

Am79C976 I/O resources, the

PCI Memory Mapped I/O Base

Address register must be pro-

grammed with an address so that

the device does not claim cycles

not intended for it.

MEMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

0 IOEN I/O Space Access Enable. The

Am79C976 controller will ignore

all I/O accesses when IOEN is

cleared. The host must set IOEN

before the first I/O access to the

device. The PCI I/O Base Ad-

dress register must be pro-

grammed with a valid I/O address

before setting IOEN.

IOEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

PCI Status Register

Offset 06h

The PCI Status register is a 16-bit register that contains

status information for the PCI bus related events.

Bit Name Description

15 PERR Parity Error. PERR is set when

the Am79C976 controller detects

a parity error.

The Am79C976 controller sam-

ples the AD[31:0], C/BE[3:0], and

the PAR lines for a parity error at

the following times:

• In slave mode, during the ad-

dress phase of any PCI bus com-

mand.

• In slave mode, for all I/O, mem-

ory and configuration write com-

mands that select the Am79C976

controller when data is trans-

ferred (TRDY and IRDY are as-

serted).

• In master mode, during the data

phase of all memory read com-

mands.

In master mode, during the data

phase of the memory write com-

mand, the Am79C976 controller

sets the PERR bit if the target re-

ports a data parity error by as-

serting the PERR signal.

PERR is not effected by the state

of the Parity Error Response en-

able bit (PCI Command register,

bit 6).

PERR is set by the Am79C976

controller and cleared by writing a

1. Writing a 0 has no effect.

PERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

14 SERR Signaled SERR. SERR is set

when the Am79C976 controller

detects an address parity error

and both SERREN and PERREN

(PCI Command register, bits 8

and 6) are set.

SERR is set by the Am79C976

controller and cleared by writing a

1. Writing a 0 has no effect.

SERR is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

13 RMABORT Received Master Abort. RM-

ABORT is set when the

Am79C976 controller terminates

a master cycle with a master

abort sequence.

RMABORT is set by the

Am79C976 controller and

cleared by writing a 1. Writing a 0

has no effect. RMABORT is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

12 RTABORT Received Target Abort. RT-

ABORT is set when a target ter-

minates an Am79C976 master

cycle with a target abort se-

quence.

RTABORT is set by the

Am79C976 controller and

116 Am79C976 9/14/00

PRELIMINARY

cleared by writing a 1. Writing a 0

has no effect. RTABORT is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

11 STABORT Send Target Abort. Read as ze-

ro; write operations have no ef-

fect. The Am79C976 controller

will never terminate a slave ac-

cess with a target abort se-

quence.

STABORT is read only.

10-9 DEVSEL Device Select Timing. DEVSEL

is set to 01b (medium), which

means that the Am79C976 con-

troller will assert DEVSEL two

clock periods after FRAME is as-

serted.

DEVSEL is read only.

8 DATAPERR Data Parity Error Detected.

DATAPERR is set when the

Am79C976 controller is the cur-

rent bus master and it detects a

data parity error and the Parity

Error Response enable bit (PCI

Command register, bit 6) is set.

During the data phase of all

memory read commands, the

Am79C976 controller checks for

parity error by sampling the

AD[31:0] and C/BE[3:0] and the

PAR lines. During the data phase

of all memory write commands,

the Am79C976 controller checks

the PERR input to detect whether

the target has reported a parity

error.

DATAPERR is set by the

Am79C976 controller and

cleared by writing a 1. Writing a 0

has no effect. DATAPERR is

cleared by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

7 FBTBC Fast Back-To-Back Capable.

Read as one; write operations

have no effect. The Am79C976

controller is capable of accepting

fast back-to-back transactions

with the first transaction address-

ing a different target.

6-5 RES Reserved locations. Read as

zero; write operations have no ef-

fect.

4 NEW_CAP New Capabilities. This bit indi-

cates whether this function imple-

ments a list of extended

capabilities such as PCI power

management. When set, this bit

indicates the presence of New

Capabilities. A value of 0 means

that this function does not imple-

ment New Capabilities.

Read as one; write operations

have no effect. The Am79C976

controller supports the Linked

Additional Capabilities List.

3-0 RES Reserved locations. Read as

zero; write operations have no ef-

fect.

PCI Revision ID Register

Offset 08h

The PCI Revision ID register is an 8-bit register that

specifies the Am79C976 controller revision number.

The value of this register is 5Xh with the lower four bits

being silicon-revision dependent.

The PCI Revision ID register is read only.

PCI Programming Interface Register

Offset 09h

The PCI Programming Interface register is an 8-bit reg-

ister that identifies the programming interface of

Am79C976 controller. PCI does not define any specific

vices. The value of this register is 00h.

The PCI Programming Interface register is read only.

PCI Sub-Class Register

Offset 0Ah

The PCI Sub-Class register is an 8-bit register that iden-

tifies specifically the function of the Am79C976 control-

ler. The value of this register is 00h which identifies the

Am79C976 device as an Ethernet controller.

The PCI Sub-Class register is read only.

PCI Base-Class Register

Offset 0Bh

The PCI Base-Class register is an 8-bit register that

broadly classifies the function of the Am79C976 con-

troller. The value of this register is 02h which classifies

the Am79C976 device as a network controller.

The PCI Base-Class register is read only.

9/14/00 Am79C976 117

PRELIMINARY

PCI Cache Line Size Register

Offset 0Ch

This register indicates the system cache line size in

units of 32-bit double words. This quantity is used to

determine when to use the advanced PCI bus com-

mands (MWI, MRL, and MRM). It is also used for align-

ing PCI burst transfers to cache line boundaries. Only

the values 4, 8, and 16 are acceptable. If the host CPU

attempts to write any other value to this location, the

contents of the register will be set to 0.

This register is cleared by H_RESET and is not effected

by S_RESET or by setting the STOP bit.

PCI Latency Timer Register

Offset 0Dh

The PCI Latency Timer register is an 8-bit register that

specifies the minimum guaranteed time the Am79C976

controller will control the bus once it starts its bus mas-

tership period. The time is measured in clock cycles.

Every time the Am79C976 controller asserts FRAME at

the beginning of a bus mastership period, it will copy

the value of the PCI Latency Timer register into a

counter and start counting down. The counter will freeze

at 0. When the system arbiter removes GNT while the

counter is non-zero, the Am79C976 controller will con-

tinue with its data transfers. It will only release the bus

when the counter has reached 0.

The PCI Latency Timer is only significant in burst trans-

actions, where FRAME stays asserted until the last data

phase. In a non-burst transaction, FRAME is only as-

serted during the address phase. The internal latency

counter will be cleared and suspended while FRAME is

deasserted.

The six most significant bits of the PCI Latency Timer

are fixed at 0. The host should read the Am79C976 PCI

MIN_GNT and PCI MAX_LAT registers to determine the

latency requirements for the device and then initialize

the Latency Timer register with an appropriate value.

The PCI Latency Timer register is read and written by

the host. The PCI Latency Timer register is cleared by

H_RESET and is not affected by S_RESET or by setting

the STOP bit.

PCI Header Type Register

Offset 0Eh

The PCI Header Type register is an 8-bit register that

describes the format of the PCI Configuration Space

locations 10h to 3Ch and that identifies a device to be

single or multi-function. The PCI Header Type register

is located at address 0Eh in the PCI Configuration

Space. It is read only.

Bit Name Description

7 FUNCT Single-function/multi-function de-

vice. Read as zero; write opera-

tions have no effect. The

Am79C976 controller is a single

function device.

6-0 LAYOUT PCI configuration space layout.

Read as zeros; write operations

have no effect. The layout of the

PCI configuration space loca-

tions 10h to 3Ch is as shown in

the table at the beginning of this

section.

PCI I/O Base Address Register

Offset 10h

The PCI I/O Base Address register is a 32-bit register

that determines the location of the Am79C976 I/O re-

sources in all of I/O space.

Bit Name Description

31-5 IOBASE I/O base address most significant

27 bits. These bits are written by

the host to specify the location of

the Am79C976 I/O resources in

all of I/O space. IOBASE must be

written with a valid address be-

fore the Am79C976 controller

slave I/O mode is turned on by

setting the IOEN bit (PCI Com-

mand register, bit 0).

When the Am79C976 controller

is enabled for I/O mode (IOEN is

set), it monitors the PCI bus for a

valid I/O command. If the value

on AD[31:5] during the address

phase of the cycles matches the

value of IOBASE, the Am79C976

controller will drive DEVSEL indi-

cating it will respond to the

access.

IOBASE is read and written by

the host. IOBASE is cleared by

H_RESET and is not affected by

S_RESET or by setting the STOP

bit.

4-2 IOSIZE I/O size requirements. Read as

zeros; write operations have no

effect.

IOSIZE indicates the size of the

I/O space the Am79C976 control-

118 Am79C976 9/14/00

PRELIMINARY

ler requires. When the host writes

a value of FFFF FFFFh to the I/O

Base Address register, it will read

back a value of 0 in bits 4-2. That

indicates an Am79C976 I/O

space requirement of 32 bytes.

1 RES Reserved location. Read as zero;

write operations have no effect.

0 IOSPACE I/O space indicator. Read as one;

write operations have no effect.

Indicating that this base address

address.

PCI Memory Mapped I/O Base Address Register

Offset 14h

The PCI Memory Mapped I/O Base Address register is

a 32-bit register that determines the location of the

Am79C976 I/O resources. Memory space claimed by

the Am79C976 device may be mapped anywhere in 32-

bit memory space.

Bit Name Description

31-12 MEMBASE Memory mapped I/O base ad-

dress, bits 31-12. These bits are

written by the host to specify the

location of the Am79C976 I/O re-

sources in 32-bit memory space.

MEMBASE must be written with a

valid address before the

Am79C976 controller slave

memory mapped I/O mode is

turned on by setting the MEMEN

bit (PCI Command register, bit 1).

When the Am79C976 controller

is enabled for memory mapped

I/O mode (MEMEN is set), it mon-

itors the PCI bus for a valid mem-

ory command. If the value on

AD[31:12] during the address

phase of the cycles matches the

value of MEMBASE, the

Am79C976 controller will drive

DEVSEL indicating it will respond

to the access.

MEMBASE is read and written by

the host. MEMBASE is cleared

by H_RESET and is not affected

by S_RESET or by setting the

STOP bit.

11-4 MEMSIZE Memory mapped I/O size re-

quirements. Read as zeros; write

operations have no effect.

MEMSIZE indicates the size of

the memory space the

Am79C976 controller requires.

When the host writes a value of

FFFF FFFFh to the Memory

Mapped I/O Base Address regis-

ter, it will read back 0s in bit 11:4

to indicate an Am79C976 memo-

ry space requirement of 4K bytes.

3 PREFETCH Prefetchable. The value of this

read-only bit is the inverse of the

value of the Disable Prefetchabil-

ity (PREFETCH_DIS) bit (CMD3,

bit 30). PREFETCH_DIS is nor-

mally loaded from EEPROM. Set-

ting PREFETCH to 1 indicates

that the memory space claimed

by this device can be prefetched.

Because of the side effects of

reading the Reset Register at off-

set 14h or 18h (depending on the

state of DWIO (CMD2, bit 28)),

locations at offsets less than 20h

cannot be prefetched. The

Am79C976 device will discon-

nect any attempted burst transfer

at offsets less than 20h.

This bit is read-only. (However,

its value is the inverse of

PREFETCH_DIS, which can be

loaded from EEPROM.)

2-1 TYPE Memory type indicator. Read as

zeros; write operations have no

effect. Indicates that this base ad-

dress register is 32 bits wide and

mapping can be done anywhere

in the 32-bit memory space.

0 MEMSPACEMemory space indicator. Read

as zero; write operations have no

effect. Indicates that this base ad-

dress register describes a memo-

ry base address.

PCI Subsystem Vendor ID Register

Offset 2Ch

The PCI Subsystem Vendor ID register is a 16-bit reg-

ister that together with the PCI Subsystem ID uniquely

identifies the add-in card or subsystem the Am79C976

controller is used in. Subsystem Vendor IDs can be ob-

tained from the PCI SIG. A value of 0 (the default) indi-

cates that the Am79C976 controller does not support

subsystem identification. The PCI Subsystem Vendor

9/14/00 Am79C976 119

PRELIMINARY

ID is an alias of BCR23, bits 15-0. It is programmable

through the EEPROM.

The PCI Subsystem Vendor ID register is read only.

PCI Subsystem ID Register

Offset 2Eh

The PCI Subsystem ID register is a 16-bit register that

together with the PCI Subsystem Vendor ID uniquely

identifies the add-in card or subsystem the Am79C976

controller is used in. The value of the Subsystem ID is

up to the system vendor. A value of 0 (the default) indi-

cates that the Am79C976 controller does not support

subsystem identification. The PCI Subsystem ID is an

alias of BCR24, bits 15-0. It is programmable through

the EEPROM.

The PCI Subsystem ID register is read only.

PCI Expansion ROM Base Address Register

Offset 30h

The PCI Expansion ROM Base Address register is a

32-bit register that defines the base address, size and

address alignment of an Expansion ROM. The host

CPU can determine the size and alignment require-

ments of the ROM by writing all 1s to this register, read-

ing back the result, and masking out the least

significant bit. The device will return 0s in all don’t care

bits.

The Am79C976 device supports ROMs ranging in size

from 2 kbytes to 16 Mbytes. The amount of address

space claimed by the ROM can be programmed

through the ROM Configuration register, which can be

loaded from the external serial EEPROM. The bits of

the ROM Configuration Register (ROM_CFG) act as

write enable bits for bits [23:11] and bit 0 of this register.

See Figure 46.

As an example, assume that ROM_CFG is pro-

grammed to 0F001h. This means that bits [23:20] and

bit 0 of ROMBASE are write enabled, and bits [19:11]

are fixed at 0. In addition, bits [31:24] of ROMBASE are

always write enabled, and bits [10:1] are always 0, re-

gardless of the contents of ROM_CFG. Therefore,

when the host CPU writes all 1s to ROMBASE, it will

read back 0FFF00001h. Masking out bit 0 leaves

0FFF00000h. This means that bits [19:0] of the base

address are don’t cares, and the ROM occupies 220 or

1 Mbytes of address space, and must be mapped to a

1 Mbyte boundary. If the CPU then writes 00300001h

to this register and sets the MEMEN bit (PCI Command

will claim the memory space between 00300000h and

003FFFFFh.

Figure 46. PCI Expansion ROM Base Address Register

Note: The procedure described in the PCI Expansion

ROM Base Address Register section specifies the

amount of address space that the ROM claims. The

ROM may be smaller than the amount of address

space claimed. The actual size of the code in the Ex-

pansion ROM is always determined by reading the Ex-

pansion ROM header.

1111 0000 0000 0 00 1

1111 1111 1111 1111 000 0000 000 1

013

1111 0000 0000 0

ROM_CFG

ROMBASE

120 Am79C976 9/14/00

PRELIMINARY

Bit Name Description

31-24 ROMBASE Expansion ROM base address

most significant 8 bits. These bits

are written by the host to specify

the location of the Expansion

ROM in PCI memory space.

ROMBASE must be written with a

valid address before the

Am79C976 Expansion ROM ac-

cess is enabled by setting

ROMEN (PCI Expansion ROM

Base Address register, bit 0) and

MEMEN (PCI Command register,

bit 1).

When the Am79C976 controller

is enabled for Expansion ROM

access (ROMEN and MEMEN

are set to 1), it monitors the PCI

bus for a valid memory com-

mand. If the value on AD[31:2]

during the address phase of the

cycle falls in the address space

specified by the contents of this

ler will drive DEVSEL indicating it

will respond to the access.

ROMBASE is read and written by

the host. ROMBASE is cleared

by H_RESET and is not affected

by S_RESET or by setting the

STOP bit.

23-11 ROMSIZE Expansion ROM base address

bits [23:11]. Those bits in this

field that are enabled by the cor-

responding bits in the ROM Con-

figuration Register (ROM_CFG)

are written by the host CPU to

specify the location of the Expan-

sion ROM in PCI memory space.

Those bits in this field that are not

enabled by the corresponding

bits in ROM_CFG are fixed at 0.

10-1 ZEROS Read as zeros; write operation

has no effect.

0 ROMEN Expansion ROM Enable. Written

by the host to enable access to

the Expansion ROM. The

Am79C976 controller will only re-

spond to accesses to the Expan-

sion ROM when both ROMEN

and MEMEN (PCI Command reg-

ister, bit 1) are set to 1. This bit

can be set to 1 only when bit 0 of

ROM_CFG is set to 1. When bit 0

of ROM_CFG is cleared to 0,

ROMEN is fixed a 0, and the Ex-

pansion ROM cannot be mapped

into PCI memory space.

ROMEN is read and written by

the host. ROMEN is cleared by

H_RESET and is not effected by

S_RESET or by setting the STOP

bit.

PCI Capabilities Pointer Register

Offset 34h

Bit Name Description

7-0 CAP_PTR The PCI Capabilities pointer

ister that points to a linked list of

capabilities implemented on this

device. This register has the val-

ue 44h.

The PCI Capabilities register is

read only.

PCI Interrupt Line Register

Offset 3Ch

The PCI Interrupt Line register is an 8-bit register that

is used to communicate the routing of the interrupt.

This register is written by the POST software as it ini-

tializes the Am79C976 controller in the system. The

interrupt channel which the POST software has as-

signed to the Am79C976 controller. The PCI Interrupt

Line register is not modified by the Am79C976 control-

ler. It has no effect on the operation of the device.

The PCI Interrupt Line register is read and written by

the host. It is cleared by H_RESET and is not affected

by S_RESET or by setting the STOP bit.

PCI Interrupt Pin Register

Offset 3Dh

This PCI Interrupt Pin register is an 8-bit register that

indicates the interrupt pin that the Am79C976 controller

is using. The value for the Am79C976 Interrupt Pin reg-

ister is 01h, which corresponds to INTA.

The PCI Interrupt Pin register is read only.

PCI MIN_GNT Register

Offset 3Eh

The PCI MIN_GNT register is an 8-bit register that

specifies the minimum length of a burst period that the

Am79C976 device needs to keep up with the network

activity. The length of the burst period is calculated as-

suming a clock rate of 33 MHz. The register value

specifies the time in units of 1/4 µs. The PCI MIN_GNT

9/14/00 Am79C976 121

PRELIMINARY

ister, which can be loaded from the serial EEPROM. It

is recommended that the shadow register be pro-

grammed to a value of 18h, which corresponds to 6 µs.

The host should use the value in this register to deter-

mine the setting of the PCI Latency Timer register.

The PCI MIN_GNT register is read only.

PCI MAX_LAT Register

Offset 3Fh

The PCI MAX_LAT register is an 8-bit register that spec-

ifies the maximum arbitration latency the Am79C976

controller can sustain without causing problems to the

network activity. The register value specifies the time in

units of 1/4 µs. The MAX_LAT register is an alias of the

Maximum Latency Shadow Register, which can be load-

ed from the serial EEPROM. It is recommended that the

shadow register be programmed to a value of 18h,

which corresponds to 6 µs.

The host should use the value in this register to deter-

mine the setting of the PCI Latency Timer register.

The PCI MAX_LAT register is read only

PCI Capability Identifier Register

Offset 44h

Bit Name Description

7-0 CAP_ID This register identifies the linked

list item as being the PCI Power

Management registers. This is a

read-only register whose value is

fixed at 1h.

PCI Next Item Pointer Register

Offset 45h

Bit Name Description

7-0 NXT_ITM_PTR

The Next Item Pointer Register

points to the starting address of

the next capability. The pointer at

this offset is a null pointer, indi-

cating that this is the last capabil-

ity in the linked list of the

capabilities. This is a read-only

PCI Power Management Capabilities Register

(PMC)

Offset 46h

Note: All bits of this register are loaded from

EEPROM. The register is aliased to BCR36 for testing

purposes.

Bit Name Description

15-11 PME_SPT PME Support. This 5-bit field indi-

cates the power states in which

the function may assert PME. A

value of 0b for any bit indicates

that the function is not capable of

asserting the PME signal while in

that power state.

Bit(11) XXXX1b - PME can be

asserted from D0.

Bit(12) XXX1Xb - PME can be

asserted from D1.

Bit(13) XX1XXb - PME can be

asserted from D2.

Bit(14) X1XXXb - PME can be

asserted from D3hot.

Bit(15) 1XXXXb - PME can be

asserted from D3cold. The value

read from bit(15) is the AND of

the value of BCR36, bit 15 and

the current state of the

VAUX_SENSE pin.

Read only.

10 D2_SPT D2 Support. If this bit is a 1, this

function supports the D2 Power

Management State.

Read only.

9 D1_SPT D1 Support. If this bit is a 1, this

function supports the D1 Power

Management State.

Read only.

8-6 RES Reserved locations. Written and

read as zeros.

5 DSI Device Specific Initialization.

When this bit is 1, it indicates that

special initialization of the func-

tion is required (beyond the stan-

dard PCI configuration header)

before the generic class device

driver is able to use it.

Read only.

4 RES Reserved location. Written and

read as zero.

122 Am79C976 9/14/00

PRELIMINARY

3 PME_CLK PME Clock. When this bit is a 1,

it indicates that the function relies

on the presence of the PCI clock

for PME operation. When this bit

is a 0 it indicates that no PCI

clock is required for the function

to generate PME.

Functions that do not support

PME generation in any state

must return 0 for this field.

Read only.

2-0 PMIS_VER Power Management Interface

Specification Version. A value of

010b indicates that this function

complies with the revision 1.1 of

the PCI Power Management In-

terface Specification.

PCI Power Management Control/Status Register

(PMCSR)

Offset 48h

Bit Name Description

15 PME_STATUS

PME Status. This bit is set when

the function would normally as-

sert the PME signal independent

of the state of the PME_EN bit.

Writing a 1 to this bit will clear it

and cause the function to stop as-

serting a PME (if enabled). Writ-

ing a 0 has no effect.

If the function supports PME from

D3cold then this bit is sticky and

must be explicitly cleared by the

operating system each time the

operating system is initially load-

ed.

Read/write accessible. Sticky bit.

This bit is reset by POR.

S_RESET or setting the STOP bit

has no effect. If the function does

not support PME# assertion from

D3cold, either because bit 15 of

the PMC Alias register is zero or

the VAUX_SENSE pin is low,

PME_STATUS will be reset fol-

lowing H_RESET. This reset is

actually done at the end of the

EEPROM read operation, since

bit 15 of the PMC Alias register

may be loaded from the EE-

PROM.

14-13 DATA_SCALE

Data Scale. This two bit read-

only field indicates the scaling

factor to be used when interpret-

ing the value of the Data register.

The value and meaning of this

field will vary depending on the

DATA_SCALE field.

Read only.

12-9 DATA_SEL Data Select. This optional four-bit

field is used to select which data

is reported through the Data reg-

ister and DATA_SCALE field.

Read/write accessible. Sticky bit.

This bit is reset by POR.

H_RESET, S_RESET, or setting

the STOP bit has no effect.

8 PME_EN PME Enable. When a 1,

PME_EN enables the function to

assert PME. When a 0, PME as-

sertion is disabled.

This bit defaults to “0” if the func-

tion does not support PME gener-

ation from D3cold.

If the function supports PME from

D3cold, then this bit is sticky and

must be explicitly cleared by the

operating system each time the

operating system is initially load-

ed.

Read/write accessible. Sticky bit.

This bit is reset by POR.

S_RESET or setting the STOP bit

has no effect. If the function does

not support PME assertion from

D3cold, either because bit 15 of

the PMC Alias register is zero or

the VAUX_SENSE pin is low,

PME_STATUS will be reset fol-

lowing H_RESET. This reset is

actually done at the end of the

EEPROM read operation, since

bit 15 of the PMC Alias register

may be loaded from the

EEPROM.

7-2 RES Reserved locations. Read only.

1-0 PWR_STATE

9/14/00 Am79C976 123

PRELIMINARY

Power State. This 2-bit field is

used both to determine the cur-

rent power state of a function and

to set the function into a new

power state.

The definition of the field values

is as follows:

00b - D0

01b - D1

10b - D2

11b - D3

These bits can be written and

read, but their contents have no

effect on the operation of the

device.

Read/write accessible.

PCI PMCSR Bridge Support Extensions Register

Offset 4Ah

Bit Name Description

7-0 PMCSR_BSE

The PCI PMCSR Bridge Support

Extensions Register is an 8-bit

Extensions are not supported.

This is a read-only register whose

content is 0.

PCI Data Register

Offset 4Bh

Note: All bits of this register are loaded from

EEPROM. The register is aliased to lower bytes of the

BCR37-44 for testing purposes.

Bit Name Description

7-0 DATA_REG The PCI Data Register is an 8-bit

read-only register that is used as

a window into an array of 8 ten-bit

PCIDATA registers. The value

read from this register is the 8

least significant bits of the PCI-

DATA register selected by

DATA_SEL field of the PMCSR

(offset 48h in PCI Configuration

Space). The two most significant

bits of the selected PCIDATA

DATA_SCALE field of the

PMCSR.

The interpretation of the contents

of this register is described in the

PCI Bus Power Management In-

terface Specification, Version

1.1.

124 Am79C976 9/14/00

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Memory-Mapped Registers

The Memory-Mapped Registers give the host CPU ac-

cess to all programmable features of the Am79C976

device. These registers are mapped directly into PCI

memory space so that any programmable feature can

be accessed with a single PCI memory read or write

transaction. Data in these registers can be accessed

as a single byte, a 16-bit word, or a 32-bit double word.

In addition, the Am79C976 controller’s memory is

prefetchable, which allows burst read and write opera-

tions. Accesses to consecutive registers or to registers

logically wider than double word (BADX, BADR, PADR,

etc.) may be treated as a single block move to take ad-

vantage of the PCI burst.

Registers that are logically wider than a double word

are shown in the register descriptions as a single reg-

ister. These may be accessed using multiple smaller

accesses or with a single burst access.

Some registers that are smaller than a double word in

width (STVAL, PADR[47:32], XMT_RING_LEN,

RCV_RING_LEN) are placed in the memory map in the

lower half of a double word. The upper half ignores

writes and reads back zeros (STVAL, PADR[47:32]) or

ones (XMT_RING_LEN, RCV_RING_LEN) as appro-

priate for sign extension. This allows these registers to

be accessed with double word reads and writes.

Memory-mapped registers can be initialized with data

loaded from the serial EEPROM.

The command and interrupt enable registers (CMD0,

CMD2, CMD3, CMD7, and INTEN0) use a write access

technique that in this document is called command

style access. Command style access allows the host

CPU to write to selected bits of a register without alter-

ing bits that are not selected. Command style registers

are divided into 4 bytes that can be written indepen-

dently. The high order bit of each byte is the ’value’ bit

that specifies the value that will be written to selected

bits of the register. The 7 low order bits of each byte

make up a bit map that selects which register bits will

be altered. If a bit in the bit map is set to 1, the corre-

sponding bit in the register will be loaded with the con-

tents of the value bit. If a bit in the bit map is cleared to

0, the corresponding bit in the register will not be al-

tered.

For example, if the value 10011010b is written to the

least significant byte of a command style register, bits

1, 3, and 4 of the register will be set to 1, and the other

bits will not be altered. If the value 00011010b is written

to the same byte, bits 1, 3, and 4 will be cleared to 0,

and the other bits will not be altered.

In the worst case it takes two write accesses to write to

all of the bits in a command style register. One access

writes to all bits that should be set to 1, and the other

access writes to all bits that should be cleared to 0.

The EEPROM loading logic bypasses the command

style access logic and treats command style registers

just like the other writable memory-mapped registers.

The value bits are ignored and the contents of the bit

map fields are written directly into the corresponding

registers. For example, if the EEPROM logic loads the

value 00011010b into the least significant byte of a com-

mand style register, bits 1, 3, and 4 of the register will be

set to 1, and bits 0, 2, 5, and 6 will be cleared to 0.

In the following register descriptions, the offset listed

for each register is the offset relative to the contents of

the PCI Memory-Mapped I/O Base Address Register.

MIB Offset

Offset 28h

This read-only register contains the offset of the block

of statistics counters. For the Am79C976 device the

content of this register is fixed at 200h. The contents of

the MIB Offset Registers and therefore the locations of

statistics counter blocks in other PCnet family devices

may be different. Therefore, software should calculate

the address of a particular MIB counter by adding the

contents of the Memory-Mapped I/O Base Address

shown in Table 7 on page 76 or Table 8 on page 78.

AP_VALUE0: Auto-Poll Value0 Register

Offset 0A8h

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 26. AP_VALUE0: Auto-Poll Value0 Register

AP_VALUE1: Auto-Poll Value1 Register

Offset 0AAh

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Bit Name Description

15-0 AP_VALUE0

This register contains the results of

the automatic polling of the user-

selectable external PHY register,

AP_REG0.

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Table 27. AP_VALUE1: Auto-Poll Value1 Register

AP_VALUE2: Auto-Poll Value2 Register

Offset 0ACh

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 28. AP_VALUE2: Auto-Poll Value2 Register

AP_VALUE3: Auto-Poll Value3 Register

Offset 0AEh

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 29. AP_VALUE3: Auto-Poll Value3 Register

AP_VALUE4: Auto-Poll Value4 Register

Offset 0B0h

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 30. AP_VALUE4: Auto-Poll Value4 Register

AP_VALUE5: Auto-Poll Value5 Register

Offset 0B2h

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 31. AP_VALUE5: Auto-Poll Value5 Register

AUTOPOLL0: Auto-Poll0 Register

Offset 088h

This register controls the automatic polling of the status

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits except for bits 15

(AP_REG0_EN) and 12:8 (AP_REG0_ADDR) is 0.

The default value for AP_REG0_EN is 1 and the de-

fault value for the AP_REG0_ADDR field is 00001b.

For legacy driver compatibility, the PHYAD field in

BCR33, bits [9:5], is aliased from AUTOPOLL0, bits

[9:5] when programmed through the EEPROM. The

default values of AUTOPOLL0, bits [12:8] remain

00001 and are read-only. The contents of

AUTOPOLL0, bits [7:5] remain reserved.

Bit Name Description

15-0 AP_VALUE

This register contains the results of

the automatic polling of the user-

selectable external PHY register,

AP_REG1.

Bit Name Description

15-0 AP_VALUE2

This register contains the results of

the automatic polling of the user-

selectable external PHY register,

AP_REG2.

Bit Name Description

15-0 AP_VALUE3

This register contains the results of

the automatic polling of the user-

selectable external PHY register,

AP_REG3.

Bit Name Description

15-0 AP_VALUE4

This register contains the results of

the automatic polling of the user-

selectable external PHY register,

AP_REG4.

Bit Name Description

15-0 AP_VALUE5

This register contains the results of

the automatic polling of the user-

selectable external PHY register,

AP_REG5.

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Table 32. AUTOPOLL0: Auto-Poll0 Register

Notes:

1. Bits [9:8] may be programmed via the EEPROM to alias the value into BCR33, bits [9:8].

2. Bits [7:5] may be programmed via the EEPROM to alias the value into BCR33, bits [7:5].

AUTOPOLL1: Auto-Poll1 Register

Offset 08Ah

This register controls the automatic polling of a user-

selectable external PHY register.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits in this register is 0.

Table 33. AUTOPOLL1: Auto-Poll1 Register

Bit Name Description

15 AP_REG0_EN Enable Bit for Autopoll Register 0. This bit is read-only and always has the value 1.

14-13 RES Reserved locations. Written as zeros and read as undefined

12-8 AP_REG0_

ADDR AP_REG0 Address. This field is read-only and always has the value 00001. See Note 1.

7-5 RES Reserved locations. Written as zero and read as undefined. See Note 2.

4-0 AP_PHY0_

ADDR

Auto-Poll PHY0 Address. This field contains the address of the external PHY that contains

AP-REG0. The Network Port Manager uses this PHY address for auto-negotiation. The

Autopoll State Machine also uses this field as the default PHY address when one or more

of the AP_PHYn_DFLT bits are set.

Bit Name Description

15 AP_REG1_EN

Enable Bit for Autopoll Register 1. When this bit and the Auto-Poll External PHY bit (APEP) in

CMD3 are both set to 1, the Auto-Poll State Machine periodically reads the external PHY register

selected by the AP_PHY1_ADDR and AP_REG1_ADDR fields and sets the APINT1 interrupt

bit if it detects a change in the register’s contents.

14-13 RES Reserved locations. Written as zeros and read as undefined.

12-8 AP_REG1_ADDR

AP_REG1 Address. This field contains the register number of an external PHY register that the

Auto-Poll State Machine will periodically read if the AP_REG1_EN bit in this register and the

APEP bit (CMD3, bit 24) is set.

7 RES Reserved location. Written as zero and read as undefined.

6 AP_PRE_SUP1

Auto-Poll Preamble Suppression. If this bit is set to 1, the Auto-Poll State Machine will suppress

the preambles of the MII Management Frames that it uses to periodically read the external PHY

This bit is ignored when the AP_PHY1_DFLT bit is set.

5 AP_PHY1_DFLT

Auto-Poll PHY1 Default. When this bit is set, the Auto-Poll State Machine ignores the contents

of the AP_PHY1_ADDR and AP_PRE_SUP1 fields and uses the AP_PHY0_ADDR field for the

address of the PHY device to be polled. If this bit is set, the Auto-Poll State Machine will

suppress preambles only if the Port Manager has determined that the default external PHY can

accept MII Management Frames without preambles. (The Port Manager examines bit 6 in

4-0 AP_PHY1_ADDR

Auto-Poll PHY1 Address. This field contains the address of the external PHY that contains

AP_REG1.

This bit is ignored when the AP_PHY1_DFLT bit is set.

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AUTOPOLL2: Auto-Poll2 Register

Offset 08Ch

This register controls the automatic polling of a user-

selectable external PHY register, AP_REG2.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits in this register is 0.

Table 34. AUTOPOLL2: Auto-Poll2 Register

Bit Name Description

15 AP_REG2_EN

Enable Bit for Autopoll Register 2. When this bit and the Auto-Poll External PHY bit (APEP) in

CMD3 are both set to 1, the Auto-Poll State Machine periodically reads the external PHY

interrupt bit if it detects a change in the register’s contents.

14-13 RES Reserved locations. Written as zeros and read as undefined.

12-8 AP_REG2_ADDR

AP_REG2 Address. This field contains the register number of an external PHY register that

the Auto-Poll State Machine will periodically read if the AP_REG2_EN bit in this register and

the APEP bit (CMD3, bit 24) is set.

7 RES Reserved location. Written as zero and read as undefined.

6 AP_PRE_SUP2

Auto-Poll Preamble Suppression. If this bit is set to 1, the Auto-Poll State Machine will

suppress the preambles of the MII Management Frames that it uses to periodically read the

external PHY register selected by the AP_PHY2_ADDR and AP_REG2_ADDR fields.

This bit is ignored when the AP_PHY2_DFLT bit is set.

5 AP_PHY2_DFLT

Auto-Poll PHY2 Default. When this bit is set, the Auto-Poll State Machine ignores the contents

of the AP_PHY2_ADDR and AP_PRE_SUP2 fields and uses the AP_PHY0_ADDR field for

the address of the PHY device to be polled. If this bit is set, the Auto-Poll State Machine will

suppress preambles only if the Port Manager has determined that the default external PHY

can accept MII Management Frames without preambles. (The Port Manager examines bit 6 in

4-0 AP_PHY2_ADDR

Auto-Poll PHY2 Address. This field contains the address of the external PHY that contains

AP_REG2.

This bit is ignored when the AP_PHY2_DFLT bit is set.

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AUTOPOLL3: Auto-Poll3 Register

Offset 08Eh

This register controls the automatic polling of a user-

selectable external PHY register, AP_REG3.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits in this register is 0.

Table 35. AUTOPOLL3: Auto-Poll3 Register

Bit Name Description

15 AP_REG3_EN

Enable Bit for Autopoll Register 3. When this bit and the Auto-Poll External PHY bit (APEP) in

CMD3 are both set to 1, the Auto-Poll State Machine periodically reads the external PHY register

selected by the AP_PHY3_ADDR and AP_REG3_ADDR fields and sets the APINT3 interrupt bit

if it detects a change in the register’s contents.

14-13 RES Reserved locations. Written as zeros and read as undefined.

12-8 AP_REG3_ADDR

AP_REG3 Address. This field contains the register number of an external PHY register that the

Auto-Poll State Machine will periodically read if the AP_REG3_EN bit in this register and the

APEP bit (CMD3, bit 24) is set.

7 RES Reserved location. Written as zero and read as undefined.

6 AP_PRE_SUP3

Auto-Poll Preamble Suppression. If this bit is set to 1, the Auto-Poll State Machine will suppress

the preambles of the MII Management Frames that it uses to periodically read the external PHY

This bit is ignored when the AP_PHY3_DFLT bit is set.

5 AP_PHY3_DFLT

Auto-Poll PHY3 Default. When this bit is set, the Auto-Poll State Machine ignores the contents

of the AP_PHY3_ADDR and AP_PRE_SUP3 fields and uses the AP_PHY0_ADDR field for the

address of the PHY device to be polled. If this bit is set, the Auto-Poll State Machine will suppress

preambles only if the Port Manager has determined that the default external PHY can accept MII

Management Frames without preambles. (The Port Manager examines bit 6 in register 1 of the

default PHY to make this determination.)

4-0 AP_PHY3_ADDR

Auto-Poll PHY3 Address. This field contains the address of the external PHY that contains

AP_REG3.

This bit is ignored when the AP_PHY3_DFLT bit is set.

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AUTOPOLL4: Auto-Poll4 Register

Offset 090h

This register controls the automatic polling of a user-

selectable external PHY register, AP_REG4.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits in this register is 0.

Table 36. AUTOPOLL4: Auto-Poll4 Register

Bit Name Description

15 AP_REG4_EN

Enable Bit for Autopoll Register 4. When this bit and the Auto-Poll External PHY bit (APEP) in

CMD3 are both set to 1, the Auto-Poll State Machine periodically reads the external PHY register

selected by the AP_PHY4_ADDR and AP_REG4_ADDR fields and sets the APINT4 interrupt bit

if it detects a change in the register’s contents.

14-13 RES Reserved locations. Written as zeros and read as undefined.

12-8 AP_REG4_ADDR

AP_REG4 Address. This field contains the register number of an external PHY register that the

Auto-Poll State Machine will periodically read if the AP_REG4_EN bit in this register and the

APEP bit (CMD3, bit 24) is set.

7 RES Reserved location. Written as zero and read as undefined.

6 AP_PRE_SUP4

Auto-Poll Preamble Suppression. If this bit is set to 1, the Auto-Poll State Machine will suppress

the preambles of the MII Management Frames that it uses to periodically read the external PHY

This bit is ignored when the AP_PHY4_DFLT bit is set.

5 AP_PHY4_DFLT

Auto-Poll PHY4 Default. When this bit is set, the Auto-Poll State Machine ignores the contents of

the AP_PHY4_ADDR and AP_PRE_SUP4 fields and uses the AP_PHY0_ADDR field for the

address of the PHY device to be polled. If this bit is set, the Auto-Poll State Machine will suppress

preambles only if the Port Manager has determined that the default external PHY can accept MII

Management Frames without preambles. (The Port Manager examines bit 6 in register 1 of the

default PHY to make this determination.)

4-0 AP_PHY4_ADDR

Auto-Poll PHY4 Address. This field contains the address of the external PHY that contains

AP_REG4.

This bit is ignored when the AP_PHY4_DFLT bit is set.

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AUTOPOLL5: Auto-Poll5 Register

Offset 092h

This register controls the automatic polling of a user-

selectable external PHY register, AP_REG5.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits in this register is 0.

Table 37. AUTOPOLL5: Auto-Poll5 Register

BADR: Receive Ring Base Address Register

Offset 120h

This 64-bit register allows the Receive Descriptor Ring

to be located anywhere in a 64-bit address space. For

systems with a 32-bit or smaller address space, it is

only necessary to program the lower 32 bits of this reg-

ister (by writing to offset 120h). The upper 32 bits will

remain at the default value of 0.

The contents of this register are set to the default value

0 when the RST pin is asserted. This register is not af-

fected by the serial EEPROM read operation or by a

serial EEPROM read error.

Table 38. Receive Ring Base Address Register

Bit Name Description

15 AP_REG5_EN

Enable Bit for Autopoll Register 5. When this bit and the Auto-Poll External PHY bit (APEP) in

CMD3 are both set to 1, the Auto-Poll State Machine periodically reads the external PHY register

selected by the AP_PHY5_ADDR and AP_REG5_ADDR fields and sets the APINT5 interrupt bit

if it detects a change in the register’s contents.

14-13 RES Reserved locations. Written as zeros and read as undefined.

12-8 AP_REG5_ADDR

AP_REG5 Address. This field contains the register number of an external PHY register that the

Auto-Poll State Machine will periodically read if the AP_REG5_EN bit in this register and the

APEP bit (CMD3, bit 24) is set.

7 RES Reserved location. Written as zero and read as undefined.

6 AP_PRE_SUP5

Auto-Poll Preamble Suppression. If this bit is set to 1, the Auto-Poll State Machine will suppress

the preambles of the MII Management Frames that it uses to periodically read the external PHY

This bit is ignored when the AP_PHY5_DFLT bit is set.

5 AP_PHY5_DFLT

Auto-Poll PHY5 Default. When this bit is set, the Auto-Poll State Machine ignores the contents

of the AP_PHY5_ADDR and AP_PRE_SUP5 fields and uses the AP_PHY0_ADDR field for the

address of the PHY device to be polled. If this bit is set, the Auto-Poll State Machine will suppress

preambles only if the Port Manager has determined that the default external PHY can accept MII

Management Frames without preambles. (The Port Manager examines bit 6 in register 1 of the

default PHY to make this determination.)

4-0 AP_PHY5_ADDR

Auto-Poll PHY5 Address. This field contains the address of the external PHY that contains

AP_REG5.

This bit is ignored when the AP_PHY5_DFLT bit is set.

Bit Name Description

63-0 BADR

Base Address of Receive Descriptor Ring. In systems with a 32-bit or smaller address space, it is

only necessary to program the 32 low-order bits of this register.

The low order 32 bits of this register are an alias of CSR24 and CSR25.

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BADX: Transmit Ring Base Address Register

Offset 100h

This 64-bit register allows the Transmit Descriptor Ring

to be located anywhere in a 64-bit address space. For

systems with a 32-bit or smaller address space, it is

only necessary to program the lower 32 bits of this reg-

ister (by writing to offset 100h). The upper 32 bits will

remain at the default value of 0.

The contents of this register are set to the default value

0 when the RST pin is asserted. This register is not af-

fected by the serial EEPROM read operation or by a

serial EEPROM read error.

Table 39. Transmit Ring Base Address Register

CHIPID: Chip ID Register

Offset 0F0h

This read-only register is an alias of CSR88.

Table 40. CHIPID: Chip ID Register

CHPOLLTIME: Chain Poll Timer Register

Offset 18Ah

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 41. CHPOLLTIME: Chain Polling Interval Register

Bit Name Description

63-0 BADX

Base Address of Transmit Descriptor Ring. In systems with a 32-bit or smaller address space, it is

only necessary to program the 32 low-order bits of this register.

The low-order 32 bits of this register are an alias of CSR30 and CSR31.

Bit Name Description

31-28 VER Version. This 4-bit pattern is silicon-revision dependent.

27-12 PARTID

Part number. The 16-bit code for the Am79C976 controller is 0010 0110 0010 1000b (2628h).

This register is exactly the same as the Device ID register in the JTAG description. However, this

part number is different from that stored in the Device ID register in the PCI configuration space.

11-1 MANFID

Manufacturer ID. The 11-bit manufacturer code for AMD is 00000000001b. This code is per the

JEDEC Publication 106-A.

Note that this code is not the same as the Vendor ID in the PCI configuration space.

0 ONE Always logic 1.

Bit Name Description

15-0 CHPOLL TIME

Chain Polling Interval. This register contains the time that the Am79C976 controller will wait

between successive polling operations when the Buffer Management Unit is in the middle of a

buffer chaining operation. The CHPOLLTIME value is expressed as the two’s complement of the

desired interval, where each bit of CHPOLLTIME approximately represents 3 ERCLK periods.

CHPOLLTIME[3:0] are ignored. (CHPOLLTIME[16] is implied to be a 1, so CHPOLLTIME[15] is

significant and does not represent the sign of the two’s complement CHPOLLTIME value.)

The default value of this register is 0000h. This corresponds to a polling interval of 65,536 clock

periods (2.185 ms when ERCLK = 90 MHz).

Setting the INIT bit starts an initialization process that sets CHPOLLTIME to its default value. If the

user wants to program a value for CHPOLLTIME other than the default, then the user must change

the value after the initialization sequence has completed.

This register is an alias for CSR49.

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CMD0: Command0

Offset 048h

CMD0 is a command-style register. All bits in this reg-

ister are cleared to 0 when the RST pin is asserted, be-

fore the serial EEPROM is read, and after a serial

EEPROM read error.

Table 42. CMD0: Command0 Register

Bit Name Description

31-16 RES Reserved locations. Written as zeros and read as undefined.

15 VAL1 Value bit for byte 1. The value of this bit is written to any bits in the CMD0 register that correspond

to bits in the CMD0[14:8] bit map field that are set to 1.

14-13 RES Reserved locations. Written as zeros and read as undefined.

12 RDMD Receive Demand, when set, causes the Descriptor Management Unit to access the Receive

Descriptor Ring without waiting for the chain poll-time counter to expire.

11-9 RES Reserved locations. Written as zeros and read as undefined.

8TDMD

Transmit Demand, when set, causes the Buffer Management Unit to access the Transmit

Descriptor Ring without waiting for the poll-time counter to elapse. If TXON is not enabled, TDMD

bit will be reset and no Transmit Descriptor Ring access will occur.

If the TXDPOLL bit in CMD2 is set, the host processor must set TDMD each time it is ready for the

Am79C976 device to poll the Transmit Descriptor Ring. When TXDPOLL = 0, setting TDMD

merely hastens the Am79C976 controller’s next access to a Transmit Descriptor Ring Entry.

7VAL0

Value bit for byte 0. The value of this bit is written to any bits in the CMD0 register that correspond

to bits in the CMD0[6:0] bit map field that are set to 1.

6UINTCMD

User Interrupt Command. UINTCMD can be used by the host to generate an interrupt unrelated to

any network activity. Writing a 1 to this bit causes the UINT bit in the Interrupt Register to be set to

1, which in turn causes INTA to be asserted if interrupts are enabled.

UINTCMD is always read as 0.

5RX_FAST_

SPND

Receive Fast Suspend. Setting this bit causes the receiver to suspend its activities as quickly as

possible without stopping in the middle of a frame reception. Setting RX_FAST_SPND does not

stop the DMA controller from transferring frame data from the receive FIFO to host memory.

If a frame is being received at the time that RX_FAST_SPND is set to 1, the reception of that frame

will be completed, but no more frames will be received until RX_FAST_SPND is cleared to 0.

After the receiver has suspended its activity, the RX_SUSPENDED bit in the Status register and

the Suspend Interrupt (SPNDINT) bit in the Interrupt register will be set, which will cause an

interrupt to occur if interrupts are enabled and the SPNDINTEN bit in the Interrupt Enable register

is set.

4 TX_FAST_SPND

Transmit Fast Suspend. Setting this bit causes the transmitter to suspend its activities as quickly

as possible without stopping in the middle of a frame transmission. Setting TX_FAST_SPND does

not stop the DMA controller from transferring frame data from host memory to the transmit FIFO.

If a frame is being transmitted at the time that TX_FAST_SPND is set to 1, the transmission of that

frame will be completed, but no more frames will be transmitted until TX_FAST_SPND is cleared

to 0.

After the transmitter has suspended its activity, the TX_SUSPENDED bit in the Status register and

the Suspend Interrupt (SPNDINT) bit in the INT0 register will be set, which will cause an interrupt

to occur if interrupts are enabled and the SPNDINTEN bit in the Interrupt Enable register is set.

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CMD2: Command2

Offset 050h

CMD2 is a command-style register. All bits in this reg-

ister are cleared to 0 when the RST pin is asserted, be-

fore the serial EEPROM is read, and after a serial

EEPROM read error.

Table 43. CMD2: Command2 Register

3 RX_SPND

Receive Suspend. Setting this bit causes the receiver to suspend its activities without stopping in

the middle of a frame reception. After the receiver suspends its activities, the DMA controller

continues copying data from the Receive FIFO into host system memory until the FIFO is empty

or until no more receive descriptors are available.

After the Receive FIFO has been emptied or after all receive descriptors have been used, the

receive DMA controller suspends its polling activity, and the RX_SUSPENDED bit in the Status

SPNDINT bit will cause an interrupt to occur if interrupts are enabled and the SPNDINTEN bit in

the Interrupt Enable register is set.

2TX_SPND

Transmit Suspend. Setting this bit causes the transmitter to suspend its activities without stopping

in the middle of a frame transmission. After the transmitter suspends its activities, the DMA

controller continues copying data from host system memory into the Transmit FIFO until the FIFO

is full or until no more transmit descriptors are available.

After the Transmit FIFO has been filled or after all transmit descriptors have been used, the

transmit DMA controller suspends its polling activity, and the TX_SUSPENDED bit in the Status

SPNDINT bit will cause an interrupt to occur if interrupts are enabled and the SPNDINTEN bit in

the Interrupt Enable register is set.

1 INTREN

Interrupt Enable. This bit allows INTA to be asserted if any bit in the Interrupt register is set. If

INTREN is cleared to 0, INTA will not be asserted, regardless of the state of the Interrupt register.

INTREN is not an alias of the IENA bit in CSR0.

0 RUN

Setting the RUN bit enables the Am79C976 controller to start processing descriptors and

transmitting and receiving packets.

Clearing the RUN bit to 0 abruptly disables the transmitter, receiver, and descriptor processing

logic, possibly while a frame is being transmitted or received.

The act of changing the RUN bit from 1 to 0 causes the following bits to be reset to 0: IENA,

TX_SPND, RX_SPND, TDMD, RDMD, UINTCMD, TX_FAST_SPND, RINT, TINT, TXSTRTINT,

TXDNINT, MPINT, and UINT.

Bit Name Description

31 VAL3 Value bit for byte 3. The value of this bit is written to any bits in the CMD2 register that correspond

to bits in the CMD2[30:24] bit map field that are set to 1.

30 NOUFLO

No Underflow on Transmit. When the NOUFLO bit is set to 1, the Am79C976 controller will not start

transmitting the preamble for a packet until the Transmit Start Point (CTRL1, bits 16-17)

requirement has been met and the complete packet has been copied into the transmit FIFO. When

the NOUFLO bit is cleared to 0, the Transmit Start Point is the only restriction on when preamble

transmission begins for transmit packets.

Setting the NOUFLO bit guarantees that the Am79C976 controller will never suffer transmit

underflows, because the arbiter that controls transfers to and from the SSRAM guarantees a worst

case latency on transfers to and from the MAC and Bus Transmit FIFOs such that it will never

underflow if the complete packet has been copied into the Am79C976 controller before packet

transmission begins.

This bit is an alias of BCR18, bit 11. It is included only to allow programming from the EEPROM for

compatibility with legacy software.

134 Am79C976 9/14/00

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29 LEDPE

LED Program Enable. When LEDPE is set to 1, programming of the LED functions through BCR4,

BCR5, BCR6, and BCR7 is enabled. When LEDPE is cleared to 0, programming of LED functions

through these registers is disabled. Writes to these registers will be ignored. However, LEDPE

does not affect the programming of LED functions through the memory mapped LED registers,

LED0, LED1, LED2 and LED3. The memory-mapped LED registers are always enabled,

regardless of the state of LEDPE.

This bit is an alias of BCR2, bit 12. It is included only to allow programming from the EEPROM for

compatibility with legacy software.

28 DWIO

Double Word I/O. When set, this bit indicates that the Am79C976 controller is programmed for

DWord I/O (DWIO) mode. When cleared, this bit indicates that the Am79C976 controller is

programmed for Word I/O (WIO) mode. This bit affects the I/O Resource Offset map and it affects

the defined width of the Am79C976 controllers I/O resources. See the DWIO and WIO sections for

more details.

The initial value of the DWIO bit is determined by the programming of the EEPROM.

The value of DWIO can be altered automatically by the Am79C976 controller. Specifically, the

Am79C976 controller will set DWIO if it detects a DWord write access to offset 10h from the

Am79C976 controller I/O base address (corresponding to the RDP resource).

This bit is an alias of BCR18, bit 7. It is included only to allow programming from the EEPROM for

compatibility with legacy software.

27 APROMWE

Address PROM Write Enable. The Am79C976 controller contains a 16-byte shadow RAM on board

that emulates a small PROM that was used in conjunction with early AMD Ethernet controllers.

Accesses to Address PROM I/O space will be directed to this RAM. When APROMWE is set to 1,

then write access to the shadow RAM will be enabled.

This bit is an alias of BCR2, bit 8. It is included only to allow programming from the EEPROM for

compatibility with legacy software.

26-24 RES Reserved locations. Written as zeros and read as undefined.

23 VAL2 Value bit for byte 2. The value of this bit is written to any bits in the CMD2 register that correspond

to bits in the CMD2[22:16] bit map field that are set to 1.

22-21 RES Reserved locations. Written as zeros and read as undefined.

20 FDRPA

Full-Duplex Runt Packet Accept. When FDRPA is cleared to 0 and full-duplex mode is enabled, the

Am79C976 controller will only receive frames that meet the minimum Ethernet frame length of 64

bytes. Receive DMA will not start until at least 64 bytes or a complete frame have been received.

By default, FDRPA is cleared to 0. When FDRPA is set to 1, the Am79C976 controller will accept

any frame of 12 bytes or greater, and receive DMA will start according to the programming of the

receive FIFO watermark.

This bit is the inverse of BCR9, bit 2.

19 RPA

Runt Packet Accept. This bit forces the Am79C976 controller to accept runt packets (packets

shorter than 64 bytes). The minimum packet size that can be received is 12 bytes.

This bit is an alias of CSR124, bit 3.

18 DRCVPA

Disable Receive Physical Address. When set, the physical address detection (Station or node ID)

of the Am79C976 controller will be disabled. Frames addressed to the node’s individual physical

address will not be recognized.

This bit is an alias of CSR15, bit 13.

17 DRCVBC

Disable Receive Broadcast. When set, disables the Am79C976 controller from receiving broadcast

messages. Used for protocols that do not support broadcast addressing, except as a function of

multicast. DRCVBC is cleared by activation of H_RESET or S_RESET (broadcast messages will

be received) and is unaffected by STOP.

This bit is an alias of CSR15, bit 14.

16 PROM

Promiscuous Mode. When PROM = 1, all incoming receive frames are accepted, regardless of

their destination addresses.

This bit is an alias of CSR15, bit 15.

Bit Name Description

9/14/00 Am79C976 135

PRELIMINARY

15 VAL1 Value bit for byte 1. The value of this bit is written to any bits in the CMD2 register that correspond

to bits in the CMD2[14:8] bit map field that are set to 1.

14 RES Reserved location. Written as zero and read as undefined.

13 ASTRP_RCV

Auto Strip Receive. When set, ASTRP_RCV enables the automatic pad stripping feature. For any

receive frame whose length field has a value less than 46, the pad and FCS fields will be stripped

and not placed in the FIFO.

This bit is an alias of CSR4, bit 10.

12 FCOLL

Force Collision. This bit allows the collision logic to be tested. The Am79C976 controller must be

in internal loopback for FCOLL to be valid. If FCOLL = 1, a collision will be forced during loopback

transmission attempts, which will result in a Retry Error. If FCOLL = 0, the Force Collision logic will

be disabled.

This bit is an alias of CSR15, bit 4.

11 EMBA

Enable Modified Back-off Algorithm (see Contention Resolution section in Media Access

Management section for more details). If EMBA is set, a modified back-off algorithm is

implemented.

This bit is an alias of CSR3, bit 3.

10 DXMT2PD

Disable Transmit Two Part Deferral (see Medium Allocation section in the Media Access

Management section for more details). If DXMT2PD is set, Transmit Two Part Deferral will be

disabled.

This bit is an alias of CSR3, bit 4.

9LTINTEN

Last Transmit Interrupt Enable. When this bit is set to 1, the LTINT bit in transmit descriptors can

be used to determine when transmit interrupts occur. The Transmit Interrupt (TINT) bit will be set

after a frame has been copied to the Transmit FIFO if the LTINT bit in the frame’s last transmit

descriptor is set. If the LTINT bit in the frame’s last descriptor is 0 TINT will not be set after the frame

has been copied to the Transmit FIFO.

This bit is an alias of CSR5, bit 14.

8DXMTFCS

Disable Transmit CRC (FCS). When DXMTFCS is set to 0, the transmitter will generate and

append an FCS to the transmitted frame. When DXMTFCS is set to 1, no FCS is generated or sent

with the transmitted frame. DXMTFCS is overridden when ADD_FCS and ENP bits are set in the

transmit descriptor.

When the auto padding logic, which is enabled by the APAD_XMT bit (CMD2, bit6), adds padding

to a frame, a valid FCS field is appended to the frame, regardless of the state of DXMTFCS.

If DXMTFCS is set and ADD_FCS is clear for a particular frame, no FCS will be generated. If

ADD_FCS is set for a particular frame, the state of DXMTFCS is ignored and a FCS will be

appended on that frame by the transmit circuitry. See also the ADD_FCS bit in the transmit

descriptor.

This bit was called DTCR in the LANCE (Am7990) device.

This bit is an alias of CSR15, bit 3.

7VAL0

Value bit for byte 0. The value of this bit is written to any bits in the CMD2 register that correspond

to bits in the CMD2[6:0] bit map field that are set to 1.

6APAD_XMT

Auto Pad Transmit. When set, APAD_XMT enables the automatic padding feature. Transmit

frames will be padded to extend them to 64 bytes including FCS. The FCS is calculated for the

entire frame, including pad, and appended after the pad field. When the auto padding logic modifies

a frame, a valid FCS field will be appended to the frame, regardless of the state of the DXMTFCS

bit (CMD2, bit 8) and of the ADD_FCS bit in the transmit descriptor.

This bit is an alias of CSR4, bit 11.

5DRTY

Disable Retry. When DRTY is set to 1, the Am79C976 controller will attempt only one transmission.

In this mode, the device will not protect the first 64 bytes of frame data in the Transmit FIFO from

being overwritten, because automatic retransmission will not be necessary. When DRTY is set to

0, the Am79C976 controller will attempt 16 transmissions before signaling a retry error.

This bit is an alias of CSR15, bit 5.

Bit Name Description

136 Am79C976 9/14/00

PRELIMINARY

4INLOOP

Internal Loopback. When this bit is set, the transmitter is internally connected to the receiver so that

the TXD[3:0] outputs are connected internally to the RXD[3:0] inputs, the TX_EN output is

connected to the RX_DV input, and RX_CLK is connected to TX_CLK. The device is forced into

full duplex mode so that collisions can not occur.

The INLOOP and EXLOOP bits should not be set at the same time.

Setting INLOOP to 1 is equivalent to setting LOOP (in CSR15) to 1 and MIIILP (in BCR32) to 1.

3 EXLOOP

External Loopback. When this bit is set, the device is forced into full duplex mode so that collisions

can not occur during loop back testing. If the TXD[3:0] outputs are connected externally to the

RXD[3:0] inputs, the TX_EN output is externally connected to the RX_DV input, and RX_CLK is

connected to TX_CLK, then transmitted frames will also be received. This connection can be made

by attaching an external jumper or by programming an attached PHY to loopback mode.

The INLOOP and EXLOOP bits should not be set at the same time.

Setting EXLOOP to 1 is equivalent to setting LOOP (in CSR15) to 1 and MIIILP (in BCR32) to 0.

2 LAPPEN

Look Ahead Packet Processing Enable. When set to a 1, the LAPPEN bit will cause the Am79C976

controller to generate an interrupt following the descriptor write operation to the first buffer of a

receive frame. This interrupt will be generated in addition to the interrupt that is generated following

the descriptor write operation to the last buffer of a receive packet. The interrupt will be signaled

through the RINT bit of CSR0 or the INT register.

Setting LAPPEN to a 1 also modifies the way the controller accesses the Receive Descriptors. See

the Look Ahead Packet Processing section.

This bit is an alias of CSR3, bit 5.

See Appendix A for more information on the Look Ahead Packet Processing concept.

1 CHDPOLL

Disable Chain Polling. If CHDPOLL is set, the Buffer Management Unit will disable chain polling.

Likewise, if CHDPOLL is cleared, automatic chain polling is enabled. If CHDPOLL is set and the

Buffer Management Unit is in the middle of a buffer-changing operation, setting the RDMD bit in

CMD0 or CSR7 will cause a poll of the current receive descriptor, and setting the TDMD bit in

CMD0 or CRR0 will cause a poll of the current transmit descriptor. If CHDPOLL is set, the RDMD

bit in CSR7 or CMD0 can be set to initiate a manual poll of a receive or transmit descriptor if the

Buffer Management Unit is in the middle of a buffer-chaining operation.

This bit is an alias of CSR7, bit 12.

0TXDPOLL

Disable Transmit Polling. If TXDPOLL is set, the Buffer Management Unit will disable transmit

polling. Likewise, if TXDPOLL is cleared, automatic transmit polling is enabled. If TXDPOLL is set,

TDMD bit in CSR0 or CMD0 must be set in order to initiate a manual poll of a transmit descriptor.

Transmit descriptor polling will not take place if TXON is reset. Transmit polling will take place

following Receive activities.

This bit is an alias of CSR4, bit 12.

Bit Name Description

9/14/00 Am79C976 137

PRELIMINARY

CMD3: Command3

Offset 054h

CMD3 is a command-style register. All bits in this reg-

ister are cleared to 0 when the RST pin is asserted, be-

fore the serial EEPROM is read, and after a serial

EEPROM read error.

Table 44. CMD3: Command3 Register

Bit Name Description

31 VAL3 Value bit for byte 3. The value of this bit is written to any bits in the CMD3 register that correspond

to bits in the CMD3[30:24] bit map field that are set to 1.

30 PREFETCH_DIS

Disable Prefetchability. This bit, which can be loaded from EEPROM, is the inverse of the value

reported in the PREFETCH bit in the PCI Memory-Mapped I/O Base Address Register, which is

read-only.

Setting PREFETCH_DIS to 1 indicates that the memory space claimed by this device can not be

prefetched.

Because of the side effects of reading the Reset Register at offset 14h or 18h (depending on the

state of DWIO (CMD2, bit 28)), locations at offsets less than 20h cannot be prefetched. The

Am79C976 device will disconnect any attempted burst transfer at offsets less than 20h.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL3 bit. If a logical 0 is written to this bit position, the corresponding bit in the

29 DIS_READ_WAIT Disable Read Wait. When this bit is set to 1, the controller will not insert IRDY wait states in burst

read transfers.

28 DIS_WRITE_WAIT Disable Write Wait. When this bit is set to 1, the controller will not insert IRDY wait states in burst

write transfers.

27 DISABLE_MWI Disable MWI. When this bit is set to 1, the controller will not generate MWI PCI bus commands.

26 RST_PHY Reset PHY. When this bit is set to 1, the controller will assert the PHY_RST signal. The signal

will remain asserted for as long as this bit remains set.

25 INIT_MIB

Initialize Management Information Base Counters. Setting this bit will cause all of the MIB

counters to be reset to 0. Resetting these counters takes about 55 ERCLK cycles. This bit is

cleared automatically after the counters have all been reset to 0. This bit must not be set to 1 by

the EEPROM logic.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL3 bit. If a logical 0 is written to this bit position, the corresponding bit in the

24 APEP

MII Auto-Poll External PHY (APEP) When set to 1, the Am79C976 controller will poll the MII

status register in the external PHY. This feature allows the software driver or upper layers to see

any changes in the status of the external PHY. An interrupt, when enabled, is generated when

the contents of the new status is different from the previous status.

This bit is an alias of BCR32, bit 11.

23 VAL2 Value bit for byte 2. The value of this bit is written to any bits in the CMD3 register that correspond

to bits in the CMD3[22:16] bit map field that are set to 1.

22 RES Reserved. Written as 1 and read as undefined.

21 JUMBO

Accept Jumbo Frames. This bit affects the way the MIB counters count long frames. If JUMBO

is 0, only frames that are between 64 and 1518 bytes (or 1522 bytes if VLAN is set to 1) are

counted as valid frames. When JUMBO is 1, any frame longer than 63 bytes with a valid FCS

field is counted as a valid frame.

20 VSIZE

VLAN Frame Size. This bit determines the maximum frame size used for determining when to

increment the XmtPkts1024to1518Octets, XmtExcessiveDefer, RcvPkts1024to1518Octets, and

RcvOversizePkts MIB counters and when to assert the Excessive Deferral Interrupt.

When this bit is set to 1 the maximum frame size is 1522 bytes. When it is cleared to 0, the

maximum frame size is 1518 bytes.

138 Am79C976 9/14/00

PRELIMINARY

19 VLONLY Admit Only VLAN Frames. When this bit is set to 1, only frames with a VLAN Tag Header

containing a non-zero VLAN ID field will be received. All other frames will be rejected.

18 REX_RTRY

Retransmit on Retry Error. When this bit is set to 1, if collisions occur for 16 attempts to transmit

a frame, the back-off logic is reset, but the frame is not discarded. Instead, it is treated as if it

were the next frame in the transmit queue.

When this bit is cleared to 0, if collisions occur for 16 attempts to transmit a frame, the frame is

dropped.

In either case, if collisions occur for 16 attempts to transmit a frame, the XmtExcessiveCollision

counter is incremented.

17 REX_UFLO

Retransmit on Underflow. When this bit is set to 1, if the transmitter is forced to abort a

transmission because the transmit FIFO underflows, the transmitter will not discard the frame.

Instead, it will automatically wait until the entire frame has been loaded into the transmit FIFO

and then will restart the transmission process.

When this bit is cleared to 0, if the transmitter is forced to abort a transmission because the FIFO

underflows, the transmitter will discard the frame.

In either case, the XmtUnderrunPkts counter will be incremented.

16 RTRY_LCOL

Retry on Late Collision. When this bit is set to 1, late collisions are treated like normal collisions,

except that the XmtLateCollision counter and the XmtCollisions counter will both be incremented.

When this bit is cleared to 0, if a late collision occurs, the transmitter will discard the frame that

was being transmitted when the collision occurred.

15 VAL1 Value bit for byte 1. The value of this bit is written to any bits in the CMD3 register that correspond

to bits in the CMD3[14:8] bit map field that are set to 1.

14 DISPM

Disable Port Manager. (The corresponding bit in older PCnet family devices is called Disable

Auto-Negotiation Auto Setup or DANAS. The name has been changed, but not the function.)

When DISPM is set, the Network Port Manager function is disabled, and the host CPU is

responsible for ensuring that the MAC and external PHY are operating in the same mode.

This bit is an alias of BCR32, bit 7.

13 INTLEVEL

Interrupt Level. This bit allows the interrupt output signals to be programmed for level- or edge-

sensitive applications.

When INTLEVEL is cleared to 0, the INTA pin is configured for level-sensitive applications. In this

mode, an interrupt request is signaled by a low level driven on the INTA pin by the Am79C976

controller. When the interrupt is cleared, the INTA pin is tri-stated by the Am79C976 controller

and allowed to be pulled to a high level by an external pull-up device. This mode is intended for

systems which allow the interrupt signal to be shared by multiple devices.

When INTLEVEL is set to 1, the INTA pin is configured for edge-sensitive applications. In this

mode, an interrupt request is signaled by a high level driven on the INTA pin by the Am79C976

controller. When the interrupt is cleared, the INTA pin is driven to a low level by the Am79C976

controller. This mode is intended for systems that do not allow interrupt channels to be shared by

multiple devices.

INTLEVEL should not be set to 1 when the Am79C976 controller is used in a PCI bus application.

This bit is an alias of BCR2, bit 7.

12 FORCE_FD

Force Full Duplex. (This bit is called Full-Duplex Enable (FDEN) in other PCnet family devices.)

This bit controls whether full-duplex operation is enabled. When FORCE_FD is cleared and the

Port Manager is disabled, the Am79C976 controller will always operate in the half-duplex mode.

When FORCE_FD is set, the Am79C976 controller will operate in full-duplex mode. Do not set

this bit when the Port Manager is enabled.

This bit is an alias of BCR9, bit 0.

11 FORCE_LS

Force Link Status. When this bit is set, the internal link status is forced to the Pass state

regardless of the actual state of the PHY device. When this bit is cleared to 0, the internal link

status is determined by the Port Manager.

Bit Name Description

9/14/00 Am79C976 139

PRELIMINARY

10 RXFRTGEN

Receive Frame Tag Enable. When this bit is set, frame tag data that is shifted in through the

External Address Detection Interface (EADI) while a frame is being received will be copied to the

receive descriptor.

9 MPPLBA

Magic Packet Physical Logical Broadcast Accept. If MPPLBA is at its default value of 0, the

Am79C976 controller will only detect a Magic Packet frame if the destination address of the

packet matches the content of the physical address register (PADR). If MPPLBA is set to 1, the

destination address of the Magic Packet frame can be unicast, multicast, or broadcast. Note that

the setting of MPPLBA only affects the address detection of the Magic Packet frame. The Magic

Packet frame’s data sequence must be made up of 16 consecutive physical addresses

(PADR[47:0]) regardless of what kind of destination address it has. This bit is OR’ed with

EMPPLBA bit (CSR116, bit 6).

This bit is an alias of CSR5, bit 5.

8 MPPEN_EE

Magic Packet Pin Enable. When either this bit or the MPPEN_SW bit in CMD7 is set, the device

enters the Magic Packet mode when the PG input goes LOW. This bit has the same function as

MPPEN_SW except that H_RESET clears MPPEN_EE to 0, while H_RESET has no effect on

MPPEN_SW.

This bit is an alias of CSR116, bit 4.

7VAL0

Value bit for byte 0. The value of this bit is written to any bits in the CMD3 register that correspond

to bits in the CMD3[6:0] bit map field that are set to 1.

6 MPEN_EE

Magic Packet Enable. When either this bit or the MPEN_SW bit in CMD7 is set, the device enters

the Magic Packet mode. This bit has the same function as MPEN_SW except that H_RESET

clears MPEN_EE to 0, while H_RESET has no effect on MPEN_SW.

5 LCMODE_EE

Link Change Wake-up Mode. When either this bit or the LCMODE_SW bit in CMD7 is set to 1,

the LCDET bit gets set when the MII auto polling logic detects a Link Change. This bit has the

same function as LCMODE_SW except that H_RESET clears LCMODE_EE to 0, while

H_RESET has no effect on LCMODE_SW.

This bit is an alias of CSR116, bit 8.

4PME_EN_OVR

PME_EN Overwrite. When this bit is set and the MPMAT or LCDET bit is set, the PME pin will

always be asserted regardless of the state of PME_EN bit.

This bit is an alias of CSR116, bit 10.

3 RWU_DRIVER

RWU Driver Type. If this bit is set to 1, RWU is a totem pole driver; otherwise, RWU is an open

drain output.

This bit is an alias of CSR116, bit 3.

2RWU_GATE

RWU Gate Control. If this bit is set, RWU is forced to the high Impedance State when PG is LOW,

regardless of the state of the MPMAT and LCDET bits.

This bit is an alias of CSR116, bit 2.

1RWU_POL

RWU Pin Polarity. If RWU_POL is set to 1, the RWU pin is normally HIGH and asserts LOW;

otherwise, RWU is normally LOW and asserts HIGH.

This bit is an alias of CSR116, bit 1.

0RST_POL

PHY_RST Pin Polarity. If the RST_POL is set to 1, the PHY_RST pin is active LOW; otherwise,

PHY_RST is active HIGH.

This bit is an alias of CSR116, bit 0.

Bit Name Description

140 Am79C976 9/14/00

PRELIMINARY

CMD7: Command7

Offset 064h

CMD7 is a command-style register. All bits in this reg-

ister are cleared to 0 when power is first applied to the

device (power-on reset). The contents of this register

are not affected by the state of the RST pin. The con-

tents of this register can not be loaded from the

EEPROM. Therefore, the contents of this register are

not disturbed when PCI bus power is removed and re-

applied.

Table 45. CMD7: Command7 Register

Bit Name Description

31-8 RES Reserved locations. Written as zeros and read as undefined.

7VAL0

Value bit for byte 0. The value of this bit is written to any bits in the CMD7 register that correspond

to bits in the CMD7[6:0] bit map field that are set to 1.

6-4 RES Reserved locations. Written as zeros and read as undefined.

3PMAT_MODE

Pattern Match Mode. Writing a 1 to this bit will enable Pattern Match Mode and should only be done

after the Pattern Match RAM has been programmed.

Pattern Match Mode is enabled when either this bit or BCR45, bit 7 is set.

2 MPPEN_SW

Magic Packet Pin Enable. When either this bit or the MPPEN_EE bit in CMD3 is set, the device

enters the Magic Packet mode when the PG input goes LOW. This bit has the same function as

MPPEN_EE except that H_RESET clears MPPEN_EE to 0, while H_RESET has no effect on

MPPEN_SW.

1 MPEN_SW

Magic Packet Software Mode Enable. The Am79C976 controller enters the Magic Packet mode

when this bit is set to 1. This bit has the same function as MPEN_EE except that H_RESET clears

MPEN_EE to 0, while H_RESET has no effect on MPEN_SW.

0 LCMODE_SW

Link Change Wake-up Mode. When either this bit or the LCMODE_EE bit in CMD3 is set to 1, the

LCDET bit gets set when the MII auto polling logic detects a Link Change. This bit has the same

function as LCMODE_EE except that H_RESET clears LCMODE_EE to 0, while H_RESET has

no effect on LCMODE_SW.

9/14/00 Am79C976 141

PRELIMINARY

CTRL0: Control0 Register

Offset 068h

This register contains several miscellaneous control

bits. Each byte of this register controls a single func-

tion. It is not necessary to do a read-modify-write oper-

ation to change a function’s settings if only a single byte

of the register is written.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits except for bits 11:8

(ROMTMG) is 0. The default value for the ROMTMG

field is 1001b.

Table 46. CTRL0: Control0 Register

Bit Name Description

31-25 RES Reserved locations. Written as zeros and read as undefined.

24 BSWP

Byte Swap. This bit is used to choose between big and little Endian modes of operation. When

BSWP is set to a 1, big Endian mode is selected. When BSWP is set to 0, little Endian mode is

selected.

When big Endian mode is selected, the Am79C976 controller will swap the order of bytes on the

AD bus during a data phase on accesses to the FIFOs only. Specifically, AD[31:24] becomes Byte

0, AD[23:16] becomes Byte 1, AD[15:8] becomes Byte 2, and AD[7:0] becomes Byte 3 when big

Endian mode is selected. When little Endian mode is selected, the order of bytes on the AD bus

during a data phase is: AD[31:24] is Byte 3, AD[23:16] is Byte 2, AD[15:8] is Byte 1, and AD[7:0]

is Byte 0.

Byte swap only affects data transfers that involve the FIFOs. Initialization block transfers are not

affected by the setting of the BSWP bit. Descriptor transfers are not affected by the setting of the

BSWP bit. RDP, RAP, BDP and PCI configuration space accesses are not affected by the setting

of the BSWP bit. Address PROM transfers are not affected by the setting of the BSWP bit.

Expansion ROM accesses are not affected by the setting of the BSWP bit.

Note that the byte ordering of the PCI bus is defined to be little Endian. BSWP should not be set

to 1 when the Am79C976 controller is used in a PCI bus application.

This bit is an alias of CSR3, bit 2.

23:18 RES Reserved locations. Written as zeros and read as undefined.

17-16 SRAM_TYPE

SSRAM Type. This field must be set up to indicate the type of external SSRAM that is connected

to the external memory interface.

15-12 RES Reserved locations. Written as zeros and read as undefined.

SRAM_TYPE[1:0] External Memory Type

00 Reserved

01 ZBT

10 Reserved

11 Pipelined Burst

142 Am79C976 9/14/00

PRELIMINARY

CTRL1: Control1 Register

Offset 06Ch

This register contains several miscellaneous control

bits. Each byte of this register controls a single func-

tion. It is not necessary to do a read-modify-write oper-

ation to change a function’s settings if only a single byte

of the register is written.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits except for bits 17:16

(XMTSP) and bits 1:0 (RCVFW) is 0. The default value

for the XMTSP field is 01b (64 bytes). The default value

for the RCVFW field is also 01b.

Table 47. CTRL1: Control1 Register

11-8 ROMTMG

Expansion ROM Timing. The value of ROMTMG is used to tune the timing for all accesses to the

external Flash/EPROM.

ROMTMG defines the amount of time that a valid address is driven on the ERA[19:0] pins.

The register value specifies delay in number of ROMCLK cycles, where ROMCLK is an internal

clock signal that runs at one fourth the speed of ERCLK.

Note: Programming ROMTMG with a value of 0 is not permitted.

To ensure adequate expansion ROM setup time, ROMTMG should be set to 1 plus tACC /

(ROMCLK period), where tACC is the access time of the expansion ROM device (Flash or

EPROM). (The extra ROMCLK cycle is added to account for the ERA[19:0] output delay from

ROMCLK plus the ERD[7:0] setup time to ROMCLK.)

ROMTMG is set to the default value of 1001b by H_RESET. It is also set to its default value before

the EEPROM read process starts or when the EEPROM read process fails. The default value

allows using an Expansion ROM with an access time of 350 ns if ERCLK is running at 90 MHz.

This field is an alias of BCR18, bits 15:12.

7-5 RES Reserved locations. Written as zeros and read as undefined.

4 BURST_ALIGN PCI Bus Burst Align. When this bit is set, if a burst transfer starts in the middle of a cache line, the

transfer will stop at the first cache line boundary.

3-0 BURST_LIMIT

PCI Bus Burst Limit. This 4-bit field limits the maximum length of a burst transfer. If the contents

of this register are 0, the burst length is limited by the amount of data available or by the amount

of FIFO space available. If the contents of this field are not zero, a burst transfer will end when the

transfer has crossed the number of cache line boundaries equal to the contents of this field.

Bit Name Description

31-26 RES Reserved locations. Written as zeros and read as undefined.

25-24 SLOTMOD

Slot Time Modulation. This field determines the value of the slot time parameter used for the MAC

half-duplex backoff algorithm.

If SLOTMOD is set to anything other than the default value of 0, the controller will not conform to

IEEE Std 802.3.

23:18 RES Reserved locations. Written as zeros and read as undefined.

Value Slot Time (bits)

00 512 (standard)

01 256

10 1024

11 Reserved

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17-16 XMTSP

Transmit Start Point. XMTSP controls the point at which preamble transmission attempts to

commence in relation to the number of bytes written to the MAC Transmit FIFO for the current

transmit frame. When the entire frame is in the MAC Transmit FIFO, transmission will start

regardless of the value in XMTSP.

If any of REX_UFLO, REX_RTRY, or RTRY_LCOL are set, no frame data will be overwritten until

the frame has been transmitted or discarded. Otherwise, no data will be overwritten until at least

64 bytes have been transmitted.

Note that when the No Underflow (NOUFLO) bit (BCR18, bit 11) is set to 1 or XMTSP = 11b,

transmission will not start until the complete frame has been copied into the Transmit FIFO. This

mode is useful in a system where high latencies cannot be avoided.

The default value for XMTSP[1:0] is 01b (64 bytes).

This field is an alias of CSR80, bits 11:10.

15-10 RES Reserved locations. Written as zeros and read as undefined.

9-8 XMTFW

Transmit FIFO Watermark. XMTFW specifies the point at which transmit DMA is requested, based

upon the number of bytes that could be written to the Transmit FIFO without FIFO overflow.

Transmit DMA is requested when the number of bytes specified by XMTFW could be written to the

FIFO without causing Transmit FIFO overflow, and the internal state machine has reached a point

where the Transmit FIFO is checked to determine if DMA servicing is required.

The default value for XMTFW[1:0] is 00b (16 bytes).

This field is an alias of CSR80, bits 9:8.

Bit Name Description

XMTSP[1:0] NOUFLO Bytes Written

00 0 16

01 0 64

10 0 128

11 0 Full Frame

XX 1 Full Frame

XMTFW[1:0] Bytes Available

00 16

01 64

10 128

11 256

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7-2 RES Reserved locations. Written as zeros and read as undefined.

1-0 RCVFW

Receive FIFO Watermark. RCVFW controls the point at which receive DMA is requested in relation

to the number of received bytes in the Receive FIFO. RCVFW specifies the number of bytes which

must be present (once the frame has been verified as a non-runt) before receive DMA is requested.

Note, however, that if the network interface is operating in half-duplex mode, in order for receive

DMA to be performed for a new frame, at least 64 bytes must have been received. This effectively

avoids having to react to receive frames which are runts or suffer a collision during the slot time

(512 bit times). If the Runt Packet Accept feature is enabled or if the network interface is operating

in full-duplex mode, receive DMA will be requested as soon as either the RCVFW threshold is

reached, or a complete valid receive frame is detected (regardless of length). When the Full Duplex

Runt Packet Accept Disable (FDRPAD) bit in CMD2 is set and the Am79C976 controller is in full-

duplex mode, in order for receive DMA to be performed for a new frame, at least 64 bytes must

have been received. This effectively disables the runt packet accept feature in full-duplex mode.

The default value for RCVFW[1:0] is 01b (64 bytes).

This field is an alias of CSR80, bits 13:12.

Bit Name Description

RCVFW[1:0] Bytes Received

00 48

01 64

10 128

11 256

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CTRL2: Control2 Register

Offset 070h

This register contains several miscellaneous control

bits. Each byte of this register controls a single func-

tion. It is not necessary to do a read-modify-write oper-

ation to change a function’s settings if only a single byte

of the register is written.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits except for bits 2:0 (APDW)

is 0. The default value for the APDW field is 100b.

Table 48. CTRL2: Control2 Register

Bit Name Description

31-19 RES Reserved locations. Written as zeros and read as undefined.

18-16 FS

Force Speed. This three-bit field sets the MAC’s internal speed indicator according to the table

below. The speed indication is used only for LEDs.

15-10 RES Reserved locations. Written as zeros and read as undefined.

9-8 FMDC

Fast Management Data Clock. When FMDC is set to 2h the MII Management Data Clock will run

at 10 MHz max. The Management Data Clock will no longer be IEEE 802.3u-compliant and setting

this bit should be used with care. The accompanying external PHY must also be able to accept

management frames at the new clock rate. When FMDC is set to 1h, the MII Management Data

Clock will run at 5 MHz max. The Management Data Clock will no longer be IEEE 802.3u-compliant

and setting this bit should be used with care. The accompanying external PHY must also be able

to accept management frames at the new clock rate. When FMDC is set to 0h, the MII

Management Data Clock will run at 2.5 MHz max and will be fully compliant to IEEE 802.3u

standards.

This field is an alias of BCR32, bits13:12

7 RES Reserved location. Written as zero and read as undefined.

6 XPHYRST

External PHY Reset. When XPHYRST is set, the Am79C976 controller after an H_RESET or

S_RESET will issue an MII management frame that will reset the external PHY. This bit is needed

when there is no way to guarantee the state of the external PHY. This bit must be reprogrammed

after every H_RESET.

XPHYRST is only valid when the internal Network Port Manager is scanning for a network port.

This bit is an alias of BCR32, bit 6.

5 XPHYANE

External PHY Auto-Negotiation Enable. This bit will force the external PHY into enabling Auto-

Negotiation. When set to 0 the Am79C976 controller will send an MII management frame disabling

Auto-Negotiation.

XPHYANE is only valid when the internal Network Port Manager is scanning for a network port.

This bit is an alias of BCR32, bit 5.

4 XPHYFD

External PHY Full Duplex. When set, this bit will force the external PHY into full duplex when Auto-

Negotiation is not enabled.

XPHYFD is only valid when the internal Network Port Manager is scanning for a network port.

This bit is an alias of BCR32, bit 4.

FS[2:0] Speed

000 Speed determined by PHY

001 Reserved

010 10 Mb/s

011 100 Mb/s

1XX Reserved

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CTRL3: Control3 Register

Offset 074h

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits is 0.

Table 49. CTRL3: Control3 Register

3 XPHYSP

External PHY Speed. When set, this bit will force the external PHY into 100 Mbps mode when Auto-

Negotiation is not enabled.

XPHYSP is only valid when the internal Network Port Manager is scanning for a network port.

This bit is an alias of BCR32, bit 3.

2-0 APDW

MII Auto-Poll Dwell Time. APDW determines the dwell time between MII Management Frames

accesses when Auto-Poll is turned on. The MDC clock is ERCLK divided by 40 and will be slower

than 2.5MHz. The actual interval between polls will be the time shown in the following table

multiplied by 100 / (ERCLK frequency in MHz).

The default value of this field is 100b.

This field is an alias of BCR32, bits 10:8.

Bit Name Description

APDW Auto-Poll Dwell Time

000 Continuous (27µs @ 2.5 MHz)

001 Every 64 MDC cycles (77 µs @ 2.5 MHz)

010 Every 128 MDC cycles (129 µs @ 2.5 MHz)

011 Every 256 MDC cycles (232 µs @ 2.5 MHz)

100 Every 512 MDC cycles (436 µs @ 2.5 MHz)

101 Every 1024 MDC cycles (845 µs @ 2.5 MHz)

110-111 Reserved

Bit Name Description

31-8 RES Reserved locations. Written as zeros and read as undefined.

7-0 SWSTYLE

Software Style register. The value in this register determines the style of register and memory

resources that shall be used by the Am79C976 controller. The Software Style selection will affect

the interpretation of a few bits within the CSR space, the order of the descriptor entries, and the

width of the descriptors and initialization block entries.

All Am79C976 controller CSR bits and BCR bits and all descriptor, buffer, and initialization block

entries not cited in Table 50 are unaffected by the Software Style selection and are, therefore,

always fully functional as specified in the CSR and BCR sections.

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Table 50. Software Styles

DATAMBIST: Memory Built-in Self-Test Access

Offset 1A0h

This register is used to control and indirectly access the

Memory Built-in Self-Test (MBIST) logic that automati-

cally tests the external SSRAM.

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 51. DATAMBIST: Memory Built-in Self-Test Access Register

SWSTYLE

[7:0]

Style

Name SSIZE32 Initialization Block Entries Descriptor Ring Entries

00h LANCE/

PCnet-ISA controller 016-bit software structures,

non-burst or burst access

16-bit software structures, non-

burst access only

01h RES 1 RES RES

02h PCnet-PCI controller 1 32-bit software structures,

non-burst or burst access

32-bit software structures, non-

burst access only

03h PCnet-PCI

controller 132-bit software structures,

non-burst or burst access

32-bit software structures, non-

burst or burst access

04h VLAN 1 Not used 32-bit software structures, non-

burst or burst access

05h 64-bit address 1 Not used

32-bit software structures, 32-

byte descriptors, non-burst or

burst access

All Other Reserved Undefined Undefined Undefined

Bit Name Description

63 DM_DONE

MBIST done indicator. This bit is set to 1 when the automatic memory test has stopped, either

because the test has completed or because an error was detected. It is cleared to 0 when either

DM_START or DM_RESUME is set.

This bit is read-only.

62 DM_ERROR

MBIST error indicator. This bit is set to 1 when the memory test logic has detected a memory error.

It is cleared to 0 when either DM_START or DM_RESUME is set.

This bit is read-only.

61 DM_START

MBIST Start. Setting this bit to 1 resets the MBIST logic, including the DM_ERROR and

DM_TEST_FAIL bits, and starts the memory test process. DM_START should not be set at the

same time that the DM_RESUME bit is set.

DM_START is automatically cleared when the memory test stops. This bit is read/write.

60 DM_RESUME

MBIST Resume. Setting this bit to 1 restarts the memory test sequence at the point where it last

stopped. Setting this bit clears the DM_ERROR bit, but it does not clear the DM_TEST_FAIL bit.

This bit should not be set at the same time that the DM_START bit is set.

DM_RESUME is automatically cleared when the memory test stops. This bit is read/write.

59 DM_FAIL_STOP

MBIST Stop on Failure Control. When this bit is set to 1, the memory test will stop each time an

error is detected. When this bit is cleared to 0, the memory test will run to completion, regardless

of the number of errors that are detected.

This bit is read/write.

148 Am79C976 9/14/00

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58 DM_TEST_FAIL

MBIST Test Failure Indicator. This bit is set when a memory test error is detected. It is reset when

DM_START is set to 1. It is not cleared when DM_RESUME is set to 1.

This bit is read-only.

57 RES Reserved. Written as 0, read as undefined.

56 DM_DIR

MBIST Test Direction. This bit is set to 1 when the MBIST memory pointer was counting down

when the test stopped. It is cleared to 0 when the MBIST memory pointer was counting up when

the test stopped.

This bit is read-only.

55-54 DM_FAIL_STAT

MBIST Error Offset Indicator. This field indicates offset of the location of the last memory test error

with respect to the value of the DM_ADDR field. The interpretation of this field depends on the

value of the DM_DIR field, which indicates whether the address pointer was counting up or down

when the error was detected.

This field is read-only.

53-52 DM_BACKG

MBIST Background. This field contains the background pattern that the memory test logic was

using when the test stopped.

This field is read-only.

51-32 DM_ADDR

MBIST Address. This field contains the contents of the MBIST address pointer at the time that the

test stopped. Because of the pipelined nature of the external SSRAM, this value may not be the

location of the memory error. The actual error location is obtained by adding or subtracting the

contents of the DM_FAIL_STATE field as described above.

This field is read-only.

31-0 DM_DATA

MBIST Data. This field contains the last data that the memory test logic read from the external

SSRAM. If the DM_ERR and DM_FAIL_STOP bits are both set to 1, the contents of this field

contains an error.

This field is read-only.

Bit Name Description

DM_DIR FAIL_STATE Error Location

0 00 Error at DM_ADDRESS

0 01 Error at DM_ADDRESS-1

0 10 Error at DM_ADDRESS-2

0 11 Error at DM_ADDRESS-3

1 00 Error at DM_ADDRESS

1 01 Error at DM_ADDRESS+1

1 10 Error at DM_ADDRESS+2

1 11 Error at DM_ADDRESS+3

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Reerved Register

Offset 0C0h

The contents of this register are written as 0, and read

back as undefined.

Table 52. Reserved Register

Bit Name Description

31-21 RES Reserved. Written as 0, read as undefined.

20-16 RES Reserved. Written as 0, read as undefined.

15-11 RES Reserved. Written as 0, read as undefined.

10-0 RES Reserved. Written as 0, read as undefined.

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EEPROM_ACC: EEPROM Access Register

Offset 17Ch

The contents of this register are set to default values

when the RST pin is asserted. The register is not

cleared at the start of a serial EEPROM read operation

or after a serial EEPROM read error. The default value

for all bits in this register is 0.

This register is an alias of BCR19.

Table 53. EEPROM_ACC: EEPROM Access Register

Bit Name Description

15 PVALID

EEPROM Valid status bit. PVALID is read only; write operations have no effect. A value of 1 in this

bit indicates that a PREAD operation has occurred, and that (1) there is an EEPROM connected

to the Am79C976 controller interface pins and (2) the contents read from the EEPROM have

passed the CRC verification operation.

A value of 0 in this bit indicates a failure in reading the EEPROM. The CRC for the EEPROM is

incorrect or no EEPROM is connected to the interface pins.

PVALID is set to 0 during H_RESET. However, following the H_RESET operation, an automatic

read of the EEPROM will be performed. Just as is true for the normal PREAD command, at the end

of this automatic read operation, the PVALID bit may be set to 1. Therefore, H_RESET will set the

PVALID bit to 0 at first, but the automatic EEPROM read operation may later set PVALID to a 1.

If PVALID becomes 0 following an EEPROM read operation (either automatically generated after

H_RESET, or requested through PREAD), then all EEPROM-programmable registers will be reset

to their default values. The content of the Address PROM locations, however, will not be cleared.

If no EEPROM is present at the EESK, EEDI, and EEDO pins, then all attempted PREAD

commands will terminate early and PVALID will not be set. This applies to the automatic read of

the EEPROM after H_RESET, as well as to host-initiated PREAD commands.

14 PREAD

EEPROM Read command bit. When this bit is set to a 1 by the host, the PVALID bit (bit 15) will

immediately be reset to a 0, and then the Am79C976 controller will perform a read operation from

the external serial EEPROM. The EEPROM data that is fetched during the read will be stored in

the appropriate internal registers on board the Am79C976 controller. Upon completion of the

EEPROM read operation, the Am79C976 controller will assert the PVALID bit.

At the end of the read operation, the PREAD bit will automatically be reset to a 0 by the Am79C976

controller and PVALID will be set, provided that an EEPROM existed on the interface pins and that

the CRC for the EEPROM was correct.

Note that when PREAD is set to a 1, then the Am79C976 controller will no longer respond to any

accesses directed toward it until the PREAD operation has completed successfully. The

Am79C976 controller will terminate these accesses with the assertion of DEVSEL and STOP while

TRDY is not asserted, signaling to the initiator to disconnect and retry the access at a later time.

If a PREAD command is given to the Am79C976 controller but no EEPROM is attached to the

interface pins, the PREAD bit will be cleared to a 0, and the PVALID bit will remain reset with a

value of 0. This applies to the automatic read of the EEPROM after H_RESET as well as to host

initiated PREAD commands. All EEPROM programmable registers will be set to their default

values by such an aborted PREAD operation.

At the end of the read operation, if bit 15 of the PMC Alias register is zero or the VAUX_SENSE pin

is low, the PME_STATUS and PME_EN bits of the PMCSR register will be reset.

13 EEDET

EEPROM Detect. This bit indicates whether or not an EEPROM was detected by the ERPROM

read operation. If this bit is a 1, it indicates that an EEPROM was detected. If this bit is a 0, it

indicates that an EEPROM was not detected.

EEDET is read only; write operations have no effect. The value of this bit is determined at the end

of the H_RESET operation.

12-5 RES Reserved locations. Written as zeros and read as undefined.

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Table 54. Interface Pin Assignment

4 EEN

EEPROM Port Enable. When this bit is set to a 1, it causes the values of ECS, ESK, and EDI to be

driven onto the EECS, EESK, and EEDI pins, respectively. If EEN = 0 and no EEPROM read

function is currently active, then EECS will be driven LOW. When EEN = 0 and no EEPROM read

function is currently active, EESK and EEDI pins will be driven by the LED1 and LED0 functions,

respectively. See Table 54.

3 RES Reserved location. Written as 0; read as undefined.

2ECS

EEPROM Chip Select. This bit is used to control the value of the EECS pin of the interface when

the EEN bit is set to 1 and the PREAD bit is set to 0. If EEN = 1 and PREAD = 0 and ECS is set to

a 1, then the EECS pin will be forced to a HIGH level at the rising edge of the next clock following

bit programming.

If EEN = 1 and PREAD = 0 and ECS is set to a 0, then the EECS pin will be forced to a LOW level

at the rising edge of the next clock following bit programming. ECS has no effect on the output

value of the EECS pin unless the PREAD bit is set to 0 and the EEN bit is set to 1.

1 ESK

EEPROM Serial Clock. This bit and the EDI/EDO bit are used to control host access to the

EEPROM. Values programmed to this bit are placed onto the EESK pin at the rising edge of the

next clock following bit programming, except when the PREAD bit is set to 1 or the EEN bit is set

to 0. If both the ESK bit and the EDI/EDO bit values are changed during the same register write

operation, while EEN = 1, then setup and hold times of the EEDI pin value with respect to the EESK

signal edge are not guaranteed.

ESK has no effect on the EESK pin unless the PREAD bit is set to 0 and the EEN bit is set to 1.

0 EDI/EDO

EEPROM Data In/EEPROM Data Out. Data that is written to this bit will appear on the EEDI output

of the interface, except when the PREAD bit is set to 1 or the EEN bit is set to 0. Data that is read

from this bit reflects the value of the EEDO input of the interface.

EDI/EDO has no effect on the EEDI pin unless the PREAD bit is set to 0 and the EEN bit is set to 1.

Bit Name Description

RST Pin

PREAD or Auto

Read in Progress EEN EECS EESK EEDI

Low X X 0 Tri-State Tri-State

High 1 X Active Active Active

High 0 1 From ECS Bit From ESK Bit From EDI Bit

High 0 0 0 LED1 LED0

152 Am79C976 9/14/00

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FLASH_ADDR: Flash Address Register

Offset 198h

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 55. FLASH_ADDR: Flash Address Register

FLASH_DATA: Flash Data Register

Offset 19Ch

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

This register is an alias of BCR30.

Table 56. FLASH_DATA: Flash Data Register

Bit Name Description

31 LAAINC

Lower Address Auto Increment. When the LAAINC bit is set to 1, the low-order 16-bit portion of the

Flash Address Register will automatically increment by one after a read or write access to the Flash

Data Register. When the low-order 16-bit portion of the Flash Address reaches FFFFh and

LAAINC is set to 1, the low-order 16-bit portion of the Flash Address will roll over to 0000h. When

the LAAINC bit is set to 0, the Flash Address Register will not be affected in any way after an

access to the Flash Data Register.

This bit is an alias of BCR29, bit 14.

30-24 RES Reserved locations. Written as zeros and read as undefined.

23-0 FLASH_

ADDR

Flash Address. This field selects the byte of the external Flash/ROM device that will be accessed

when the Flash Data Register is accessed.

This field is an alias of BCR29, bits [7:0] concatenated with BCR28, bits [15:0].

Bit Name Description

15-8 RES Reserved locations. Written as zeros and read as undefined.

7-0 FLASH_DATA

Flash Data. This field contains data written to or read from the external Flash/ROM device. When

the host CPU writes to this register, the contents of this field are written to the external Flash device

at the location selected by the Flash Address Register. When the host CPU reads this register, the

Am79C976 device first reads the location in the Flash device selected by the Flash Address

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FLOW: Flow Control Register

Offset 0C8h

FLOW is a command-style register. All bits in this reg-

ister are cleared to 0 when the RST pin is asserted, be-

fore the serial EEPROM is read, and after a serial

EEPROM read error.

Table 57. FLOW: Flow Control Register

Bit Name Description

31-24 RES Reserved locations. Written as zeros and read as undefined.

23 VAL2 Value bit for byte 2. The value of this bit is written to any bits in the FLOW register that correspond

to bits in the FLOW[22:16] bit map field that are set to 1.

22-21 RES Reserved locations. Written as zeros and read as undefined.

20 FPA

Force Pause Ability. When this bit is set, Pause Ability is enabled regardless of the Pause Ability

state of the external PHY’s link partner. When Pause Ability is enabled, the receipt of a MAC

Control Pause Frame causes the device to stop transmitting for a time period that is determined by

the contents of the Pause Frame.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the

19 NPA

Negotiate Pause Ability. When this bit is set and the Force Pause Ability bit is not set, Pause Ability

is enabled only if the auto-negotiation process determines that the external PHY’s link partner

supports IEEE 802.3 flow control. When Pause Ability is enabled, the receipt of a MAC Control

Pause Frame causes the device to stop transmitting for a time period that is determined by the

contents of the Pause Frame.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the

18 FIXP

Fixed Length Pause. When this bit is set to 1, all MAC Control Pause Frames transmitted from the

device will contain a Request_operand field that is copied from the PAUSE_LEN field of this

When this bit is cleared to 0, a Pause Frame with its Request_operand field set to 0FFFFh will be

sent when the FCCMD bit in this register is changed from 0 to 1 or when the signal on the FC pin

changes from 0 to 1 while the FCPEN bit has the value 1. Also a Pause Frame with its

Request_operand field set to 0000h will be sent when the FCCMD bit in this register is changed

from 1 to 0 or when the signal on the FC pin changes from 1 to 0 while the FCPEN bit has the value

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the

17 FCPEN

Flow Control Pin Enable. When the value of this bit is 1, MAC Control Pause frames will be

transmitted or half-duplex back pressure will be applied when the FC pin is asserted. When the

value of this bit is 0, the state of the FC pin is ignored.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the

154 Am79C976 9/14/00

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IFS1: Inter-Frame Spacing Part 1 Register

Offset 18Ch

The contents of this register are set to 3ch when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 58. IFS1: Inter-Frame Spacing Part 1 Register

16 FCCMD Flow Control Command. In full-duplex mode this bit allows the host CPU to cause a Pause Frame

to be sent by issuing a single command. In half-duplex mode, setting this bit puts the device into

back-pressure mode, which has the effect of forcing the remote transmitter to delay transmissions

while the local system is freeing up congested resources.

If the device is operating in full-duplex mode and the value of the FIXP bit is 1, when FCCMD is

changed from 0 to 1, a Pause Frame is sent with its Request_operand field copied from the

PAUSE_LEN field of this register. After the Pause Frame is sent, the FCCMD bit is automatically

reset to 0.

If the device is operating in full-duplex mode and the value of the FIXP bit is 0, when FCCMD is

changed from 0 to 1, a Pause Frame is sent with its Request_operand field filled with all 1s, and

the FCCMD bit is not automatically reset to 0. When FCCMD is changed from 1 to 0, a Pause

Frame is sent with its Request_operand field filled with all 0s.

If the device is operating in half-duplex mode, setting FCCMD to 1 puts the MAC into back-pressure

mode. In back-pressure mode, whenever the MAC detects receiver activity, it transmits a series of

alternating 1s and 0s to force a collision.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the

15-0 PAUSE_LEN Pause Length. The contents of this field are copied into the Request_operand fields of MAC

Control Pause Frames that are transmitted while the FIXP bit in this register is set to 1.

Bit Name Description

7-0 IFS1

InterFrameSpacingPart1. Changing IFS1 allows the user to program the value of the InterFrame-

SpacePart1 timing. The Am79C976 controller sets the default value at 60 bit times (3ch). See the

subsection on Medium Allocation in the section Media Access Management for more details. The

equation for setting IFS1 when IPG ≥ 96 bit times is:

IFS1 = IPG - 36 bit times

IPG should be programmed to the nearest nibble. The two least significant bits are ignored. For

example, programming IPG to 63h has the same effect as programming it to 60h.

This register is an alias for CSR125, bits [7:0].

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INT0: Interrupt0

Offset 038h

INT0 identifies the source or sources of an interrupt.

With the exception of INTR, all bits in this register are

“write 1 to clear” so that the CPU can clear the interrupt

condition by reading the register and then writing back

the same data that it read. Writing a 0 to a bit in this reg-

ister has no effect.

All bits in this register are cleared to 0 by H_RESET. In

addition, TINT, TXDNINT, TXSTRTINT, and RINT are

cleared when the RUN bit in CMD0 is cleared.

Table 59. INT0: Interrupt0 Register

Bit Name Description

31 INTR

Interrupt Summary. This bit indicates that one or more of the other interrupt bits in this register are

set and the associated enable bit or bits in INTEN0 are also set. If INTREN in CMD0 is set to 1 and

INTR is set, INTA will be active. When INTR is set by SINT, INTA will be active independent of the

state of INEA.

INTR is read only. INTR is cleared by clearing all of the active individual interrupt bits that have not

been masked out.

31-28 RES Reserved locations. Written as zeros and read as undefined.

27 LCINT Link Change Interrupt. This bit is set when the Port Manager detects a change in the link status of

the external PHY.

26 APINT5 Auto-Poll Interrupt from Register 5. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 5.

25 APINT4 Auto-Poll Interrupt from Register 4. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 4.

24 APINT3 Auto-Poll Interrupt from Register 3. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 3.

23 RES Reserved locations. Written as zeros and read as undefined.

22 APINT2 Auto-Poll Interrupt from Register 2. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 2.

21 APINT1 Auto-Poll Interrupt from Register 1. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 1.

20 APINT0 Auto-Poll Interrupt from Register 0. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 0.

19 MIIPDTINT

MII PHY Detect Transition Interrupt. The MII PHY Detect Transition Interrupt is set by the

Am79C976 controller whenever the MIIPD bit in STAT0 transitions from 0 to 1 or vice versa.

This bit is an alias of CSR7, bit 1.

18 MCCIINT

MII Management Command Complete Internal Interrupt. The MII Management Command

Complete Interrupt is set by the Am79C976 controller when a read or write operation on the MII

management port is complete from an internal operation. Examples of internal operations are Auto-

Poll or Network Port Manager generated MII management frames.

This bit is an alias of CSR7, bit 3.

17 MCCINT

MII Management Command Complete Interrupt. The MII Management Command Complete

Interrupt is set by the Am79C976 controller when a read or write operation to the MII Data Port

(PHY Access Register) is complete.

This bit is an alias of CSR7, bit 5.

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16 MREINT

MII Management Read Error Interrupt. The MII Read Error interrupt is set by the Am79C976

controller to indicate that the currently read register from the external PHY is invalid. The contents

of the PHY Access Register are incorrect and that the operation should be performed again. The

indication of an incorrect read comes from the PHY. During the read turnaround time of the MII

management frame the external PHY should drive the MDIO pin to a LOW state. If this does not

happen, it indicates that the PHY and the Am79C976 controller have lost synchronization.

This bit is an alias of CSR7, bit 9

15 RES Reserved locations. Written as zeros and read as undefined.

14 SPNDINT Suspend Interrupt. This bit is set when a receiver or transmitter suspend operation has finished.

13 MPINT

Magic Packet Interrupt. Magic Packet Interrupt is set by the Am79C976 controller when the device

is in the Magic Packet mode and the Am79C976 controller receives a Magic Packet frame.

This bit is an alias of CSR5, bit 4.

12 SINT

System Interrupt is set by the Am79C976 controller when it detects a system error during a bus

master transfer on the PCI bus. System errors are data parity error, master abort, or a target abort.

The setting of SINT due to data parity error is not dependent on the setting of PERREN (PCI

Command register, bit 6).

Note that because INEA is cleared by the STOP reset generated by the system error, the system

interrupt bypasses the global interrupt enable bits INEA and INTREN. This means that if SINTEN

in INTEN0 or SINTE in CSR5 is set to 1, INTA will be asserted when SINT is 1 regardless of the

state of INEA and INTREN.

The state of SINT is not affected by clearing any of the PCI Status register bits that get set when a

data parity error (DATAPERR, bit 8), master abort (RMABORT, bit 13), or target abort (RTABORT,

bit 12) occurs.

This bit is an alias of CSR5, bit 11.

11-9 RES Reserved locations. Written as zeros and read as undefined.

8TINT

Transmit Interrupt is set by the Am79C976 controller after the OWN bit in the last descriptor of a

transmit frame has been cleared to indicate the frame has been copied to the transmit FIFO.

This bit is an alias of CSR0, bit 9.

7UINT

User Interrupt. UINT is set by the Am79C976 controller after the host has issued a user interrupt

command by setting UINTCMD in the CMD0 register.

This bit is an alias of CSR4, bit 6.

6 TXDNINT Transmission Done Interrupt. This bit is set when the transmitter has finished sending a frame. This

bit is included for debugging purposes.

5 TXSTRTINT

Transmit Start Interrupt. This bit is set when the transmitter begins the transmission of a frame. This

bit is included for debugging purposes.

This bit is an alias of CSR4, bit 3.

4STINT

Software Timer Interrupt. The Software Timer interrupt is set by the Am79C976 controller when the

Software Timer counts down to 0. The Software Timer will immediately load the contents of the

Software Timer Value Register, STVAL, into the Software Timer and begin counting down.

This bit is an alias of CSR7, bit 11.

3-1 RES Reserved locations. Written as zeros and read as undefined.

0RINT

Receive Interrupt is set by the Am79C976 controller after the last descriptor of a receive frame has

been updated by writing a 0 to the OWNership bit. RINT may also be set when the first descriptor

of a receive frame has been updated by writing a 0 to the OWNership bit if the LAPPEN bit in CMD2

has been set to a 1.

This bit is an alias of CSR0, bit 10.

Bit Name Description

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INTEN0: Interrupt0 Enable

Offset 040h

This register allows the software to specify which types

of interrupt events will cause the INTR bit in the

Interrupt0 register to be set, which in turn will cause

INTA pin to be asserted if the INTREN bit in CMD0 is

set. Each bit in this register corresponds to a bit in the

Interrupt0 register. Setting a bit in this register enables

the corresponding bit in the Interrupt0 register to cause

the INTR bit to be set.

INTEN0 is a command style register. The high order bit

of each byte of this register is a ’value’ bit that specifies

the value that will be written to selected bits of the reg-

ister. The seven low order bits of each byte make up a

bit map that selects which register bits will be altered.

All bits in this register are cleared to 0 by H_RESET. All

bits are also cleared before EEPROM data are loaded

or after an EEPROM read failure.

The RINTEN and TINTEN bits are set after S_RESET

(but not H_RESET).

Table 60. INTEN0: Interrupt0 Enable Register

Bit Name Description

31 VAL3 Value bit for byte 3. The value of this bit is written to any bits in the INTEN0 register that correspond

to bits in the INTEN0[30:24] bit map field that are set to 1.

30-28 RES Reserved locations. Written as zeros and read as undefined.

27 LCINTEN Link Change Interrupt Enable. When this bit is set, the INTR bit will be set when the LCINT bit in

INT0 is set.

26 APINT5EN Auto-Poll Interrupt from Register 5 Enable. When this bit is set, the INTR bit will be set when the

APINT5 bit in INT0 is set.

25 APINT4EN Auto-Poll Interrupt from Register 4 Enable. When this bit is set, the INTR bit will be set when the

APINT4 bit in INT0 is set.

24 APINT3EN Auto-Poll Interrupt from Register 3 Enable. When this bit is set, the INTR bit will be set when the

APINT3 bit in INT0 is set.

23 VAL2 Value bit for byte 2. The value of this bit is written to any bits in the INTEN0 register that correspond

to bits in the INTEN0[22:16] bit map field that are set to 1.

22 APINT2EN Auto-Poll Interrupt from Register 2 Enable. When this bit is set, the INTR bit will be set when the

APINT2 bit in INT0 is set.

21 APINT1EN Auto-Poll Interrupt from Register 1 Enable. When this bit is set, the INTR bit will be set when the

APINT1 bit in INT0 is set.

20 APINT0EN Auto-Poll Interrupt from Register 0 Enable. When this bit is set, the INTR bit will be set when the

APINT0 bit in INT0 is set.

19 MIIPDTINTEN

MII PHY Detect Transition Interrupt Enable. When this bit is set, the INTR bit will be set when the

MIIPDTINT bit in INT0 is set.

This bit is an alias of CSR7, bit 0.

18 MCCIINTEN

MII Management Command Complete Internal Interrupt Enable. When this bit is set, the INTR bit

will be set when the MCCIINT bit in INT0 is set.

This bit is an alias of CSR7, bit 2.

17 MCCINTEN

MII Management Command Complete Interrupt Enable. When this bit is set, the INTR bit will be

set when the MCCINT bit in INT0 is set.

This bit is an alias of CSR7, bit 4.

16 MREINTEN

MII Management Read Error Interrupt Enable. When this bit is set, the INTR bit will be set when

the MREINT bit in INT0 is set.

This bit is an alias of CSR7, bit 8

15 VAL1 Value bit for byte 1. The value of this bit is written to any bits in the INTEN0 register that correspond

to bits in the INTEN0[14:8] bit map field that are set to 1.

14 SPNDINTEN Suspend Interrupt Enable. When this bit is set, the INTR bit will be set when the SPNDINT bit in

INT0 is set.

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13 MPINTEN

Magic Packet Interrupt Enable. When this bit is set, the INTR bit will be set when the MPINT bit in

INT0 is set.

This bit is an alias of CSR5, bit 3.

12 SINTEN

System Interrupt Enable. When this bit is set, the INTR bit will be set when the SINT bit in INT0 is

set.

This bit is an alias of CSR5, bit 10.

11-9 RES Reserved locations. Written as zeros and read as undefined.

8TINTEN

Transmit Interrupt Enable. When this bit is set, the INTR bit will be set when the TINT bit in INT0 is

set.

This bit is an alias of CSR3, bit 9 with reversed polarity. (When TINTM in CSR3 is set, the transmit

interrupt is disabled.)

Previous devices in the PCnet family enable receive and transmit interrupts following reset. The

Am79C976 controller disables these interrupts following H_RESET (but not S_RESET). For

compatibility with legacy software, the Am79C976 controller will set RINTEN and TINTEN following

S_RESET. If, in addition, the user programs the EEPROM to load ones into RINTEN and TINTEN,

these interrupts will also be enabled after H_RESET. This matches the behavior of the previous

PCnet devices.

7VAL1

Value bit for byte 1. The value of this bit is written to any bits in the INTEN0 register that correspond

to bits in the INTEN0[6:0] bit map field that are set to 1.

6 TXDNINTEN

Transmission Done Interrupt Enable. When this bit is set, the INTR bit will be set when the

TXDNINT bit in INT0 is set.

This bit is an alias of CSR5, bit 12.

5 TXSTRTINTEN

Transmit Start Interrupt Enable. When this bit is set, the INTR bit will be set when the TXSTRTINT

bit in INT0 is set.

This bit is an alias of CSR4, bit 2.

4STINTEN

Software Timer Interrupt Enable. When this bit is set, the INTR bit will be set when the STINT bit

in INT0 is set.

This bit is an alias of CSR7, bit 10.

3-1 RES Reserved locations. Written as zeros and read as undefined.

0RINTEN

Receive Interrupt Enable. When this bit is set, the INTR bit will be set when the RINT bit in INT0 is

set.

This bit is an alias of CSR3, bit 10 with reversed polarity. (When RINTM in CSR3 is set, the receive

interrupt is disabled.)

Previous devices in the PCnet family enable receive and transmit interrupts following reset. The

Am79C976 controller disables these interrupts following H_RESET (but not S_RESET). For

compatibility with legacy software, the Am79C976 controller will set RINTEN and TINTEN following

S_RESET. If, in addition, the user programs the EEPROM to load ones into RINTEN and TINTEN,

these interrupts will also be enabled after H_RESET. This matches the behavior of the previous

PCnet devices.

Bit Name Description

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IPG: Inter-Packet Gap Register

Offset 18Dh

The contents of this register are set to 60h when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 61. IPG: Inter-Packet Gap Register

LADRF: Logical Address Filter Register

Offset 168h

The contents of this register are cleared to 0 when the

RST pin is asserted. This register is not cleared by the

serial EEPROM read operation or by a serial EEPROM

read error.

Table 62. Logical Address Filter Register

Bit Name Description

7-0 IPG

Inter Packet Gap. This value indicates the minimum number of network bit times after the end of a

frame that the transmitter will wait before it starts transmitting another frame. In half-duplex mode

the end of the frame is determined by CRS, while in full-duplex mode the end of the frame is

determined by TX_EN. The IPG value can be adjusted to compensate for delays through the

external PHY device.

IPG should be programmed to the nearest nibble. The two least significant bits are ignored. For

example, programming IPG to 63h has the same effect as programming it to 60h.

CAUTION: Use this parameter with care. By lowering the IPG below the IEEE 802.3 standard 96

bit times, the Am79C976 controller can interrupt normal network behavior.

This register is an alias for CSR125, bits [15:8].

Bit Name Description

63-0 LADRF

Logical Address Filter, LADRF[63:0]. This register contains a 64-bit mask that is used to accept

incoming logical (or multicast) addresses. If the first bit in the incoming address (as transmitted on

the wire) is a 1, the destination address is a logical address.

A logical address is passed through the CRC generator to produce a 32-bit result. The high order

6 bits of this result are used to select one of the 64-bit positions in the Logical Address Filter. If the

selected filter bit is set, the address is accepted, and the frame is copied into host system memory.

The Logical Address Filter is used in multicast addressing schemes. The acceptance of the

incoming frame based on the filter value indicates that the message may be intended for the node.

It is the responsibility of the host CPU to compare the destination address of the stored message

with a list of acceptable multicast addresses to determine whether or not the message is actually

intended for the node.

The contents of this register should be loaded from EEPROM. This register can also be loaded

from the initialization block after the INIT bit in CSR0 has been set. This register is an alias for

CSR8, CSR9, CSR10, and CSR11.

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LED0 Control Register

Offset 0E0h

This register controls the function(s) that the LED0 pin

displays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabled functions. This register de-

faults to Link Status (LNKST) with pulse stretcher en-

abled (PSE = 1) and is fully programmable.

All bits in this register are restored to their default val-

ues when the RST pin is asserted, before the serial

EEPROM is read, and after a serial EEPROM read er-

ror.

This register is an alias of BCR4.

Table 63. LED0 Control Register

Bit Name Description

15 LEDOUT

This bit indicates the current (non-stretched) value of the LED output pin. A value of 1 in this bit

indicates that the OR of the enabled signals is true.

The logical value of the LEDOUT status signal is determined by the settings of the individual Status

Enable bits of the LED register (bits 8 and 6-0).

14 LEDPOL

LED Polarity. When this bit has the value 0, then the LED pin will be driven to a LOW level

whenever the OR of the enabled signals is true, and the LED pin will be disabled and allowed to

float high whenever the OR of the enabled signals is false (i.e., the LED output will be an Open

Drain output and the output value will be the inverse of the LEDOUT status bit).

When this bit has the value 1, then the LED pin will be driven to a HIGH level whenever the OR of

the enabled signals is true, and the LED pin will be driven to a LOW level whenever the OR of the

enabled signals is false (i.e., the LED output will be a Totem Pole output and the output value will

be the same polarity as the LEDOUT status bit.).

The setting of this bit will not effect the polarity of the LEDOUT bit for this register.

The default value of this bit is 0.

13 LEDDIS

LED Disable. This bit is used to disable the LED output. When LEDDIS has the value 1, then the

LED output will always be disabled. When LEDDIS has the value 0, then the LED output value will

be governed by the LEDOUT and LEDPOL values.

The default value of this bit is 0.

12 100E

100 Mbps Enable. When this bit is set to 1, a value of 1 is passed to the LEDOUT bit in this register

when the Am79C976 controller is operating in 100 Mbps mode.

The default value of this bit is 0.

11-10 RES Reserved locations. Written and read as undefined.

9 MPSE

Magic Packet Status Enable. When this bit is set to 1, a value of 1 is passed to the LEDOUT bit in

this register when Magic Packet frame mode is enabled and a Magic Packet frame is detected on

the network.

The default value of this bit is 0.

8FDLSE

Full-Duplex Link Status Enable. Indicates the Full-Duplex Link Test Status. When this bit is set, a

value of 1 is passed to the LEDOUT signal when the Am79C976 controller is functioning in a Link

Pass state and full-duplex operation is enabled. When the Am79C976 controller is not functioning

in a Link Pass state with full-duplex operation being enabled, a value of 0 is passed to the LEDOUT

signal.

The default value of this bit is 0.

7 PSE

Pulse Stretcher Enable. When this bit is set, the LED illumination time is extended for each new

occurrence of the enabled function for this LED output. A value of 0 disables the pulse stretcher.

The default value of this bit is 1.

6 LNKSE

Link Status Enable. When this bit is set, a value of 1 will be passed to the LEDOUT bit in this

The default value of this bit is 1.

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LED1 Control Register

Offset 0E2h

This register controls the function(s) that the LED1 pin

displays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabled functions. This register de-

faults to transmit or receive activity (XMTE = 1 and

RCVE = 1) with pulse stretcher enabled (PSE = 1) and

is fully programmable.

All bits in this register are restored to their default val-

ues when the RST pin is asserted, before the serial

EEPROM is read, and after a serial EEPROM read er-

ror.

This register is an alias of BCR5.

The functions of the bits in this register are identical to

those of the LED0 Control Register, except that for this

PSE bits is 1, and the default value for all other bits is 0.

LED2 Control Register

Offset 0E4h

This register controls the function(s) that the LED2 pin

displays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabled functions. This register de-

faults to 100 Mb/s speed indication (100E = 1) with

pulse stretcher enabled (PSE = 1) and is fully program-

mable.

All bits in this register are restored to their default val-

ues when the RST pin is asserted, before the serial

EEPROM is read, and after a serial EEPROM read

error.

This register is an alias of BCR6.

The functions of the bits in this register are identical to

those of the LED0 Control Register, except that for this

1, and the default value for all other bits is 0.

LED3 Control Register

Offset 0E6h

This register controls the function(s) that the LED3 pin

displays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabled functions. This register de-

faults to collision indication (COLE = 1) with pulse

stretcher enabled (PSE = 1) and is fully programmable.

All bits in this register are restored to their default val-

ues when the RST pin is asserted, before the serial

EEPROM is read, and after a serial EEPROM read er-

ror.

This register is an alias of BCR7.

The functions of the bits in this register are identical to

those of the LED0 Control Register, except that for this

1, and the default value for all other bits is 0.

5 RCVME

Receive Match Status Enable. When this bit is set, a value of 1 is passed to the LEDOUT bit in this

for this node. All address matching modes are included: physical, logical filtering, broadcast and

promiscuous.

The default value of this bit is 0.

4XMTE

Transmit Status Enable. When this bit is set, a value of 1 is passed to the LEDOUT bit in this

The default value of this bit is 0.

3 RES Reserved location. Written and read as undefined.

2 RCVE

Receive Status Enable. When this bit is set, a value of 1 is passed to the LEDOUT bit in this register

when there is receive activity on the network.

The default value of this bit is 0.

1SFBDE

Start Frame/Byte Delimiter Enable. When this bit is set, a value of 1 is passed to the LEDOUT bit

in this register when the RXD[3:0] pins are presenting the least significant nibble of valid frame

data.

The default value of this bit is 0.

0COLE

Collision Status Enable. When this bit is set, a value of 1 is passed to the LEDOUT bit in this

The default value of this bit is 0.

Bit Name Description

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MAX_LAT_A: PCI Maximum Latency Alias Register

Offset 1B1h

This register is a writable alias of the Maximum Latency

field at offset 3Fh in PCI configuration space, which is

read only. The purpose of this register is to allow the

PCI Maximum Latency value to be loaded from the se-

rial EEPROM.

The contents of this register are set to 18h when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 64. MAX_LAT_A: PCI Maximum Latency Alias Register

MIN_GNT_A: PCI Minimum Grant Alias Register

Offset 1B0h

This register is a writable alias of the Minimum Grant

field at offset 3Eh in PCI configuration space, which is

read only. The purpose of this register is to allow the

PCI Minimum Grant value to be loaded from the serial

EEPROM.

The contents of this register are set to 18h when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 65. MIN_GNT_A: PCI Minimum Grant Alias Register

PADR: Physical Address Register

Offset 160h

The contents of this register are cleared to 0 when the

RST pin is asserted. This register is not cleared by the

serial EEPROM read operation or by a serial EEPROM

read error.

Bit Name Description

7-0 MAX_LAT

Maximum Latency. Specifies the maximum arbitration latency the Am79C976 controller can

sustain without causing problems to the network activity. The register value specifies the time in

units of 1/4 microseconds. MAX_LAT is aliased to the PCI configuration space register

MAX_LAT (offset 3Fh). The host will use the value in the register to determine the setting of the

Am79C976 Latency Timer register.

The default value for MAX_LAT is 18h which corresponds to 6 µs.

This register is an alias of BCR22, bits [15:8] and of offset 3Fh in PCI configuration space.

Bit Name Description

7-0 MIN_GNT

Minimum Grant. Specifies the minimum length of a burst period the Am79C976 controller needs to

keep up with the network activity. The length of the burst period is calculated assuming a clock rate

of 33 MHz. The register value specifies the time in units of 1/4 µs. MIN_GNT is aliased to the PCI

configuration space register MIN_GNT (offset 3Eh). The host will use the value in the register to

determine the setting of the Am79C976 Latency Timer register.

The default value for MIN_GNT is 18h which corresponds to 6 µs.

This register is an alias of BCR22, bits [7:0] and of offset 3Eh in PCI configuration space.

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Table 66. PADR: Physical Address Register

Pause Count Register

Offset 0DEh

All bits in this register are cleared to 0 when the RST

pin is asserted, before the serial EEPROM is read, and

after a serial EEPROM read error. This register is read-

only.

Table 67. PAUSE_CNT: Pause Count Register

PCIDATA0: PCI DATA Register Zero Alias Register

Offset 1BCh

This register contains the data that appears in the

DATA_SCALE field of the PCI Power Management

Control/Status Register (PMCSR) and the PCI Data

0. Since the DATA_SCALE and DATA fields in the con-

figuration space are read only, this register provides a

means of programming them indirectly, normally by

loading them from the serial EEPROM.

This register is an alias of BCR37.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 68. PCIDATA0: PCI DATA Register Zero Alias Register

PCIDATA1: PCI DATA Register One Alias Register

Offset 1BEh

This register is identical to the PCI Data Register Zero

Alias Register except that it contains the data that ap-

pears in the DATA_SCALE field of the PCI Power Man-

agement Control/Status Register (PMCSR) and the

PCI Data Register when the DATA_SEL field of

PMCSR is set to 1.

Bit Name Description

47-0 PADR

MAC Physical Address, PADR[47:0]. This register contains 48-bit, globally unique station address

assigned to this device. If the least significant bit of the first byte of a received frame is 0, the

destination address of the frame is a unicast address, which will be compared with the contents of

the PADR. If this bit is 0 and the frame’s destination address exactly matches the contents of PADR,

the frame is accepted and copied into the host system memory.

The byte order is such that PADR7[7:0] corresponds to the first address byte transferred over the

network.

Unicast address matching can be disabled by setting the Disable Receive Physical Address bit

(DCRVPA, bit 18 in CMD2). If DRCVPA is set to 1, a match of a frame’s destination address with

the contents of PADR will not cause the frame to be accepted and copied into the host memory.

The contents of this register should be loaded from EEPROM.

This register can also be loaded from the initialization block after the INIT bit in CSR0 has been set.

This register is an alias for CSR12, CSR13, and CSR14.

Bit Name Description

31-16 RES Reserved locations. Written as zeros and read as undefined

15-0 PAUSE_CNT Pause Count. This field indicates the pause time parameter that was contained in the

request_operand field of the most recently received MAC Control Pause frame.

Bit Name Description

15-10 RES Reserved locations. Written as zeros and read as undefined.

9-8 D0_SCALE

These bits correspond to the DATA_SCALE field of the PMCSR (offset Register 44 of the PCI

configuration space, bits 14-13). Refer to the description of DATA_SCALE for the meaning of this

field.

7-0 DATA0 These bits correspond to the PCI DATA register (offset Register 47 of the PCI configuration space,

bits 7-0). Refer to the description of DATA register for the meaning of this field.

164 Am79C976 9/14/00

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This register is an alias of BCR38.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

PCIDATA2: PCI DATA Register Two Alias Register

Offset 1C0h

This register is identical to the PCI Data Register Zero

Alias Register except that it contains the data that ap-

pears in the DATA_SCALE field of the PCI Power Man-

agement Control/Status Register (PMCSR) and the

PCI Data Register when the DATA_SEL field of

PMCSR is set to 2.

This register is an alias of BCR39.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

PCIDATA3: PCI DATA Register Three Alias Register

Offset 1C2h

This register is identical to the PCI Data Register Zero

Alias Register except that it contains the data that ap-

pears in the DATA_SCALE field of the PCI Power Man-

agement Control/Status Register (PMCSR) and the

PCI Data Register when the DATA_SEL field of

PMCSR is set to 3.

This register is an alias of BCR40.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

PCIDATA4: PCI DATA Register Four Alias Register

Offset 1C4h

This register is identical to the PCI Data Register Zero

Alias Register except that it contains the data that ap-

pears in the DATA_SCALE field of the PCI Power Man-

agement Control/Status Register (PMCSR) and the

PCI Data Register when the DATA_SEL field of

PMCSR is set to 4.

This register is an alias of BCR41.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

PCIDATA5: PCI DATA Register Five Alias Register

Offset 1C6h

This register is identical to the PCI Data Register Zero

Alias Register except that it contains the data that ap-

pears in the DATA_SCALE field of the PCI Power Man-

agement Control/Status Register (PMCSR) and the

PCI Data Register when the DATA_SEL field of

PMCSR is set to 5.

This register is an alias of BCR42.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

PCIDATA6: PCI DATA Register Six Alias Register

Offset 1C8h

This register is identical to the PCI Data Register Zero

Alias Register except that it contains the data that ap-

pears in the DATA_SCALE field of the PCI Power Man-

agement Control/Status Register (PMCSR) and the

PCI Data Register when the DATA_SEL field of

PMCSR is set to 6.

This register is an alias of BCR43.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

PCIDATA7: PCI DATA Register Seven Alias

Offset 1CAh

This register is identical to the PCI Data Register Zero

Alias Register except that it contains the data that ap-

pears in the DATA_SCALE field of the PCI Power Man-

agement Control/Status Register (PMCSR) and the

PCI Data Register when the DATA_SEL field of

PMCSR is set to 7.

This register is an alias of BCR44.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

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PHY Access Register

Offset 0D0h

This register gives the host CPU indirect access to the

MII Management Bus (MDC/MDIO). Through this reg-

ister the host CPU can read or write any external PHY

Bus.

All bits in this register are cleared to 0 when the RST

pin is asserted. This register is not affected by the serial

EEPROM read operation or by a serial EEPROM read

error.

Table 69. PHY_ACCESS: PHY Access Register

Bit Name Description

31 PHY_CMD_DONE

PHY Command Complete. This bit is cleared by writing a 1 to it. It is set at the end of the MII

Management Frame that is generated by setting any one of PHY_WR_CMD,

PHY_BLK_RD_CMD or PHY_NBLK_RD_CMD bits. When the value of this bit is 1 and the

previous operation was a read, the PHY_DATA field contains valid data.

30 PHY_WR_CMD

PHY Write Command. When this bit is set, an MII Management Frame will be sent to write the

contents of the PHY_DATA field to the external PHY register addressed by the PHY_ADDR

and PHY_REG_ADDR fields. This bit must not be set at the same time that the

PHY_BLK_RD_CMD bit or the PHY_NBLK_RD_CMD bit is set.

29 PHY_BLK_RD_CMD

PHY Blocking Read Command. When the bit is set, an MII Management Frame will be sent to

read the contents of the PHY_DATA field to the external PHY register addressed by the

PHY_ADDR and PHY_REG_ADDR fields. After this bit is set, the next attempt to read this

data read from the selected PHY register.

This bit must not be set at the same time that the PHY_WR_CMD bit or the

PHY_NBLK_RD_CMD bit is set.

28 PHY_NBLK_RD_CM

PHY Non-Blocking Read Command. When the bit is set, an MII Management Frame will be

sent to read the contents of the PHY_DATA field to the external PHY register addressed by the

PHY_ADDR and PHY_REG_ADDR fields. After this bit is set, the host CPU can read this

PHY_DATA field contains valid data read from the selected PHY register. Alternatively, the

host CPU can wait for the MCCINT interrupt (INT0, bit 17).

This bit must not be set at the same time that the PHY_WR_CMD bit or the

PHY_BLK_RD_CMD bit is set.

27 PHY_PRE_SUP

Preamble Suppression. If this bit is set, the MII Management Frame will be sent without a

preamble. Before setting this bit the host CPU must make sure that the external PHY

addressed by the PHY_ADDR field is capable of accepting MII Management Frames without

preambles.

26 RES Reserved location. Written as zero and read as undefined.

25-21 PHY_ADDR PHY Address. The address of the external PHY device to be accessed.

20-16 PHY_REG_ADDR PHY Register Address. The address of the register in the external PHY device to be accessed.

15-0 PHY_DATA

Data written or read from the external PHY register specified by the PHY_ADDR and

PHY_REG_ADDR. Data read from this field is valid only following a PHY register read when

PHY_CMD_DONE is 1. It is meaningless after a PHY register write.

166 Am79C976 9/14/00

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PMAT0: OnNow Pattern Register 0

Offset 190h

This register is used to control and indirectly access the

Pattern Match RAM (PMR). When the PMAT_MODE

bit (CMD7, bit3) is 1, Pattern Match logic is enabled. No

bus accesses into PMR are possible, and PMAT0 and

PMAT1 are ignored. When PMAT_MODE is set, a read

of PMAT0 or PMAT1 returns all undefined bits.

When the PMAT_MODE bit (CMD7, bit3) is 0, the Pat-

tern Match logic is disabled and accesses to the PMR

are possible. Bits 6-0 of PMAT0 specify the address of

the PMR word to be accessed. Following the write to

PMAT0, the PMR word may be read by reading PMAT1

and the high order bytes of PMAT0 in any order. To

write to PMR word, the write to PMAT0 must be fol-

lowed by a write to PMAT1 to complete the operation.

The RAM will not actually be written until the write to

PMAT1 is complete. The write to PMAT1 causes all 5

bytes (two bytes of PMAT1 and the upper three bytes

of PMAT0) to be written to whatever PMR word is ad-

dressed by bits 6:0 of PMAT0.

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 70. PMAT0: OnNow Pattern Register 0

PMAT1: OnNow Pattern Register 1

Offset 194h

This register is used to control and indirectly access the

Pattern Match RAM (PMR). When the PMAT_MODE

bit (CMD7, bit3) is 1, Pattern Match logic is enabled. No

bus accesses into PMR are possible, and PMAT0 and

PMAT1 are ignored. When PMAT_MODE is set, a read

of PMAT0 or PMAT1 returns all undefined bits.

When the PMAT_MODE bit (CMD7, bit3) is 0, the Pat-

tern Match logic is disabled and accesses to the PMR

are possible. Bits 6-0 of PMAT0 specify the address of

the PMR word to be accessed. Following the write to

PMAT0, the PMR word may be read by reading PMAT1

and the high order bytes of PMAT0 in any order. To

write to PMR word, the write to PMAT0 must be fol-

lowed by a write to PMAT1 to complete the operation.

The RAM will not actually be written until the write to

PMAT1 is complete. The write to PMAT1 causes all

5 bytes (two bytes of PMAT1 and the upper three bytes

of PMAT0) to be written to whatever PMR word is ad-

dressed by bits 6:0 of PMAT0.

The contents of this register are cleared to 0 when the

RST pin is asserted. The register is not cleared at the

start of a serial EEPROM read operation or after a se-

rial EEPROM read error.

Table 71. PMAT1: OnNow Pattern Register 1

Bit Name Description

31-24 PMR_B2 Pattern Match RAM Byte 2. This byte is written into or read from Byte 2 of the Pattern Match RAM.

This field is an alias of BCR46, bits [15:8].

23-16 PMR_B1 Pattern Match RAM Byte 1. This byte is written into or read from Byte 1 of the Pattern Match RAM.

This field is an alias of BCR46, bits [7:0].

15-8 PMR_B0 Pattern Match RAM Byte 0. This byte is written into or read from Byte 0 of the Pattern Match RAM.

This field is an alias of BCR45, bits [15:8].

7 RES Reserved location. Written as zero and read as undefined.

6-0 PMR_ADDR Pattern Match RAM Address. These bits are the Pattern Match RAM address to be written to or

read from.

Bit Name Description

15-8 PMR_B4 Pattern Match RAM Byte 4. This byte is written into or read from Byte 4 of the Pattern Match RAM.

This field is an alias of BCR47, bits [15:8].

7-0 PMR_B3 Pattern Match RAM Byte 3. This byte is written into or read from Byte 3 of the Pattern Match RAM.

This field is an alias of BCR47, bits [7:0].

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PMC_A: PCI Power Management Capabilities Alias

Offset 1B8h

This register is an alias of the PMC register located at

offset 42h of the PCI Configuration Space. Since the

PMC register is read only, this register provides a

means of programming it through the EEPROM. For

the definition of the bits in this register, refer to the PMC

The contents of this register are set to the default value

of 0C802h when the RST pin is asserted, before the se-

rial EEPROM is read, and after a serial EEPROM read

error.

Receive Protect Register

Offset 0DCh

The contents of this register are set to the default value

64 when the RST pin is asserted. This register is not af-

fected by the serial EEPROM read operation or by a

serial EEPROM read error.

Table 72. Receive Protect Register

RCV_RING_LEN: Receive Ring Length Register

Offset 150h

The contents of this register are set to the default value

0 when the RST pin is asserted. This register is not af-

fected by the serial EEPROM read operation or by a

serial EEPROM read error.

Table 73. RCV_RING_LEN: Receive Ring Length Register

Bit Name Description

15-0 RCV_

PROTECT

Receive Protect. This register indicates the number of bytes of an incoming frame that must be

received before the DMA controller starts to copy the frame data into the host system memory. If

the size of the frame (in bytes) is less than the contents of this register and the frame contains a

valid FCS, the DMA transfer can start any time after the end of the frame is received.

The Receive Protect Register also determines the period during which the External Address Reject

(EAR) pin is monitored when the External Address Detection Interface (EADI) is used. The state of

the EAR pin is ignored except for a period of time that starts when the Start of Frame Delimiter of

an incoming frame is received and ends when the number of frame data bytes indicated by the

Receive Protect Register have been received.

Bit Name Description

15-0 RCV_RING_

LEN

Receive Ring Length. Contains the two’s complement of the receive descriptor ring length. This

value in the RLEN field of the initialization block. However, this register can be manually altered.

The actual receive ring length is defined by the current value in this register. The ring length can

be defined as any value from 1 to 65535.

This register is an alias of CSR76.

168 Am79C976 9/14/00

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ROM_CFG: ROM Base Address Configuration

Offset 18Eh

This register, which should normally be loaded from the

serial EEPROM, determines which bits in the Expan-

sion ROM Base Address Register (ROMBASE) in PCI

Configuration Space can be altered by PCI Configura-

tion Space write accesses. Therefore this register indi-

rectly determines the amount of PCI memory space

that the Am79C976 device will claim for the PCI Expan-

sion ROM.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 74. ROM_CFG: ROM Base Address Configuration Register

SID_A: PCI Subsystem ID Alias Register

Offset 1B4h

This register is a writable alias of the Subsystem ID

field at offset 2Eh in PCI configuration space, which is

read only. The purpose of this register is to allow the

PCI Subsystem Vendor ID value to be loaded from the

serial EEPROM.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 75. SID_A: PCI Subsystem ID Alias Register

Bit Name Description

15-3 ROMBASE

[23:11]

This field contains write enable bits for bits [23:11] of the Expansion ROM Base Address Register

(ROMBASE) in PCI Configuration Space. If a bit in this field is set to 1, the corresponding bit in the

ROMBASE register can be written by PCI Configuration Space accesses. If a bit in this field is

cleared to 0, the corresponding bit in the ROMBASE register will be fixed at 0, and can not be

altered by PCI Configuration Space accesses.

Bits 15-3 of this field correspond to bits 23-11 of the ROMBASE register.

2-1 RES Reserved locations. Written as zeros; read as undefined.

0 ROMBASE[0]

This bit is the write enable bit for bit [0] of the Expansion ROM Base Address Register (ROMBASE)

in PCI Configuration Space. If this bit is set to 1, the Expansion ROM Enable bit in the ROMBASE

the Expansion ROM Enable bit in the ROMBASE register will be fixed at 0, and can not be altered

by PCI Configuration Space accesses.

This bit should be set to 1, normally by the EEPROM read operation, if an expansion ROM is

present in the system. It should be cleared to 0 (the default state) if there is no expansion ROM in

the system.

Bit Name Description

15-0 SID

Subsystem ID. SID is used together with SVID (BCR23, bits 15-0) to uniquely identify the add-in

board or subsystem the Am79C976 controller is used in. The value of SID is determined by the

system vendor. A value of 0 (the default) indicates that the Am79C976 controller does not support

subsystem identification.

This register is an alias of BCR24 and of the PCI configuration space Subsystem ID field at offset

2Eh.

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SRAM Boundary Register

Offset 17Ah

All bits in this register are cleared to 0 when the RST

pin is asserted, before the serial EEPROM is read, and

after a serial EEPROM read error.

Table 76. SRAM Boundary Register

SRAM Size Register

Offset 178h

All bits in this register are cleared to 0 when the RST

pin is asserted, before the serial EEPROM is read, and

after a serial EEPROM read error.

Table 77. SRAM Size Register

Bit Name Description

15-0 SRAM_BND

SRAM Boundary. Specifies the size of the transmit buffer portion of the SRAM in units of 512-byte

pages. For example, if SRAM_BND is set to 10, then 5120 bytes of the SRAM will be allocated for

the transmit buffer and the rest will be allocated for the receive buffer.

The transmit buffer in the SRAM begins at address 0 and ends at the address (SRAM_BND*512)-

1. Therefore, the receive buffer always begins on a 512-byte boundary.

SRAM_BND must be initialized to an appropriate value, either by the EEPROM or by the host CPU.

SRAM_BND must be set to a value less than or equal to IFFCh. Values larger than IFFCh will

cause incorrect behavior.

Note: The minimum allowed number of pages for normal network operation is four, and the

maximum is SRAM_SIZE - 4.

This register is an alias of BCR26.

Bit Name Description

15-0 SRAM_SIZE

SRAM Size. Specifies the total size of the SSRAM buffer in units of 512-byte pages. For example,

assume that the external memory consists of one 64K X 32 bit SSRAM, for a total of 256K bytes.

In this case SRAM_SIZE should be set to 512 (256K divided by 512).

This field must be initialized to the appropriate value, either by the EEPROM or by the host CPU.

SRAM_SIZE must be set to a value less than or equal to 2000h. Values larger than 2000h will

cause incorrect behavior.

Note: The minimum allowed number of pages is eight for normal network operation.

This register is an alias of BCR25.

170 Am79C976 9/14/00

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STAT0: Status0

Offset 030h

STAT0 indicates the status of various Am79C976 func-

tions. All bits in this register except for bits 12:10 indi-

cate current status and are read only. Bits 12:10 are

latches that indicate the cause of a wake-up event.

These three bits are cleared to 0 when power is first ap-

plied to the device (power-on reset), but they are not af-

fected by the state of the RST pin so that they are not

disturbed when PCI bus power is removed and reap-

plied. Bits 12:10 are “write 1 to clear”. Therefore, the

CPU can clear bits 12:10 by reading the register and

then writing back the same data that it read.

Table 78. STAT0: Status0 Register

Bit Name Description

31-15 RES Reserved locations. Written as zeros and read as undefined.

14 PAUSE_PEND

Pause Pending. This bit is set to 1 during the interval between the time that the Am79C976 device

receives a command to transmit a MAC Control Pause frame and the time that the device finishes

transmitting the frame. The host CPU should not attempt to write to the Pause Length Register

while this bit is 1.

This bit is read only and is cleared by H_RESET.

13 PAUSING

Pausing. This bit indicates that the device has received a MAC Control Pause frame, and the

pause timer has not yet timed out.

This bit is read only and is cleared by H_RESET.

12 PMAT_DET

Pattern Match Detected. This bit indicates that an OnNow pattern match has occurred while the

Am79C976 device was in the OnNow pattern match mode.

This bit is an alias of PMAT in CSR116.

This bit can be cleared to 0 either by writing 0 to CSR116, bit 7, or by writing 1 to STAT0, bit 12.

This bit is cleared to 0 when power is first applied to the device, but not by the assertion of RST.

11 MP_DET

Magic Packet Frame Detected. This bit indicates that a Magic Packet pattern match has occurred

while the Am79C976 device was in the Magic Packet mode.

This bit is an alias of MPMAT in CSR116.

This bit can be cleared to 0 either by writing 0 to CSR116, bit 5, or by writing 1 to STAT0, bit 11.

This bit is cleared to 0 when power is first applied to the device, but not by the assertion of RST.

10 LC_DET

Link Change Detected. This bit indicates that a change in the link status of the external PHY device

has been detected while the device was in the Link Change Wake-up mode.

This bit is an alias of LCDET in CSR116.

This bit can be cleared to 0 either by writing 1 to CSR116, bit 9, or by writing 1 to STAT0, bit 10.

This bit is cleared to 0 when power is first applied to the device, but not by the assertion of RST.

9-7 SPEED

Speed. This field indicates the bit rate at which the network is running. The following encoding is

used:

000 Unknown

001 Reserved

010 10 Mb/s

011 100 Mb/s

100-111 Reserved

These bits are read only and are cleared by H_RESET.

6 FULL_DPLX Full Duplex. This bit is set when the device is operating in full-duplex mode.

This bit is read only and is cleared by H_RESET.

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Software Timer Value Register

Offset 0D8h

The contents of this register are set to the default value

(0FFFFh) when the RST pin is asserted. This register

is not affected by the serial EEPROM read operation or

by a serial EEPROM read error.

Table 79. Software Timer Value Register

5 LINK_STAT

Link Status. This bit is set to the value of the Link Status bit in the status register (R1) of the default

external PHY. (The default external PHY is the PHY addressed by the AP_PHY0_ADDR field of

the AUTOPOLL0 Register.) This bit is updated each time the external PHY’s status register is read,

either by the Auto-Poll State Machine, by the Network Port Manager, or by a CPU-initiated read.

However, when the Force Link Status bit in CMD3 is set to 1, this bit is forced to 1, regardless of

the contents of the external PHY’s status register.

This bit is read only and is cleared by H_RESET.

4AUTONEG_

COMPLETE

Auto-negotiation Complete. This bit is set to the value of the Auto-Negotiation Complete bit in

This bit is read only and is cleared by H_RESET.

3 MIIPD

MII PHY Detect. MIIPD reflects the quiescent state of the MDIO pin. MIIPD is continuously updated

whenever there is no management operation in progress on the MII interface. When a

management operation begins on the interface, the state of MIIPD is preserved until the operation

ends, when the quiescent state is again monitored and continuously updates the MIIPD bit. When

the MDIO pin is at a quiescent LOW state, MIIPD is cleared to 0. When the MDIO pin is at a

quiescent HIGH state, MIIPD is set to 1. Any transition on the MIIPD bit will set the MIIPDTINT bit

in INT0.

This bit is an alias of BCR32, bit 14.

This bit is read only and is cleared by H_RESET.

2RX_

SUSPENDED

Receiver Suspended. This bit has the value 1 while the receiver is suspended, and it has the value

0 when the receiver is not suspended.

This bit is read only and is cleared by H_RESET.

1TX_

SUSPENDED

Transmitter Suspended. This bit has the value 1 while the transmitter is suspended, and it has the

value 0 when the transmitter is not suspended.

This bit is read only and is cleared by H_RESET.

0 RUNNING

This bit is a read-only alias of the RUN bit in CMD0. When this bit is set, the device is enabled to

transmit and receive frames and process descriptors. Note that even though RUNNING is set, the

receiver or transmitter might be disabled because RX_SPND or TX_SPND is set (in CMD0).

This bit is read only and is cleared by H_RESET.

Bit Name Description

15-0 STVAL

Software Timer Value. STVAL controls the maximum time for the Software Timer to count before

generating the STINT (CSR7, bit 11) interrupt. The Software Timer is a free-running timer that is

started upon the first write to STVAL. After the first write, the Software Timer will continually count

and set the STINT interrupt at the STVAL period.

The STVAL value is interpreted as an unsigned number with a resolution of 10.24µs. For instance,

if STVAL is set to 48,828 (0BEBCh), the Software Timer period will be 0.5 s. The default value

(0FFFFh) corresponds to 0.6710784 s.

Setting STVAL to a value of 0 will result in erratic behavior.

This register is an alias of BCR31.

172 Am79C976 9/14/00

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SVID_A: PCI Subsystem Vendor ID Alias Register

Offset 1B6h

This register is a writable alias of the Subsystem Ven-

dor ID field at offset 2Ch in PCI configuration space,

which is read only. The purpose of this register is to

allow the PCI Subsystem Vendor ID value to be loaded

from the serial EEPROM.

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 80. SVID: PCI Subsystem Vendor ID Shadow Register

TEST0: Test Register

Offset 1A8h

This register is used for factory test purposes only. All

bits must be zero for normal operation.

Table 81. TEST0: Test Register

Bit Name Description

15-0 SVID

Subsystem Vendor ID. SVID is used together with the PCI Subsystem ID Register to uniquely

identify the add-in board or subsystem the Am79C976 controller is used in. Subsystem Vendor IDs

can be obtained form the PCI SIG. A value of 0 (the default) indicates that the Am79C976 controller

does not support subsystem identification. SVID is aliased to the PCI configuration space register

Subsystem Vendor ID (offset 2Ch).

This register is an alias of BCR23 and of the PCI configuration space Subsystem Vendor

ID field at offset 2Ch.

Bit Name Description

31:18 RES Factory test bits; must be 0 for normal operation.

17 CBIO_EN Factory test bit; must be 0 for normal operation.

16:14 RES Factory test bits; must be 0 for normal operation.

13 EEBUSY_T Factory test bit; must be 0 for normal operation.

12 RES Factory test bit; must be 0 for normal operation.

11 TSEL Factory test bit; must be 0 for normal operation.

10 MFSM_RESET Factory test bit; must be 0 for normal operation.

9 BFD_SCALE_DOWN Factory test bit; must be 0 for normal operation.

8 ANTST Factory test bit; must be 0 for normal operation.

7:6 RES Factory test bits; must be 0 for normal operation.

5 LEDCHTTST Factory test bit; must be 0 for normal operation.

4 RTYTST_BUMP Factory test bit; must be 0 for normal operation.

3 RTYTST_OUT Factory test bit; must be 0 for normal operation.

2 RTYTST_RANGEN Factory test bit; must be 0 for normal operation.

1 RTYTST_SLOT Factory test bit; must be 0 for normal operation.

0 SERRLEVEL Factory test bit; must be 0 for normal operation.

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VID_A: PCI Vendor ID Alias Register

Offset 1B2h

This register is a writable alias of the Vendor ID field at

offset 0 in PCI configuration space, which is read only.

The purpose of this register is to allow the PCI Vendor

ID value to be loaded from the serial EEPROM.

The contents of this register are set to 1022h when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 82. VID_A: PCI Vendor ID Alias Register

XMT_RING_LEN: Transmit Ring Length Register

Offset 140h

The contents of this register are set to the default value

0 when the RST pin is asserted. This register is not af-

fected by the serial EEPROM read operation or by a

serial EEPROM read error.

Table 83. XMT_RING_LEN: Transmit Ring Length Register

XMTPOLLTIME: Transmit Poll Timer Register

Offset 188h

The contents of this register are cleared to 0 when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Bit Name Description

15-0 VID

Vendor ID. The PCI Vendor ID register is a 16-bit register that identifies the manufacturer of the

Am79C976 controller. AMD’s Vendor ID is 1022h. Note that this Vendor ID is not the same as the

Manufacturer ID in CSR88 and CSR89. The Vendor ID is assigned by the PCI Special Interest

Group.

The Vendor ID is not normally programmable, but the Am79C976 controller allows this due to

legacy operating systems that do not look at the PCI Subsystem Vendor ID and the Vendor ID to

uniquely identify the add-in board or subsystem that the Am79C976 controller is used in.

Note: If the operating system or the network operating system supports PCI Subsystem

Vendor ID and Subsystem ID, use those to identify the add-in board or subsystem and

program the VID with the default value of 1022h.

Software supplied by AMD may not operate if the VID is anything other than 1022h.

This register is an alias of the PCI configuration space Vendor ID field at offset 00h and of BCR35.

Bit Name Description

15-0 XMT_RING_

LEN

Transmit Ring Length. Contains the two's complement of the transmit descriptor ring length. This

value in the TLEN field of the initialization block. However, this register can be manually altered.

The actual transmit ring length is defined by the current value in this register. The ring length can

be defined as any value from 1 to 65535.

This register is an alias of CSR78.

174 Am79C976 9/14/00

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Table 84. XMTPOLLTIME: Transmit Polling Interval Register

RAP Register

The RAP (Register Address Pointer) register is used to

gain access to CSR and BCR registers on board the

Am79C976 controller. The RAP contains the address

of a CSR or BCR.

As an example of RAP use, consider a read access to

CSR4. In order to access this register, it is necessary

to first load the value 0004h into the RAP by performing

a write access to the RAP offset of 12h (12h when WIO

mode has been selected, 14h when DWIO mode has

been selected). Then a second access is performed,

this time to the RDP offset of 10h (for either WIO or

DWIO mode). The RDP access is a read access, and

since RAP has just been loaded with the value of 0004h,

the RDP read will yield the contents of CSR4. A read of

the BDP at this time (offset of 16h when WIO mode has

been selected, 1Ch when DWIO mode has been select-

ed) will yield the contents of BCR4, since the RAP is

used as the pointer into both BDP and RDP space.

RAP: Register Address Port

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 RES Reserved locations. Read and

written as zeros.

7-0 RAP Register Address Port. The value

of these 8 bits determines which

CSR or BCR will be accessed

when an I/O access to the RDP

or BDP port, respectively, is per-

formed.

A write access to undefined CSR

or BCR locations may cause un-

expected reprogramming of the

Am79C976 control registers. A

read access will yield undefined

values.

Read/Write accessible. RAP is

cleared by H_RESET or

S_RESET and is unaffected by

setting the STOP bit.

Bit Name Description

15-0 XMTPOLLTIME

Transmit Polling Interval. This register contains the time that the Am79C976 controller will wait

between successive polling operations. The XMTPOLLTIME value is expressed as the two’s

complement of the desired interval, where each bit of XMTPOLLTIME represents ERCLK clock

periods. XMTPOLLTIME[3:0] are ignored. (XMTPOLLTIME[16] is implied to be a one, so

XMTPOLLTIME[15] is significant and does not represent the sign of the two’s complement

XMTPOLLTIME value.)

The default value of this register is 0000h. This corresponds to a polling interval of 65,536 clock

periods (2.185 ms when ERCLK = 90 MHz).

Setting the INIT bit starts an initialization process that sets XMTPOLLTIME to its default value. If

the user wants to program a value for XMTPOLLTIME other than the default, then he must change

the value after the initialization sequence has completed.

This register is an alias for CSR47.

9/14/00 Am79C976 175

PRELIMINARY

Control and Status Registers

The Control and Status Registers (CSRs) are included

for compatibility with older PCnet Family software. All

CSR functions can be accessed more efficiently through

the memory-mapped registers.

The CSR space is accessible by performing accesses

to the RDP (Register Data Port). The particular CSR

that is read or written during an RDP access will de-

pend upon the current setting of the RAP. RAP serves

as a pointer into the CSR space.

Am79C976 CSRs can be accessed at any time. For

older PCnet family devices certain CSRs could only be

accessed when the device is stopped.

CSR0: Am79C976 Controller Status and Control

Certain bits in CSR0 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR0 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 ERR Obsolete function. Read/Write

accessible. Read returns zero.

14 BABL Obsolete function. Read/Write

accessible. Read returns zero.

13 CERR Obsolete function. Read/Write

accessible. Read returns zero.

12 MISS Obsolete function. Read/Write

accessible. Read returns zero.

11 MERR Obsolete function. Read/Write

accessible. Read returns zero.

10 RINT Receive Interrupt is set by the

Am79C976 controller after the

last descriptor of a receive frame

has been updated by writing a 0

to the OWNership bit. RINT may

also be set when the first descrip-

tor of a receive frame has been

updated by writing a 0 to the

OWNership bit if the LAPPEN bit

of CSR3 has been set to a 1.

When RINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

RINTM (CSR3, bit 10) is 0.

Read/Write accessible. RINT is

cleared by the host by writing a 1.

Writing a 0 has no effect. RINT is

cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

9 TINT Transmit Interrupt is set by the

Am79C976 controller after the

OWN bit in the last descriptor of a

transmit frame has been cleared

to indicate the frame has been

copied to the transmit FIFO.

When TINT is set, INTA is assert-

ed if IENA is 1 and the mask bit

TINTM (CSR3, bit 9) is 0.

Read/Write accessible. TINT is

cleared by the host by writing a 1.

Writing a 0 has no effect. TINT is

cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

8 IDON Initialization Done is set by the

Am79C976 controller after the

initialization sequence has com-

pleted. When IDON is set, the

Am79C976 controller has read

the initialization block from mem-

ory.

When IDON is set, INTA is as-

serted if IENA is 1 and the mask

bit IDONM (CSR3, bit 8) is 0.

Read/Write accessible. IDON is

cleared by the host by writing a 1.

Writing a 0 has no effect. IDON is

cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

7 INTR Interrupt Flag indicates that one

or more following interrupt caus-

ing conditions has occurred:

IDON, RINT, SINT, TINT, TX-

STRT, UINT, STINT, MREINT,

MCCINT, MCCIINT, MIIPDTINT,

MAPINT, MPINT, APINT, LCINT,

SPNDINT and the associated

mask or enable bit is pro-

grammed to allow the event to

cause an interrupt. If IENA is set

to 1 and INTR is set, INTA will be

active. When INTR is set by SINT

or SLPINT, INTA will be active in-

dependent of the state of IENA.

176 Am79C976 9/14/00

PRELIMINARY

INTR is read only. INTR is

cleared by clearing all of the ac-

tive individual interrupt bits that

have not been masked out.

6 IENA Interrupt Enable allows INTA to

be active if the Interrupt Flag is

set. If IENA = 0, then INTA will be

disabled regardless of the state

of INTR.

Read/Write accessible. IENA is

set by writing a 1 and cleared by

writing a 0. IENA is cleared by

H_RESET or S_RESET and set-

ting the STOP bit.

5 RXON Receive On indicates that the re-

ceive function is enabled. RXON

is set if DRX (CSR15, bit 0) is set

to 0 after the STRT bit is set. If

INIT and STRT are set together,

RXON will not be set until after

the initialization block has been

read in.

RXON is read only. RXON is

cleared by H_RESET or

S_RESET and setting the STOP

bit.

4 TXON Transmit On indicates that the

transmit function is enabled.

TXON is set if DTX (CSR15, bit 1)

is set to 0 after the STRT bit is

set. If INIT and STRT are set to-

gether, TXON will not be set until

after the initialization block has

been read in.

This bit will reset if the DXSUFLO

bit (CSR3, bit 6) is reset and there

is an underflow condition encoun-

tered.

TXON is read only. TXON is

cleared by H_RESET or

S_RESET and setting the STOP

bit.

3 TDMD Transmit Demand, when set,

causes the Buffer Management

Unit to access the Transmit De-

scriptor Ring without waiting for

the poll-time counter to elapse. If

TXON is not enabled, TDMD bit

will be reset and no Transmit De-

scriptor Ring access will occur.

TDMD is required to be set if the

TXDPOLL bit in CSR4 is set. Set-

ting TDMD while TXDPOLL = 0

merely hastens the Am79C976

controller’s next access to a

Transmit Descriptor Ring Entry.

Read/Write accessible. TDMD is

set by writing a 1. Writing a 0 has

no effect. TDMD will be cleared

by the Buffer Management Unit

when it fetches a Transmit De-

scriptor. TDMD is cleared by

H_RESET or S_RESET and set-

ting the STOP bit.

2 STOP STOP assertion disables the chip

from all DMA activity. The chip re-

mains inactive until either STRT

or INIT are set. If STOP, STRT

and INIT are all set together,

STOP will override STRT and

INIT.

Read/Write accessible. STOP is

set by writing a 1, by H_RESET

or S_RESET. Writing a 0 has no

effect. STOP is cleared by setting

either STRT or INIT.

1 STRT STRT assertion enables

Am79C976 controller to send and

receive frames, and perform buff-

er management operations. Set-

ting STRT clears the STOP bit. If

STRT and INIT are set together,

the Am79C976 controller initial-

ization will be performed first.

Read/Write accessible. STRT is

set by writing a 1. Writing a 0 has

no effect. STRT is cleared by

H_RESET, S_RESET, or by set-

ting the STOP bit.

0 INIT INIT assertion enables the

Am79C976 controller to begin the

initialization procedure which

reads in the initialization block

from memory. Setting INIT clears

the STOP bit. If STRT and INIT

are set together, the Am79C976

controller initialization will be per-

formed first. INIT is not cleared

when the initialization sequence

has completed.

Read/Write accessible. INIT is

set by writing a 1. Writing a 0 has

9/14/00 Am79C976 177

PRELIMINARY

no effect. INIT is cleared by

H_RESET, S_RESET, or by set-

ting the STOP bit.

CSR1: Initialization Block Address 0

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IADR[15:0] Lower 16 bits of the address of

the Initialization Block. Bit loca-

tions 1 and 0 must both be 0 to

align the initialization block to a

DWord boundary.

This register is aliased with

CSR16.

Read/Write accessible. Unaffect-

ed by H_RESET or S_RESET, or

by setting the STOP bit.

CSR2: Initialization Block Address 1

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 IADR[31:24] If SSIZE32 is set (BCR20, bit 8),

then the IADR[31:24] bits will be

used strictly as the upper 8 bits of

the initialization block address.

However, if SSIZE32 is reset

(BCR20, bit 8), then the

IADR[31:24] bits will be used to

generate the upper 8 bits of all

bus mastering addresses, as re-

quired for a 32-bit address bus.

Note that the 16-bit software

structures specified by the

SSIZE32 = 0 setting will yield

only 24 bits of address for the

Am79C976 bus master access-

es, while the 32-bit hardware for

which the Am79C976 controller is

intended will require 32 bits of ad-

dress. Therefore, whenever

SSIZE32 = 0, the IADR[31:24]

bits will be appended to the 24-bit

initialization address, to each 24-

bit descriptor base address and

to each beginning 24-bit buffer

address in order to form complete

32-bit addresses. The upper 8

bits that exist in the descriptor ad-

dress registers and the buffer ad-

dress registers which are stored

on board the Am79C976 control-

ler will be overwritten with the

IADR[31:24] value, so that CSR

accesses to these registers will

show the 32-bit address that in-

cludes the appended field.

If SSIZE32 = 1, then software will

provide 32-bit pointer values for

all of the shared software struc-

tures - i.e., descriptor bases and

buffer addresses, and therefore,

IADR[31:24] will not be written to

the upper 8 bits of any of these

resources, but it will be used as

the upper 8 bits of the initializa-

tion address.

This register is aliased with

CSR17.

Read/Write accessible. Unaffect-

ed by H_RESET, S_RESET, or

by setting the STOP bit.

7-0 IADR[23:16] Bits 23 through 16 of the address

of the Initialization Block. When-

ever this register is written,

CSR17 is updated with CSR2’s

contents.

Read/Write accessible Unaffect-

ed by H_RESET, S_RESET, or

by setting the STOP bit.

CSR3: Interrupt Masks and Deferral Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-13 RES Reserved locations. Read and

written as zero.

12 MISSM Obsolete function. Writing has no

effect. Read as undefined.

11 MERRM Obsolete function. Writing has no

effect. Read as undefined.

10 RINTM Receive Interrupt Mask. If RINTM

is set, the RINT bit will be masked

and unable to set the INTR bit.

Read/Write accessible. RINTM is

set by H_RESET but cleared by

S_RESET and is not affected by

STOP.

178 Am79C976 9/14/00

PRELIMINARY

9 TINTM Transmit Interrupt Mask. If

TINTM is set, the TINT bit will be

masked and unable to set the

INTR bit.

Read/Write accessible. TINTM is

set by H_RESET but cleared by

S_RESET and is not affected by

STOP.

8 IDONM Initialization Done Mask. If

IDONM is set, the IDON bit will be

masked and unable to set the

INTR bit.

Read/Write accessible. IDONM is

cleared by H_RESET or

S_RESET and is not affected by

STOP.

7 RES Reserved location. Read and

written as zeros.

6 DXSUFLO Obsolete function. Writing has no

effect. Read as undefined.

5 LAPPEN Look Ahead Packet Processing

Enable. When set to a 1, the

LAPPEN bit will cause the

Am79C976 controller to generate

an interrupt following the descrip-

tor write operation to the first buff-

er of a receive frame. This

interrupt will be generated in ad-

dition to the interrupt that is gen-

erated following the descriptor

write operation to the last buffer

of a receive packet. The interrupt

will be signaled through the RINT

bit of CSR0.

Setting LAPPEN to a 1 also en-

ables the Am79C976 controller to

read the STP bit of receive de-

scriptors. The Am79C976 con-

troller will use the STP

information to determine where it

should begin writing a receive

packet’s data. Note that while in

this mode, the Am79C976 con-

troller can write intermediate

packet data to buffers whose de-

scriptors do not contain STP bits

set to 1. Following the write to the

last descriptor used by a packet,

the Am79C976 controller will

scan through the next descriptor

entries to locate the next STP bit

that is set to a 1. The Am79C976

controller will begin writing the

next packets data to the buffer

pointed to by that descriptor.

Note that because several de-

scriptors may be allocated by the

host for each packet, and not all

messages may need all of the de-

scriptors that are allocated be-

tween descriptors that contain

STP = 1, then some descriptors/

buffers may be skipped in the

ring. While performing the search

for the next STP bit that is set to

1, the Am79C976 controller will

advance through the receive de-

scriptor ring regardless of the

state of ownership bits. If any of

the entries that are examined

during this search indicate

Am79C976 controller ownership

of the descriptor but also indicate

STP = 0, then the Am79C976

controller will reset the OWN bit

to 0 in these entries. If a scanned

entry indicates host ownership

with STP = 0, then the

Am79C976 controller will not al-

ter the entry, but will advance to

the next entry.

When the STP bit is found to be

true, but the descriptor that con-

tains this setting is not owned by

the Am79C976 controller, then

the Am79C976 controller will stop

advancing through the ring en-

tries and begin periodic polling of

this entry. When the STP bit is

found to be true, and the descrip-

tor that contains this setting is

owned by the Am79C976 control-

ler, then the Am79C976 control-

ler will stop advancing through

the ring entries, store the descrip-

tor information that it has just

read, and wait for the next re-

ceive to arrive.

This behavior allows the host

software to pre-assign buffer

space in such a manner that the

header portion of a receive pack-

et will always be written to a par-

ticular memory area, and the data

portion of a receive packet will al-

ways be written to a separate

memory area. The interrupt is

9/14/00 Am79C976 179

PRELIMINARY

generated when the header bytes

have been written to the header

memory area.

Read/Write accessible. The LAP-

PEN bit will be reset to 0 by

H_RESET or S_RESET and will

be unaffected by STOP.

See Appendix B for more infor-

mation on the Look Ahead Pack-

et Processing concept.

4 DXMT2PD Disable Transmit Two Part Defer-

ral (see Medium Allocation sec-

tion in the Media Access

Management section for more

details). If DXMT2PD is set,

Transmit Two Part Deferral will

be disabled.

Read/Write accessible.

DXMT2PD is cleared by

H_RESET or S_RESET and is

not affected by STOP.

3 EMBA Enable Modified Back-off Algo-

rithm (see Contention Resolution

section in Media Access Man-

agement section for more de-

tails). If EMBA is set, a modified

back-off algorithm is implement-

ed.

Read/Write accessible. EMBA is

cleared by H_RESET or

S_RESET and is not affected by

STOP.

2 BSWP Byte Swap. This bit is used to

choose between big and little En-

dian modes of operation. When

BSWP is set to a 1, big Endian

mode is selected. When BSWP is

set to 0, little Endian mode is se-

lected.

When big Endian mode is select-

ed, the Am79C976 controller will

swap the order of bytes on the AD

bus during a data phase on ac-

cesses to the FIFOs only. Specif-

ically, AD[31:24] becomes Byte

0, AD[23:16] becomes Byte 1,

AD[15:8] becomes Byte 2, and

AD[7:0] becomes Byte 3 when

big Endian mode is selected.

When little Endian mode is se-

lected, the order of bytes on the

AD bus during a data phase is:

AD[31:24] is Byte 3, AD[23:16] is

Byte 2, AD[15:8] is Byte 1, and

AD[7:0] is Byte 0.

Byte swap only affects data

transfers that involve the FIFOs.

Initialization block transfers are

not affected by the setting of the

BSWP bit. Descriptor transfers

are not affected by the setting of

the BSWP bit. RDP, RAP, BDP

and PCI configuration space ac-

cesses are not affected by the

setting of the BSWP bit. Address

PROM transfers are not affected

by the setting of the BSWP bit.

Expansion ROM accesses are

not affected by the setting of the

BSWP bit.

Note that the byte ordering of the

PCI bus is defined to be little En-

dian. BSWP should not be set to

1 when the Am79C976 controller

is used in a PCI bus application.

Read/Write accessible. BSWP is

cleared by H_RESET or

S_RESET and is not affected by

STOP.

1-0 RES Reserved locations. The values

written to these bits have no ef-

fect on the operation of the de-

vice. These bits should be read

as undefined.

CSR4: Test and Features Control

Certain bits in CSR4 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR4 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 RES Reserved location. The value

written to this bit has no effect on

the operation of the device. This

bit should be read as undefined.

14 DMAPLUS Writing and reading from this bit

has no effect. DMAPLUS is al-

ways 0.

180 Am79C976 9/14/00

PRELIMINARY

13 RES Reserved Location. Written as

zero and read as undefined.

12 TXDPOLL Disable Transmit Polling. If TXD-

POLL is set, the Buffer Manage-

ment Unit will disable transmit

polling. Likewise, if TXDPOLL is

cleared, automatic transmit poll-

ing is enabled. If TXDPOLL is set,

TDMD bit in CSR0 must be set in

order to initiate a manual poll of a

transmit descriptor. Transmit de-

scriptor polling will not take place

if TXON is reset. Transmit polling

will take place following Receive

activities.

Read/Write accessible. TXD-

POLL is cleared by H_RESET or

S_RESET and is unaffected by

the STOP bit.

11 APAD_XMT Auto Pad Transmit. When set,

APAD_XMT enables the auto-

matic padding feature. Transmit

frames will be padded to extend

them to 64 bytes including FCS.

The FCS is calculated for the en-

tire frame, including pad, and ap-

pended after the pad field. When

the auto padding logic modifies a

frame, a valid FCS field will be

appended to the frame, regard-

less of the state of the DXMTFCS

bit (CSR15, bit 3) and of the

ADD_FCS bit in the transmit de-

scriptor.

Read/Write accessible.

APAD_XMT is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

10 ASTRP_RCVAuto Strip Receive. When set,

ASTRP_RCV enables the auto-

matic pad stripping feature. The

pad and FCS fields will be

stripped from receive frames and

not placed in the FIFO.

Read/Write accessible.

ASTRP_RCV is cleared by

H_RESET or S_RESET and is

unaffected by the STOP bit.

9 MFCO Obsolete function. Writing has no

effect. Read as undefined.

8 MFCOM Obsolete function. Writing has no

effect. Read as undefined.

7 UINTCMD User Interrupt Command.

UINTCMD can be used by the

host to generate an interrupt un

related to any network activity.

Writing a 1 to this bit causes

UINT to be set to 1, which in turn

causes INTA to be asserted if in-

terrupts are enabled.

Read/Write accessible. UINTC-

MD is always read as 0.

6 UINT User Interrupt. UINT is set by the

Am79C976 controller after the

host has issued a user interrupt

command by setting UINTCMD

(CSR4, bit 7) to 1.

Read/Write accessible. UINT is

cleared by the host by writing a 1.

Writing a 0 has no effect. UINT is

cleared by H_RESET or

S_RESET or by setting the STOP

bit.

5 RCVCCO Obsolete function. Writing has no

effect. Read as undefined.

4 RCVCCOM Obsolete function. Writing has no

effect. Read as undefined.

3 TXSTRT Transmit Start status is set by the

Am79C976 controller whenever it

begins transmission of a frame.

When TXSTRT is set, INTA is as-

serted if IENA is 1 and the mask

bit TXSTRTM is 0.

Read/Write accessible. TXSTRT

is cleared by the host by writing a

1. Writing a 0 has no effect. TX-

STRT is cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

2 TXSTRTM Transmit Start Mask. If TX-

STRTM is set, the TXSTRT bit

will be masked and unable to set

the INTR bit.

Read/Write accessible. TX-

STRTM is set to 1 by H_RESET

or S_RESET and is not affected

by the STOP bit.

9/14/00 Am79C976 181

PRELIMINARY

1-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR5: Extended Control and Interrupt 1

Certain bits in CSR5 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR5 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 TOKINTD Obsolete function. Writing has no

effect. Read as undefined.

14 LTINTEN Last Transmit Interrupt Enable.

When this bit is set to 1, the

LTINT bit in transmit descriptors

can be used to determine when

transmit interrupts occur. The

Transmit Interrupt (TINT) bit will

be set after a frame has been

copied to the Transmit FIFO if the

LTINT bit in the frame’s last

transmit descriptor is set. If the

LTINT bit in the frame’s last de-

scriptor is 0 TINT will not be set

after the frame has been copied

to the Transmit FIFO.

Read/Write accessible. LTINTEN

is cleared by H_RESET or

S_RESET and is unaffected by

STOP.

13 TXDNINT Transmission Done Interrupt.

This bit is set when the transmit-

ter has finished sending a frame.

This bit is included for debugging

purposes.

Read/Write accessible. TXDN-

INT is cleared by the host by writ-

ing a 1. Writing a 0 has no effect.

The state of TXDNINT is not af-

fected by clearing any of the PCI

Status register bits that get set

when a data parity error

(DATAPERR, bit 8), master abort

(RMABORT, bit 13), or target

abort (RTABORT, bit 12) occurs.

TXDNINT is cleared by

H_RESET, S_RESET, or by set-

ting the STOP bit.

12 TXDNINTENTransmission Done Interrupt En-

able. When this bit is set, the

INTR bit will be set when the

TXDNINT bit in INT0 is set.

Read/Write accessible. TXDN-

INTEN is cleared by H_RESET or

S_RESET and is unaffected by

STOP.

11 SINT System Interrupt is set by the

Am79C976 controller when it de-

tects a system error during a bus

master transfer on the PCI bus.

System errors are data parity er-

ror, master abort, or a target

abort. The setting of SINT due to

data parity error is not dependent

on the setting of PERREN (PCI

Command register, bit 6).

When SINT is set, INTA is assert-

ed if the enable bit SINTE is 1.

Note that the assertion of an in-

terrupt due to SINT is not depen-

dent on the state of the INEA bit,

since INEA is cleared by the

STOP reset generated by the

system error.

Read/Write accessible. SINT is

cleared by the host by writing a 1.

Writing a 0 has no effect. The

state of SINT is not affected by

clearing any of the PCI Status

data parity error (DATAPERR, bit

8), master abort (RMABORT, bit

13), or target abort (RTABORT,

bit 12) occurs. SINT is cleared by

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

10 SINTE System Interrupt Enable. If SIN-

TE is set, the SINT bit will be able

to set the INTR bit.

Read/Write accessible. SINTE is

set to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

9-8 RES Reserved locations. Written as

zeros and read as undefined.

7 EXDINT Obsolete function. Writing has no

effect. Read as undefined.

182 Am79C976 9/14/00

PRELIMINARY

6 EXDINTE Obsolete function. Writing has no

effect. Read as undefined.

5 MPPLBA Magic Packet Physical Logical

Broadcast Accept. If MPPLBA is

at its default value of 0, the

Am79C976 controller will only de-

tect a Magic Packet frame if the

destination address of the packet

matches the content of the physi-

cal address register (PADR). If

MPPLBA is set to 1, the destina-

tion address of the Magic Packet

frame can be unicast, multicast,

or broadcast. Note that the set-

ting of MPPLBA only affects the

address detection of the Magic

Packet frame. The Magic Packet

frame’s data sequence must be

made up of 16 consecutive phys-

ical addresses (PADR[47:0]) re-

gardless of what kind of

destination address it has. This

bit is OR’ed with EMPPLBA bit

(CSR116, bit 6).

Read/Write accessible. MPPLBA

is set to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

4 MPINT Magic Packet Interrupt. Magic

Packet Interrupt is set by the

Am79C976 controller when the

device is in the Magic Packet

mode and the Am79C976 con-

troller receives a Magic Packet

frame. When MPINT is set to 1,

INTA is asserted if IENA (CSR0,

bit 6) and the enable bit MPINTE

are set to 1.

Read/Write accessible. MPINT is

cleared by the host by writing a 1.

Writing a 0 has no affect. MPINT

is cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

3 MPINTE Magic Packet Interrupt Enable. If

MPINTE is set to 1, the MPINT bit

will be able to set the INTR bit.

Read/Write accessible. MPINTE

is cleared to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

2 MPEN Magic Packet Enable. MPEN al-

lows activation of the Magic

Packet mode by the host. The

Am79C976 controller will enter

the Magic Packet mode when

both MPEN and MPMODE are

set to 1.

Read/Write accessible. MPEN is

cleared to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

1 MPMODE The Am79C976 controller will en-

ter the Magic Packet mode when

MPMODE is set to 1 and either

PG is asserted or MPEN is set

to 1.

Read/Write accessible. MP-

MODE is cleared to 0 by

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

0 SPND Suspend. Setting SPND to 1 will

cause the Am79C976 controller

to start requesting entrance into

suspend mode. The host must

poll SPND until it reads back 1 to

determine that the Am79C976

controller has entered the sus-

pend mode. Setting SPND to 0

will get the Am79C976 controller

out of suspend mode. SPND can

only be set to 1 if STOP (CSR0,

bit 2) is set to 0. H_RESET,

S_RESET or setting the STOP bit

will get the Am79C976 controller

out of suspend mode.

Requesting entrance into the

suspend mode by the host de-

pends on the setting of the

FASTSPNDE bit (CSR7, bit 15).

Refer to the bit description of the

FASTSPNDE bit and the Sus-

pend section in Detailed Func-

tions, Buffer Management Unit

for details.

In suspend mode, all of the CSR

and BCR registers are accessi-

ble. As long as the Am79C976

controller is not reset while in

suspend mode (by H_RESET,

S_RESET or by setting the STOP

bit), no re-initialization of the de-

vice is required after the device

9/14/00 Am79C976 183

PRELIMINARY

comes out of suspend mode. The

Am79C976 controller will contin-

ue at the transmit and receive de-

scriptor ring locations, from

where it had left, when it entered

the suspend mode.

Read/Write accessible. SPND is

cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR6: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR7: Extended Control and Interrupt 2

Certain bits in CSR7 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR7 and write back

the value just read to clear the interrupt condition.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 FASTSPNDE

Fast Suspend Enable. When

FASTSPNDE is set to 1, the

Am79C976 controller performs a

fast suspend whenever the

SPND bit is set.

When a fast suspend is request-

ed, the Am79C976 controller per-

forms a quick entry into the

suspend mode. At the time the

SPND bit is set, the Am79C976

controller will complete the DMA

process of any transmit and/or re-

ceive packet that had already be-

gun DMA activity. In addition, any

transmit packet that had started

transmission will be fully transmit-

ted and any receive packet that

had begun reception will be fully

received. However, no additional

packets will be transmitted or re-

ceived and no additional transmit

or receive DMA activity will begin.

Hence, the Am79C976 controller

may enter the suspend mode

with transmit and/or receive

packets still in the FIFOs or the

SRAM.

When FASTSPNDE is 0 and the

SPND bit is set, the Am79C976

controller may take longer before

entering the suspend mode. At

the time the SPND bit is set, the

Am79C976 controller will com-

plete the DMA process of a trans-

mit packet if it had already begun

and the Am79C976 controller will

completely receive a receive

packet if it had already begun.

Additionally, all transmit packets

stored in the transmit FIFOs and

the transmit buffer area in the

SRAM (if one is enabled) will be

transmitted and all receive pack-

ets stored in the receive FIFOs,

and the receive buffer area in the

SRAM (if one is enabled) will be

transferred into system memory.

Since the FIFO and SRAM con-

tents are flushed, it may take

much longer before the

Am79C976 controller enters the

suspend mode. The amount of

time that it takes depends on

many factors including the size of

the SRAM, bus latency, and net-

work traffic level.

When a write to CSR5 is per-

formed with bit 0 (SPND) set to 1,

the value that is simultaneously

written to FASTSPNDE is used to

determine which approach is

used to enter suspend mode.

Read/Write accessible. FASTSP-

NDE is cleared by H_RESET,

S_RESET or by setting the STOP

bit.

14 RES Reserved location. Written as ze-

ro, read as undefined.

13 RDMD Receive Demand, when set,

causes the Buffer Management

Unit to access the Receive De-

scriptor Ring without waiting for

the chain poll-time counter to ex-

pire.

Read/Write accessible. RDMD is

set by writing a 1. Writing a 0 has

no effect. RDMD will be cleared

by the Buffer Management Unit

184 Am79C976 9/14/00

PRELIMINARY

when it fetches a receive De-

scriptor. RDMD is cleared by

H_RESET or by S_RESET.

RDMD is unaffected by setting

the STOP bit.

12 CHDPOLL Disable Chain Polling. If CHD-

POLL is set, the Buffer Manage-

ment Unit will disable chain

polling. Likewise, if CHDPOLL is

cleared, automatic chain polling

is enabled. If CHDPOLL is set and

the Buffer Management Unit is in the

middle of a buffer-changing opera-

tion, setting the RDMD bit in CMD0 or

CSR7 will cause a poll of the current

receive descriptor, and setting the

TDMD bit in CMD0 or CSR0 will

cause a poll of the current transmit

descriptor. If CHDPOLL is set, the

RDMD bit in CSR7 can be set to

initiate a manual poll of a receive

or transmit descriptor if the Buffer

Management Unit is in the middle

of a buffer-chaining operation.

Read/Write accessible. CHD-

POLL is cleared by H_RESET.

CHDPOLL is unaffected by

S_RESET or by setting the STOP

bit.

11 STINT Software Timer Interrupt. The

Software Timer interrupt is set by

the Am79C976 controller when

the Software Timer counts down

to 0. The Software Timer will im-

mediately load the STVAL (BCR

31, bits 5-0) into the Software

Timer and begin counting down.

When STINT is set to 1, INTA is

asserted if the enable bit STINTE

is set to 1.

Read/Write accessible. STINT is

cleared by the host by writing a 1.

Writing a 0 has no effect. STINT

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

10 STINTE Software Timer Interrupt Enable.

If STINTE is set, the STINT bit

will be able to set the INTR bit.

Read/Write accessible. STINTE

is set to 0 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

9 MREINT MII Management Read Error In-

terrupt. The MII Read Error inter-

rupt is set by the Am79C976

controller to indicate that the cur-

rently read register from the ex-

ternal PHY is invalid. The

contents of BCR34 are incorrect

and that the operation should be

performed again. The indication

of an incorrect read comes from

the PHY. During the read turn-

around time of the MII manage-

ment frame the external PHY

should drive the MDIO pin to a

LOW state. If this does not hap-

pen, it indicates that the PHY and

the Am79C976 controller have

lost synchronization.

When MREINT is set to 1, INTA is

asserted if the enable bit MREIN-

TE is set to 1.

Read/Write accessible. MREINT

is cleared by the host by writing a

1. Writing a 0 has no effect. MRE-

INT is cleared by H_RESET and

is not affected by S_RESET or

setting the STOP bit.

8 MREINTE MII Management Read Error In-

terrupt Enable. If MREINTE is

set, the MREINT bit will be able to

set the INTR bit.

Read/Write accessible. MREIN-

TE is set to 0 by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit

7 MAPINT MII Management Auto-Poll Inter-

rupt. This bit is set when the

Auto-Poll State Machine detects

a change in any PHY register that

is polled by the Auto-Poll State

Machine.

When MAPINT is set to 1, INTA is

asserted if the enable bit MAP-

INTE is set to 1.

Read/Write accessible. MAPINT

is cleared by the host by writing a

1. Writing a 0 has no effect. MAP-

INT is cleared by H_RESET and

9/14/00 Am79C976 185

PRELIMINARY

is not affected by S_RESET or

setting the STOP bit.

6 MAPINTE MII Auto-Poll Interrupt Enable. If

MAPINTE is set, the MAPINT bit

will be able to set the INTR bit.

Read/Write accessible. MAP-

INTE is set to 0 by H_RESET and

is not affected by S_RESET or

setting the STOP bit

5 MCCINT MII Management Command

Complete Interrupt. The MII Man-

agement Command Complete In-

terrupt is set by the Am79C976

controller when a read or write

operation to the MII Data Port

(BCR34) is complete.

When MCCINT is set to 1, INTA

is asserted if the enable bit

MCCINTE is set to 1.

Read/Write accessible. MCCINT

is cleared by the host by writing a

1. Writing a 0 has no effect.

MCCINT is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

4 MCCINTE MII Management Command

Complete Interrupt Enable. If

MCCINTE is set to 1, the

MCCINT bit will be able to set the

INTR bit when the host reads or

writes to the MII Data Port

(BCR34) only. Internal MII Man-

agement Commands will not gen-

erate an interrupt. For instance,

Auto-Poll state machine generat-

ed MII management frames will

not generate an interrupt upon

completion unless there is a com-

pare error which gets reported

through the MAPINT (CSR7, bit

6) interrupt or the MCCIINTE is

set to 1.

Read/Write accessible. MC-

CINTE is set to 0 by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

3 MCCIINT MII Management Command

Complete Internal Interrupt. The

MII Management Command

Complete Interrupt is set by the

Am79C976 controller when a

read or write operation on the MII

management port is complete

from an internal operation. Exam-

ples of internal operations are

Auto-Poll or MII Management

Port generated MII management

frames. These are normally hid-

den to the host.

When MCCIINT is set to 1, INTA

is asserted if the enable bit

MCCINTE is set to 1.

Read/Write accessible. MCCIINT

is cleared by the host by writing a

1. Writing a 0 has no effect.

MCCIINT is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

2 MCCIINTE MII Management Command

Complete Internal Interrupt En-

able. If MCCIINTE is set to 1, the

MCCIINT bit will be able to set

the INTR bit when the internal

state machines generate MII

management frames. For in-

stance, when MCCIINTE is set to

1 and the Auto-Poll state ma-

chine generates a MII manage-

ment frame, the MCCIINT will set

the INTR bit upon completion of

the MII management frame re-

gardless of the comparison out-

come.

Read/Write accessible.

MCCIINTE is set to 0 by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

1 MIIPDTINT MII PHY Detect Transition Inter-

rupt. The MII PHY Detect Transi-

tion Interrupt is set by the

Am79C976 controller whenever

the MIIPD bit (BCR32, bit 14)

transitions from 0 to 1 or vice ver-

sa.

Read/Write accessible. MIIP-

DTINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MIIPDTINT is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

186 Am79C976 9/14/00

PRELIMINARY

0 MIIPDTINTEMII PHY Detect Transition Inter-

rupt Enable. If MIIPDTINTE is set

to 1, the MIIPDTINT bit will be

able to set the INTR bit.

Read/Write accessible. MIIP-

DTINTE is set to 0 by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

CSR8: Logical Address Filter 0

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[15:0]

Logical Address Filter,

LADRF-[15:0]. The content of this

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible. These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

CSR9: Logical Address Filter 1

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[31:16]

Logical Address Filter, LADRF-

[31:16]. The content of this regis-

ter is undefined until loaded from

the initialization block after the

INIT bit in CSR0 has been set or

a direct register write has been

performed on this register.

Read/Write accessible. These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

CSR10: Logical Address Filter 2

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[47:32]Logical Address Filter,

LADRF[47:32]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has been performed on this

Read/Write accessible. These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

CSR11: Logical Address Filter 3

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[63:48]

Logical Address Filter,

LADRF[63:48]. The content of

this register is undefined until

loaded from the initialization

block after the INIT bit in CSR0

has been set or a direct register

write has been performed on this

Read/Write accessible. These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

CSR12: Physical Address Register 0

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[15:0] Physical Address Register,

PADR[15:0]. The contents of this

EEPROM after H_RESET or by

an EEPROM read command

(PREAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

9/14/00 Am79C976 187

PRELIMINARY

or a direct register write has been

performed on this register.

Read/Write accessible. These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

CSR13: Physical Address Register 1

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[31:16]Physical Address Register,

PADR[31:16]. The contents of

this register are loaded from EE-

PROM after H_RESET or by an

EEPROM read command

(PREAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible. These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

CSR14: Physical Address Register 2

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 PADR[47:32]Physical Address Register,

PADR[47:32].The contents of

this register are loaded from

EEPROM after H_RESET or by

an EEPROM read command

(PREAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible. These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

CSR15: Mode

This register’s fields are loaded during the Am79C976

controller initialization routine with the corresponding

Initialization Block values, or when a direct register write

has been performed on this register.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 PROM Promiscuous Mode. When

PROM = 1, all incoming receive

frames are accepted.

Read/Write accessible.

14 DRCVBC Disable Receive Broadcast.

When set, disables the

Am79C976 controller from re-

ceiving broadcast messages.

Used for protocols that do not

support broadcast addressing,

except as a function of multicast.

DRCVBC is cleared by activation

of H_RESET or S_RESET

(broadcast messages will be re-

ceived) and is unaffected by

STOP.

Read/Write accessible.

13 DRCVPA Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) of the Am79C976 controller

will be disabled. Frames ad-

dressed to the node’s individual

physical address will not be rec-

ognized.

Read/Write accessible.

12-9 RES Reserved locations. Written as

zeros and read as undefined.

8-7 PORTSEL[1:0]Obsolete function. Writing has

no effect. Read as undefined.

6 INTL Obsolete function. Writing has no

effect. Read as undefined.

188 Am79C976 9/14/00

PRELIMINARY

5 DRTY Disable Retry. When DRTY is set

to 1, the Am79C976 controller will

attempt only one transmission. In

this mode, the device will not pro-

tect the first 64 bytes of frame

data in the Transmit FIFO from

being overwritten, because auto-

matic retransmission will not be

necessary. When DRTY is set to

0, the Am79C976 controller will

attempt 16 transmissions before

signaling a retry error.

Read/Write accessible.

4 FCOLL Force Collision. This bit allows

the collision logic to be tested.

The Am79C976 controller must

be in internal loopback for FCOLL

to be valid. If FCOLL = 1, a colli-

sion will be forced during loop-

back transmission attempts,

which will result in a Retry Error.

If FCOLL = 0, the Force Collision

logic will be disabled. FCOLL is

defined after the initialization

block is read.

Read/Write accessible.

3 DXMTFCS Disable Transmit CRC (FCS).

When DXMTFCS is set to 0, the

transmitter will generate and ap-

pend an FCS to the transmitted

frame. When DXMTFCS is set to

1, no FCS is generated or sent

with the transmitted frame.

DXMTFCS is overridden when

ADD_FCS and ENP bits are set

in the transmit descriptor.

When the auto padding logic,

which is enabled by the

APAD_XMT bit (CSR4, bit11),

adds padding to a frame, a valid

FCS field is appended to the

frame, regardless of the state of

DXMTFCS.

If DXMTFCS is set and

ADD_FCS is clear for a particular

frame, no FCS will be generated.

If ADD_FCS is set for a particular

frame, the state of DXMTFCS is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry. See also the

ADD_FCS bit in the transmit de-

scriptor.

This bit was called DTCR in the

LANCE (Am7990) device.

Read/Write accessible.

2 LOOP Loopback Enable allows the

Am79C976 controller to operate

in full-duplex mode for test pur-

poses. The setting of the full-

duplex control bits in BCR9 have

no effect when the device oper-

ates in loopback mode. When

LOOP = 1, loopback is enabled.

In combination with INTL and

MIIILP, various loopback modes

are defined as follows:.

Refer to Loop Back Operation

section for more details.

Read/Write accessible. LOOP is

cleared by H_RESET or

S_RESET and is unaffected by

STOP.

1 DTX Disable Transmit results in

Am79C976 controller not access-

ing the Transmit Descriptor Ring

and, therefore, no transmissions

are attempted. DTX = 0, will set

TXON bit (CSR0 bit 4) if STRT

(CSR0 bit 1) is asserted.

Read/Write accessible.

0 DRX Disable Receiver results in the

Am79C976 controller not access-

ing the Receive Descriptor Ring

and, therefore, all receive frame

data are ignored. DRX = 0, will

set RXON bit (CSR0 bit 5) if

STRT (CSR0 bit 1) is asserted.

Read/Write accessible.

CSR16-23: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

LOOP MIIILP Function

0 0 Normal Operation

0 1 Internal Loop

1 0 External Loop

9/14/00 Am79C976 189

PRELIMINARY

CSR24: Base Address of Receive Ring Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADRL Contains the lower 16 bits of the

base address of the Receive

Ring.

Read/Write accessible. These

bits are unaffected by H_RESET,

S_RESET, or STOP.

CSR25: Base Address of Receive Ring Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADRU Contains the upper 16 bits of the

base address of the Receive

Ring.

Read/Write accessible. These

bits are unaffected by H_RESET,

S_RESET, or STOP.

CSR26-29: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR30: Base Address of Transmit Ring Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADXL Contains the lower 16 bits of the

base address of the Transmit

Ring.

Read/Write accessible. These

bits are unaffected by H_RESET,

S_RESET, or STOP.

CSR31: Base Address of Transmit Ring Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 BADXU Contains the upper 16 bits of the

base address of the Transmit

Ring.

190 Am79C976 9/14/00

PRELIMINARY

Read/Write accessible. These

bits are unaffected by H_RESET,

S_RESET, or STOP.

CSR32-46: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR47: Transmit Polling Interval

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 TXPOLLINT Transmit Polling Interval. This

Am79C976 controller will wait be-

tween successive polling opera-

tions. The TXPOLLINT value is

expressed as the two’s comple-

ment of the desired interval,

where each bit of TXPOLLINT

represents 1 PCI clock period.

TXPOLLINT[3:0] are ignored.

(TXPOLLINT[16] is implied to be

a one, so TXPOLLINT[15] is sig-

nificant and does not represent

the sign of the two’s complement

TXPOLLINT value.)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods (2.185 ms when

ERCLK = 90 MHz).

Setting the INIT bit starts an ini-

tialization process that sets TX-

POLLINT to its default value. If

the user wants to program a val-

ue for TXPOLLINT other than the

default, then he must change the

value after the initialization se-

quence has completed.

If the user does not use the initial-

ization block to initialize the

Am79C976 device, but instead,

chooses to write directly to each

of the registers that are involved

in the INIT operation, then it is im-

perative that the user also writes

an acceptable value to CSR47 as

part of the alternative initialization

sequence.

Read/Write accessible. These

bits are unaffected by H_RESET,

S_RESET, or STOP.

CSR48: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR49: Chain Polling Interval

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 CHPOLLINT Chain Polling Interval. This regis-

ter contains the time that the

Am79C976 controller will wait be-

tween successive polling opera-

tions when the Buffer

Management Unit is in the middle

of a buffer chaining operation.

The CHPOLLINT value is ex-

pressed as the two’s complement

of the desired interval, where

each bit of CHPOLLINT approxi-

mately represents one PCI clock

time period. CHPOLLINT[3:0] are

ignored. (CHPOLLINT[16] is im-

plied to be a 1, so CHPOL-

LINT[15] is significant and does

not represent the sign of the two’s

complement CHPOLLINT value.)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods (1.966 ms when

CLK = 33 MHz).

Setting the INIT bit starts an ini-

tialization process that sets

CHPOLLINT to its default value.

If the user wants to program a

value for CHPOLLINT other than

the default, then he must change

the value after the initialization

sequence has completed.

If the user does not use the initial-

ization block to initialize the

Am79C976 device, but instead,

chooses to write directly to each

of the registers that are involved

in the INIT operation, then it is im-

perative that the user also writes

an acceptable value to CSR49 as

9/14/00 Am79C976 191

PRELIMINARY

part of the alternative initialization

sequence.

Read/Write accessible. These

bits are unaffected by H_RESET,

S_RESET, or STOP.

CSR50-57: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR58: Software Style

This register is an alias of the location BCR20. Accesses

to and from this register are equivalent to accesses to

BCR20.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-11 RES Reserved locations. Written as

zeros and read as undefined.

10 APERREN Obsolete function. Writing has no

effect. Read as undefined.

9 RES Reserved locations. Written as

zeros and read as undefined.

8 SSIZE32 Software Size 32 bits. When set,

this bit indicates that the

Am79C976 controller utilizes 32-

bit software structures for the ini-

tialization block and the transmit

and receive descriptor entries.

When cleared, this bit indicates

that the Am79C976 controller uti-

lizes 16-bit software structures

for the initialization block and the

transmit and receive descriptor

entries. In this mode, the

Am79C976 controller is back-

wards compatible with the

Am7990 LANCE and Am79C960

PCnet-ISA controllers.

The value of SSIZE32 is deter-

mined by the Am79C976 control-

ler according to the setting of the

Software Style (SWSTYLE, bits

7-0 of this register).

SSIZE32 is read only; write oper-

ations will be ignored. SSIZE32

will be cleared after H_RESET

(since SWSTYLE defaults to 0)

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

upper 8 bits of the 32-bit address

bus during master accesses initi-

ated by the Am79C976 controller.

This action is required, since the

16-bit software structures speci-

fied by the SSIZE32 = 0 setting

will yield only 24 bits of address

for the Am79C976 controller bus

master accesses.

If SSIZE32 is set, then the soft-

ware structures that are common

to the Am79C976 controller and

the host system will supply a full

32 bits for each address pointer

that is needed by the Am79C976

controller for performing master

accesses.

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress pins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE32 bit has no effect on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0 SWSTYLE Software Style register. The val-

ue in this register determines the

style of register and memory re-

sources that shall be used by the

Am79C976 controller. The Soft-

ware Style selection will affect the

interpretation of a few bits within

the CSR space, the order of the

descriptor entries and the width

of the descriptors and initializa-

tion block entries.

All Am79C976 controller CSR

bits and BCR bits and all descrip-

tor, buffer, and initialization block

entries not cited in Table 85 are

unaffected by the Software Style

selection and are, therefore, al-

ways fully functional as specified

in the CSR and BCR sections.

192 Am79C976 9/14/00

PRELIMINARY

Read/Write accessible. The SW-

STYLE register will contain the

value 00h following H_RESET

and will be unaffected by

S_RESET or STOP.

Table 85. Software Styles

SWSTYLE

[7:0]

Style

Name SSIZE32

Initialization Block

Entries Descriptor Ring Entries

00h LANCE/

PCnet-ISA controller 016-bit software structures,

non-burst or burst access

16-bit software structures,

non-burst access only

01h RES 1 RES RES

02h PCnet-PCI

controller 132-bit software structures,

non-burst or burst access

32-bit software structures,

non-burst access only

03h PCnet-PCI

controller 132-bit software structures,

non-burst or burst access

32-bit software structures,

non-burst or burst access

04h VLAN 1 Not Used 32-bit software structures,

non-burst or burst access

05h 64-bit Address 1 Not Used

32-bit software structures,

32-byte descriptors, non-

burst or burst access

All Other Reserved Undefined Undefined Undefined

9/14/00 Am79C976 193

PRELIMINARY

CSR59-75: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR76: Receive Ring Length

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RCVRL Receive Ring Length. Contains

the two’s complement of the re-

ceive descriptor ring length. This

optional Am79C976 controller ini-

tialization routine based on the

value in the RLEN field of the ini-

tialization block. However, this

The actual receive ring length is

defined by the current value in

this register. The ring length can

be defined as any value from

1 to 65535.

Read/Write accessible. These

bits are unaffected by H_RESET,

S_RESET, or STOP.

CSR77: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR78: Transmit Ring Length

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 XMTRL Transmit Ring Length. Contains

the two’s complement of the

transmit descriptor ring length.

This register is initialized during

the optional Am79C976 control-

ler initialization routine based on

the value in the TLEN field of the

initialization block. However, this

The actual transmit ring length is

defined by the current value in

this register. The ring length can

be defined as any value from 1 to

65535.

Read/Write accessible. These

bits are unaffected by H_RESET,

S_RESET, or STOP.

CSR79: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR80: DMA Transfer Counter and FIFO Threshold

Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-14 RES Reserved locations. Written as

zeros and read as undefined.

13-12 RCVFW[1:0]Receive FIFO Watermark.

RCVFW controls the point at

which receive DMA is requested

in relation to the number of re-

ceived bytes in the Receive

FIFO. RCVFW specifies the num-

ber of bytes which must be

present (once the frame has

been verified as a non-runt) be-

fore receive DMA is requested.

Note however that, if the network

interface is operating in half-du-

plex mode, in order for receive

DMA to be performed for a new

frame, at least 64 bytes must

have been received. This effec-

tively avoids having to react to re-

ceive frames which are runts or

suffer a collision during the slot

time (512 bit times). If the Runt

Packet Accept feature is enabled

or if the network interface is oper-

ating in full-duplex mode, receive

DMA will be requested as soon

as either the RCVFW threshold is

reached, or a complete valid re-

ceive frame is detected (regard-

less of length). When the Full

Duplex Runt Packet Accept Dis-

able (FDRPAD) bit (BCR9, bit 2)

is set and the Am79C976 control-

ler is in full-duplex mode, in order

for receive DMA to be performed

for a new frame, at least 64 bytes

must have been received. This

effectively disables the runt pack-

et accept feature in full duplex.

194 Am79C976 9/14/00

PRELIMINARY

Table 86. Receive Watermark Programming

Read/Write accessible.

RCVFW[1:0] is set to a value of

01b (64 bytes) after H_RESET or

S_RESET and is unaffected by

STOP.

11-10 XMTSP[1:0] Transmit Start Point. XMTSP

controls the point at which pre-

amble transmission attempts to

commence in relation to the num-

ber of bytes written to the MAC

Transmit FIFO for the current

transmit frame. When the entire

frame is in the MAC Transmit

FIFO, transmission will start re-

gardless of the value in XMTSP.

If the network interface is operat-

ing in half-duplex mode, regard-

less of XMTSP, the FIFO will not

internally overwrite its data until

at least 64 bytes (or the entire

frame if shorter than 64 bytes)

have been transmitted onto the

network. This ensures that for

collisions within the slot time win-

dow, transmit data need not be

rewritten to the Transmit FIFO,

and retries will be handled auton-

omously by the MAC. If the Dis-

able Retry feature is enabled, or if

the network is operating in full-

duplex mode, the Am79C976

controller can overwrite the be-

ginning of the frame as soon as

the data is transmitted, because

no collision handling is required

in these modes.

Note that when the No Underflow

(NOUFLO) bit (BCR18, bit 11) is

set to 1, there is the additional re-

striction that the complete trans-

mit frame must be DMA’d into the

Am79C976 controller and reside

within the MAC Transmit FIFO.

This mode is useful in a system

where high latencies cannot be

avoided. See Table 87.

Read/Write accessible. XMTSP

is set to a value of 01b (64 bytes)

after H_RESET or S_RESET and

is unaffected by STOP.

Table 87. Transmit Start Point Programming

9-8 XMTFW[1:0] Transmit FIFO Watermark. XMT-

FW specifies the point at which

transmit DMA is requested,

based upon the number of bytes

that could be written to the Trans-

mit FIFO without FIFO overflow.

Transmit DMA is requested at

any time when the number of

bytes specified by XMTFW could

be written to the FIFO without

causing Transmit FIFO overflow,

and the internal state machine

has reached a point where the

Transmit FIFO is checked to de-

termine if DMA servicing is re-

quired. See Table 88.

Table 88. Transmit Watermark Programming

Read/Write accessible. XMTFW

is set to a value of 00b (16 bytes)

after H_RESET or S_RESET and

is unaffected by STOP.

7-0 DMATC[7:0]Obsolete function. Writing has no

effect. Read as undefined.

RCVFW[1:0] Bytes Received

00 48

01 64

10 128

11 256

XMTSP[1:0] NOUFLO Bytes Written

00 0 16

01 0 64

10 0 128

11 0 Full Frame

XX 1 Full Frame

XMTFW[1:0] Bytes Available

00 16

01 64

10 128

11 256

9/14/00 Am79C976 195

PRELIMINARY

CSR81-87: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR88: Chip ID Register Lower

Bit Name Description

31-16 RES Reserved locations.

Read as undefined.

15-12 PARTIDL Lower 4 bits of the Am79C976

controller part number, i.e. 1000b

(8h). PARTIDU and PARTIDL

comprise the 16-bit code for the

Am79C976 controller, which is

0010 0110 0010 1000b (2628h).

This register is exactly the same

as the Device ID register in the

JTAG description. However, this

part number is different from that

stored in the Device ID register in

the PCI configuration space.

PARTIDL is read only. Write op-

erations are ignored.

11-1 MANFID Manufacturer ID. The 11-bit man-

ufacturer code for AMD is

00000000001b. This code is per

the JEDEC Publication 106-A.

Note that this code is not the

same as the Vendor ID in the PCI

configuration space.

MANFID is read only. Write oper-

ations are ignored.

0 ONE Always a logic 1.

ONE is read only. Write opera-

tions are ignored.

CSR89: Chip ID Register Upper

Bit Name Description

31-16 RES Reserved locations. Read as un-

defined.

15-12 VER Version. This 4-bit pattern is sili-

con-revision dependent.

VER is read only. Write opera-

tions are ignored.

11-0 PARTIDU Upper 12 bits of the Am79C976

controller part number, i.e., 0010

0110 0010b (262h).

PARTIDU is read only. Write op-

erations are ignored.

CSR90-99: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR100: Bus Timeout

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MERRTO Obsolete function. Writing has no

effect. Read as undefined.

CSR101-111: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR112: Missed Frame Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MFC Obsolete function. Replaced by

MIB counter. Writing has no ef-

fect. Read as undefined.

CSR113: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR114: Receive Collision Count

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 RCC Obsolete function. Replaced by

MIB counter. Writing has no ef-

fect. Read as undefined.

CSR115: Reserved

Bit Name Description

196 Am79C976 9/14/00

PRELIMINARY

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR116: OnNow Power Mode Register

Note: Bits 10-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-11 RES Reserved locations. Written as

zeros and read as undefined.

10 PME_EN_OVR

PME_EN Overwrite. When this

bit is set and the MPMAT or LC-

DET bit is set, the PME pin will al-

ways be asserted regardless of

the state of PME_EN bit.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

9 LCDET Link Change Detected. This bit is

set when the MII auto-polling log-

ic detects a change in link status

and the LCMODE bit is set.

This bit can be cleared to 0 either

by writing 1 to CSR116, bit 9 or by

writing 1 to STAT0, bit 10.

LCDET is cleared when power is

initially applied (POR).

Read/Write accessible.

8 LCMODE Link Change Wake-up Mode.

When this bit is set to 1, the LC-

DET bit gets set when the MII

auto polling logic detects a Link

Change.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7 PMAT Pattern Matched. This bit is set

when the PMMODE bit is set and

an OnNow pattern match occurs.

This bit can be cleared to 0 either

by writing 0 to CSR116, bit 7 or by

writing 1 to STAT0, bit 12.

PMAT is cleared when power is

initially applied (POR).

Read/Write accessible.

6 EMPPLBA Magic Packet Physical Logical

Broadcast Accept. If both EMP-

PLBA and MPPLBA (CSR5, bit 5)

are at their default value of 0, the

Am79C976 controller will only de-

tect a Magic Packet frame if the

destination address of the packet

matches the content of the physi-

cal address register (PADR). If ei-

ther EMPPLBA or MPPLBA is set

to 1, the destination address of

the Magic Packet frame can be

unicast, multicast, or broadcast.

Note that the setting of EMPPL-

BA and MPPLBA only affects the

address detection of the Magic

Packet frame. The Magic Packet

frame’s data sequence must be

made up of 16 consecutive phys-

ical addresses (PADR[47:0]) re-

gardless of what kind of

destination address it has.

Read/Write accessible.

EMPPLBA is set to 0 by

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

5 MPMAT Magic Packet Match. This bit is

set when PCnet-FAST+ detects a

Magic Packet while it is in the

Magic Packet mode.

This bit can be cleared to 0 either

by writing 0 to CSR116, bit 5 or by

writing 1 to STAT0, bit 11.

MPMAT is cleared when power is

initially applied (POR).

Read/Write accessible.

4 MPPEN Magic Packet Pin Enable. When

this bit is set, the device enters

the Magic Packet mode when the

PG input goes LOW or MPEN bit

(CSR5, bit 2) gets set to 1. This

bit is OR’ed with MPEN (CSR5,

bit 2).

Read/Write accessible. Cleared

by H_RESET and is not affected

9/14/00 Am79C976 197

PRELIMINARY

by S_RESET or setting the STOP

bit.

3 RWU_DRIVER RWU Driver Type. If this bit is set

to 1, RWU is a totem pole driver;

otherwise RWU is an open drain

output.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

2 RWU_GATE RWU Gate Control. If this bit is

set, RWU is forced to the high Im-

pedance State when PG is LOW,

regardless of the state of the

MPMAT and LCDET bits.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

1 RWU_POL RWU Pin Polarity. If RWU_POL

is set to 1, the RWU pin is normal-

ly HIGH and asserts LOW; other-

wise, RWU is normally LOW and

asserts HIGH.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

0 RST_POL PHY_RST Pin Polarity. If the

RST_POL is set to 1, the

PHY_RST pin is active LOW; oth-

erwise, PHY_RST is active

HIGH.

Read/Write accessible. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

CSR117-121: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR122: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR123: Reserved

Bit Name Description

31-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR124: Test Register 1

This register is used to place the Am79C976 controller

into various test modes. The Runt Packet Accept is the

only user accessible test mode. All other test modes are

for AMD internal use only.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-4 RES Reserved locations. Written as

zeros and read as undefined.

3 RPA Runt Packet Accept. This bit forc-

es the Am79C976 controller to

accept runt packets (packets

shorter than 64 bytes).

The minimum packet size that

can be received is 12 bytes.

Read/Write accessible. RPA is

cleared by H_RESET or

S_RESET and is not affected by

STOP.

2-0 RES Reserved locations. Written as

zeros and read as undefined.

CSR125: MAC Enhanced Configuration Control

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 IPG Inter Packet Gap. This value indi-

cates the minimum number of

network bit times after the end of

a frame that the transmitter will

wait before it starts transmitting

another frame. In half-duplex

mode the end of the frame is de-

termined by CRS, while in full-du-

plex mode the end of the frame is

determined by TX_EN. The IPG

value can be adjusted to com-

pensate for delays through the

external PHY device.

IPG should be programmed to

the nearest nibble. The two least

significant bits are ignored. For

198 Am79C976 9/14/00

PRELIMINARY

example, programming IPG to

63h has the same effect as pro-

gramming it to 60h.

CAUTION: Use this parameter

with care. By lowering the IPG

below the IEEE 802.3 standard

96 bit times, the Am79C976 con-

troller can interrupt normal net-

work behavior.

Read/Write accessible. IPG is set

to 60h (96 Bit times) by

H_RESET or S_RESET and is

not affected by STOP.

7-0 IFS1 InterFrameSpacingPart1.

Changing IFS1 allows the user to

program the value of the Inter-

Frame-SpacePart1 timing. The

Am79C976 controller sets the de-

fault value at 60 bit times (3ch).

See the subsection on Medium

Allocation in the section Media

Access Management for more

details. The equation for setting

IFS1 when IPG ≥ 96 bit times is:

IFS1 = IPG - 36 bit times

IPG should be programmed to

the nearest nibble. The two least

significant bits are ignored. For

example, programming IPG to

63h has the same effect as pro-

gramming it to 60h.

Read/Write accessible. IFS1 is

set to 3ch (60 bit times) by

H_RESET or S_RESET and is

not affected by STOP.

9/14/00 Am79C976 199

PRELIMINARY

Bus Configuration Registers

The Bus Configuration Registers (BCRs) are included

for compatibility with older PCnet Family software All

BCR functions can be accessed more efficiently

through the memory-mapped registers.

BCRs are used to program the configuration of the bus

interface and other special features of the Am79C976

controller that are not related to the IEEE 8802-3 MAC

functions. The BCRs are accessed by first setting the

appropriate RAP value and then by performing a slave

access to the BDP. See Table 89.

All BCR registers are 16 bits in width in Word I/O mode

(DWIO = 0, BCR18, bit 7) and 32 bits in width in DWord

I/O mode (DWIO = 1). The upper 16 bits of all BCR reg-

isters is undefined when in DWord I/O mode. These

bits should be written as zeros and should be treated

as undefined when read. The default value given for

any BCR is the value in the register after H_RESET.

Some of these values may be changed shortly after

H_RESET when the contents of the external EEPROM

is automatically read in. None of the BCR register val-

ues are affected by the assertion of the STOP bit or

S_RESET.

Note that several registers have no default value.

BCR0, BCR1, BCR3, BCR8, BCR10-17, and BCR21

are reserved and have undefined values. BCR2 and

BCR34 are not observable without first being pro-

grammed through the EEPROM read operation or a

user register write operation.

BCR0, BCR1, BCR16, BCR17, and BCR21 are regis-

ters that are used by other devices in the PCnet family.

Writing to these registers have no effect on the opera-

tion of the Am79C976 controller.

Writes to those registers marked as “Reserved” will

have no effect. Reads from these locations will produce

undefined values.

Table 89. BCR Registers

RAP Mnemonic Default Name

Programmability

User EEPROM

0 MSRDA 0005h Reserved No No

1 MSWRA 0005h Reserved No No

2 MC 0000h Miscellaneous Configuration Yes Yes

3 Reserved N/A Reserved No No

4 LED0 00C0h LED0 Status Yes Yes

5 LED1 0094h LED1 Status Yes Yes

6 LED2 1080h LED2 Status Yes Yes

7 LED3 0081h LED3 Status Yes Yes

8 Reserved N/A Reserved No No

9 FDC 0004h Full-Duplex Control Yes Yes

10-15 Reserved N/A Reserved No No

16 IOBASEL N/A Reserved No No

17 IOBASEU N/A Reserved No No

18 BSBC 9000h Burst and Bus Control Yes Yes

19 EECAS 0000h EEPROM Control and Status Yes No

20 SWS 0000h Software Style Yes No

21 Reserved N/A Reserved No No

22 PCILAT 1818h PCI Latency Yes Yes

23 PCISID 0000h PCI Subsystem ID No Yes

24 PCISVID 0000h PCI Subsystem Vendor ID No Yes

200 Am79C976 9/14/00

PRELIMINARY

BCR0: Master Mode Read Active

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MSRDA Reserved locations. After

H_RESET, the value in this regis-

ter will be 0005h. The setting of

this register has no effect on any

Am79C976 controller function. It

is only included for software com-

patibility with other PCnet family

devices.

Read always. MSRDA is read

only. Write operations have no ef-

fect.

BCR1: Master Mode Write Active

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MSWRA Reserved locations. After

H_RESET, the value in this regis-

ter will be 0005h. The setting of

this register has no effect on any

Am79C976 controller function. It

is only included for software com-

patibility with other PCnet family

devices.

Read always. MSWRA is read

only. Write operations have no ef-

fect.

25 SRAMSIZE 0000h SRAM Size Yes Yes

26 SRAMBND 0000h SRAM Boundary Yes Yes

27 Reserved N/A Reserved No No

28 EBADDRL N/A Expansion Bus Address Lower Yes No

29 EBADDRU N/A Expansion Bus Address Upper Yes No

30 EBDR N/A Expansion Bus Data Port Yes No

31 STVAL FFFFh Software Timer Value Yes No

32 MIICAS 0400h MII Control and Status Yes Yes

33 MIIADDR N/A MII Address Yes Yes

34 MIIMDR N/A MII Management Data Yes No

35 PCIVID 1022h PCI Vendor ID No Yes

36 PMC_A C802h PCI Power Management Capabilities

(PMC) Alias Register No Yes

37 DATA0 0000h PCI DATA Register Zero Alias Register No Yes

38 DATA1 0000h PCI DATA Register One Alias Register No Yes

39 DATA2 0000h PCI DATA Register Two Alias Register No Yes

40 DATA3 0000h PCI DATA Register Three Alias Register No Yes

41 DATA4 0000h PCI DATA Register Four Alias Register No Yes

42 DATA5 0000h PCI DATA Register Five Alias Register No Yes

43 DATA6 0000h PCI DATA Register Six Alias Register No Yes

44 DATA7 0000h PCI DATA Register Seven Alias Register No Yes

45 PMR1 N/A Pattern Matching Register 1 Yes No

46 PMR2 N/A Pattern Matching Register 2 Yes No

47 PMR3 N/A Pattern Matching Register 3 Yes No

9/14/00 Am79C976 201

PRELIMINARY

BCR2: Miscellaneous Configuration

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-13 RES Reserved locations. Written and

read as zeros.

12 LEDPE LED Program Enable. When

LEDPE is set to 1, programming

of the LED0 (BCR4), LED1

(BCR5), LED2 (BCR6), and

LED3 (BCR7) registers is en-

abled. When LEDPE is cleared to

0, programming of LED0 (BCR4),

LED1 (BCR5), LED2 (BCR6),

and LED3 (BCR7) registers is

disabled. Writes to those regis-

ters will be ignored.

Read/Write accessible. LEDPE is

cleared to 0 by H_RESET and is

unaffected by S_RESET or by

setting the STOP bit.

11-9 RES Reserved locations. Written and

read as zeros.

8 APROMWE Address PROM Write Enable.

The Am79C976 controller con-

tains a shadow RAM on board for

storage of the first 16 bytes load-

ed from the serial EEPROM.

Accesses to Address PROM I/O

Resources will be directed to-

ward this RAM. When APROM-

WE is set to 1, then write access

to the shadow RAM will be en-

abled.

Read/Write accessible. APROM-

WE is cleared to 0 by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

7 INTLEVEL Interrupt Level. This bit allows the

interrupt output signals to be pro-

grammed for level or edge-

sensitive applications.

When INTLEVEL is cleared to 0,

the INTA pin is configured for

level-sensitive applications. In

this mode, an interrupt request is

signaled by a low level driven on

the INTA pin by the Am79C976

controller. When the interrupt is

cleared, the INTA pin is tri-stated

by the Am79C976 controller and

allowed to be pulled to a high lev-

el by an external pull-up device.

This mode is intended for

systems which allow the interrupt

signal to be shared by multiple

devices.

When INTLEVEL is set to 1, the

INTA pin is configured for edge-

sensitive applications. In this

mode, an interrupt request is sig-

naled by a high level driven on

the INTA pin by the Am79C976

controller. When the interrupt is

cleared, the INTA pin is driven to

a low level by the Am79C976

controller. This mode is intended

for systems that do not allow

interrupt channels to be shared

by multiple devices.

INTLEVEL should not be set to 1

when the Am79C976 controller is

used in a PCI bus application.

Read/Write accessible. INTLEV-

EL is cleared to 0 by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

6-4 RES Reserved locations. Written as

zeros and read as undefined.

3 EADISEL Obsolete function. Writing has no

effect. Read as undefined.

2 RES Reserved location. Written and

read as zeros.

1 ASEL Obsolete function. Writing has no

effect. Read as undefined.

0 RES Reserved location. Written and

read as zeros.

BCR4: LED0 Status

BCR4 controls the function(s) that the LED0 pin dis-

plays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabled functions. BCR4 defaults to

Link Status (LNKST) with pulse stretcher enabled

(PSE = 1) and is fully programmable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED0 Status register is enabled.

202 Am79C976 9/14/00

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When LEDPE is cleared to 0, programming of the

LED0 register is disabled. Writes to this register will be

ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of the LED

output pin. A value of 1 in this bit

indicates that the OR of the

enabled signals is true.

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

This bit is read only; writes have

no effect. LEDOUT is unaffected

by H_RESET, S_RESET, or

STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, then the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals is false (i.e., the LED out-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole output and the output value

will be the same polarity as the

LEDOUT status bit.).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible. LEDPOL

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be governed by the LEDOUT

and LEDPOL values.

Read/Write accessible. LEDDIS

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a value of 1 is passed

to the LEDOUT bit in this register

when the Am79C976 controller is

operating at 100 Mbps mode.

Read/Write accessible. 100E is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

11-10 RES Reserved locations. Written and

read as zeros.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value

of 1 is passed to the LEDOUT bit

in this register when Magic Pack-

et frame mode is enabled and a

Magic Packet frame is detected

on the network.

Read/Write accessible. MPSE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT signal when the Am79C976

controller is functioning in a Link

Pass state and full-duplex opera-

tion is enabled. When the

Am79C976 controller is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

9/14/00 Am79C976 203

PRELIMINARY

Read/Write accessible. FDLSE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretcher.

Read/Write accessible. PSE is

set to 1 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

6 LNKSE Link Status Enable. When this bit

is set, a value of 1 will be passed

to the LEDOUT bit in this register

when in Link Pass state.

Read/Write accessible. LNKSE is

set to 1 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast and promiscuous.

Read/Write accessible. RCVME

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible. XMTE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

3 RES Reserved location. Written and

read as zeros.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

Read/Write accessible. RCVE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

1 SFBDE Start Frame/Byte Delimiter En-

able. When this bit is set, a value

of 1 is passed to the LEDOUT bit

in this register when the RXD[3:0]

pins are presenting the least sig-

nificant nibble of valid frame data.

Read/Write accessible. RCVE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible. COLE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR5: LED1 Status

BCR5 controls the function(s) that the LED1 pin dis-

plays. Multiple functions can be simultaneously en-

abled on this LED pin. The LED display will indicate the

logical OR of the enabled functions. BCR5 defaults to

transmit or receive activity (XMTE = 1 and RCVE = 1)

with pulse stretcher enabled (PSE = 1) and is fully pro-

grammable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED1 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED1 register is disabled. Writes to this register will be

ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of the LED

output pin. A value of 1 in this bit

indicates that the OR of the en-

abled signals is true.

204 Am79C976 9/14/00

PRELIMINARY

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

This bit is read only, writes have

no effect. LEDOUT is unaffected

by H_RESET, S_RESET, or

STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, then the LED pin will

be driven to a LOW level whenev-

er the OR of the enabled signals

is true, and the LED pin will be

disabled and allowed to float high

whenever the OR of the enabled

signals is false (i.e., the LED out-

put will be an Open Drain output

and the output value will be the

inverse of the LEDOUT status

bit).

When this bit has the value 1,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true, and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false (i.e.,

the LED output will be a Totem

Pole output and the output value

will be the same polarity as the

LEDOUT status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible. LEDPOL

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be governed by the LEDOUT

and LEDPOL values.

Read/Write accessible. LEDDIS

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a value of 1 is passed

to the LEDOUT bit in this register

when the Am79C976 controller is

operating at 100 Mbps mode.

Read/Write accessible. 100E is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

11-10 RES Reserved locations. Written and

read as zeros.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value

of 1 is passed to the LEDOUT bit

in this register when Magic Pack-

et mode is enabled and a Magic

Packet frame is detected on the

network.

Read/Write accessible. MPSE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT signal when the Am79C976

controller is functioning in a Link

Pass state and full-duplex opera-

tion is enabled. When the

Am79C976 controller is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

Read/Write accessible. FDLSE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretcher.

Read/Write accessible. PSE is

set to 1 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

9/14/00 Am79C976 205

PRELIMINARY

6 LNKSE Link Status Enable. When this bit

is set, a value of 1 will be passed

to the LEDOUT bit in this register

in Link Pass state.

Read/Write accessible. LNKSE

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

Read/Write accessible. RCVME

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible. XMTE is

set to 1 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

3 RES Reserved location. Written and

read as zeros.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

Read/Write accessible. RCVE is

set to 1 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

1 SFBDE Start Frame/Byte Delimiter En-

able. When this bit is set, a value

of 1 is passed to the LEDOUT bit

in this register when the RXD[3:0]

pins are presenting the least sig-

nificant nibble of valid frame data.

Read/Write accessible. RCVE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible. COLE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR6: LED2 Status

BCR6 controls the function(s) that the LED2 pin dis-

plays. Multiple functions can be simultaneously enabled

on this LED pin. The LED display will indicate the logical

OR of the enabled functions. BCR5 defaults to 100 Mb/

s speed indication (100E = 1) with pulse stretcher en-

abled (PSE = 1).

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED2 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED2 register is disabled. Writes to this register will be

ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM PREAD operation.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of the LED

output pin. A value of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

This bit is read only; writes have

no effect. LEDOUT is unaffected

by H_RESET, S_RESET, or

STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the LED pin will be

driven to a LOW level whenever

the OR of the enabled signals is

true. The LED pin will be disabled

206 Am79C976 9/14/00

PRELIMINARY

and allowed to float high whenev-

er the OR of the enabled signals

is false (i.e., the LED output will

be an Open Drain output and the

output value will be the inverse of

the LEDOUT status bit).

When this bit has the value 1, the

LED pin will be driven to a HIGH

level whenever the OR of the en-

abled signals is true. The LED pin

will be driven to a LOW level

whenever the OR of the enabled

signals is false (i.e., the LED out-

put will be a Totem Pole output

and the output value will be the

same polarity as the LEDOUT

status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible. LEDPOL

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be governed by the LEDOUT

and LEDPOL values.

Read/Write accessible. LEDDIS

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a value of 1 is passed

to the LEDOUT bit in this register

when the Am79C976 controller is

operating at 100 Mbps mode.

Read/Write accessible. 100E is

set to 1 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

11-10 RES Reserved locations. Written and

read as zeros.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value

of 1 is passed to the LEDOUT bit

in this register when Magic Pack-

et frame mode is enabled and a

Magic Packet frame is detected

on the network.

Read/Write accessible. MPSE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT signal when the Am79C976

controller is functioning in a Link

Pass state and full-duplex opera-

tion is enabled. When the

Am79C976 controller is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

Read/Write accessible. FDLSE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretcher.

Read/Write accessible. PSE is

set to 1 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

6 LNKSE Link Status Enable. When this bit

is set, a value of 1 will be passed

to the LEDOUT bit in this register

in Link Pass state.

Read/Write accessible. LNKSE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

9/14/00 Am79C976 207

PRELIMINARY

physical, logical filtering, broad-

cast, and promiscuous.

Read/Write accessible. RCVME

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible. XMTE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

3 RES Reserved location. Written and

read as zeros.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

Read/Write accessible. RCVE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

1 SFBDE Start Frame/Byte Delimiter En-

able. When this bit is set, a value

of 1 is passed to the LEDOUT bit

in this register when the RXD[3:0]

pins are presenting the least sig-

nificant nibble of valid frame data.

Read/Write accessible. RCVE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible. COLE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR7: LED3 Status

BCR7 controls the function(s) that the LED3 pin dis-

plays. Multiple functions can be simultaneously enabled

on this LED pin. The LED display will indicate the logical

OR of the enabled functions. BCR7 defaults to collision

indication (COLE = 1) with pulse stretcher enabled

(PSE = 1) and is fully programmable.

Note: When LEDPE (BCR2, bit 12) is set to 1, pro-

gramming of the LED3 Status register is enabled.

When LEDPE is cleared to 0, programming of the

LED3 register is disabled. Writes to this register will be

ignored.

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 LEDOUT This bit indicates the current

(non-stretched) value of the LED

output pin. A value of 1 in this bit

indicates that the OR of the en-

abled signals is true.

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of the LED register

(bits 8 and 6-0).

This bit is read only; writes have

no effect. LEDOUT is unaffected

by H_RESET, S_RESET, or

STOP.

14 LEDPOL LED Polarity. When this bit has

the value 0, the LED pin will be

driven to a LOW level whenever

the OR of the enabled signals is

true. The LED pin will be disabled

and allowed to float high whenev-

er the OR of the enabled signals

is false (i.e., the LED output will

be an Open Drain output and the

output value will be the inverse of

the LEDOUT status bit).

When this bit has the value 1, the

LED pin will be driven to a HIGH

level whenever the OR of the en-

abled signals is true. The LED pin

will be driven to a LOW level

whenever the OR of the enabled

signals is false (i.e., the LED out-

put will be a Totem Pole output

and the output value will be the

208 Am79C976 9/14/00

PRELIMINARY

same polarity as the LEDOUT

status bit).

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible. LEDPOL

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

13 LEDDIS LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value 1, then the

LED output will always be dis-

abled. When LEDDIS has the val-

ue 0, then the LED output value

will be governed by the LEDOUT

and LEDPOL values.

Read/Write accessible. LEDDIS

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

12 100E 100 Mbps Enable. When this bit

is set to 1, a value of 1 is passed

to the LEDOUT bit in this register

when the Am79C976 controller is

operating at 100 Mbps mode.

Read/Write accessible. 100E is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

11-10 RES Reserved locations. Written and

read as zeros.

9 MPSE Magic Packet Status Enable.

When this bit is set to 1, a value

of 1 is passed to the LEDOUT bit

in this register when magic frame

mode is enabled and a magic

frame is detected on the network.

Read/Write accessible. MPSE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

8 FDLSE Full-Duplex Link Status Enable.

Indicates the Full-Duplex Link

Test Status. When this bit is set,

a value of 1 is passed to the LED-

OUT signal when the Am79C976

controller is functioning in a Link

Pass state and full-duplex opera-

tion is enabled. When the

Am79C976 controller is not func-

tioning in a Link Pass state with

full-duplex operation being en-

abled, a value of 0 is passed to

the LEDOUT signal.

Read/Write accessible. FDLSE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

7 PSE Pulse Stretcher Enable. When

this bit is set, the LED illumination

time is extended for each new oc-

currence of the enabled function

for this LED output. A value of 0

disables the pulse stretcher.

Read/Write accessible. PSE is

set to 1 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

6 LNKSE Link Status Enable. When this bit

is set, a value of 1 will be passed

to the LEDOUT bit in this register

in Link Pass state.

Read/Write accessible. LNKSE

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

5 RCVME Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

Read/Write accessible. RCVME

is cleared by H_RESET and is

not affected by S_RESET or set-

ting the STOP bit.

4 XMTE Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible. XMTE is

cleared by H_RESET and is not

9/14/00 Am79C976 209

PRELIMINARY

affected by S_RESET or setting

the STOP bit.

3 RES Reserved location. Written and

read as zeros.

2 RCVE Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

Read/Write accessible. RCVE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

1 SFBDE Start Frame/Byte Delimiter En-

able. When this bit is set, a value

of 1 is passed to the LEDOUT bit

in this register when the RXD[3:0]

pins are presenting the least sig-

nificant nibble of valid frame data.

Read/Write accessible. RCVE is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

0 COLE Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible. COLE is

set to 1 by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

BCR9: Full-Duplex Control

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-3 RES Reserved locations. Written as

zeros and read as undefined.

2 FDRPAD Full-Duplex Runt Packet Accept

Disable. When FDRPAD is set to

1 and full-duplex mode is en-

abled, the Am79C976 controller

will only receive frames that meet

the minimum Ethernet frame

length of 64 bytes. Receive DMA

will not start until at least 64 bytes

or a complete frame have been

received. When FDRPAD is

cleared to 0, the Am79C976 con-

troller will accept any frame of 12

bytes or greater, and receive

DMA will start according to the

programming of the receive FIFO

watermark.

Read/Write accessible. FDRPAD

is set to 1 by H_RESET and is not

affected by S_RESET or by set-

ting the STOP bit.

1 RES Reserved locations. Written as

zeros and read as undefined.

0 FDEN Full-Duplex Enable. FDEN con-

trols whether full-duplex opera-

tion is enabled. When FDEN is

cleared and the Auto-Negotiation

is disabled, full-duplex operation

is not enabled and the

Am79C976 controller will always

operate in the half-duplex mode.

When FDEN is set, the

Am79C976 controller will operate

in full-duplex mode when the MII

port is enabled. Do not set this

bit when Auto-Negotiation is

enabled.

Read/Write accessible. FDEN is

reset to 0 by H_RESET, and is

unaffected by S_RESET and the

STOP bit.

BCR16: I/O Base Address Lower

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-5 IOBASEL Reserved locations. After

H_RESET, the value of these bits

will be undefined. The settings of

these bits will have no effect on

any Am79C976 controller func-

tion. It is only included for soft-

ware compatibility with other

PCnet family devices.

Read/Write accessible. IO-

BASEL is not affected by

S_RESET or STOP.

4-0 RES Reserved locations. Written as

zeros, read as undefined.

210 Am79C976 9/14/00

PRELIMINARY

BCR17: I/O Base Address Upper

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 IOBASEU Reserved locations. After

H_RESET, the value in this regis-

ter will be undefined. The settings

of this register will have no effect

on any Am79C976 controller

function. It is only included for

software compatibility with other

PCnet family devices.

Read/Write accessible. IO-

BASEU is not affected by

S_RESET or STOP.

BCR18: Burst and Bus Control Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-12 ROMTMG Expansion ROM Timing. The val-

ue of ROMTMG is used to tune

the timing for all accesses to the

external Flash/EPROM.

ROMTMG defines the amount of

time that a valid address is driven

on the ERA[19:0] pins.

The register value specifies delay

in number of ROMCLK cycles,

where ROMCLK is an internal

clock signal that runs at one

fourth the speed of ERCLK.

Note: Programming ROMTNG

with a value of 0 is not permitted.

To ensure adequate expansion

ROM setup time, ROMTMG

should be set to 1 plus tACC /

(ROMCLK period), where tACC

is the access time of the expan-

sion ROM device (Flash or

EPROM). (The extra ROMCLK

cycle is added to account for the

ERA[19:0] output delay from

ROMCLK plus the ERD[7:0] set-

up time to ROMCLK.)

This field is an alias of CTRL0,

bits 11-8.

Read/Write accessible. ROMT-

MG is set to the value of 1001b by

H_RESET and is not affected by

S_RESET or STOP. The default

value allows the use of an Expan-

sion ROM with an access time of

350 ns if ERCLK is running at 90

MHz.

11 NOUFLO No Underflow on Transmit. When

the NOUFLO bit is set to 1, the

Am79C976 controller will not

start transmitting the preamble

for a packet until the Transmit

Start Point (CTRL1, bits 16-17)

requirement has been met and

the complete packet has been

copied into the transmit FIFO.

When the NOUFLO bit is cleared

to 0, the Transmit Start Point is

the only restriction on when pre-

amble transmission begins for

transmit packets.

Setting the NOUFLO bit guaran-

tees that the Am79C976 control-

ler will never suffer transmit

underflows, because the arbiter

that controls transfers to and from

the SSRAM guarantees a worst

case latency on transfers to and

from the MAC and Bus Transmit

FIFOs such that it will never un-

derflow if the complete packet

has been copied into the

Am79C976 controller before

packet transmission begins.

Read/Write accessible. NOUFLO

is cleared to 0 after H_RESET or

S_RESET and is unaffected by

STOP.

10 RES Reserved location. Written as ze-

ros and read as undefined.

9 MEMCMD Obsolete function. Writing has no

effect. Read as undefined.

8 EXTREQ Obsolete function. Writing has no

effect. Read as undefined.

7 DWIO Double Word I/O. When set, this

bit indicates that the Am79C976

controller is programmed for

DWord I/O (DWIO) mode. When

9/14/00 Am79C976 211

PRELIMINARY

cleared, this bit indicates that the

Am79C976 controller is pro-

grammed for Word I/O (WIO)

mode. This bit affects the I/O Re-

source Offset map and it affects

the defined width of the

Am79C976 controllers I/O re-

sources. See the DWIO and WIO

sections for more details.

The initial value of the DWIO bit is

determined by the programming

of the EEPROM.

The value of DWIO can be al-

tered automatically by the

Am79C976 controller. Specifical-

ly, the Am79C976 controller will

set DWIO if it detects a DWord

write access to offset 10h from

the Am79C976 controller I/O

base address (corresponding to

the RDP resource).

Once the DWIO bit has been set

to a 1, only a H_RESET or an EE-

PROM read can reset it to a 0.

(Note that the EEPROM read op-

eration will only set DWIO to a 0 if

the appropriate bit inside of the

EEPROM is set to 0.)

DWIO is read only, write opera-

tions have no effect. DWIO is

cleared by H_RESET and is not

affected S_RESET or by setting

the STOP bit.

6 BREADE Obsolete function. Writing has no

effect. Read as undefined.

5 BWRITE Obsolete function. Writing has no

effect. Read as undefined.

4-3 TSTSHDW Reserved locations. Written and

read as zeros.

2-0 LINBC Reserved locations. Written and

read as zeros.

BCR19: EEPROM Control and Status

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 PVALID EEPROM Valid status bit.

PVALID is read only; write opera-

tions have no effect. A value of 1

in this bit indicates that a PREAD

operation has occurred, and that

(1) there is an EEPROM connect-

ed to the Am79C976 controller in-

terface pins and (2) the contents

read from the EEPROM have

passed the checksum verification

operation.

A value of 0 in this bit indicates a

failure in reading the EEPROM.

The checksum for the EEPROM

contents is incorrect or no EE-

PROM is connected to the inter-

face pins.

PVALID is set to 0 during

H_RESET and is unaffected by

S_RESET or the STOP bit. How-

ever, following the H_RESET op-

eration, an automatic, sequential

read of the EEPROM will be per-

formed. Just as is true for the nor-

mal PREAD command, at the

end of this automatic, sequential

read operation, the PVALID bit

may be set to 1. Therefore,

H_RESET will set the PVALID bit

to 0 at first, but the automatic EE-

PROM read operation may later

set PVALID to a 1.

If PVALID becomes 0 following

an EEPROM read operation (ei-

ther automatically generated af-

ter H_RESET, or requested

through PREAD), then all EE-

PROM-programmable BCR loca-

tions will be reset to their

H_RESET values. The content of

the Address PROM locations,

however, will not be cleared.

If no EEPROM is present at the

EESK, EEDI, and EEDO pins,

then all attempted PREAD com-

mands will terminate early and

PVALID will not be set. This ap-

plies to the automatic read of the

EEPROM after H_RESET, as

well as to host-initiated PREAD

commands.

14 PREAD EEPROM Read command bit.

When this bit is set to a 1 by the

host, the PVALID bit (BCR19, bit

15) will immediately be reset to a

0, and then the Am79C976 con-

troller will perform a sequential

212 Am79C976 9/14/00

PRELIMINARY

read operation of the EEPROM

through the interface. The EE-

PROM data that is fetched during

the read will be stored in the ap-

propriate internal registers on

board the Am79C976 controller.

Upon completion of the EEPROM

read operation, the Am79C976

controller will assert the PVALID

bit. EEPROM contents will be in-

directly accessible to the host

through read accesses to the Ad-

dress PROM (offsets 0h through

Fh) and through read accesses to

other EEPROM programmable

registers. Note that read access-

es from these locations will not

actually access the EEPROM it-

self, but instead will access the

Am79C976 controller’s internal

copy of the EEPROM contents.

Write accesses to these locations

may change the Am79C976 con-

troller register contents, but the

EEPROM locations will not be af-

fected. EEPROM locations may

be accessed directly through

BCR19.

At the end of the sequential read

operation, the PREAD bit will au-

tomatically be reset to a 0 by the

Am79C976 controller and

PVALID will be set, provided that

an EEPROM existed on the inter-

face pins and that the checksum

for the EEPROM contents was

correct.

Note that when PREAD is set to a

1, then the Am79C976 controller

will no longer respond to any ac-

cesses directed toward it, until

the PREAD operation has com-

pleted successfully. The

Am79C976 controller will termi-

nate these accesses with the as-

sertion of DEVSEL and STOP

while TRDY is not asserted, sig-

naling to the initiator to discon-

nect and retry the access at a

later time.

If a PREAD command is given to

the Am79C976 controller but no

EEPROM is attached to the inter-

face pins, the PREAD bit will be

cleared to a 0, and the PVALID bit

will remain reset with a value of 0.

This applies to the automatic, se-

quential read of the EEPROM af-

ter H_RESET as well as to host

initiated PREAD commands. EE-

PROM programmable locations

on board the Am79C976 control-

ler will be set to their default val-

ues by such an aborted PREAD

operation. For example, if the

aborted PREAD operation imme-

diately followed the H_RESET

operation, then the final state of

the EEPROM programmable lo-

cations will be equal to the

H_RESET programming for

those locations.

If a PREAD command is given to

the Am79C976 controller and the

auto-detection pin (EESK/LED1/

SFBD) indicates that no

EEPROM is present, then the

EEPROM read operation will still

be attempted.

Note that at the end of the

H_RESET operation, a read of

the EEPROM will be performed

automatically. This H_RESET-

generated EEPROM read func-

tion will not proceed if the auto-

detection pin (EESK/LED1) indi-

cates that no EEPROM is

present.

Read/Write accessible. PREAD

is set to 0 during H_RESET and

is unaffected by S_RESET or the

STOP bit.

13 EEDET EEPROM Detect. This bit indi-

cates the sampled value of the

EESK/LED1 pin at the end of

H_RESET. This value indicates

whether or not an EEPROM is

present at the EEPROM inter-

face. If this bit is a 1, it indicates

that an EEPROM is present. If

this bit is a 0, it indicates that an

EEPROM is not present.

EEDET is read only; write opera-

tions have no effect. The value of

this bit is determined at the end of

the H_RESET operation. It is un-

affected by S_RESET or the

STOP bit.

9/14/00 Am79C976 213

PRELIMINARY

Table 90 indicates the possible

combinations of EEDET and the

existence of an EEPROM and the

resulting operations that are pos-

sible on the EEPROM interface.

Table 90. EEDET Setting

12-5 RES Reserved locations. Written as

zeros; read as undefined.

4 EEN EEPROM Port Enable. When this

bit is set to a 1, it causes the val-

ues of ECS, ESK, and EDI to be

driven onto the EECS, EESK,

and EEDI pins, respectively. If

EEN = 0 and no EEPROM read

function is currently active, then

EECS will be driven LOW. When

EEN = 0 and no EEPROM read

function is currently active, EESK

and EEDI pins will be driven by

the LED registers BCR5 and

BCR4, respectively. See Table

91.

Read/Write accessible. EEN is

set to 0 by H_RESET and is unaf-

fected by S_RESET or STOP.

* PREAD and Auto Read required an EEPROM with support for sequential read (automatic address increment).

3 RES Reserved location. Written as

zero and read as undefined.

2 ECS EEPROM Chip Select. This bit is

used to control the value of the

EECS pin of the interface when

the EEN bit is set to 1 and the

PREAD bit is set to 0. If EEN = 1

and PREAD = 0 and ECS is set

to a 1, then the EECS pin will be

forced to a HIGH level at the ris-

ing edge of the next clock follow-

ing bit programming.

If EEN = 1 and PREAD = 0 and

ECS is set to a 0, then the EECS

pin will be forced to a LOW level

at the rising edge of the next

clock following bit programming.

ECS has no effect on the output

value of the EECS pin unless the

PREAD bit is set to 0 and the

EEN bit is set to 1.

Read/Write accessible. ECS is

set to 0 by H_RESET and is not

affected by S_RESET or STOP.

EEDET Value

(BCR19[13])

EEPROM

Connected? Result if PREAD is Set to 1

Result of Automatic EEPROM Read

Operation Following H_RESET

0No

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

failure will result; PVALID is reset to 0.

First two EESK clock cycles are generated,

then EEPROM read operation is aborted

and PVALID is reset to 0.

0Yes

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

operation will pass; PVALID is set to 1.

First two EESK clock cycles are generated,

then EEPROM read operation is aborted

and PVALID is reset to 0.

1No

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

failure will result; PVALID is reset to 0.

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

failure will result; PVALID is reset to 0.

1Yes

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

operation will pass; PVALID is set to 1.

EEPROM read operation is attempted.

Entire read sequence will occur; checksum

operation will pass; PVALID is set to 1.

Table 91. Interface Pin Assignment

RST Pin

*PREAD or Auto

Read in Progress EEN EECS EESK EEDI

Low X X 0 Tri-State Tri-State

High 1 X Active Active Active

High 0 1 From ECS

Bit of BCR19

From ESK Bit of

BCR19

From EEDI Bit of

BCR19

High 0 0 0 LED1 LED0

214 Am79C976 9/14/00

PRELIMINARY

1 ESK EEPROM Serial Clock. This bit

and the EDI/EDO bit are used to

control host access to the

EEPROM. Values programmed

to this bit are placed onto the

EESK pin at the rising edge of the

next clock following bit program-

ming, except when the PREAD

bit is set to 1 or the EEN bit is set

to 0. If both the ESK bit and the

EDI/EDO bit values are changed

during one BCR19 write opera-

tion, while EEN = 1, then setup

and hold times of the EEDI pin

value with respect to the EESK

signal edge are not guaranteed.

ESK has no effect on the EESK

pin unless the PREAD bit is set to

0 and the EEN bit is set to 1.

Read/Write accessible. ESK is

reset to 0 by H_RESET and is not

affected by S_RESET or STOP.

0 EDI/EDO EEPROM Data In/EEPROM

Data Out. Data that is written to

this bit will appear on the EEDI

output of the interface, except

when the PREAD bit is set to 1 or

the EEN bit is set to 0. Data that

is read from this bit reflects the

value of the EEDO input of the in-

terface.

EDI/EDO has no effect on the

EEDI pin unless the PREAD bit is

set to 0 and the EEN bit is set to

Read/Write accessible. EDI/EDO

is reset to 0 by H_RESET and is

not affected by S_RESET or

STOP.

BCR20: Software Style

This register is an alias of the location CSR58. Accesses

to and from this register are equivalent to accesses to

CSR58.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-11 RES Reserved locations. Written as

zeros and read as undefined.

10 APERREN Obsolete function. Writing has no

effect. Read as undefined.

9 RES Reserved locations. Written as

zeros; read as undefined.

8 SSIZE32 Software Size 32 bits. When set,

this bit indicates that the

Am79C976 controller utilizes

32-bit software structures for the

initialization block and the trans-

mit and receive descriptor en-

tries. When cleared, this bit

indicates that the Am79C976

controller utilizes 16-bit software

structures for the initialization

block and the transmit and re-

ceive descriptor entries. In this

mode, the Am79C976 controller

is backwards compatible with the

Am7990 LANCE and Am79C960

PCnet-ISA controllers.

The value of SSIZE32 is deter-

mined by the Am79C976 control-

ler according to the setting of the

Software Style (SWSTYLE, bits

7-0 of this register).

SSIZE32 is read only; write oper-

ations will be ignored. SSIZE32

will be cleared after H_RESET

(since SWSTYLE defaults to 0)

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

upper 8 bits of the 32-bit address

bus during master accesses initi-

ated by the Am79C976 controller.

This action is required, since the

16-bit software structures speci-

fied by the SSIZE32 = 0 setting

will yield only 24 bits of address

for Am79C976 controller bus

master accesses.

If SSIZE32 is set, then the soft-

ware structures that are common

to the Am79C976 controller and

the host system will supply a full

32 bits for each address pointer

that is needed by the Am79C976

controller for performing master

accesses.

9/14/00 Am79C976 215

PRELIMINARY

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress pins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE32 bit has no effect on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0 SWSTYLE Software Style register. The val-

ue in this register determines the

style of register and memory re-

sources that shall be used by the

Am79C976 controller. The Soft-

ware Style selection will affect the

interpretation of a few bits within

the CSR space, the order of the

descriptor entries and the width

of the descriptors and initializa-

tion block entries.

All Am79C976 controller CSR

bits and all descriptor, buffer, and

initialization block entries not cit-

ed in the Table 92 are unaffected

by the Software Style selection

and are, therefore, always fully

functional as specified in the CSR

and BCR sections.

Read/Write accessible. The SW-

STYLE register will contain the

value 00h following H_RESET

and will be unaffected by

S_RESET or STOP.

216 Am79C976 9/14/00

PRELIMINARY

BCR22: PCI Latency Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 MAX_LAT Maximum Latency. Specifies the

maximum arbitration latency the

Am79C976 controller can sustain

without causing problems to the

network activity. The register val-

ue specifies the time in units of

1/4 microseconds. MAX_LAT is

aliased to the PCI configuration

space register MAX_LAT (offset

3Fh). The host will use the value

in the register to determine the

setting of the Am79C976 Latency

Timer register.

Read/Write accessible.

MAX_LAT is set to the value of

18h by H_RESET which results

in a default maximum latency of 6

microseconds. MAX_LAT is not

affected by S_RESET or STOP.

7-0 MIN_GNT Minimum Grant. Specifies the min-

imum length of a burst period the

Am79C976 controller needs to

keep up with the network activity.

The length of the burst period is

calculated assuming a clock rate of

33 MHz. The register value speci-

fies the time in units of 1/4 µs.

MIN_GNT is aliased to the PCI

configuration space register

MIN_GNT (offset 3Eh). The host

will use the value in the register to

determine the setting of the

Am79C976 Latency Timer

Read/Write accessible.

MIN_GNT is set to the value of

18h by H_RESET which results

in a default minimum grant of 6

µs. MIN_GNT is not affected by

S_RESET or STOP.

BCR23: PCI Subsystem Vendor ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 SVID Subsystem Vendor ID. SVID is

used together with SID (BCR24,

bits 15-0) to uniquely identify the

add-in board or subsystem the

Am79C976 controller is used in.

Subsystem Vendor IDs can be ob-

tained from the PCI SIG. A value

of 0 (the default) indicates that the

Am79C976 controller does not

support subsystem identification.

Table 92. Software Styles

SWSTYLE

[7:0]

Style

Name SSIZE32

Initialization Block

Entries Descriptor Ring Entries

00h

LANCE/

PCnet-ISA

controller

16-bit software

structures, non-burst or

burst access

16-bit software structures,

non-burst access only

01h RES 1RES RES

02h PCnet-PCI

controller 1

32-bit software

structures, non-burst or

burst access

32-bit software structures,

non-burst access only

03h PCnet-PCI

controller 1

32-bit software

structures, non-burst or

burst access

32-bit software structures,

non-burst or burst access

04h VLAN 1Not used 32-bit software structures,

non-burst or burst access

05h 64-bit address 1Not used

32-bit software structures,

32-byte descriptors, non-

burst or burst access

All Other Reserved Undefined Undefined Undefined

9/14/00 Am79C976 217

PRELIMINARY

SVID is aliased to the PCI config-

uration space register Subsystem

Vendor ID (offset 2Ch).

SVID is read only. Write opera-

tions are ignored. SVID is cleared

to 0 by H_RESET and is not af-

fected by S_RESET or by setting

the STOP bit.

BCR24: PCI Subsystem ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 SID Subsystem ID. SID is used to-

gether with SVID (BCR23, bits

15-0) to uniquely identify the add-

in board or subsystem the

Am79C976 controller is used in.

The value of SID is up to the sys-

tem vendor. A value of 0 (the de-

fault) indicates that the

Am79C976 controller does not

support subsystem identification.

SID is aliased to the PCI configu-

ration space register Subsystem

ID (offset 2Eh).

SID is read only. Write operations

are ignored. SID is cleared to 0 by

H_RESET and is not affected by

S_RESET or by setting the STOP

bit.

BCR25: SRAM Size Register

Bit Name Description

Note: Bits 7-0 in this register are programmable

through the EEPROM.

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 SRAM_SIZE SRAM Size. Specifies the total

size of the SSRAM buffer in units

of 512-byte pages. For example,

assume that the external memory

consists of one 64K X 32 bit SS-

RAM, for a total of 256K bytes. In

this case SRAM_SIZE should be

set to 512 (256K divided by 512).

This field must be initialized to the

appropriate value, either by the

EEPROM or by the host CPU.

SRAM_SIZE must be set to a val-

ue less than or equal to 2000h.

Values larger than 2000h will

cause incorrect behavior.

Note: The minimum allowed

number of pages is eight for nor-

mal network operation. The

Am79C976 controller will not op-

erate correctly with less than the

eight pages of memory. When

the minimum number of pages is

used, these pages must be allo-

cated four each for transmit and

receive.

CAUTION: Programming

SRAM_BND and SRAM_SIZE to

the same value will cause data

corruption.

Read/Write accessible.

SRAM_SIZE is set to 000000b

during H_RESET and is unaffect-

ed by S_RESET or STOP.

BCR26: SRAM Boundary Register

Bit Name Description

Note: Bits 7-0 in this register are programmable

through the EEPROM.

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 SRAM_BND SRAM Boundary. Specifies the

size of the transmit buffer portion

of the SRAM in units of 512-byte

pages. For example if

SRAM_BND is set to 10, then

5120 bytes of the SRAM will be

allocated for the transmit buffer

and the rest will be allocated for

the receive buffer.

The transmit buffer in the SRAM

begins at address 0 and ends at

the address (SRAM_BND*512)-

1. Therefore, the receive buffer

always begins on a 512-byte

boundary.

SRAM_BND must be initialized to

an appropriate value, either by

the EEPROM or by the host CPU.

SRAM_BND must be set to a val-

ue less than or equal to IFFCh.

218 Am79C976 9/14/00

PRELIMINARY

Values larger than IFFCh will

cause incorrect behavior.

Note: The minimum allowed

number of pages is four and the

maximum is SRAM_SIZE-4. The

Am79C976 controller will not op-

erate correctly with less than four

pages of memory per queue. See

Table 93 for SRAM_BND pro-

gramming details.

CAUTION: Programming

SRAM_BND and SRAM_SIZE to

the same value will cause data

corruption.

Read/Write accessible.

SRAM_BND is set to 00000000b

during H_RESET and is unaffect-

ed by S_RESET or STOP.

BCR27: SRAM Interface Control Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 PTR TST Reserved. Reserved for manu-

facturing tests. Written as zero

and read as undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

Read/Write accessible.

PTR_TST is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

14 LOLATRX Obsolete function. Writing has no

effect. Read as undefined.

13-6 RES Reserved locations. Written as

zeros and read as undefined.

5-3 EBCS Obsolete function. Writing has no

effect. Read as undefined.

2-0 CLK_FAC Obsolete function. Writing has no

effect. Read as undefined.

BCR28: Expansion Bus Port Address Lower (Used

for Flash/EPROM and SRAM Accesses)

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 EPADDRL Expansion Port Address Lower.

This address is used to provide

addresses for the Flash port ac-

cesses.

Flash accesses are started when

a read or write is performed on

BCR30. During Flash accesses

all bits in EPADDR are valid.

Read accessible always; write

accessible only when STOP is

set or when SRAM_SIZE

(BCR25, bits 7-0) is 0. EPADDRL

is undefined after H_RESET and

is unaffected by S_RESET or

STOP.

BCR29: Expansion Port Address Upper (Used for

Flash/EPROM Accesses)

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 FLASH Obsolete function. Read only. Al-

ways returns logic 1.

14 LAAINC Lower Address Auto Increment.

When the LAAINC bit is set to 1,

the Expansion Port Lower Ad-

dress will automatically increment

by one after a read or write ac-

cess to EBDATA (BCR30). When

EBADDRL reaches FFFFh and

LAAINC is set to 1, the Expansion

Port Lower Address (EPADDRL)

will roll over to 0000h. When the

LAAINC bit is set to 0, the Expan-

sion Port Lower Address will not

be affected in any way after an

access to EBDATA (BCR30) and

must be programmed.

Read accessible always; write

accessible only when the STOP

bit is set. LAINC is 0 after

H_RESET and is unaffected by

S_RESET or the STOP bit.

Table 93. SRAM_BND Programming

SRAM Addresses SRAM_BND 11:0]

Minimum SRAM_BND

Address 004h

Maximum SRAM_BND Address SRAM_SIZE - 4

9/14/00 Am79C976 219

PRELIMINARY

13-8 RES Reserved locations. Written as

zeros and read as undefined.

7-0 EPADDRU Expansion Port Address Upper.

This upper portion of the Expan-

sion Bus address is used to pro-

vide addresses for Flash/EPROM

port accesses.

Read accessible always; write

accessible only when the STOP

bit is set or when SRAM SIZE

(BCR25, bits 7-0) is 0. EPADD-

RU is undefined after H_RESET

and is unaffected by S_RESET or

the STOP bit.

BCR30: Expansion Bus Data Port Register

Bit Name Description

31-8 RES Reserved locations. Written as

zeros and read as undefined.

7-0 EBDATA Expansion Bus Data Port. EBDA-

TA is the data port for operations

on the Expansion Port involving

Flash accesses.

Flash read cycles are performed

when BCR30 is read. Upon com-

pletion of the read cycle, the 8-bit

result for Flash access is stored

in EBDATA[7:0]. Flash write cy-

cles are performed when BCR30

is written and the FLASH bit

(BCR29, bit 15) is set to 1.

Read and write accessible. EB-

DATA is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

BCR31: Software Timer Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 STVAL Software Timer Value. STVAL

controls the maximum time for

the Software Timer to count be-

fore generating the STINT

(CSR7, bit 11) interrupt. The Soft-

ware Timer is a free-running tim-

er that is started upon the first

write to STVAL. After the first

write, the Software Timer will

continually count and set the

STINT interrupt at the STVAL pe-

riod.

The STVAL value is interpreted

as an unsigned number with a

resolution of 10.24µs. For in-

stance, if STVAL is set to 48,828

(0BEBCh), the Software Timer

period will be 0.5 s.

Setting STVAL to a value of 0 will

result in erratic behavior.

Read and write accessible.

STVAL is set to FFFFh after

H_RESET and is unaffected by

S_RESET and the STOP bit.

BCR32: MII Control and Status Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15 ANTST Reserved for manufacturing

tests. Written as 0 and read as

undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

Read/Write accessible. ANTST is

set to 0 by H_RESET and is unaf-

fected by S_RESET and the

STOP bit.

14 MIIPD MII PHY Detect. MIIPD reflects

the quiescent state of the MDIO

pin. MIIPD is continuously updat-

ed whenever there is no manage-

ment operation in progress on the

MII interface. When a manage-

ment operation begins on the in-

terface, the state of MIIPD is

preserved until the operation

ends, when the quiescent state is

again monitored and continuous-

ly updates the MIIPD bit. When

the MDIO pin is at a quiescent

LOW state, MIIPD is cleared to 0.

When the MDIO pin is at a quies-

cent HIGH state, MIIPD is set to

1. Any transition on the MIIPD bit

will set the MIIPDTINT bit (CSR7,

bit 1).

220 Am79C976 9/14/00

PRELIMINARY

MIIPD is read only. Write opera-

tions are ignored.

13-12 FMDC Fast Management Data Clock.

When FMDC is set to 2h the MII

Management Data Clock will run

at 10 MHz max. The Manage-

ment Data Clock will no longer be

IEEE 802.3u-compliant and set-

ting this bit should be used with

care. The accompanying external

PHY must also be able to accept

management frames at the new

clock rate. When FMDC is set to

1h, the MII Management Data

Clock will run at 5 MHz max. The

Management Data Clock will no

longer be IEEE 802.3u-compliant

and setting this bit should be

used with care. The accompany-

ing external PHY must also be

able to accept management

frames at the new clock rate.

When FMDC is set to 0h, the MII

Management Data Clock will run

at 2.5 MHz max and will be fully

compliant to IEEE 802.3u stan-

dards. See Table 94.

Read/Write accessible. FMDC is

set to 0 during H_RESET, and is

unaffected by S_RESET and the

STOP bit

11 APEP MII Auto-Poll External PHY.

when APEP is set to 1, the

Am79C976 controller will poll the

MII status register in the external

PHY. This feature allows the soft-

ware driver or upper layers to see

any changes in the status of the

external PHY. An interrupt, when

enabled, is generated when the

contents of the new status is dif-

ferent from the previous status.

Read/Write accessible. APEP is

set to 0 during H_RESET and is

unaffected by S_RESET and the

STOP bit.

10-8 APDW MII Auto-Poll Dwell Time. APDW

determines the dwell time be-

tween MII Management Frames

accesses when Auto-Poll is

turned on. The MDC clock is ER-

CLK divided by 40 and will be

slower than 2.5MHz. The actual

interval between polls will be the

time shown in Table 95 multiplied

by 100 / (ERCLK frequency in

MHz).

Read/Write accessible. APDW is

set to 100b after H_RESET and

is unaffected by S_RESET and

the STOP bit.

7 DISPM Disable Port Manager. (The cor-

responding bit in older PCnet

family devices is called Disable

Auto-Negotiation Auto Setup or

DANAS. The name has been

changed, but not the function.)

When DISPM is set, the

Am79C976 controller after a

H_RESET or S_RESET will re-

main dormant and not automati-

cally start up the Auto-

Negotiation section or the en-

hanced automatic port selection

section. Instead, the Am79C976

controller will wait for the soft-

ware driver to set up the Auto-Ne-

gotiation portions of the device.

The MII programming in BCR33

and BCR34 is still valid. The

Am79C976 controller will not

generate any management

frames unless Auto-Poll is en-

abled.

Read/write accessible. DISPM is

set to 0 by H_RESET and is unaf-

fected by S_RESET and the

STOP bit.

Table 94. FMDC Values

FMDC Fast Management Data Clock

00 2.5 MHz max

01 5 MHz max

10 10 MHz max

11 Reserved

Table 95. APDW Values

APDW Auto-Poll Dwell Time

000 Continuous (27 µs @ 2.5 MHz)

001 Every 64 MDC cycles (77 µs @ 2.5 MHz)

010 Every 128 MDC cycles (129 µs @ 2.5 MHz)

011 Every 256 MDC cycles (232 µs @ 2.5 MHz)

100 Every 512 MDC cycles (436 µs @ 2.5 MHz)

101 Every 1024 MDC cycles (845 µs @ 2.5 MHz)

110-111 Reserved

9/14/00 Am79C976 221

PRELIMINARY

6 XPHYRST External PHY Reset. When XPH-

YRST is set, the Am79C976 con-

troller after an H_RESET or

S_RESET will issue an MII man-

agement frame that will reset the

external PHY. This bit is needed

when there is no way to guaran-

tee the state of the external PHY.

This bit must be reprogrammed

after every H_RESET.

Read/Write accessible. XPH-

YRST is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit. XPHYRST is

only valid when the internal Net-

work Port Manager is scanning

for a network port.

5 XPHYANE External PHY Auto-Negotiation

Enable. This bit will force the ex-

ternal PHY into enabling Auto-

Negotiation. When set to 0 the

Am79C976 controller will send a

MII management frame disabling

Auto-Negotiation.

Read/Write accessible.

XPHYANE is set to 0 by

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYANE is only valid when the

internal Network Port Manager is

scanning for a network port.

4 XPHYFD External PHY Full Duplex. When

set, this bit will force the external

PHY into full duplex when Auto-

Negotiation is not enabled.

Read/Write accessible. XPHYFD

is set to 0 by H_RESET, and is

unaffected by S_RESET and the

STOP bit. XPHYFD is only valid

when the internal Network Port

Manager is scanning for a net-

work port.

3 XPHYSP External PHY Speed. When set,

this bit will force the external PHY

into 100 Mbps mode when Auto-

Negotiation is not enabled.

Read/Write accessible. XPHYSP

is set to 0 by H_RESET, and is

unaffected by S_RESET and the

STOP bit. XPHYSP is only valid

when the internal Network Port

Manager is scanning for a net-

work port.

2 RES Reserved location. Written as ze-

ros and read as undefined.

1 MIIILP Media Independent Interface In-

ternal Loopback. When set, this

bit will cause the internal portion

of the MII data port to loop back

on itself. The interface is mapped

in the following way. The

TXD[3:0] nibble data path is

looped back onto the RXD[3:0]

nibble data path. TX_CLK is

looped back as RX_CLK. TX_EN

is looped back as RX_DV. CRS is

correctly OR’d with TX_EN and

RX_DV and always encompass-

es the transmit frame. TX_ER is

looped back as RX_ER. Howev-

er, TX_ER will not get asserted

by the Am79C976 controller to

signal an error. The TX_ER func-

tion is reserved for future use.

Read/Write accessible. MIIILP is

set to 0 by H_RESET and is unaf-

fected by S_RESET and the

STOP bit.

0 RES Reserved location. Written as ze-

ros and read as undefined.

BCR33: MII Address Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-5 PHYAD MII Management Frame PHY Ad-

dress. PHYAD contains the 5-bit

PHY Address field that is used in

the management frame that gets

clocked out via the MII manage-

ment port pins (MDC and MDIO)

whenever a read or write transac-

tion occurs to BCR34. The PHY

address 1Fh is not valid.

Read/Write accessible. PHYAD

is undefined after H_RESET and

is unaffected by S_RESET and

the STOP bit.

222 Am79C976 9/14/00

PRELIMINARY

The PHYAD field is loaded from

bits [9:5] of the AUTOPOLL0 reg-

ister when AUTOPOLL0 is load-

ed from EEPROM. See

“AUTOPOLL0: Auto-Poll0 Regis-

ter” on page 125

4-0 REGAD MII Management Frame Register

Address. REGAD contains the

5-bit Register Address field that is

used in the management frame

that gets clocked out via the MII

management port pins (MDC and

MDIO) whenever a read or write

transaction occurs to BCR34.

Read/Write accessible. REGAD

is undefined after H_RESET and

is unaffected by S_RESET and

the STOP bit.

BCR34: MII Management Data Register

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 MIIMD MII Management Data. MIIMD is

the data port for operations on

the MII management interface

(MDIO and MDC). The

Am79C976 device builds man-

agement frames using the PHY-

AD and REGAD values from

BCR33. The operation code used

in each frame is based upon

whether a read or write operation

has been performed to BCR34.

Read cycles on the MII manage-

ment interface are invoked when

BCR34 is read. Upon completion

of the read cycle, the 16-bit result

of the read operation is stored in

MIIMD. Write cycles on the MII

management interface are in-

voked when BCR34 is written.

The value written to MIIMD is the

value used in the data field of the

management write frame.

Read/Write accessible. MIIMD is

undefined after H_RESET and is

unaffected by S_RESET and the

STOP bit.

BCR35: PCI Vendor ID Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-0 VID Vendor ID. The PCI Vendor ID

identifies the manufacturer of the

Am79C976 controller. AMD’s

Vendor ID is 1022h. Note that this

Vendor ID is not the same as the

Manufacturer ID in CSR88 and

CSR89. The Vendor ID is as-

signed by the PCI Special Inter-

est Group.

The Vendor ID is not normally

programmable, but the

Am79C976 controller allows this

due to legacy operating systems

that do not look at the PCI Sub-

system Vendor ID and the Ven-

dor ID to uniquely identify the

add-in board or subsystem that

the Am79C976 controller is used

in.

Note: If the operating system or

the network operating system

supports PCI Subsystem Vendor

ID and Subsystem ID, use those

to identify the add-in board or

subsystem and program the VID

with the default value of 1022h.

VID is aliased to the PCI configu-

ration space register Vendor ID

(offset 00h).

VID is read only. Write operations

are ignored. VID is set to 1022h

by H_RESET and is not affected

by S_RESET or by setting the

STOP bit.

BCR36: PCI Power Management Capabilities (PMC)

Alias Register

This register is an alias of the PMC register located at

offset 42h of the PCI Configuration Space. It is included

for compatibility with older PCnet devices. Since the

PMC register is read only, in older PCnet devices

BCR36 provides a means of programming PMC

through the EEPROM.

In the Am79C976 controller there is a single PMC reg-

ister that can be accessed through three different

memory spaces. It can be accessed as read-only

through PCI Configuration Space (at offset 42h), read-

only through BCR36, or read-write through the mem-

9/14/00 Am79C976 223

PRELIMINARY

ory-mapped PMC Alias Register at offset 1B8h. It can

be loaded from the EEPROM through offset 1B8h in

the Am79C976 controller’s memory-mapped I/O

space.

For the definition of the bits in this register, refer to the

PMC register definition. BCR36 is read only. It is set to

0C802h by H_RESET and is not affected by S_RESET

or setting the STOP bit.

BCR37: PCI DATA Register Zero (DATA0) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PMCSR register.

Since these two are read only, BCR37 provides a

means of programming them indirectly. The contents of

this register are copied into the corresponding fields

pointed with the DATA_SEL field set to zero. Bits 15-0

in this register are programmable through the EE-

PROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D0_SCALE These bits correspond to the

DATA_SCALE field of the

PMCSR (offset Register 44 of the

PCI configuration space, bits 14-

13). Refer to the description of

DATA_SCALE for the meaning of

this field.

D0_SCALE is read only. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0 DATA0 These bits correspond to the PCI

DATA register (offset Register 47

of the PCI configuration space,

bits 7-0). Refer to the description

of DATA register for the meaning

of this field.

DATA0 is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR38: PCI DATA Register One (DATA1) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PMCSR register.

Since these two are read only, BCR38 provides a

means of programming them through the EEPROM.

The contents of this register are copied into the corre-

sponding fields pointed with the DATA_SEL field set to

one. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D1_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offset Register 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

D1_SCALE is read only. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0 DATA1 These bits correspond to the PCI

DATA register (offset Register 47

of the PCI configuration space,

bits 7-0). Refer to the description

of DATA register for the meaning

of this field.

DATA1 is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR39: PCI DATA Register Two (DATA2) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PMCSR register.

Since these two are read only, BCR39 provides a

means of programming them through the EEPROM.

The contents of this register are copied into the corre-

sponding fields pointed to with the DATA_SEL field set

to two. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D2_SCALE These bits correspond to the

DATA_SCALE field of the

PMCSR (offset Register 44 of the

PCI configuration space, bits 14-

13). Refer to the description of

DATA_SCALE for the meaning of

this field.

D2_SCALE is read only. Cleared

by H_RESET and is not affected

224 Am79C976 9/14/00

PRELIMINARY

by S_RESET or setting the STOP

bit.

7-0 DATA2 These bits correspond to the PCI

DATA register (offset Register 47

of the PCI configuration space,

bits 7-0). Refer to the description

of DATA register for the meaning

of this field.

DATA2 is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP bit.

BCR40: PCI DATA Register Three (DATA3) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PCMCR register.

Since these two are read only, BCR40 provides a

means of programming them through the EEPROM.

The contents of this register are copied into the corre-

sponding fields pointed with the DATA_SEL field set to

three. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D3_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offset Register 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

D3_SCALE is read only. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0 DATA3 These bits correspond to the PCI

DATA register (offset Register 47

of the PCI configuration space,

bits 7-0). Refer to the description

of DATA register for the meaning

of this field.

DATA3 is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR41: PCI DATA Register Four (DATA4) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PCMCR register.

Since these two are read only, BCR41 provides a

means of programming them through the EEPROM.

The contents of this register are copied into the corre-

sponding fields pointed with the DATA_SEL field set to

four. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D4_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offset register 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

D4_SCALE is read only. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit

7-0 DATA4 These bits correspond to the PCI

DATA register (offset Register 47

of the PCI configuration space,

bits 7-0). Refer to the description

of DATA register for the meaning

of this field.

DATA4 is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR42: PCI DATA Register Five (DATA5) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PCMCR register.

Since these two are read only, BCR42 provides a

means of programming them through the EEPROM.

The contents of this register are copied into the corre-

sponding fields pointed with the DATA_SEL field set to

five. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D5_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offset Register 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

9/14/00 Am79C976 225

PRELIMINARY

D5_SCALE is read only. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0 DATA5 These bits correspond to the PCI

DATA register (offset Register 47

of the PCI configuration space,

bits 7-0). Refer to the description

of DATA register for the meaning

of this field.

DATA5 is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR43: PCI DATA Register Six (DATA6) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PCMCR register.

Since these two are read only, BCR43 provides a

means of programming them through the EEPROM.

The contents of this register are copied into the corre-

sponding fields pointed with the DATA_SEL field set to

six. Bits 15-0 in this register are programmable through

the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D6_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offset Register 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

D6_SCALE is read only. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit

7-0 DATA6 These bits correspond to the PCI

DATA register (offset Register 47

of the PCI configuration space,

bits 7-0). Refer to the description

of DATA register for the meaning

of this field.

DATA6 is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR44: PCI DATA Register Seven (DATA7) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PCMCR register.

Since these two are read only, BCR44 provides a

means of programming them through the EEPROM.

The contents of this register are copied into the corre-

sponding fields pointed with the DATA_SEL field set to

seven. Bits 15-0 in this register are programmable

through the EEPROM.

Bit Name Description

15-10 RES Reserved locations. Written as

zeros and read as undefined.

9-8 D7_SCALE These bits correspond to the

DATA_SCALE field of the PMC-

SR (offset Register 44 of the PCI

configuration space, bits 14-13).

Refer to the description of

DATA_SCALE for the meaning of

this field.

D7_SCALE is read only. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0 DATA7 These bits correspond to the PCI

DATA register (offset register 47

of the PCI configuration space,

bits 7-0). Refer to the description

of DATA register for the meaning

of this field.

DATA7 is read only. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR45: OnNow Pattern Matching Register 1

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is written and the PMAT_MODE bit is 0,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress of the PMR word to be accessed. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

226 Am79C976 9/14/00

PRELIMINARY

complete the operation. The RAM will not actually be

written until the write to BCR47 is complete. The write

to BCR47 causes all 5 bytes (four bytes of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 PMR_B0 Pattern Match RAM Byte 0. This

byte is written into or read from

Byte 0 of the Pattern Match RAM.

Read and write accessible.

PMR_B0 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

7 PMAT_MODE

Pattern Match Mode. Writing a 1

to this bit will enable Pattern

Match Mode and should only be

done after the Pattern Match

RAM has been programmed.

Read and write accessible.

PMAT_MODE is reset to 0 when

power is initially applied to the de-

vice, and is unaffected by

S_RESET and the STOP bit.

6-0 PMR_ADDR Pattern Match Ram Address.

These bits are the Pattern Match

Ram address to be written to or

read from.

Read and write accessible.

PMR_ADDR is reset to 0 when

power is first applied to the de-

vice (after power-on reset), and is

unaffected by H_RESET,

S_RESET and the STOP bit.

BCR46: OnNow Pattern Matching Register 2

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is written and the PMAT_MODE bit is 0,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress of the PMR word to be accessed. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

written until the write to BCR47 is complete. The write

to BCR47 causes all 5 bytes (four bytes of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 PMR_B2 Pattern Match RAM Byte 2. This

byte is written into or read from

Byte 2 of the Pattern Match RAM.

Read and write accessible.

PMR_B2 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

7-0 PMR_B1 Pattern Match RAM Byte 1. This

byte is written into or read from

Byte 1 of Pattern Match RAM.

Read and write accessible.

PMR_B1 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

BCR47: OnNow Pattern Matching Register 3

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is written and the PMAT_MODE bit is 0,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress of the PMR word to be accessed. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

written until the write to BCR47 is complete. The write

to BCR47 causes all 5 bytes (four bytes of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

When PMAT_MODE is 0, the contents of the word ad-

dressed by bits 6:0 of BCR45 can be read by reading

BCR45-47 in any order.

9/14/00 Am79C976 227

PRELIMINARY

Bit Name Description

31-16 RES Reserved locations. Written as

zeros and read as undefined.

15-8 PMR_B4 Pattern Match RAM Byte 4. This

byte is written into or read from

Byte 4 of Pattern Match RAM.

Read and write accessible.

PMR_B4 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

7-0 PMR_B3 Pattern Match RAM Byte 3. This

byte is written into or read from

Byte 3 of Pattern Match RAM.

Read and write accessible.

PMR_B3 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

Initialization Block

Note: When SSIZE32 (BCR20, bit 8) is set to 0, the

software structures are defined to be 16 bits wide. The

base address of the initialization block must be aligned

to a word boundary, i.e., CSR1, bit 0 must be cleared

to 0. When SSIZE32 is set to 0, the initialization block

looks like Table 96.

Note: The Am79C976 controller performs DWord ac-

cesses to read the initialization block. This statement is

always true, regardless of the setting of the SSIZE32

bit.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide. The base ad-

dress of the initialization block must be aligned to a

DWord boundary, i.e., CSR1, bits 1 and 0 must be

cleared to 0. When SSIZE32 is set to 1, the initialization

block looks like Table 97.

Table 96. Initialization Block (SSIZE32 = 0)

Address Bits 15-13 Bit 12 Bits 11-8 Bits 7-4 Bits 3-0

IADR+00h MODE 15-00

IADR+02h PADR 15-00

IADR+04h PADR 31-16

IADR+06h PADR 47-32

IADR+08h LADRF 15-00

IADR+0Ah LADRF 31-16

IADR+0Ch LADRF 47-32

IADR+0Eh LADRF 63-48

IADR+10h RDRA 15-00

IADR+12h RLEN 0RES RDRA 23-16

IADR+14h TDRA 15-00

IADR+16h TLEN 0RES TDRA 23-16

Table 97. Initialization Block (SSIZE32 = 1)

Address

Bits Bits Bits Bits Bits Bits Bits Bits

31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0

IADR+00h TLEN RES RLEN RES MODE

IADR+04h PADR 31-00

IADR+08h RES PADR 47-32

IADR+0Ch LADRF 31-00

IADR+10h LADRF 63-32

IADR+14h RDRA 31-00

IADR+18h TDRA 31-00

228 Am79C976 9/14/00

PRELIMINARY

RLEN and TLEN

When SSIZE32 (BCR20, bit 8) is set to 0, the software

structures are defined to be 16 bits wide, and the RLEN

and TLEN fields in the initialization block are each three

bits wide. The values in these fields determine the num-

ber of transmit and receive Descriptor Ring Entries

(DRE) which are used in the descriptor rings. Their

meaning is shown in Table 98. If a value other than those

listed in Table 98 is desired, CSR76 and CSR78 can be

written after initialization is complete.

When SSIZE32 (BCR20, bit 8) is set to 1, the software

structures are defined to be 32 bits wide, and the RLEN

and TLEN fields in the initialization block are each 4 bits

wide. The values in these fields determine the number

of transmit and receive Descriptor Ring Entries (DRE)

which are used in the descriptor rings. Their meaning

is shown in Table 99.

If a value other than those listed in Table 99 is desired,

CSR76 and CSR78 can be written after initialization is

complete.

RDRA and TDRA

RDRA and TDRA indicate where the transmit and re-

ceive descriptor rings begin. Each DRE must be located

at a 16-byte address boundary when SSIZE32 is set to

1 (BCR20, bit 8). Each DRE must be located at an

8-byte address boundary when SSIZE32 is set to 0

(BCR20, bit 8).

LADRF

The Logical Address Filter (LADRF) is a 64-bit mask

that is used to accept incoming Logical Addresses. If

the first bit in the incoming address (as transmitted on

the wire) is a 1, it indicates a logical address. If the first

bit is a 0, it is a physical address and is compared

against the physical address that was loaded through

the initialization block.

A logical address is passed through the CRC generator,

producing a 32-bit result. The high order 6 bits of the

CRC is used to select one of the 64 bit positions in the

Logical Address Filter. If the selected filter bit is set, the

address is accepted and the frame is placed into mem-

ory.

The Logical Address Filter is used in multicast address-

ing schemes. The acceptance of the incoming frame

based on the filter value indicates that the message may

be intended for the node. It is the node’s responsibility

to determine if the message is actually intended for the

node by comparing the destination address of the stored

message with a list of acceptable logical addresses.

If the Logical Address Filter is loaded with all zeros and

promiscuous mode is disabled, all incoming logical ad-

dresses except broadcast will be rejected. If the

DRCVBC bit (CSR15, bit 14) is set as well, the broad-

cast packets will be rejected. See Figure 47.

PADR

This 48-bit value represents the unique node address

assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and

used for internal address comparison. PADR[0] is com-

pared with the first bit in the destination address of the

incoming frame. It must be 0 since only the destination

address of a unicast frames is compared to PADR. The

six hex-digit nomenclature used by the ISO 8802-3

(IEEE/ANSI 802.3) maps to the Am79C976 PADR reg-

ister as follows: the first byte is compared with

PADR[7:0], with PADR[0] being the least significant bit

of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3)

byte is compared with PADR[15:8], again from the least

significant bit to the most significant bit, and so on. The

sixth byte is compared with PADR[47:40], the least sig-

nificant bit being PADR[40].

Mode

The mode register field of the initialization block is cop-

ied into CSR15 and interpreted according to the

description of CSR15.

Table 98. R/TLEN Decoding (SSIZE32 = 0)

R/TLEN Number of DREs

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

Table 99. R/TLEN Decoding (SSIZE32 = 1)

R/TLEN Number of DREs

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 512

1X1X 512

11XX 512

Table 99. R/TLEN Decoding (SSIZE32 = 1)

9/14/00 Am79C976 229

PRELIMINARY

Figure 47. Address Match Logic

Receive Descriptors

When SWSTYLE (BCR20, bits 7-0) is set to 0, then the

software structures are defined to be 16 bits wide, and

receive descriptors look like Table 100.

When SWSTYLE is set to 2, then the software struc-

tures are defined to be 32 bits wide, and receive de-

scriptors look like Table 101.

When SWSTYLE is set to 3, then the software struc-

tures are defined to be 32 bits wide, and receive de-

scriptors look like Table 102.

When SWSTYLE is set to 4, then the software struc-

tures are defined to be 32 bits wide, and receive de-

scriptors look like Table 103.

When SWSTYLE is set to 5, then the software struc-

tures are defined to be 32 bits wide, and receive de-

scriptors look like Table 104. Also, when SWSTYLE is

5, the Am79C976 controller uses 64-bit addressing for

software structures that are located above the 32-bit

address boundary.

Table 100. Receive Descriptor (SWSTYLE = 0)

1CRC

GEN

SEL

31 26

MUX

63 0

Match = 1 Packet Accepted

Match = 0 Packet Rejected

Match

Logical

Address Filter

(LADRF)

32-Bit Resultant CRC

Received Message

Destination Address

21485B55

Offset 15 14 13 12 11 10 9 8 7-0

00h RBADR[15:0]

02h OWN ERR FRAM OFLO CRC STP ENP RBADR[23:16]

04h BCNT

06h 0 0 0 0 MCNT

Table 101. Receive Descriptor (SWSTYLE = 2)

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19-16 15-0

00h RBADR[31:0]

04h OWN ERR FRA

OFL

OCRC STP ENP PAM LAFM BAM RES BCNT

08h RES RFRTAG[14:0] MCNT

0Ch USER SPACE

230 Am79C976 9/14/00

PRELIMINARY

Table 102. Receive Descriptor (SWSTYLE = 3)

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19-18 17-16 15-0

00h RFRTAG[14:0] MCNT

04h OWN ERR FRAM OFLO CRC STP ENP PAM LAFM BAM BCNT

08h RBADR[31:0]

0Ch USER SPACE

Table 103. Receive Descriptor (SWSTYLE = 4)

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19-18 17-16 15-0

00h TCI[15:0] MCNT

04h OWN ERR FRAM OFLO CRC STP ENP PAM LAFM BAM TT BCNT

08h RBADR[31:0]

0Ch USER SPACE

Table 104. Receive Descriptor (SWSTYLE = 5)

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19-18 17-16 15-0

00h RFRTAG[31:0]

04h TCI[15:0] MCNT

08h OWN ERR FRAM OFLO CRC STP ENP PAM LAFM BAM TT BCNT

0Ch RBADR[31:0]

10h RBADR[63:32]

14h USER SPACE

18h USER SPACE

1Ch USER SPACE

9/14/00 Am79C976 231

PRELIMINARY

The following tables describe the bits of the receive

descriptors in more detail.

Table 105. Receive Descriptor, SWSTYLE = 0

Offset Bit Name Description

0 15-0 RBADR Receive Buffer Address. This field contains the address of the receive buffer that is

associated with this descriptor.

15 OWN

This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by

the Am79C976 controller (OWN = 1). The host sets the OWN bit after it has emptied

the buffer pointed to by the descriptor entry. The Am79C976 controller clears the

OWN bit after filling the buffer that the description points to. Both the Am79C976

controller and the host must not alter a descriptor entry after it has relinquished

ownership.

14 ERR Error Summary. ERR is the OR of FRAM, OFLO, and CRC. ERR is set by the

Am79C976 controller and cleared by the host.

13 FRAM

Framing error indicates that the incoming frame contains a non-integer multiple of

eight bits and there was an FCS error. If there was no FCS error on the incoming

frame, then FRAM will not be set even if there was a non- integer multiple of eight bits

in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only when

ENP is set and OFLO is not. FRAM is set by the Am79C976 controller and cleared by

the host.

12 OFLO

Overflow error indicates that the receiver has lost all or part of the incoming frame,

due to an inability to move data from the receive FIFO into a memory buffer before the

internal FIFO overflowed. OFLO is set by the Am79C976 controller and cleared by the

host.

11 CRC

CRC indicates that the receiver has detected a CRC (FCS) error on the incoming

frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the

Am79C976 controller and cleared by the host. CRC will also be set when Am79C976

receives an RX_ER indication from the external PHY through the MII.

10 Reserved.

9STP

Start of Packet indicates that this is the first buffer used by the Am79C976 controller

for this frame. If STP and ENP are both set to 1, the frame fits into a single buffer.

Otherwise, the frame is spread over more than one buffer. When LAPPEN (CSR3, bit

5) is cleared to 0, STP is set by the Am79C976 controller and cleared by the host.

When LAPPEN is set to 1, STP must be set by the host.

8ENP

End of Packet indicates that this is the last buffer used by the Am79C976 controller

for this frame. It is used for data chaining buffers. If both STP and ENP are set, the

frame fits into one buffer and there is no data chaining. ENP is set by the Am79C976

controller and cleared by the host.

7-0 RBADR[23:16] Receive Buffer Address (high order bits)

4 15-0 BCNT

Buffer Byte Count is the length of the buffer pointed to by this descriptor, expressed

as the two’s complement of the length of the buffer. This field is written by the host and

unchanged by the Am79C976 controller.

15-12 ZEROS This field is reserved. Am79C976 controller will write zeros to these locations.

11-0 MCNT

Message Byte Count is the number of bytes of the received message written to the

receive buffer. This is the actual frame length (including FCS) unless stripping is

enabled and the length field is < 46 bytes. In this case, MCNT is 14 + length_field.

MCNT can take values in the range 15 to 59 and values greater than or equal to 64.

MCNT is expressed as an unsigned binary integer. MCNT is valid only when ERR is

clear and ENP is set. MCNT is written by the Am79C976 controller and cleared by the

host.

232 Am79C976 9/14/00

PRELIMINARY

Table 106. Receive Descriptor, SWSTYLE = 2

Offset Bit Name Description

0 31-0 RBADR[31:0] Receive Buffer Address. This field contains the address of the receive buffer that is

associated with this descriptor.

431 OWN

This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by

the Am79C976 controller (OWN = 1). The host sets the OWN bit after it has emptied

the buffer pointed to by the descriptor entry. The Am79C976 controller clears the

OWN bit after filling the buffer that the descriptor points to. Both the Am79C976

controller and the host must not alter a descriptor entry after it has relinquished

ownership.

430 ERR Error Summary. ERR is the OR of FRAM, OFLO, and CRC. ERR is set by the

Am79C976 controller and cleared by the host.

429 FRAM

Framing error indicates that the incoming frame contains a non-integer multiple of

eight bits and there was an FCS error. If there was no FCS error on the incoming

frame, then FRAM will not be set even if there was a non-integer multiple of eight bits

in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only when

ENP is set and OFLO is not. FRAM is set by the Am79C976 controller and cleared

by the host.

428 OFLO

Overflow error indicates that the receiver has lost all or part of the incoming frame,

due to an inability to move data from the receive FIFO into a memory buffer before

the internal FIFO overflowed. OFLO is set by the Am79C976 controller and cleared

by the host.

4 27 CRC

CRC indicates that the receiver has detected a CRC (FCS) error on the incoming

frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the

Am79C976 controller and cleared by the host. CRC will also be set when Am79C976

controller receives an RX_ER indication from the external PHY through the MII.

4 26 Reserved.

425 STP

Start of Packet indicates that this is the first buffer used by the Am79C976 controller

for this frame. If STP and ENP are both set to 1, the frame fits into a single buffer.

Otherwise, the frame is spread over more than one buffer. When LAPPEN (CSR3,

bit 5) is cleared to 0, STP is set by the Am79C976 controller and cleared by the host.

When LAPPEN is set to 1, STP must be set by the host.

424 ENP

End of Packet indicates that this is the last buffer used by the Am79C976 controller

for this frame. It is used for data chaining buffers. If both STP and ENP are set, the

frame fits into one buffer and there is no data chaining. ENP is set by the Am79C976

controller and cleared by the host.

4 23 Reserved.

422 PAM

Physical Address Match is set by the Am79C976 controller when it accepts the

received frame due to a match of the frame’s destination address with the content of

the physical address register. PAM is valid only when ENP is set. PAM is set by the

Am79C976 controller and cleared by the host.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

9/14/00 Am79C976 233

PRELIMINARY

421 LAFM

Logical Address Filter Match is set by the Am79C976 controller when it accepts the

received frame based on the value in the logical address filter register. LAFM is valid

only when ENP is set. LAFM is set by the Am79C976 controller and cleared by the

host.

Note that if DRCVBC (CSR15, bit 14) is cleared to 0, only BAM, but not LAFM will be

set when a Broadcast frame is received, even if the Logical Address Filter is

programmed in such a way that a Broadcast frame would pass the hash filter. If

DRCVBC is set to 1 and the Logical Address Filter is programmed in such a way that

a Broadcast frame would pass the hash filter, LAFM will be set on the reception of a

Broadcast frame.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

4 20 BAM

Broadcast Address Match is set by the Am79C976 controller when it accepts the

received frame, because the frame’s destination address is of the type ’Broadcast.’

BAM is valid only when ENP is set. BAM is set by the Am79C976 controller and

cleared by the host.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

4 19-16 Reserved.

415-0 BCNT

Buffer Byte Count is the length of the buffer pointed to by this descriptor, expressed

as the two’s complement of the length of the buffer. This field is written by the host

and unchanged by the Am79C976 controller.

31 Reserved.

30-16 RFRTAG[14:0]

Receive Frame Tag. Indicates the Receive Frame Tag applied from the EADI

interface. This field is user defined and has a default value of all zeros. When

RXFRTG (CSR7, bit 14) is set to 0, RFRTAG will be read as all zeros. See the section

on Receive Frame Tagging for details.

15-0 MCNT

Message Byte Count is the number of bytes of the received message written to the

receive buffer. This is the actual frame length (including FCS) unless stripping is

enabled and the length field is < 46 bytes. In this case, MCNT is 14 + length_field.

MCNT can take values in the range 15 to 59 and values greater than or equal to 64.

MCNT is expressed as an unsigned binary integer. MCNT is valid only when ERR is

clear and ENP is set. MCNT is written by the Am79C976 controller and cleared by

the host.

0Ch 31:0 USER SPACE User Space. Reserved for user defined data.

Offset Bit Name Description

234 Am79C976 9/14/00

PRELIMINARY

Table 107. Receive Descriptor, SWSTYLE = 3

Offset Bit Name Description

31 Reserved

30-16 RFRTAG[14:0]

Receive Frame Tag. Indicates the Receive Frame Tag applied from the EADI

interface. This field is user defined and has a default value of all zeros. When

RXFRTG (CSR7, bit 14) is set to 0, RFRTAG will be read as all zeros. See the

section on Receive Frame Tagging for details.

15-0 MCNT

Message Byte Count is the number of bytes of the received message written to the

receive buffer. This is the actual frame length (including FCS) unless stripping is

enabled and the length field is < 46 bytes. In this case, MCNT is 14 + length_field.

MCNT can take values in the range 15 to 59 and values greater than or equal to 64.

MCNT is expressed as an unsigned binary integer. MCNT is valid only when ERR is

clear and ENP is set. MCNT is written by the Am79C976 controller and cleared by

the host.

431 OWN

This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by

the Am79C976 controller (OWN = 1). The host sets the OWN bit after it has emptied

the buffer pointed to by the descriptor entry. The Am79C976 controller clears the

OWN bit after filling the buffer that the descriptor points to. Both the Am79C976

controller and the host must not alter a descriptor entry after it has relinquished

ownership.

430 ERR Error Summary. ERR is the OR of FRAM, OFLO, and CRC. ERR is set by the

Am79C976 controller and cleared by the host.

429 FRAM

Framing error indicates that the incoming frame contains a non-integer multiple of

eight bits and there was an FCS error. If there was no FCS error on the incoming

frame, then FRAM will not be set even if there was a non-integer multiple of eight

bits in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only

when ENP is set and OFLO is not. FRAM is set by the Am79C976 controller and

cleared by the host.

428 OFLO

Overflow error indicates that the receiver has lost all or part of the incoming frame,

due to an inability to move data from the receive FIFO into a memory buffer before

the internal FIFO overflowed. OFLO is set by the Am79C976 controller and cleared

by the host.

4 27 CRC

CRC indicates that the receiver has detected a CRC (FCS) error on the incoming

frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the

Am79C976 controller and cleared by the host. CRC will also be set when Am79C976

controller receives an RX_ER indication from the external PHY through the MII.

4 26 Reserved.

425 STP

Start of Packet indicates that this is the first buffer used by the Am79C976 controller

for this frame. If STP and ENP are both set to 1, the frame fits into a single buffer.

Otherwise, the frame is spread over more than one buffer. When LAPPEN (CSR3,

bit 5) is cleared to 0, STP is set by the Am79C976 controller and cleared by the host.

When LAPPEN is set to 1, STP must be set by the host.

424 ENP

End of Packet indicates that this is the last buffer used by the Am79C976 controller

for this frame. It is used for data chaining buffers. If both STP and ENP are set, the

frame fits into one buffer and there is no data chaining. ENP is set by the Am79C976

controller and cleared by the host.

4 23 Reserved.

9/14/00 Am79C976 235

PRELIMINARY

Table 108. Receive Descriptor, SWSTYLE = 4

422 PAM

Physical Address Match is set by the Am79C976 controller when it accepts the

received frame due to a match of the frame’s destination address with the content of

the physical address register. PAM is valid only when ENP is set. PAM is set by the

Am79C976 controller and cleared by the host.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

421 LAFM

Logical Address Filter Match is set by the Am79C976 controller when it accepts the

received frame based on the value in the logical address filter register. LAFM is valid

only when ENP is set. LAFM is set by the Am79C976 controller and cleared by the

host.

Note that if DRCVBC (CSR15, bit 14) is cleared to 0, only BAM, but not LAFM will

be set when a Broadcast frame is received, even if the Logical Address Filter is

programmed in such a way that a Broadcast frame would pass the hash filter. If

DRCVBC is set to 1 and the Logical Address Filter is programmed in such a way that

a Broadcast frame would pass the hash filter, LAFM will be set on the reception of a

Broadcast frame.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

4 20 BAM

Broadcast Address Match is set by the Am79C976 controller when it accepts the

received frame, because the frame’s destination address is of the type ’Broadcast.’

BAM is valid only when ENP is set. BAM is set by the Am79C976 controller and

cleared by the host.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

4 19-16 Reserved.

4 15-0 BCNT

Buffer Byte Count is the length of the buffer pointed to by this descriptor, expressed

as the two’s complement of the length of the buffer. This field is written by the host

and unchanged by the Am79C976 controller.

8 31-0 RBADR[31:0] Receive Buffer Address. This field contains the address of the receive buffer that is

associated with this descriptor.

0Ch 31:0 USER SPACE User Space. Reserved for user defined data.

Offset Bit Name Description

31-16 TCI[15:0] VLAN Tag Control Information copied from the received frame.

15-0 MCNT

Message Byte Count is the number of bytes of the received message written to the

receive buffer. This is the actual frame length (including FCS) unless stripping is

enabled and the length field is < 46 bytes. In this case, MCNT is 14 + length_field.

MCNT can take values in the range 15 to 59 and values greater than or equal to 64.

MCNT is expressed as an unsigned binary integer. MCNT is valid only when ERR is

clear and ENP is set. MCNT is written by the Am79C976 controller and cleared by

the host.

431 OWN

This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by

the Am79C976 controller (OWN = 1). The host sets the OWN bit after it has emptied

the buffer pointed to by the descriptor entry. The Am79C976 controller clears the

OWN bit after filling the buffer that the descriptor points to. Both the Am79C976

controller and the host must not alter a descriptor entry after it has relinquished

ownership.

Offset Bit Name Description

236 Am79C976 9/14/00

PRELIMINARY

430 ERR Error Summary. ERR is the OR of FRAM, OFLO, and CRC. ERR is set by the

Am79C976 controller and cleared by the host.

429 FRAM

Framing error indicates that the incoming frame contains a non-integer multiple of

eight bits and there was an FCS error. If there was no FCS error on the incoming

frame, then FRAM will not be set even if there was a non-integer multiple of eight

bits in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only

when ENP is set and OFLO is not. FRAM is set by the Am79C976 controller and

cleared by the host.

428 OFLO

Overflow error indicates that the receiver has lost all or part of the incoming frame,

due to an inability to move data from the receive FIFO into a memory buffer before

the internal FIFO overflowed. OFLO is set by the Am79C976 controller and cleared

by the host.

4 27 CRC

CRC indicates that the receiver has detected a CRC (FCS) error on the incoming

frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the

Am79C976 controller and cleared by the host. CRC will also be set when Am79C976

controller receives an RX_ER indication from the external PHY through the MII.

4 26 Reserved.

425 STP

Start of Packet indicates that this is the first buffer used by the Am79C976 controller

for this frame. If STP and ENP are both set to 1, the frame fits into a single buffer.

Otherwise, the frame is spread over more than one buffer. When LAPPEN (CSR3,

bit 5) is cleared to 0, STP is set by the Am79C976 controller and cleared by the host.

When LAPPEN is set to 1, STP must be set by the host.

424 ENP

End of Packet indicates that this is the last buffer used by the Am79C976 controller

for this frame. It is used for data chaining buffers. If both STP and ENP are set, the

frame fits into one buffer and there is no data chaining. ENP is set by the Am79C976

controller and cleared by the host.

4 23 Reserved.

422 PAM

Physical Address Match is set by the Am79C976 controller when it accepts the

received frame due to a match of the frame’s destination address with the content of

the physical address register. PAM is valid only when ENP is set. PAM is set by the

Am79C976 controller and cleared by the host.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

421 LAFM

Logical Address Filter Match is set by the Am79C976 controller when it accepts the

received frame based on the value in the logical address filter register. LAFM is valid

only when ENP is set. LAFM is set by the Am79C976 controller and cleared by the

host.

Note that if DRCVBC (CSR15, bit 14) is cleared to 0, only BAM, but not LAFM will

be set when a Broadcast frame is received, even if the Logical Address Filter is

programmed in such a way that a Broadcast frame would pass the hash filter. If

DRCVBC is set to 1 and the Logical Address Filter is programmed in such a way that

a Broadcast frame would pass the hash filter, LAFM will be set on the reception of a

Broadcast frame.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

Offset Bit Name Description

9/14/00 Am79C976 237

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Table 109. Receive Descriptor, SWSTYLE = 5

4 20 BAM

Broadcast Address Match is set by the Am79C976 controller when it accepts the

received frame, because the frame’s destination address is of the type ’Broadcast.’

BAM is valid only when ENP is set. BAM is set by the Am79C976 controller and

cleared by the host.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

4 19-18 TT[1:0]

VLAN Tag Type. Indicates what type of VLAN tag, if any, is included in the received

frame.

00 = Reserved

01 = Frame is Untagged

10 = Frame is Priority-tagged

11 = Frame is VLAN-tagged

4 17-16 Reserved.

4 15-0 BCNT

Buffer Byte Count is the length of the buffer pointed to by this descriptor, expressed

as the two’s complement of the length of the buffer. This field is written by the host

and unchanged by the Am79C976 controller.

8 31-0 RBADR[31:0] Receive Buffer Address. This field contains the address of the receive buffer that is

associated with this descriptor.

0Ch 31:0 USER SPACE User Space. Reserved for user defined data.

Offset Bit Name Description

0 31-0 RFRTAG[31:0]

Receive Frame Tag. Indicates the Receive Frame Tag applied from the EADI

interface. This field is user defined and has a default value of all zeros. When

RXFRTG (CSR7, bit 14) is set to 0, RFRTAG will be read as all zeros. See the

section on Receive Frame Tagging for details.

31-16 TCI[15:0] VLAN Tag Control Information copied from the received frame.

15-0 MCNT

Message Byte Count is the number of bytes of the received message written to the

receive buffer. This is the actual frame length (including FCS) unless stripping is

enabled and the length field is < 46 bytes. In this case, MCNT is 14 + length_field.

MCNT can take values in the range 15 to 59 and values greater than or equal to 64.

MCNT is expressed as an unsigned binary integer. MCNT is valid only when ERR is

clear and ENP is set. MCNT is written by the Am79C976 controller and cleared by

the host.

831 OWN

This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by

the Am79C976 controller (OWN = 1). The host sets the OWN bit after it has emptied

the buffer pointed to by the descriptor entry. The Am79C976 controller clears the

OWN bit after filling the buffer that the descriptor points to. Both the Am79C976

controller and the host must not alter a descriptor entry after it has relinquished

ownership.

830 ERR Error Summary. ERR is the OR of FRAM, OFLO, and CRC. ERR is set by the

Am79C976 controller and cleared by the host.

829 FRAM

Framing error indicates that the incoming frame contains a non-integer multiple of

eight bits and there was an FCS error. If there was no FCS error on the incoming

frame, then FRAM will not be set even if there was a non-integer multiple of eight

bits in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only

when ENP is set and OFLO is not. FRAM is set by the Am79C976 controller and

cleared by the host.

Offset Bit Name Description

238 Am79C976 9/14/00

PRELIMINARY

828 OFLO

Overflow error indicates that the receiver has lost all or part of the incoming frame,

due to an inability to move data from the receive FIFO into a memory buffer before

the internal FIFO overflowed. OFLO is set by the Am79C976 controller and cleared

by the host.

8 27 CRC

CRC indicates that the receiver has detected a CRC (FCS) error on the incoming

frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the

Am79C976 controller and cleared by the host. CRC will also be set when Am79C976

controller receives an RX_ER indication from the external PHY through the MII.

8 26 Reserved.

825 STP

Start of Packet indicates that this is the first buffer used by the Am79C976 controller

for this frame. If STP and ENP are both set to 1, the frame fits into a single buffer.

Otherwise, the frame is spread over more than one buffer. When LAPPEN (CSR3,

bit 5) is cleared to 0, STP is set by the Am79C976 controller and cleared by the host.

When LAPPEN is set to 1, STP must be set by the host.

824 ENP

End of Packet indicates that this is the last buffer used by the Am79C976 controller

for this frame. It is used for data chaining buffers. If both STP and ENP are set, the

frame fits into one buffer and there is no data chaining. ENP is set by the Am79C976

controller and cleared by the host.

8 23 Reserved.

822 PAM

Physical Address Match is set by the Am79C976 controller when it accepts the

received frame due to a match of the frame’s destination address with the content of

the physical address register. PAM is valid only when ENP is set. PAM is set by the

Am79C976 controller and cleared by the host.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

821 LAFM

Logical Address Filter Match is set by the Am79C976 controller when it accepts the

received frame based on the value in the logical address filter register. LAFM is valid

only when ENP is set. LAFM is set by the Am79C976 controller and cleared by the

host.

Note that if DRCVBC (CSR15, bit 14) is cleared to 0, only BAM, but not LAFM will

be set when a Broadcast frame is received, even if the Logical Address Filter is

programmed in such a way that a Broadcast frame would pass the hash filter. If

DRCVBC is set to 1 and the Logical Address Filter is programmed in such a way that

a Broadcast frame would pass the hash filter, LAFM will be set on the reception of a

Broadcast frame.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

8 20 BAM

Broadcast Address Match is set by the Am79C976 controller when it accepts the

received frame, because the frame’s destination address is of the type ’Broadcast.’

BAM is valid only when ENP is set. BAM is set by the Am79C976 controller and

cleared by the host.

This bit does not exist when the Am79C976 controller is programmed to use 16-bit

software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is

cleared to 0).

8 19-18 TT[1:0]

VLAN Tag Type. Indicates what type of VLAN tag, if any, is included in the received

frame.

00 = Reserved

01 = Frame is Untagged

10 = Frame is Priority-tagged

11 = Frame is VLAN-tagged

8 17-16 Reserved.

Offset Bit Name Description

9/14/00 Am79C976 239

PRELIMINARY

815-0 BCNT

Buffer Byte Count is the length of the buffer pointed to by this descriptor, expressed

as the two’s complement of the length of the buffer. This field is written by the host

and unchanged by the Am79C976 controller.

0Ch 31-0 RBADR[31:0] Receive Buffer Address. This field contains the low order bits of the address of the

receive buffer that is associated with this descriptor.

10h 31-0 RBADR[63:32] Receive Buffer Address. This field contains the high order bits of the address of the

receive buffer that is associated with this descriptor.

14h 31:0 USER SPACE User Space. Reserved for user defined data.

18h 31:0 USER SPACE User Space. Reserved for user defined data.

1Ch 31:0 USER SPACE User Space. Reserved for user defined data.

Offset Bit Name Description

240 Am79C976 9/14/00

PRELIMINARY

Transmit Descriptors

When SWSTYLE (BCR20, bits 7-0) is set to 0, the soft-

ware structures are defined to be 16 bits wide, and

transmit descriptors look like Table 110.

When SWSTYLE is set to 2, the software structures

are defined to be 32 bits wide, and transmit descriptors

look like Table 111.

When SWSTYLE is set to 3, then the software struc-

tures are defined to be 32 bits wide, and transmit de-

scriptors look like Table 112.

When SWSTYLE is set to 4, then the software struc-

tures are defined to be 32 bits wide, and transmit de-

scriptors look like Table 113.

When SWSTYLE is set to 5, then the software struc-

tures are defined to be 32 bits wide, and transmit de-

scriptors look like Table 114. Also when SWSTYLE is

5, the Am79C976 controller uses 64-bit addressing for

software structures that are located above the 32-bit

address boundary.

Table 110. Transmit Descriptor (SWSTYLE = 0)

Offset 15 14 13 12 11 10 9 8 7-0

00h TBADR[15:0]

02h OWN ADD_

FCS LTINT STP ENP TBADR[23:16]

04h BCNT

06h Reserved

Table 111. Transmit Descriptor (SWSTYLE = 2)

Offset 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0

00h TBADR[31:0]

04h OWN ADD_

FCS LTINT STP ENP BCNT

08h Reserved

0Ch USER SPACE

Table 112. Transmit Descriptor (SWSTYLE = 3)

Offset 31 30 29 28 27 26 25 24 23 22-16 15-0

00h Reserved

04h OWN ADD_

FCS LTINT STP ENP BCNT

08h TBADR[31:0]

0Ch USER SPACE

Table 113. Transmit Descriptor (SWSTYLE = 4)

Offset 31 30 29 28 27-26 25 24 23 22 21-18 17-16 15-0

00h OWN ADD_

FCS LTINT STP ENP KILL BCNT

04h TCC[1:0] TCI[15:0]

08h TBADR[31:0]

0Ch USER SPACE

9/14/00 Am79C976 241

PRELIMINARY

The following tables describe the transmit descriptor

bits in more detail.

Table 115. Transmit Descriptor, SWSTYLE = 0

Table 114. Transmit Descriptor (SWSTYLE = 5)

Offset 31 30 29 28 27-26 25 24 23 22 21-18 17-16 15-0

00h OWN ADD_

FCS LTINT STP ENP KILL BCNT

04h TCC[1:0] TCI[15:0]

08h TBADR[31:0]

0Ch TBADR[63:32]

10h Reserved

14h USER SPACE

18h USER SPACE

1Ch USER SPACE

Offset Bit Name Description

0 15-0 TBADR[15:0] Transmit Buffer Address. This field contains the high order bits of the address of the

Transmit buffer that is associated with this descriptor.

215 OWN

This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by

the Am79C976 controller (OWN = 1). The host sets the OWN bit after filling the buffer

pointed to by the descriptor entry. The Am79C976 controller clears the OWN bit after

transmitting the contents of the buffer. Both the Am79C976 controller and the host

must not alter a descriptor entry after it has relinquished ownership.

2 14 Reserved location.

2 13 ADD_FCS

ADD_FCS dynamically controls the generation of FCS on a frame by frame basis.

This bit should be set with the ENP bit. However, for backward compatibility, it is

recommended that this bit be set for every descriptor of the intended frame. When

ADD_FCS is set, the state of DXMTFCS is ignored and transmitter FCS generation is

activated. When ADD_FCS is cleared to 0, FCS generation is controlled by

DXMTFCS. When APAD_XMT (CSR4, bit 11) is set to 1, the setting of ADD_FCS has

no effect. ADD_FCS is set by the host, and is not changed by the Am79C976

controller. This is a reserved bit in the C-LANCE (Am79C90) controller.

212 LTINT

Last Transmit Interrupt. When enabled by the LTINTEN bit (CSR5, bit 14), LTINT is

used to suppress interrupts after selected frames have been copied to the transmit

FIFO. When LTINT is cleared to 0 and ENP is set to 1, the Am79C976 controller will

not set TINT (CSR0, bit 9) after the corresponding frame has been copied to the

transmit FIFO. TINT will only be set when the last descriptor of a frame has both

LTINT and ENP set to 1. When LTINTEN is cleared to 0, the LTINT bit is ignored.

2 11-10 Reserved.

29 STP

Start of Packet indicates that this is the first buffer to be used by the Am79C976

controller for this frame. It is used for data chaining buffers. The STP bit must be set

in the first buffer of the frame, or the Am79C976 controller will skip over the descriptor

and poll the next descriptor(s) until the OWN and STP bits are set. STP is set by the

host and is not changed by the Am79C976 controller.

28 ENP

End of Packet indicates that this is the last buffer to be used by the Am79C976

controller for this frame. It is used for data chaining buffers. If both STP and ENP are

set, the frame fits into one buffer and there is no data chaining. ENP is set by the host

and is not changed by the Am79C976 controller.

242 Am79C976 9/14/00

PRELIMINARY

2 7-0 TBADR[23:16] Transmit Buffer Address (high order bits)

4 15-0 BCNT

Buffer Byte Count is the usable length of the buffer pointed to by this descriptor,

expressed as the two’s complement of the length of the buffer. This is the number of

bytes from this buffer that will be transmitted by the Am79C976 controller. This field is

written by the host and is not changed by the Am79C976 controller. There are no

minimum buffer size restrictions.

6 15-0 Reserved.

Offset Bit Name Description

Table 116. Transmit Descriptor, SWSTYLE = 2

Offset Bit Name Description

0 31-0 TBADR[31:0] Transmit Buffer Address. This field contains the address of the Transmit buffer that is

associated with this descriptor.

431 OWN

This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by

the Am79C976 controller (OWN = 1). The host sets the OWN bit after filling the buffer

pointed to by the descriptor entry. The Am79C976 controller clears the OWN bit after

transmitting the contents of the buffer. Both the Am79C976 controller and the host

must not alter a descriptor entry after it has relinquished ownership.

4 30 Reserved location.

4 29 ADD_FCS