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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUITS PD789101, 789102, 789104, 789111, 789112, 789114 8-BIT SINGLE-CHIP MICROCONTROLLERS The PD789101, 789102, and 789104 are PD789104 Subseries products of the 78K/0S Series. The PD789111, 789112, and 789114 are PD789114 Subseries products of the 78K/0S Series. Besides an 8-bit CPU, these microcontrollers incorporate a variety of hardware such as I/O ports, timers, a serial interface, A/D converters, and interrupt control. In addition, a flash memory version (PD78F9116) that can operate within the same power supply voltage range as the mask ROM version, and a range of development tools are also being developed. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD789104, 789114, 789124, 789134 Subseries User's Manual: U13045E 78K/0S Series User's Manual Instruction: U11047E FEATURES * On-chip multiplier: 8 bits x 8 bits = 16 bits * ROM and RAM sizes Item Program Memory (ROM) Data Memory (Internal High-Speed RAM) PD789101, 789111 2 Kbytes 256 bytes PD789102, 789112 4 Kbytes PD789104, 789114 8 Kbytes Part Number Package 30-pin plastic shrink SOP (300 mils) (GS type, MC-5A4 type) * Minimum instruction execution time can be changed from high-speed (0.4 s) to low-speed (1.6 s) (@ 5.0-MHz operation with system clock) * I/O ports: 20 * Serial interface: 1 channel: Switchable between 3-wire serial I/O and UART modes * 8-bit resolution A/D converter: 4 channels (PD789101, 789102, 789104) * 10-bit resolution A/D converter: 4 channels (PD789111, 789112, 789114) * Timers: 3 channels * 16-bit timer: 1 channel * 8-bit timer/event counter: 1 channel * Watchdog timer: 1 channel * Power supply voltage: VDD = 2.7 to 5.5 V APPLICATIONS Cleaners, washing machines, and refrigerators The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12815EJ2V1DS00 (2nd edition) Date Published November 1999 N CP(K) Printed in Japan The mark shows major revised points. (c) 1997, 1999 PD789101, 789102, 789104, 789111, 789112, 789114 ORDERING INFORMATION Part Number Package PD789101GS-xxx 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789101MC-xxx-5A4 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789102GS-xxx 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789102MC-xxx-5A4 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789104GS-xxx 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789104MC-xxx-5A4 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789111GS-xxx 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789111MC-xxx-5A4 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789112GS-xxx 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789112MC-xxx-5A4 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789114GS-xxx 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789114MC-xxx-5A4 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) Remark 2 xxx indicates ROM code suffix. Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 78K/0S SERIES LINEUP The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass-production Products under development Small-scale package, general-purpose applications 44-pin PD789046 PD789026 with internal subsystem clock 42/44-pin 28-pin PD789026 PD789014 PD789014 with enhanced timer function and expanded ROM and RAM On-chip UART and capable of low-voltage (1.8 V) operation Small-scale package, general-purpose applications and A/D function 44/48-pin 44/48-pin 44-pin 44-pin 30-pin 30-pin 28/30-pin 28/30-pin 28/30-pin 28/30-pin PD789217AY PD789197AY PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A RC oscillation version of the PD789197AY PD789177 with internal EEPROMTM and SMB PD789167 with enhanced A/D converter PD789104A with enhanced timer PD789146 with enhanced A/D converter PD789104A with EEPROM PD789124A with enhanced A/D converter RC oscillation version of the PD789104A PD789104A with enhanced A/D converter PD789026 with A/D converter and multiplier For Inverter control 44-pin 78K/0S Series PD789842 On-chip inverter control circuit and UART For LCD drive 88-pin PD789830 On-chip UART and dot LCD 80-pin PD789417A PD789407A PD789457 PD789447 PD789437 PD789427 PD789316 PD789306 PD789407A with enhanced A/D converter PD789457 with enhanced I/O PD789447 with enhanced A/D converter RC oscillation version of the PD789427 PD789427 with enhanced A/D converter PD789306 with A/D converter RC oscillation version of the PD789306 Basic subseries for LCD drive 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin For ASSP 42/44-pin 44-pin 20-pin 20-pin PD789800 PD789840 PD789861 PD789860 For PC keyboard, on-chip USB function For key pad, on-chip POC RC oscillation version of the PD789860 For keyless entry, on-chip key return circuit For IC card 5-pin PD789810 On-chip EEPROM and security circuit Data Sheet U12815EJ2V1DS00 3 PD789101, 789102, 789104, 789111, 789112, 789114 The major functional differences among the subseries are listed below. Function Subseries Name Small-scale PD789046 package, PD789026 generalpurpose applications PD789014 ROM Capacity 16 K Timer 8-bit 16-bit Watch WDT 1ch 1ch 4 K to 16 K 1ch 10-bit A/D Serial Interface I/O VDD MIN. Value Remark - - 1ch (UART: 1ch) 34 1.8 V - 1.8 V RC oscillation version, onchip EEPROM - 2 K to 4 K 2 ch Small-scale PD789217AY 16 K to package, 24 K generalpurpose PD789197AY applications + A/D converter PD789177 1ch 8-bit A/D 3 ch - 1 ch 22 1 ch 1 ch - 8 ch On-chip EEPROM 1 ch (UART: 1 ch) 8 ch - - 4 ch 4 ch - - 4 ch PD789124A 4 ch - PD789114A - 4 ch PD789104A 4 ch - PD789146 PD789134A 8 K to 16 K 31 SMB: 1ch PD789167 PD789156 2ch UART: 1ch - 1 ch 2 K to 8 K - On-chip EEPROM 20 RC oscillation version - Inverter control PD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch - 1 ch (UART: 1 ch) 30 4.0 V - LCD drive PD789830 24 K 1 ch 1 ch - - 1 ch (UART: 1 ch) 30 2.7 V - PD789417A 12 K to 24 K 3 ch 7 ch 43 1.8 V 7 ch - 25 16 K to 24 K 2 ch - 4 ch 4 ch - PD789437 - 4 ch PD789427 4 ch - PD789407A PD789457 PD789447 PD789316 1 ch 1 ch 8 K to 16 K RC oscillation version 2 ch (UART: 1 ch) - - RC oscillation version 23 PD789306 ASSP PD789800 - 8K 2 ch 1 ch - 1 ch PD789840 PD789861 - - 4 ch 4K - - 2 ch (USB: 1 ch) 31 4.0 V 1 ch 29 2.8 V 14 1.8 V - PD789860 IC card PD789810 RC oscillation version - 6K - - - 1 ch - - Note 10-bit timer: 1 channel 4 - Data Sheet U12815EJ2V1DS00 - 1 2.7 V On-chip EEPROM PD789101, 789102, 789104, 789111, 789112, 789114 OVERVIEW OF FUNCTIONS PD789101 PD789111 Item Internal memory ROM 2 Kbytes High-speed RAM 256 bytes PD789102 PD789112 PD789104 PD789114 4 Kbytes 8 Kbytes Minimum instruction execution time 0.4/1.6 s (@ 5.0-MHz operation with system clock) General-purpose registers 8 bits x 8 registers Instruction set * 16-bit operations * Bit manipulations (set, reset, and test) Multiplier 8 bits x 8 bits = 16 bits I/O ports Total: 20 * CMOS input: * CMOS I/O: * N-ch open-drain (12-V withstand voltage): 4 12 4 * 8-bit resolution x 4 channels (PD789104 Subseries) A/D converters * 10-bit resolution x 4 channels (PD789114 Subseries) Serial interface * Switchable between 3-wire serial I/O and UART modes Timer * 16-bit timer: 1 channel * 8-bit timer/event counter: 1 channel * Watchdog timer: 1 channel Timer output 1 output (16-bit/8-bit timer alternate function) Vectored interrupt sources Maskable Internal: 6, External: 3 Non-maskable Internal: 1 Power supply voltage VDD = 2.7 to 5.5 V Operating ambient temperature TA = -40 to +85C Package * 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) * 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) Data Sheet U12815EJ2V1DS00 5 PD789101, 789102, 789104, 789111, 789112, 789114 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) .............................................................................................. 7 2. BLOCK DIAGRAM ........................................................................................................................... 8 3. PIN FUNCTIONS............................................................................................................................... 9 4. 5. 3.1 Port Pins.................................................................................................................................................. 9 3.2 Non-Port Pins.......................................................................................................................................... 10 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins...................................................... 11 MEMORY SPACE ............................................................................................................................. 13 PERIPHERAL HARDWARE FUNCTIONS...................................................................................... 14 5.1 Ports ........................................................................................................................................................ 14 5.2 Clock Generator...................................................................................................................................... 14 5.3 Timer........................................................................................................................................................ 15 5.4 A/D Converter ......................................................................................................................................... 17 5.5 Serial Interface 20................................................................................................................................... 18 5.6 Multiplier.................................................................................................................................................. 19 6. INTERRUPT FUNCTION .................................................................................................................. 20 7. STANDBY FUNCTION ..................................................................................................................... 22 8. RESET FUNCTION ........................................................................................................................... 22 9. INSTRUCTION SET OVERVIEW..................................................................................................... 23 9.1 Conventions............................................................................................................................................ 23 9.2 Operations............................................................................................................................................... 25 10. ELECTRICAL SPECIFICATIONS .................................................................................................... 30 11. CHARACTERISTICS CURVES (REFERENCE VALUES) ............................................................. 45 12. PACKAGE DRAWING ...................................................................................................................... 48 13. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 50 APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 52 APPENDIX B RELATED DOCUMENTS .............................................................................................. 54 6 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 1. PIN CONFIGURATION (TOP VIEW) * 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789101GS-xxx PD789102GS-xxx PD789104GS-xxx PD789111GS-xxx PD789112GS-xxx PD789114GS-xxx * 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789101MC-xxx-5A4 PD789102MC-xxx-5A4 PD789104MC-xxx-5A4 PD789111MC-xxx-5A4 PD789112MC-xxx-5A4 PD789114MC-xxx-5A4 P23/INTP0/CPT20/SS20 1 30 P22/SI20/RXD20 P24/INTP1/TO80/TO20 2 29 P21/SO20/TXD20 P25/INTP2/TI80 3 28 P20/SCK20/ASCK20 AVDD 4 27 P11 P60/ANI0 5 26 P10 P61/ANI1 6 25 VDD P62/ANI2 7 24 VSS P63/ANI3 8 23 X1 AVSS 9 22 X2 IC0 10 21 IC0 P50 11 20 IC0 P51 12 19 RESET P52 13 18 P03 P53 14 17 P02 P00 15 16 P01 Cautions 1. Connect the IC0 (Internally Connected) pin directly to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. ANI0 to ANI3: Analog Input RESET: Reset ASCK20: Asynchronous Serial Input RXD20: Receive Data AVDD: Analog Power Supply SCK20: Serial Clock Input/Output AVSS: Analog Ground SI20: Serial Data Input CPT20: Capture Trigger Input SO20: Serial Data Output IC0: Internally Connected SS20: Chip Select Input INTP0 to INTP2: Interrupt from Peripherals TI80: Timer Input P00 to P03: Port0 TO20, TO80: Timer Output P10, P11: Port1 TXD20: Transmit Data P20 to P25: Port2 VDD: Power Supply P50 to P53: Port5 VSS: Ground P60 to P63: Port6 X1, X2: Crystal 1, 2 Data Sheet U12815EJ2V1DS00 7 PD789101, 789102, 789104, 789111, 789112, 789114 2. BLOCK DIAGRAM TI80/INTP2/P25 TO80/TO20 /INTP1/P24 TO20/TO80 /INTP1/P24 8-BIT TIMER EVENT/COUNTER 80 16-BIT TIMER 20 PORT 0 P00 to P03 PORT 1 P10, P11 PORT 2 P20 to P25 PORT 5 P50 to P53 PORT 6 P60 to P63 CPT20/INTP0 /SS20/P23 WATCHDOG TIMER 78K/0S CPU CORE ROM SCK20/ASCK20 /P20 SO20/TxD20/P21 SI20/RxD20/P22 SERIAL INTERFACE 20 SS20/INTP0 /CPT20/P23 RAM ANI0/P60 to ANI3/P63 AVDD AVSS A/D CONVERTER SYSTEM CONTROL INTERRUPT CONTROL VDD Remark 8 VSS IC0 The internal ROM capacity varies depending on the product. Data Sheet U12815EJ2V1DS00 RESET X1 X2 INTP0/CPT20 /P23/SS20 INTP1/TO80 /TO20/P24 INTP2/TI80/P25 PD789101, 789102, 789104, 789111, 789112, 789114 3. PIN FUNCTIONS 3.1 Port Pins Pin Name I/O P00 to P03 I/O Function Port 0 After Reset Alternate Function Input - Input - 4-bit input/output port Input/output can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by means of software. P10, P11 I/O Port 1 2-bit input/output port Input/output can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by means of software. P20 I/O Input Port 2 6-bit input/output port P21 SO20/TxD20 Input/output can be specified in 1-bit units P22 SI20/RxD20 When used as an input port, an on-chip pull-up resistor can be P23 SCK20/ASCK20 INTP0/CPT20 /SS20 specified by means of software. P24 INTP1/TO80/TO20 P25 INTP2/TI80 P50 to P53 I/O Input Port 5 - 4-bit N-ch open-drain input/output port Input/output can be specified in 1-bit units An on-chip pull-up resistor can be specified by the mask option. P60 to P63 Input Port 6 4-bit input-only port Input Data Sheet U12815EJ2V1DS00 ANI0 to ANI3 9 PD789101, 789102, 789104, 789111, 789112, 789114 3.2 Non-Port Pins Pin Name INTP0 I/O Input INTP1 INTP2 Function After Reset Alternate Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Input P23/CPT20/SS20 P24/TO80/TO20 P25/TI80 SI20 Input Serial interface serial data input Input P22/RxD20 SO20 Output Serial interface serial data output Input P21/TxD20 SCK20 I/O Serial interface serial clock input/output Input P20/ASCK20 ASCK20 Input Serial clock input for asynchronous serial interface Input P20/SCK20 SS20 Input Chip select input for serial interface Input P23/CPT20/INTP0 RxD20 Input Serial data input for asynchronous serial interface Input P22/SI20 TxD20 Output Serial data output for asynchronous serial interface Input P21/SO20 TI80 Input External count clock input to 8-bit timer (TM80) Input P25/INTP2 TO80 Output 8-bit timer (TM80) output Input P24/INTP1/TO20 TO20 Output 16-bit timer (TM20) output Input P24/INTP1/TO80 CPT20 Input Capture edge input Input P23/INTP0/SS20 ANI0 to ANI3 Input A/D converter analog input Input P60 to P63 AVDD AVSS X1 X2 RESET Input A/D converter analog power supply - A/D converter ground potential - - Connecting crystal resonator for main system clock oscillation - - - - - Input - VDD - Positive power supply - - VSS - Ground potential - - IC0 - Internally connected. Connect directly to VSS. - - 10 Input - System reset input Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin Input/Output Circuits Pin Name P00 to P03 Input/Output Circuit Type I/O 5-A I/O P10, P11 P20/SCK20/ASCK20 Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open 8-A P21/SO20/TXD20 P22/SI20/RXD20 P23/INTP0/CPT20/SS20 P24/INTP1/TO80/TO20 P25/INTP2/TI80 P50 to P53 P60/ANI0 to P63/ANI3 AVDD 13-W Input: Independently connect to VDD via a resistor. Output: Leave open 9-C Input - - AVSS Connect directly to VDD or VSS. Connect to VDD. Connect to VSS. RESET 2 Input IC0 - - - Connect directly to VSS. Data Sheet U12815EJ2V1DS00 11 PD789101, 789102, 789104, 789111, 789112, 789114 Figure 3-1. Pin Input/Output Circuits Type 2 Type 9-C IN Comparator P-ch N-ch IN + - AVSS VREF (Threshold voltage) Schmitt-triggered input with hysteresis characteristics Type 5-A Type 13-W VDD Pull-up enable Input enable VDD Pull-up resistor (mask option) P-ch IN/OUT VDD Data Output data Output disable P-ch IN/OUT Output disable N-ch N-ch VSS Input enable VSS Middle-voltage input buffer Input enable Type 8-A VDD Pull-up enable P-ch VDD Data P-ch IN/OUT Output disable 12 N-ch VSS Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 4. MEMORY SPACE Figure 4-1 shows the memory map of the PD789101, 789102, 789104, 789111, 789112, and 789114. Figure 4-1. Memory Map FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH Reserved Data memory space nnnnH nnnnH+1 nnnnH Program area Program memory space Internal ROMNote 0080H 007FH CALLT table area 0040H 003FH 0016H 0015H Program area Vector table area 0000H 0000H Note The internal ROM capacity depends on the product. (See the following table). Part Number Last Address of Internal ROM nnnnH PD789101, 789111 07FFH PD789102, 789112 0FFFH PD789104, 789114 1FFFH Data Sheet U12815EJ2V1DS00 13 PD789101, 789102, 789104, 789111, 789112, 789114 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 Ports The following three types of I/O ports are available: * CMOS Input (port 6): 4 * CMOS input/output (ports 0 to 2): 12 * N-ch open-drain input/output (port 5): 4 Total: 20 Table 5-1. Port Functions Port Name Pin Name Function Port 0 P00 to P03 Input/output port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Port 1 P10, P11 Input/output port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Port 2 P20 to P25 Input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Port 5 P50 to P53 N-channel open-drain input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by the mask option. Port 6 P60 to P63 Input-only port 5.2 Clock Generator An on-chip system clock generator is provided. The minimum instruction execution time can be changed. * 0.4 s/1.6 s (@ 5.0-MHz operation with system clock) Figure 5-1. Clock Generator Block Diagram Prescaler X1 X2 System clock oscillator Clock to peripheral hardware Prescaler fX STOP 14 Selector fX 22 Standby control circuit Data Sheet U12815EJ2V1DS00 Wait control circuit CPU clock (fCPU) PD789101, 789102, 789104, 789111, 789112, 789114 5.3 Timer Three on-chip timers are provided. * 16-bit timer 20: 1 channel * 8-bit timer/event counter 80: 1 channel * Watchdog timer: 1 channel Table 5-2. Timer Operation Operation mode Function 16-Bit Timer 20 8-Bit Timer/Event Counter 80 Watchdog Timer Interval timer - 1 channel 1 channel External event counter - 1 channel - Timer output 1 output 1 output - PWM output - 1 output - Square wave output - 1 output - 1 input - - 1 1 1 Capture Interrupt request Figure 5-2. Block Diagram of 16-Bit Timer 20 (TM20) Internal bus Output control circuit 16-bit compare register 20 (CR20) TO20/P24/ INTP1/TO80 Match 6 fX/2 CPT20/P23 /INTP0/SS20 Selector INTTM20 fX/22 Edge detection circuit 16-bit timer counter 20 (TM20) 16-bit capture register 20 (TCP20) OVF 16-bit counter read buffer Internal bus Data Sheet U12815EJ2V1DS00 15 PD789101, 789102, 789104, 789111, 789112, 789114 Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter 80 (TM80) Internal bus 8-bit compare register 80 (CR80) Match INTTM80 fX/23 Selector fX 8-bit timer counter 80 (TM80) TI80/P25/ INTP2 OVF Output control circuit TO80/P24/ INTP1/TO20 Clear Internal bus Figure 5-4. Watchdog Timer Block Diagram fX 24 Prescaler fX 28 fX 210 Selector fX 26 16 INTWDT maskable interrupt request 7-bit counter Data Sheet U12815EJ2V1DS00 Control circuit RESET INTWDT non-maskable interrupt request PD789101, 789102, 789104, 789111, 789112, 789114 5.4 A/D Converter The conversion resolution of the A/D converter differs depending on the product as shown below. * 8-bit A/D converter x 4 channels *** PD789101, 789102, 789104 * 10-bit A/D converter x 4 channels *** PD789111, 789112, 789114 A/D conversion can be only started by software. Figure 5-5. A/D Converter Block Diagram INTAD0 ANI1/P61 ANI2/P62 Selector ANI0/P60 A/D converter (8-/10-bits) Sample& hold circuit A/D conversion result register (ADCR0) ANI3/P63 Internal bus Data Sheet U12815EJ2V1DS00 17 PD789101, 789102, 789104, 789111, 789112, 789114 5.5 Serial Interface 20 A one-channel serial interface is incorporated. Serial interface 20 has following three modes: * Operation stop mode: Power consumption can be reduced. * Asynchronous serial interface (UART) mode: A dedicated baud rate generator is incorporated. * 3-wire serial I/O mode: A function to select the clock phase or data phase is incorporated. Figure 5-6. Block Diagram of Serial Interface 20 Internal bus Reception buffer register 20 (RXB20/SIO20) SI20/P22/RXD20 Transmission shift register 20 (TXS20/SIO20) Reception shift register 20 (RXS20) SO20/P21/TXD20 Transmission data counter Reception data counter Selector Data phase control INTST20 INTSR20/INTCSI20 SS20/P23 /CPT20/INTP0 Baud rate generator SCK20/P20 /ASCK20 Clock phase control fX/2 to fX/28 18 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 5.6 Multiplier The calculation of 8 bits x 8 bits = 16 bits can be performed. Figure 5-7. Multiplier Block Diagram Internal bus Multiplication data register A0 (MRA0) Multiplication data register B0 (MRB0) Multiplier 16-bit multiplication result storing register (MUL0) Internal bus Data Sheet U12815EJ2V1DS00 19 PD789101, 789102, 789104, 789111, 789112, 789114 6. INTERRUPT FUNCTION A total of 10 interrupt sources are provided, divided into the following two types. * Non-maskable interrupts: 1 source * Maskable interrupts: 9 sources Table 6-1. Interrupt Source List Interrupt Source Interrupt Type Priority Note 1 Internal/External Name Trigger Vector Table Address Non-maskable - INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (with the interval timer mode selected) 1 INTP0 Pin input edge detection 2 INTP1 0008H 3 INTP2 000AH 4 INTSR20 End of serial interface 20 UART reception INTCSI20 End of serial interface 20 3-wire SIO transfer reception 5 INTST20 End of serial interface 20 UART transmission 000EH 6 INTTM80 Generation of matching signal of 8-bit timer/event counter 80 0010H 7 INTTM20 Generation of matching signal of 16-bit timer 20 0012H 8 INTAD0 A/D conversion completion signal 0014H Internal 0004H Basic Configuration Note 2 Type (A) (B) External Internal 0006H 000CH (C) (B) Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest order and 8 is the lowest order. 2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 6-1. 20 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 Figure 6-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (C) External maskable interrupt Internal bus External interrupt mode register (INTM0) Interrupt request Edge detection circuit MK IE Vector table address generator IF Standby release signal IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag Data Sheet U12815EJ2V1DS00 21 PD789101, 789102, 789104, 789111, 789112, 789114 7. STANDBY FUNCTION The following two standby functions are available for further reduction of system current consumption. * HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. * STOP mode: In this mode, oscillation of the system clock is stopped. All the operations performed on the system clock are suspended, resulting in extremely small power consumption. Figure 7-1. Standby Function System clock operation Interrupt request ( STOP instruction Interrupt request STOP mode System clock oscillation stopped ( HALT instruction ( HALT mode Clock supply to CPU halted, oscillation maintained 8. RESET FUNCTION The following two reset methods are available. 22 * External reset by RESET signal input * Internal reset by watchdog timer runaway time detection Data Sheet U12815EJ2V1DS00 ( PD789101, 789102, 789104, 789111, 789112, 789114 9. INSTRUCTION SET OVERVIEW The instruction set for the PD789101, 789102, 789104, 789111, 789112, 789114 is listed later. 9.1 Conventions 9.1.1 Operand identifiers and description methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords and must be described as they are. Each symbol has the following meaning. * #: Immediate data specification * $: * !: * [ ]: Indirect address specification Absolute address specification Relative address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #,!, $, or [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 9-1. Operand Identifiers and Description Methods Identifier Description Method r rp sfr X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7), AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr saddrp FE20H to FF1FH immediate data or label FE20H to FF1FH immediate data or label (even address only) addr16 addr5 0000H to FFFFH immediate data or label (Only even addresses for 16-bit data transfer instructions) 0040H to 007FH immediate data or label (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label Data Sheet U12815EJ2V1DS00 23 PD789101, 789102, 789104, 789111, 789112, 789114 9.1.2 Descriptions of the operation field A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Non-maskable interrupt servicing flag ( ): Memory contents indicated by address or register contents in parentheses XH, XL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : Exclusive OR : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 9.1.3 Description of the flag operation field 24 (Blank): Not affected 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is restored Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 9.2 Operations Mnemonic Operand Byte Clock Operation Flag Z AC CY MOV r, #byte 3 6 r byte saddr , #byte 3 6 (addr) byte 3 6 sfr byte A, r Note 1 2 4 Ar r, A Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL + byte] 2 6 A (HL + byte) [HL + byte], A 2 6 (HL + byte) A 1 4 A X 2 6 A r A, saddr 2 6 A (saddr) A, sfr 2 6 A (sfr) A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL + byte] 2 8 A (HL + byte) rp, #word 3 6 rp word AX, saddrp 2 6 AX (saddrp) sfr, #byte XCH A, X A, r MOVW Note 2 2 8 (saddrp) AX AX, rp Note 3 1 4 AX rp rp, AX Note 3 1 4 rp AX AX, rp Note 3 1 8 AX rp saddrp, AX XCHW x x x x x x Notes 1. Except r = A 2. Except r = A or X 3. Only when rp = BC, DE, HL Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC). Data Sheet U12815EJ2V1DS00 25 PD789101, 789102, 789104, 789111, 789112, 789114 Mnemonic Operand Byte Clock Operation Flag Z AC CY ADD ADDC SUB SUBC AND Remark A, #byte 2 4 A, CY A + byte x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte x x x A, r 2 4 A ,CY A + r x x x A, saddr 2 4 A, CY A + (saddr) x x x A, !addr16 3 8 A, CY A + (addr16) x x x A, [HL] 1 6 A, CY A + (HL) x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) x x x A, #byte 2 4 A, CY A + byte + CY x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte + CY x x x A, r 2 4 A, CY A + r + CY x x x A, saddr 2 4 A, CY A + (saddr) + CY x x x A, !addr16 3 8 A, CY A + (addr16) + CY x x x A, [HL] 1 6 A, CY A + (HL) + CY x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) + CY x x x A, #byte 2 4 A, CY A - byte x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte x x x A, r 2 4 A, CY A - r x x x A, saddr 2 4 A, CY A - (saddr) x x x A, !addr16 3 8 A, CY A - (addr16) x x x A, [HL] 1 6 A, CY A - (HL) x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) x x x A, #byte 2 4 A, CY A - byte - CY x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte - CY x x x A, r 2 4 A, CY A - r - CY x x x A, saddr 2 4 A, CY A - (saddr) - CY x x x A, !addr16 3 8 A, CY A - (addr16) - CY x x x A, [HL] 1 6 A, CY A - (HL) - CY x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) - CY x x x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC). 26 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 Mnemonic Operand Byte Clock Operation Flag Z AC CY A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A - byte x x x saddr, #byte 3 6 (saddr) - byte x x x A, r 2 4 A-r x x x A, saddr 2 4 A - (saddr) x x x A, !addr16 3 8 A - (addr16) x x x A, [HL] 1 6 A - (HL) x x x A, [HL + byte] 2 6 A - (HL + byte) x x x ADDW AX, #word 3 6 AX, CY AX + word x x x SUBW AX, #word 3 6 AX, CY AX - word x x x CMPW AX, #word 3 6 AX - word x x x INC r 2 4 rr+1 x x saddr 2 4 (saddr) (saddr) + 1 x x r 2 4 rr-1 x x saddr 2 4 (saddr) (saddr) - 1 x x INCW rp 1 4 rp rp + 1 DECW rp 1 4 rp rp - 1 ROR A, 1 1 2 (CY, A7 A0, Am - 1 Am) x 1 x ROL A, 1 1 2 (CY, A0 A7, Am + 1 Am) x 1 x RORC A, 1 1 2 (CY A0, A7 CY, Am - 1 Am) x 1 x ROLC A, 1 1 2 (CY A7, A0 CY, Am + 1 Am) x 1 x OR XOR CMP DEC Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC). Data Sheet U12815EJ2V1DS00 27 PD789101, 789102, 789104, 789111, 789112, 789114 Mnemonic Operand Byte Clock Operation Flag Z AC CY saddr. bit 3 6 (saddr. bit) 1 sfr. bit 3 6 sfr. bit 1 A. bit 2 4 A. bit 1 PSW. bit 3 6 PSW. bit 1 [HL]. bit 2 10 (HL) . bit 1 saddr. bit 3 6 (saddr. bit) 0 sfr. bit 3 6 sfr. bit 0 A. bit 2 4 A. bit 0 PSW. bit 3 6 PSW. bit 0 [HL]. bit 2 10 (HL) . bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x CALL !addr16 3 6 (SP - 1) (PC + 3)H,(SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLT [addr5] 1 8 (SP - 1) (PC + 1)H,(SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 RET 1 6 PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 8 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PSW 1 2 (SP - 1) PSW, SP SP - 1 rp 1 4 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 1 4 PSW (SP), SP SP + 1 rp 1 6 rpH (SP + 1), rpL (SP), SP SP + 2 SP, AX 2 8 SP AX AX, SP 2 6 AX SP !addr16 3 6 PC addr16 $addr16 2 6 PC PC + 2 + jdisp8 AX 1 6 PCH A, PCL X SET1 CLR1 PUSH POP MOVW BR Remark x x x x x R R R R R R One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC). 28 x Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 Mnemonic Operand Byte Clock Operation Flag Z AC CY BC $addr16 2 6 PC PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 PC PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 PC PC + 2 + jdisp8 if Z = 0 BT saddr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr. bit = 1 A. bit , $addr16 3 8 PC PC + 3 + jdisp8 if A. bit = 1 PSW. bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW. bit = 1 saddr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr. bit = 0 A. bit, $addr16 3 8 PC PC + 3 + jdisp8 if A. bit = 0 PSW. bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW. bit = 0 B, $addr16 2 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 C C - 1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if(saddr) 0 NOP 1 2 No Operation EI 3 6 IE 1(Enable Interrupt) DI 3 6 IE 0(Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode BF DBNZ Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control register (PCC). Data Sheet U12815EJ2V1DS00 29 PD789101, 789102, 789104, 789111, 789112, 789114 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Symbol VDD, AVDD Conditions Ratings Unit -0.3 to +6.5 V -0.3 to VDD + 0.3 V -0.3 to +13 V -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V Per pin -10 mA Total for all pins -30 mA Per pin 30 mA Total for all pins 160 mA VDD = AVDD VI1 Pins other than P50 to P53 VI2 P50 to P53 With N-ch open drain With an on-chip pull-up resistor Output voltage VO Output current, high IOH Output current, low IOL Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -65 to +150 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 30 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V) Resonator Recommended Circuit Parameter Conditions Note 1 Ceramic resonator IC0 X1 C1 IC0 X1 Crystal resonator C1 External clock X1 X2 C2 X2 C2 MAX. Unit 5.0 MHz 4 ms 5.0 MHz VDD = 4.5 to 5.5 V 10 ms VDD = 2.7 to 5.5 V 30 Oscillation frequency (fX) VDD = oscillation voltage range Oscillation stabilization Note 2 time After VDD reaches oscillation voltage range MIN. MIN. Note 1 Oscillation frequency (fX) Oscillation stabilization Note 2 time 1.0 1.0 Note 1 TYP. X2 X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level width (tXH, tXL) 85 500 ns OPEN Notes 1. Indicates only oscillator characteristics. Refer to AC characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Use the resonator that stabilizes oscillation during the oscillation wait time. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Data Sheet U12815EJ2V1DS00 31 PD789101, 789102, 789104, 789111, 789112, 789114 Recommended Oscillator Constant Ceramic resonator (TA = -40 to +85C) (1/4) Manufacturer Murata Mfg. Co., Ltd. (Lead pin type) Part Number Frequency Recommended (MHz) Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. MAX. 1.00 100 100 2.7 5.5 2.00 30 30 - - 30 30 CST4.00MGW - - CSA4.00MGU 30 30 CST4.00MGWU - - 30 30 CST4.19MG - - CSA4.19MGU 30 30 CST4.19MGU - - 30 30 CST4.91MGW - - CSA4.91MGU 30 30 CST4.91MGWU - - 30 30 CST5.00MGW - - CSA5.00MGU 30 30 CST5.00MGWU - - CSB1000J Note CSA2.00MG CST2.00MG CSA4.00MG CSA4.19MG CSA4.91MG CSA5.00MG 4.00 4.19 4.91 5.00 Remarks Rd = 2.2 k On-chip capacitor On-chip capacitor On-chip capacitor On-chip capacitor On-chip capacitor On-chip capacitor On-chip capacitor On-chip capacitor On-chip capacitor Note When using the CSB1000J (1.0 MHz) of Murata Mfg. Co., Ltd. as a ceramic resonator, a limited resistor (Rd = 2.2 k) is required (see the figure below). The resistor is not required when a recommended resonator other than the CSB1000J is used. X2 X1 CSB1000J C1 Caution Rd C2 The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 32 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 Ceramic resonator (TA = -40 to +85C) (2/4) Manufacturer Murata Mfg. Co., Ltd. (SMD type) Part Number CSBF1000J Note CSAC2.00MGC Frequency Recommended (MHz) Circuit Constant (pF) C1 C2 MIN. MAX. 1.00 100 100 2.7 5.5 2.00 30 30 - - 30 30 - - 30 30 - - 30 30 - - 30 30 - - CSTC2.00MG CSAC4.00MGC Oscillation Voltage Range (VDD) 4.00 Remarks Rd = 2.2 k On-chip capacitor CSAC4.00MGCU CSTCC4.00MG On-chip capacitor CSTCC4.00MGU CSAC4.19MGC 4.19 CSAC4.19MGCU CSTCC4.19MG On-chip capacitor CSTCC4.19MGU CSAC4.91MGC 4.91 CSAC4.91MGCU CSTCC4.91MG On-chip capacitor CSTCC4.91MGU CSAC5.00MGC 5.00 CSAC5.00MGCU CSTCC5.00MG On-chip capacitor CSTCC5.00MGU Note When using the CSBF1000J (1.0 MHz) of Murata Mfg. Co., Ltd. as a ceramic resonator, a limited resistor (Rd = 2.2 k) is required (see the figure below). The resistor is not required when a recommended resonator other than the CSBF1000J is used. X2 X1 CSBF1000J C1 Caution Rd C2 The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. Data Sheet U12815EJ2V1DS00 33 PD789101, 789102, 789104, 789111, 789112, 789114 Ceramic resonator (TA = -40 to +85C) (3/4) Manufacturer Kyocera Corporation (Lead pin type) Part Number Frequency Recommended (MHz) Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. MAX. 2.7 5.5 KBR-1000F 1.00 100 100 KBR-2.0MS 2.00 68 68 KBR-4.0MKC 4.00 - - 33 33 - - 33 33 - - 33 33 - - 33 33 Remarks On-chip capacitor KBR-4.0MKD KBR-4.0MKS KBR-4.0MSA KBR-4.0MSB KBR-4.19MKC 4.19 On-chip capacitor KBR-4.19MKD KBR-4.19MKS KBR-4.19MSA KBR-4.19MSB KBR-4.91MKC 4.91 On-chip capacitor KBR-4.91MKD KBR-4.91MKS KBR-4.91MSA KBR-4.91MSB KBR-5.0MKC 5.00 On-chip capacitor KBR-5.0MKD KBR-5.0MKS KBR-5.0MSA KBR-5.0MSB Kyocera Corporation (SMD type) KBR-1000Y 1.00 100 100 PBRC4.00A 4.00 33 33 - - 33 33 - - 33 33 - - 33 33 - - PBRC4.00B PBRC4.19A 4.19 PBRC4.19B PBRC4.91A 4.91 PBRC4.91B PBRC5.00A PBRC5.00B Caution 5.00 2.7 5.5 On-chip capacitor On-chip capacitor On-chip capacitor On-chip capacitor The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 34 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 Ceramic resonator (TA = -40 to +85C) (4/4) Manufacturer TDK Part Number Frequency Recommended (MHz) Circuit Constant (pF) Oscillation Voltage Range (VDD) C1 C2 MIN. MAX. - - 2.7 5.5 FCR4.0M5 33 33 FCR4.0MC5 - - FCR4.19M5 33 33 FCR4.19MC5 - - CCR4.0MC3 CCR4.19MC3 4.00 Remarks On-chip capacitor On-chip capacitor 4.19 CCR4.91MC3 4.91 CCR5.0MC3 5.00 On-chip capacitor FCR5.0MC5 Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. Data Sheet U12815EJ2V1DS00 35 PD789101, 789102, 789104, 789111, 789112, 789114 DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V) (1/2) Parameter Output current, high Output current, low Input voltage, high Input voltage, low Symbol IOH IOL Output voltage, low Input leakage current, low TYP. MAX. Unit Per pin -1 mA Total for all pins -15 mA Per pin 10 mA Total for all pins 80 mA Pins other than described below 0.7VDD VDD V VIH2 P50 to P53, VDD = 3.5 to 5.5 V With N-ch open drain 0.7VDD 12 V With on-chip pull-up resistor 0.7VDD VDD V VIH3 RESET, P20 to P25, P40 to P45 0.8VDD VDD V VIH4 X1, X2 VDD = 2.7 to 5.5 V VDD - 0.1 VDD V VDD = 4.5 to 5.5 V VDD - 0.5 VDD V VIL1 Pins other than described below 0 0.3VDD V VIL2 P50 to P53, VDD = 3.5 to 5.5 V 0 0.3VDD V VIL3 RESET, P20 to P25, P40 to P45 0 0.2VDD V = 2.7 to 5.5 V 0 0.1 V VDD = 4.5 to 5.5 V 0 0.4 V VDD X1, X2 VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VOH2 VDD = 2.7 to 5.5 V, IOH = -100 A VDD - 0.5 V VOL1 Pins other than P50 to P53 VOL2 Input leakage current, high MIN. VIH1 VIL4 Output voltage, high Conditions P50 to P53 VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VDD = 2.7 to 5.5 V IOL = 400 A 0.5 V VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VDD = 2.7 to 5.5 V IOL = 1.6 mA 0.4 V 3 A 20 A VIN = VDD ILIH1 Pins other than X1, X2, or P50 to P53 ILIH2 X1, X2 ILIH3 P50 to P53 (N-ch open drain) VIN = 12 V 20 A ILIL1 Pins other than X1, X2, or P50 to P53 VIN = 0 V -3 A ILIL2 X1, X2 -20 A ILIL3 P50 to P53 (N-ch open drain) -3 Note A Note When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in input mode, a low-level input leakage current of -30 A (MAX.) flows only for 1 cycle time after a read instruction has been executed to port 5. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 36 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output leakage current, high ILOH VOUT = VDD 3 A Output leakage current, low ILOL VOUT = 0 V -3 A Software pull-up resistor R1 VIN = 0 V, for pins other than P50 to P53 50 100 200 k Mask option pull-up resistor R2 VIN = 0 V, P50 to P53 10 30 60 k Power supply Note 1 current IDD1 Note 3 1.8 3.2 mA Note 4 0.45 0.9 mA Note 3 0.8 1.6 mA Note 4 VDD = 3.0 V10% 0.3 0.6 mA VDD = 5.0 V10% 0.1 10 A VDD = 3.0 V10% 0.05 5.0 A VDD = 5.0 V10% 3.0 5.5 mA VDD = 3.0 V10% 1.65 3.2 mA Note 1 Note 1 IDD2 Note 1 IDD3 Note 2 IDD4 5.0-MHz crystal oscillation operating mode (C1 = C2 = 22pF) 5.0-MHz crystal oscillation HALT mode (C1 = C2 = 22pF) STOP mode 5.0-MHz crystal oscillation A/D operating mode (C1 = C2 = 22pF) VDD = 5.0 V10% VDD = 3.0 V10% VDD = 5.0 V10% Notes 1. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and AVDD current are not included. 2. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) is not included. 3. High-speed mode operation (when processor clock control register (PCC) is set to 00H.) 4. Low-speed mode operation (when PCC is set to 02H). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U12815EJ2V1DS00 37 PD789101, 789102, 789104, 789111, 789112, 789114 AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 2.7 to 5.5 V) Parameter Symbol Conditions MIN. Cycle time (minimum instruction execution time) TCY 0.4 TI80 input high-/lowlevel width tTIH, tTIL 0.1 TI80 input frequency fTI Interrupt input high/low-level width tINTH, tINTL RESET low-level width tRSL 0 INTP0 to INTP2 Cycle time TCY [ s] 1.0 0.5 0.4 0.1 4 5 Supply voltage VDD [V] 38 Data Sheet U12815EJ2V1DS00 s s 4 MHz s Guaranteed operation range 3 8 10 10 2 Unit s 60 1 MAX. 10 TCY vs VDD (at 5.0 MHz operation with system clock) 2.0 TYP. 6 PD789101, 789102, 789104, 789111, 789112, 789114 (2) Serial interface (TA = -40 to +85C, VDD = 2.7 to 5.5 V) (i) 3-wire serial I/O mode (SCK20...Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK20 cycle time tKCY1 800 ns SCK20 high-/lowlevel width tKH1, tKL1 tKCY1/2 - 50 ns SI20 setup time (to SCK20) tSIK1 150 ns SI20 hold time (from SCK20) tKSI1 400 ns SO20 output delay time from SCK20 tKSO1 R = 1 k , Note C = 100 pF 0 250 ns MAX. Unit Note R and C are the load resistance and load capacitance of the SO output line. (ii) 3-wire serial I/O mode (SCK20...External clock input) Parameter Symbol Conditions MIN. TYP. SCK20 cycle time tKCY2 900 ns SCK20 high-/lowlevel width tKH2, tKL2 400 ns SI20 setup time (to SCK20) tSIK2 100 ns SI20 hold time (from SCK20) tKSI2 400 ns SO20 output delay time from SCK20 tKSO2 SO20 setup time (for SS20 when SS20 is used) SO20 disable time (for SS20 when SS20 is used) R = 1 k, Note C = 100 pF 0 300 ns tKAS2 120 ns tKDS2 240 ns MAX. Unit 78125 bps Note R and C are the load resistance and load capacitance of the SO output line. (iii) UART mode (Dedicated baud rate generator output) Parameter Symbol Conditions Transfer rate Data Sheet U12815EJ2V1DS00 MIN. TYP. 39 PD789101, 789102, 789104, 789111, 789112, 789114 (iv) UART mode (external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit ASCK20 cycle time tKCY3 900 ns ASCK20 high-/lowlevel width tKH3, tKL3 400 ns Transfer rate ASCK20 rise/fall time 40 tR, tF Data Sheet U12815EJ2V1DS00 39063 bps 1 s PD789101, 789102, 789104, 789111, 789112, 789114 AC Timing Test Points (excluding X1 input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 input VIL4 (MAX.) TI Timing 1/fTI tTIL tTIH TI80 Interrupt Input Timing tINTL tINTH INTP0 to INTP2 RESET Input Timing tRSL RESET Data Sheet U12815EJ2V1DS00 41 PD789101, 789102, 789104, 789111, 789112, 789114 Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 m = 1, 2 3-wire serial I/O mode (when SS20 is used): SS20 tKAS2 tKDS2 SO20 Output data UART mode (external clock input): tKCY3 tKL3 tKH3 tR ASCK20 42 Data Sheet U12815EJ2V1DS00 tF PD789101, 789102, 789104, 789111, 789112, 789114 8-Bit A/D Converter Characteristics (PD789101, 789102, 789104) (TA = -40 to +85C, AVDD = VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions Resolution MIN. TYP. MAX. Unit 8 8 8 bit 0.4 0.6 %FSR Note Overall error Conversion time tCONV 14 100 s Analog input voltage VIAN 0 AVDD V Note Excludes quantization error (0.2%). FSR: Full-scale range Remark 10-Bit A/D Converter Characteristics (PD789111, 789112, 789114) (TA = -40 to +85C, AVDD = VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 bit 4.5 V VDD 5.5 V 0.2 0.4 %FSR 2.7 V VDD < 4.5 V 0.4 0.6 %FSR 100 s 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 4.5 V VDD 5.5 V 0.4 %FSR 2.7 V VDD < 4.5 V 0.6 %FSR 4.5 V VDD 5.5 V 2.5 LSB 2.7 V VDD < 4.5 V 4.5 LSB 4.5 V VDD 5.5 V 1.5 LSB 2.7 V VDD < 4.5 V 2.0 LSB AVDD V Resolution Note Overall error Conversion time Zero-scale error tCONV Note Note Full-scale error Non-integral linearity Note error INL Non-differential Note linearity error DNL Analog input voltage VIAN 14 0 Note Excludes quantization error (0.05%). Remark FSR: Full-scale range Data Sheet U12815EJ2V1DS00 43 PD789101, 789102, 789104, 789111, 789112, 789114 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Conditions MIN. Data retention supply voltage VDDDR 1.8 Release signal set time tSREL 0 Oscillation stabilization wait Note 1 time tWAIT TYP. MAX. Unit 5.5 V s 15 Release by RESET Release by interrupt request 2 /fX ms Note 2 ms Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid unstable operation at the beginning of oscillation. 12 15 17 2. Selection of 2 /fX, 2 /fX, or 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register. Remark fX: System clock oscillation frequency Data Retention Timing (STOP mode release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby release signal: STOP mode release by interrupt signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 44 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 11. CHARACTERISTICS CURVES (REFERENCE VALUES) IDD vs VDD (System clock: 5.0-MHz crystal resonator) (TA = 25C) 10 5.0 PCC = 00H 1.0 PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode) Power supply current IDD (mA) 0.5 0.1 0.05 0.01 X2 X1 0.005 Crystal resonator 5.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 6 7 8 Power supply voltage VDD (V) Data Sheet U12815EJ2V1DS00 45 PD789101, 789102, 789104, 789111, 789112, 789114 IDD vs VDD (System clock: 4.0-MHz crystal resonator) (TA = 25C) 10 5.0 PCC = 00H 1.0 PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode) Power supply current IDD (mA) 0.5 0.1 0.05 0.01 X2 X1 0.005 Crystal resonator 4.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 Power supply voltage VDD (V) 46 Data Sheet U12815EJ2V1DS00 6 7 8 PD789101, 789102, 789104, 789111, 789112, 789114 IDD vs VDD (System clock: 2.0-MHz crystal resonator) (TA = 25C) 10 5.0 1.0 PCC = 00H PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode) Power supply current IDD (mA) 0.5 0.1 0.05 0.01 X2 X1 0.005 Crystal resonator 2.0 MHz 47 pF 47 pF 0.001 0 1 2 3 4 5 6 7 8 Power supply voltage VDD (V) Data Sheet U12815EJ2V1DS00 47 PD789101, 789102, 789104, 789111, 789112, 789114 12. PACKAGE DRAWING 30 PIN PLASTIC SHRINK SOP (300 mil) 30 16 detail of lead end P 1 15 A F H G I J S C D N M B S L K M E NOTES 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 9.850.26 0.3880.011 B 0.51 MAX. 0.020 MAX. C 0.65 (T.P.) 0.026 (T.P.) D 0.32+0.08 -0.07 0.013 +0.003 -0.004 E 0.1250.075 0.0050.003 F 2.0 MAX. 0.079 MAX. G 1.70.1 0.0670.004 H 8.10.2 0.3190.008 I 6.10.2 0.2400.008 J 1.00.2 0.039 +0.009 -0.008 K 0.17 +0.08 -0.07 0.007 +0.003 -0.004 L 0.50.2 0.020 +0.008 -0.009 M 0.10 0.004 N 0.10 0.004 P 3 +7 -3 3 +7 -3 P30GS-65-300B-2 48 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 30 PIN PLASTIC SSOP (300 mil) 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B K M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 9.850.15 B 0.45 MAX. C 0.65 (T.P.) D 0.24 +0.08 -0.07 E 0.10.05 F 1.30.1 G 1.2 H 8.10.2 I 6.10.2 J 1.00.2 K 0.170.03 L 0.5 M 0.13 N 0.10 P 3 +5 -3 T 0.25 U Data Sheet U12815EJ2V1DS00 0.60.15 S30MC-65-5A4-1 49 PD789101, 789102, 789104, 789111, 789112, 789114 13. RECOMMENDED SOLDERING CONDITIONS The PD789101, 789102, 789104, 789111, 789112, and 789114 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 13-1. Surface Mounting Type Soldering Conditions (1/2) PD789101GS-xxx: 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789102GS-xxx: 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789104GS-xxx: 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789111GS-xxx: 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789112GS-xxx: 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) PD789114GS-xxx: 30-pin plastic shrink SOP (300 mils, resin thickness 1.7 mm) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher), Note Count: twice or less, Exposure limit: 7 days (after that, prebake at 125C for 20 Recommended Condition Symbol IR35-207-2 hours) VPS Package peak temperature: 215C, Time: 40 sec. Max. (at 200C or higher), Note Count: twice or less, Exposure limit: 7 days (after that, prebake at 125C for 20 VP15-207-2 hours) Wave soldering Solder bath temperature: 260C Max., Time: 10 sec. Max., Count: once, Preheating temperature: 120C Max. (package surface temperature), Exposure Note limit: 7 days (after that, prebake at 125C for 20 hours) Partial heating Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row) WS60-207-1 - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution 50 Do not use different soldering methods together (except for partial heating). Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 Table 13-1. Surface Mounting Type Soldering Conditions (2/2) PD789101MC-xxx-5A4: 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789102MC-xxx-5A4: 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789104MC-xxx-5A4: 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789111MC-xxx-5A4: 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789112MC-xxx-5A4: 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) PD789114MC-xxx-5A4: 30-pin plastic shrink SOP (300 mils, resin thickness 1.2 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher), Count: three times or less IR35-00-3 VPS Package peak temperature: 215C, Time: 40 sec. Max. (at 200C or higher), Count: three times or less VP15-00-3 Wave soldering Solder bath temperature: 260C Max., Time: 10 sec. Max., Count: once, Preheating temperature: 120C Max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row) Caution - Do not use different soldering methods together (except for partial heating). Data Sheet U12815EJ2V1DS00 51 PD789101, 789102, 789104, 789111, 789112, 789114 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for system development using the PD789101, PD789102, PD789104, PD789111, PD789112, and PD789114. Language Processing Software RA78K0S Notes 1, 2, 3 Assembler package common to 78K/0S Series Notes 1, 2, 3 C compiler package common to 78K/0S Series CC78K0S DF789136 Notes 1, 2, 3 Device file for PD789104, 789114 Subseries Flash Memory Writing Tools Flashpro lIl Note 4 (Model number: FL-PR3 , Dedicated flash programmer for on-chip flash memory PG-FP3) FA-30GS Note 4 Flash memory writing adapter Notes 4, 5 FA30MC Debugging Tools (1/2) IE-78K0S-NS In-circuit emulator In-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0S Series product. It supports the ID78K0S-NS integrated debugger. Used in combination with an AC adapter, emulation probe, and interface adapter connecting to the host machine. IE-70000-MC-PS-B AC adapter Adapter used to supply power from a power outlet of 100 V AC to 240 V AC. IE-70000-98-IF-C Interface adapter Adapter when PC-9800 series PC (except notebook type) is used as the IE-78K0S-NS host machine (C bus supported). IE-70000-CD-IF-A PC card interface PC card and interface cable when notebook PC is used as the IE-78K0S-NS host machine (PCMCIA socket supported). IE-70000-PC-IF-C Interface adapter Adapter when using an IBM PC/ATTM or compatible as the IE-78K0S-NS host machine. IE-70000-PCI-IF Interface adapter Adapter when using PC that includes a PCI bus as the IE-78K0S-NS host machine. IE-789136-NS-EM1 Emulation board Board for emulation of the peripheral hardware peculiar to a device. Used in combination with an in-circuit emulator. NP-36GS Note 4 Board used to connect the in-circuit emulator to the target system. For a 30-pin plastic shrink SOP (GS, MC-5A4 type), used in combination with NGS-30. Note 4 NGS-30 Conversion socket Conversion socket used to connect the NP-36GS to the target system board designed to mount a 30-pin plastic shrink SOP (GS, MC-5A4 type). Notes 1. PC-9800 series (MS-DOSTM + WindowsTM) based 2. IBM PC/AT or compatibles (Japanese/English Windows) based 3. HP9000 series 700TM (HP-UXTM), SPARCstationTM (SunOSTM, SolarisTM), or NEWSTM (NEWS-OSTM) based. 4. Products made by Naito Densei Machida Mfg. Co., Ltd. (Phone: +81-44-822-3813). Contact an NEC distributor regarding the purchase of these products. 5. Under development Remark 52 RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789136. Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 Debugging Tools (2/2) SM78K0S Notes 1, 2 ID78K0S-NS DF789136 Notes 1, 2 Notes 1, 2 System simulator common to 78K/0S Series Integrated debugger common to 78K/0S Series Device file for PD789104, 789114 Subseries Real-time OS MX78K0S Notes 1, 2 OS for 78K/0S Series Notes 1. PC-9800 series (MS-DOS + Windows) based. 2. IBM PC/AT or compatibles (Japanese/English Windows) based. Data Sheet U12815EJ2V1DS00 53 PD789101, 789102, 789104, 789111, 789112, 789114 APPENDIX B RELATED DOCUMENTS Documents Related to Devices Document No. Document Name Japanese English PD789101, 789102, 789104, 789111, 789112, 789114 Data Sheet U12815J This manual PD78F9116 Data Sheet U13037J U13037E PD789104, 789114, 789124, 789134 Subseries User's Manual U13045J U13045E 78K/0S Series User's Manual Instruction U11047J U11047E Documents Related to Development Tools (User's Manuals) Document No. Document Name Japanese RA78K0S Assembler Package English Operation U11622J U11622E Assembly Language U11599J U11599E Structured Assembly Language U11623J U11623E Operation U11816J U11816E Language U11817J U11817E SM78K0S System Simulator Windows Based Reference U11489J U11489E SM78K Series System Simulator External Parts User Open Interface Specifications U10092J U10092E ID78K0S-NS Integrated Debugger Windows Based Reference U12901J U12901E IE-78K0S-NS In-circuit Emulator U13549J U13549E IE-789136-NS-EM1 Emulation Board To be prepared To be prepared CC78K0S C Compiler Documents Related to Embedded Software (User's Manuals) Document No. Document Name Japanese 78K/0S Series OS MX78K0S Caution Fundamental U12938E The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 54 U12938J English Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 Other Related Documents Document No. Document Name Japanese English SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Guide to Microcomputer-Related Products by Third Party U11416J - Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U12815EJ2V1DS00 55 PD789101, 789102, 789104, 789111, 789112, 789114 [MEMO] 56 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 [MEMO] Data Sheet U12815EJ2V1DS00 57 PD789101, 789102, 789104, 789111, 789112, 789114 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. MS-DOS and Windows are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. 58 Data Sheet U12815EJ2V1DS00 PD789101, 789102, 789104, 789111, 789112, 789114 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Hong Kong Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U12815EJ2V1DS00 59 PD789101, 789102, 789104, 789111, 789112, 789114 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8