IS42S16400D-6BLI-TR - ISSI, Integrated Silicon Solution Inc

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

FEATURES

• Clock frequency: 166, 143 MHz

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access/precharge

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length

– (1, 2, 4, 8, full page)

• Programmable burst sequence:

Sequential/Interleave

• Self refresh modes

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

operations capability

• Burst termination by burst stop and precharge

command

• Byte controlled by LDQM and UDQM

• Industrial temperature availability

• Package:

400-mil 54-pin TSOP II, 60-ball fBGA

• Lead-free package is available

OVERVIEW

ISSI's 64Mb Synchronous DRAM IS42S16400D is organized

as 1,048,576 bits x 16-bit x 4-bank for improved performance.

The synchronous DRAMs achieve high-speed data transfer

using pipeline architecture. All inputs and outputs signals

refer to the rising edge of the clock input.

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

NOVEMBER 2007

PIN CONFIGURATIONS

54-Pin TSOP (Type II)

VDD

DQ0

VDDQ

DQ1

DQ2

GNDQ

DQ3

DQ4

VDDQ

DQ5

DQ6

GNDQ

DQ7

VDD

LDQM

CAS

RAS

BA0

BA1

A10

VDD

GND

DQ15

GNDQ

DQ14

DQ13

VDDQ

DQ12

DQ11

GNDQ

DQ10

DQ9

VDDQ

DQ8

GND

UDQM

CLK

CKE

A11

GND

PIN DESCRIPTIONS

A0-A11 Address Input

BA0, BA1 Bank Select Address

DQ0 to DQ15 Data I/O

CLK System Clock Input

CKE Clock Enable

CS Chip Select

RAS Row Address Strobe Command

CAS Column Address Strobe Command

WE Write Enable

LDQM Lower Bye, Input/Output Mask

UDQM Upper Bye, Input/Output Mask

VDD Power

GND Ground

VDDQPower Supply for DQ Pin

GNDQGround for DQ Pin

NC No Connection

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

GENERAL DESCRIPTION

The 64Mb SDRAM is a high speed CMOS, dynamic

random-access memory designed to operate in 3.3V

memory systems containing 67,108,864 bits. Internally

configured as a quad-bank DRAM with a synchronous

interface. Each 16,777,216-bit bank is organized as 4,096

rows by 256 columns by 16 bits.

The 64Mb SDRAM includes an AUTO REFRESH MODE,

and a power-saving, power-down mode. All signals are

registered on the positive edge of the clock signal, CLK.

All inputs and outputs are LVTTL compatible.

The 64Mb SDRAM has the ability to synchronously burst

data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks

to hide precharge time and the capability to randomly

change column addresses on each clock cycle during

burst access.

A self-timed row precharge initiated at the end of the burst

sequence is available with the AUTO PRECHARGE

function enabled.

Precharge

one bank while accessing one

of the other three banks will hide the

precharge

cycles and

provide seamless, high-speed, random-access operation.

SDRAM

read and write accesses are burst oriented starting

at a selected location and continuing for a programmed

number of locations in a programmed sequence. The

registration of an ACTIVE command begins accesses,

followed by a READ or WRITE command. The ACTIVE

command in conjunction with address bits registered are

used to select the bank and row to be accessed (BA0, BA1

select the bank; A0-A11 select the row). The READ or

WRITE commands in conjunction with address bits reg-

istered are used to select the starting column location for

the burst access.

Programmable READ or WRITE burst lengths consist of

1, 2, 4 and 8 locations, or full page, with a burst terminate

option.

CLK

CKE

RAS

CAS

A10

BA0

BA1

A11

COMMAND

DECODER

CLOCK

GENERATOR MODE

REFRESH

CONTROLLER

REFRESH

COUNTER

SELF

REFRESH

CONTROLLER

ROW

ADDRESS

LATCH

MULTIPLEXER

COLUMN

ADDRESS LATCH

BURST COUNTER

COLUMN

ADDRESS BUFFER

COLUMN DECODER

DATA IN

BUFFER

DATA OUT

BUFFER

DQM

DQ 0-15

VDD/VDDQ

GND/GNDQ

16 16

256K

(x 16)

4096

ROW DECODER

4096

MEMORY CELL

ARRAY

BANK 0

SENSE AMP I/O GATE

BANK CONTROL LOGIC

ROW

ADDRESS

BUFFER

FUNCTIONAL BLOCK DIAGRAM

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

PIN CONFIGURATION

PACKAGE CODE:

B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)

1 2 3 4 5 6 7

VSS

DQ14

DQ13

DQ12

DQ10

DQ9

DQ8

CKE

A11

VSS

DQ15

VSSQ

VDDQ

DQ11

VSSQ

VDDQ

UDQM

CLK

DQ0

VDDQ

VSSQ

DQ4

VDDQ

VSSQ

VDD

LDQM

RAS

BA1

VDD

DQ1

DQ2

DQ3

DQ5

DQ6

DQ7

CAS

BA0

A10

VDD

PIN DESCRIPTIONS

A0-A11 Row Address Input

A0-A7 Column Address Input

BA0, BA1 Bank Select Addresses

DQ0 to DQ15 Data I/O

CLK System Clock Input

CKE Clock Enable

CS Chip Select

RAS Row Address Strobe Command

CAS Column Address Strobe Command

WE Write Enable

LDQM, UDQM x16 Input/Output Mask

VDD Power

Vss Ground

VDDQ Power Supply for I/O Pin

VssQGround for I/O Pin

NC No Connection

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

PIN FUNCTIONS

Symbol TSOP Pin No. Type Function (In Detail)

A0-A11

23 to 26 Input Pin

Address Inputs: A0-A11 are sampled during the ACTIVE

29 to 34

command (row-address A0-A11) and READ/WRITE command (A0-A7

22, 35

with A10 defining auto precharge) to select one location out of the memory array

in the respective bank. A10 is sampled during a PRECHARGE command to

determine if all banks are to be precharged (A10 HIGH) or bank selected by

BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD

MODE REGISTER command.

BA0, BA1 20, 21 Input Pin

Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied.

CAS

17 Input Pin

CAS, in conjunction with the RAS and WE, forms the device command. See the

"Command Truth Table" for details on device commands.

CKE

37 Input Pin

The CKE input determines whether the CLK input is enabled. The next rising edge

of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When

CKE is LOW, the device will be in either power-down mode, clock suspend mode,

or self refresh mode.

CKE is an

asynchronous i

nput.

CLK

38 Input Pin

CLK is the master clock input for this device. Except for CKE, all inputs to this

device are acquired in synchronization with the rising edge of this pin.

19 Input Pin

The CS input determines whether command input is enabled within the device.

Command input is enabled when CS is LOW, and disabled with CS is HIGH. The

device remains in the previous state when CS is HIGH.

DQ0 to

2, 4, 5, 7, 8, 10, DQ Pin

DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units

DQ15

11,13, 42, 44, 45,

using the LDQM and UDQM pins.

47, 48, 50, 51, 53

LDQM,

15, 39 Input Pin

LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read

UDQM mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the

corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the

HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE

in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer.

When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can

be written to the device. When LDQM or UDQM is HIGH, input data is masked and

cannot be written to the device.

RAS

18 Input Pin

RAS, in conjunction with CAS and WE, forms the device command. See the "Command

Truth Table" item for details on device commands.

16 Input Pin

WE, in conjunction with RAS and CAS, forms the device command. See the "Command

Truth Table" item for details on device commands.

VDDQ

3, 9, 43, 49 Power Supply Pin

VDDQ is the output buffer power supply.

VDD

1, 14, 27 Power Supply Pin

VDD is the device internal power supply.

GNDQ

6, 12, 46, 52 Power Supply Pin

GNDQ is the output buffer ground.

GND

28, 41, 54 Power Supply Pin

GND is the device internal ground.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

FUNCTION (In Detail)

A0-A11 are address inputs sampled during the ACTIVE

(row-address A0-A11)

and READ/WRITE command

(A0-A7

with A10 defining auto PRECHARGE)

. A10 is sampled during

a PRECHARGE command to determine if all banks are to

be PRECHARGED

(A10 HIGH)

or bank selected by BA0,

BA1

(LOW)

. The address inputs also provide the op-code

during a LOAD MODE REGISTER command.

Bank Select Address

(BA0 and BA1)

defines which bank the

ACTIVE, READ, WRITE or PRECHARGE command is

being applied.

CAS, in conjunction with the RAS and WE, forms the

device command. See the “Command Truth Table” for

details on device commands.

The CKE input determines whether the CLK input is

enabled. The next rising edge of the CLK signal will be

valid when is CKE HIGH and invalid when LOW. When

CKE is LOW, the device will be in either power-down

mode, CLOCK SUSPEND mode, or SELF-REFRESH

mode. CKE is an asynchronous input.

CLK is the master clock input for this device. Except for

CKE, all inputs to this device are acquired in synchroni-

zation with the rising edge of this pin.

The CS input determines whether command input is

enabled within the device. Command input is enabled

when CS is LOW, and disabled with CS is HIGH. The

device remains in the previous state when CS is HIGH. DQ0

to DQ15 are DQ pins. DQ through these pins can be

controlled in byte units using the LDQM and UDQM pins.

LDQM and UDQM control the lower and upper bytes of the

DQ buffers. In read mode, LDQM and UDQM control the

output buffer. When LDQM or UDQM is LOW, the corre-

sponding buffer byte is enabled, and when HIGH, dis-

abled. The outputs go to the HIGH Impedance State when

LDQM/UDQM is HIGH. This function corresponds to OE

in conventional DRAMs. In write mode, LDQM and UDQM

control the input buffer. When LDQM or UDQM is LOW,

the corresponding buffer byte is enabled, and data can be

written to the device. When LDQM or UDQM is HIGH,

input data is masked and cannot be written to the device.

RAS, in conjunction with CAS and WE , forms the device

command. See the “Command Truth Table” item for

details on device commands.

WE , in conjunction with RAS and CAS , forms the device

command. See the “Command Truth Table” item for

details on device commands.

VDDQ is the output buffer power supply.

VDD is the device internal power supply.

GNDQ is the output buffer ground.

GND is the device internal ground.

READ

The READ command selects the bank from BA0, BA1

inputs and starts a burst read access to an active row.

Inputs A0-A7 provides the starting column location. When

A10 is HIGH, this command functions as an AUTO

PRECHARGE command. When the auto precharge is

selected, the row being accessed will be precharged at

the end of the READ burst. The row will remain open for

subsequent accesses when AUTO PRECHARGE is not

selected. DQ’s read data is subject to the logic level on

the DQM inputs two clocks earlier. When a given DQM

signal was registered HIGH, the corresponding DQ’s will

be High-Z two clocks later. DQ’s will provide valid data

when the DQM signal was registered LOW.

WRITE

A burst write access to an active row is initiated with the

WRITE command. BA0, BA1 inputs selects the bank, and

the starting column location is provided by inputs A0-A7.

Whether or not AUTO-PRECHARGE is used is deter-

mined by A10.

The row being accessed will be precharged at the end of

the WRITE burst, if AUTO PRECHARGE is selected. If

AUTO PRECHARGE is not selected, the row will remain

open for subsequent accesses.

A memory array is written with corresponding input data

on DQ’s and DQM input logic level appearing at the same

time. Data will be written to memory when DQM signal is

LOW. When DQM is HIGH, the corresponding data inputs

will be ignored, and a WRITE will not be executed to that

byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the

open row in a particular bank or the open row in all banks.

BA0, BA1 can be used to select which bank is precharged

or they are treated as “Don’t Care”. A10 determined

whether one or all banks are precharged. After executing

this command, the next command for the selected banks(s)

is executed after passage of the period tRP, which is the

period required for bank precharging. Once a bank has

been precharged, it is in the idle state and must be

activated prior to any READ or WRITE commands being

issued to that bank.

AUTO PRECHARGE

The AUTO PRECHARGE function ensures that the

precharge is initiated at the earliest valid stage within a

burst. This function allows for individual-bank precharge

without requiring an explicit command. A10 to enables the

AUTO PRECHARGE function in conjunction with a spe-

cific READ or WRITE command. For each individual

READ or WRITE command, auto precharge is either

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

enabled or disabled. AUTO PRECHARGE does not apply

except in full-page burst mode. Upon completion of the

READ or WRITE burst, a precharge of the bank/row that

is addressed is automatically performed.

AUTO REFRESH COMMAND

This command executes the AUTO REFRESH operation.

The row address and bank to be refreshed are automatically

generated during this operation. The stipulated period (tRC)

is required for a single refresh operation, and no other

commands can be executed during this period. This com-

mand is executed at least 4096 times every 64ms. During

an AUTO REFRESH command, address bits are “Don’t

Care”. This command corresponds to CBR Auto-refresh.

SELF REFRESH

During the SELF REFRESH operation, the row address to

be refreshed, the bank, and the refresh interval are

generated automatically internally. SELF REFRESH can

be used to retain data in the SDRAM without external

clocking, even if the rest of the system is powered down.

The SELF REFRESH operation is started by dropping the

CKE pin from HIGH to LOW. During the SELF REFRESH

operation all other inputs to the SDRAM become “Don’t

Care”. The device must remain in self refresh mode for a

minimum period equal to tRAS or may remain in self refresh

mode for an indefinite period beyond that. The SELF-

REFRESH operation continues as long as the CKE pin

remains LOW and there is no need for external control of

any other pins. The next command cannot be executed until

the device internal recovery period (tRC) has elapsed. Once

CKE goes HIGH, the NOP command must be issued

(minimum of two clocks)

to provide time for the completion of

any internal refresh in progress. After the self-refresh, since

it is impossible to determine the address of the last row to

be refreshed, an AUTO-REFRESH should immediately be

performed for all addresses.

BURST TERMINATE

The BURST TERMINATE command forcibly terminates the

burst read and write operations by truncating either fixed-

length or full-page bursts and the most recently registered

READ or WRITE command prior to the BURST TERMI-

NATE.

COMMAND INHIBIT

COMMAND INHIBIT prevents new commands from being

executed. Operations in progress are not affected, apart

from whether the CLK signal is enabled

NO OPERATION

When CS is low, the NOP command prevents unwanted

commands from being registered during idle or wait

states.

LOAD MODE REGISTER

During the LOAD MODE REGISTER command the mode

be issued when all banks are idle.

ACTIVE COMMAND

When the ACTIVE COMMAND is activated, BA0, BA1

inputs selects a bank to be accessed, and the address

inputs on A0-A11 selects the row. Until a PRECHARGE

command is issued to the bank, the row remains open for

accesses.

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Rev. E

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IS42S16400D

TRUTH TABLE – COMMANDS AND DQM OPERATION(1)

FUNCTION CSCS

CSCS

CS RASRAS

RASRAS

RAS CASCAS

CASCAS

CAS WEWE

WEWE

WE DQM ADDR DQs

COMMAND INHIBIT (NOP) H X X X X X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row)(3) L L H H X Bank/Row X

READ (Select bank/column, start READ burst)

(4) LHLHL/H

(8) Bank/Col X

WRITE (Select bank/column, start WRITE burst)

(4) L H L L L/H(8) Bank/Col Valid

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks)

(5) L L H L X Code X

AUTO REFRESH or SELF REFRESH(6,7) LLLHXXX

(Enter self refresh mode)

LOAD MODE REGISTER(2) L L L L X Op-Code X

Write Enable/Output Enable(8) — — — — L — Active

Write Inhibit/Output High-Z(8) — — — — H — High-Z

NOTES:

1. CKE is HIGH for all commands except SELF REFRESH.

2. A0-A11 define the op-code written to the mode register.

3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.

4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables

auto precharge; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”

6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

IS42S16400D

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Rev. E

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TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK

(1-6)

CURRENT STATE

COMMAND (ACTION) CS RAS CAS WE

Any COMMAND INHIBIT

(NOP/Continue previous operation)

HX XX

NO OPERATION

(NOP/Continue previous operation)

LH HH

Idle ACTIVE (Select and activate row) L L H H

AUTO REFRESH(7) LL LH

LOAD MODE REGISTER(7) LL LL

PRECHARGE(11) LL HL

Row Active READ (Select column and start READ burst)(10) LH LH

WRITE (Select column and start WRITE burst)(10) LH LL

PRECHARGE (Deactivate row in bank or banks)(8) LL HL

Read READ (Select column and start new READ burst)(10) LH LH

(Auto WRITE (Select column and start WRITE burst)(10) LH LL

Precharge PRECHARGE (Truncate READ burst, start PRECHARGE)(8) LL HL

Disabled) BURST TERMINATE(9) LH HL

Write READ (Select column and start READ burst)(10) LH LH

(Auto WRITE (Select column and start new WRITE burst)(10) LH LL

Precharge PRECHARGE (Truncate WRITE burst, start PRECHARGE)(8) LL HL

Disabled) BURST TERMINATE(9) LH HL

TRUTH TABLE – CKE (1-4)

CURRENT STATE COMMANDn ACTIONn CKEn-1 CKEn

Power-Down X Maintain Power-Down L L

Self Refresh X Maintain Self Refresh L L

Clock Suspend X Maintain Clock Suspend L L

Power-Down(5) COMMAND INHIBIT or NOP Exit Power-Down L H

Self Refresh(6) COMMAND INHIBIT or NOP Exit Self Refresh L H

Clock Suspend(7) X Exit Clock Suspend L H

All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry H L

All Banks Idle AUTO REFRESH Self Refresh Entry H L

Reading or Writing VALID Clock Suspend Entry H L

See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK

NOTES:

1. CKEn is the logic state of CKE at clock edge

; CKEn-1

was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge

3. COMMANDn is the command registered at clock edge

, and ACTONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge

will put the device in the all banks idle state in time for clock edge

n+1

(provided that t

CKS

is met)

6. Exiting self refresh at clock edge

will put the device in all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands

should be issued on clock edges occurring during the tXSR period. A minimum of two NOP commands must be sent during tXSR period.

7. After exiting clock suspend at clock edge

, the device will resume operation and recognize the next command at clock edge

n+1

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IS42S16400D

NOTE:

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after tXSR has been met (if the

previous state was SELF REFRESH).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those

allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register

accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or

allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to

the other bank are determined by its current state and CURRENT STATE BANK n truth tables.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank

will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will

be in the row active state.

Read w/Auto

Precharge Enabled:

Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met.

Once tRP is met, the bank will be in the idle state.

Write w/Auto

Precharge Enabled:

Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met.

Once tRP is met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be

applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the

SDRAM will be in the all banks idle state.

Accessing Mode

tMRD is met, the SDRAM will be in the all banks idle state.

Precharging All:

Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all

banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs

or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

IS42S16400D

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Rev. E

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TRUTH TABLE – CURRENT STATE BANK

COMMAND TO BANK

(1-6)

CURRENT STATE

COMMAND (ACTION) CS RAS CAS WE

Any COMMAND INHIBIT (NOP/Continue previous operation) H X X X

NO OPERATION (NOP/Continue previous operation) L H H H

Idle Any Command Otherwise Allowed to Bank

XX XX

Row ACTIVE (Select and activate row) L L H H

Activating, READ (Select column and start READ burst)(7) LH LH

Active, or WRITE (Select column and start WRITE burst)(7) LH LL

Precharging PRECHARGE L L H L

Read ACTIVE (Select and activate row) L L H H

(Auto READ (Select column and start new READ burst)(7,10) LH LH

Precharge WRITE (Select column and start WRITE burst)(7,11) LH LL

Disabled) PRECHARGE(9) LL HL

Write ACTIVE (Select and activate row) L L H H

(Auto READ (Select column and start READ burst)(7,12) LH LH

Precharge WRITE (Select column and start new WRITE burst)(7,13) LH LL

Disabled) PRECHARGE(9) LL HL

Read ACTIVE (Select and activate row) L L H H

(With Auto READ (Select column and start new READ burst)(7,8,14) LH LH

Precharge) WRITE (Select column and start WRITE burst)(7,8,15) LH LL

PRECHARGE(9) LL HL

Write ACTIVE (Select and activate row) L L H H

(With Auto READ (Select column and start READ burst)(7,8,16) LH LH

Precharge) WRITE (Select column and start new WRITE burst)(7,8,17) LH LL

PRECHARGE(9) LL HL

NOTE:

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after tXSR has been met (if the previous

state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank

and the commands shown

are those allowed to be issued to bank

(assuming that bank

is in such a state that the given command is allowable)

. Exceptions are

covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register

accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

Read w/Auto

Precharge Enabled:

Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met.

Once tRP is met, the bank will be in the idle state.

Write w/Auto

Precharge Enabled:

Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been

met. Once tRP is met, the bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

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Rev. E

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IS42S16400D

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled

and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-

rupted by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the

READ on bank n, CAS latency later (Consecutive READ Bursts).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt

the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent

bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt

the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to

bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt

the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock

prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the

READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1).

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the

READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The

PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the

WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after

tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered

one clock prior to the READ to bank m (Fig CAP 3).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the

WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where t WR begins when the WRITE

to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4).

IS42S16400D

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Rev. E

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ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameters Rating Unit

VDD MAX Maximum Supply Voltage –1.0 to +4.6 V

VDDQ

MAX Maximum Supply Voltage for Output Buffer –1.0 to +4.6 V

VIN Input Voltage –1.0 to VDDQ + 0.5 V

VOUT Output Voltage –1.0 to VDDQ + 0.5 V

PD MAX Allowable Power Dissipation 1 W

ICS Output Shorted Current 50 mA

TOPR Operating Temperature Com. 0 to +70 °C

Ind. –40 to +85

TSTG Storage Temperature –65 to +150 °C

DC RECOMMENDED OPERATING CONDITIONS(2) (At TA = 0 to +70°C)

Symbol Parameter Min. Typ. Max. Unit

VDD, VDDQ Supply Voltage 3.0 3.3 3.6 V

VIH Input High Voltage(3) 2.0 — VDD + 0.3 V

VIL Input Low Voltage(4) -0.3 — +0.8 V

CAPACITANCE CHARACTERISTICS(1,2) (At TA = 0 to +25°C, VDD = VDDQ = 3.3 ± 0.3V, f = 1 MHz)

Symbol Parameter Typ. Max. Unit

CIN Input Capacitance: Address and Control — 3.8 pF

CCLK Input Capacitance: (CLK) — 3.5 pF

CI/O Data Input/Output Capacitance: I/O0-I/O15 — 6.5 pF

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

2. All voltages are referenced to GND.

3. VIH(max) = VDDQ + 2.0V with a pulse width < 3ns.

4. VIL(min) = GND - 2.0V with a pulse width < 3ns.

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Rev. E

11/21/07

IS42S16400D

DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IIL Input Leakage Current 0V ≤ V IN ≤ V DD, with pins other than –5 5 µA

the tested pin at 0V

IOL Output Leakage Current Output is disabled, 0V ≤ V OUT ≤ V DD –5 5 µA

VOH Output High Voltage Level IOUT = –2 mA 2.4 — V

VOL Output Low Voltage Level IOUT = +2 mA — 0.4 V

ICC1 Operating Current

(1,2)

One Bank Operation, CAS latency = 3 Com. -6 — 95 mA

Burst Length=1 Com. -7 — 85 mA

tRC ≥ t RC (min.) Ind. -7 — 145 mA

IOUT = 0mA

ICC2P Precharge Standby Current CKE ≤ VIL (MAX)tCK = 15ns Com. — — 2 mA

Ind. — — 4 mA

ICC2PS (In Power-Down Mode) tCK = ∞Com. — — 1 mA

Ind. — — 3 mA

ICC2N

(3)

Precharge Standby Current CKE ≥ VIH (MIN)tCK = 15ns — — 20 mA

ICC2NS (In Non Power-Down Mode) tCK = ∞Com. — — 15 mA

Ind. — — 15 mA

ICC3P Active Standby Current CKE ≤ VIL (MAX)tCK = 10ns Com. — — 7 mA

Ind. — — 7 mA

ICC3PS (In Power-Down Mode) tCK = ∞Com. — — 5 mA

Ind. — — 5 mA

ICC3N

(3)

Active Standby Current CKE ≥ VIH (MIN)tCK = 15ns — — 30 mA

ICC3NS (In Non Power-Down Mode) tCK = ∞Com. — — 25 mA

Ind. — — 25 mA

ICC4 Operating Current tCK = tCK (MIN) CAS latency = 3 Com. -6 — 130 mA

(In Burst Mode)

(1)

IOUT = 0mA Com. -7 — 100 mA

BL = 4; 4 banks activated Ind. -7 — 110 mA

ICC5 Auto-Refresh Current tRC = tRC (MIN) CAS latency = 3 Com. -6 — 150 mA

tCLK = tCLK ( MIN) Com. -7 — 130 mA

Ind. -7 — 150 mA

ICC6 Self-Refresh Current CKE ≤ 0.2V — — 1 mA

Notes:

1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time

increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between VDD and GND for each memory

chip to suppress power supply voltage noise (voltage drops) due to these transient currents.

2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.

3. Input signal chnage once per 30ns.

IS42S16400D

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AC ELECTRICAL CHARACTERISTICS (1,2,3)

-6 -7

Symbol Parameter Min. Max. Min. Max. Units

tCK3 Clock Cycle Time CAS Latency = 3 6 — 7 — ns

tCK2 CAS Latency = 2 7.5 — 7.5 — ns

tAC3 Access Time From CLK

(4,6)

CAS Latency = 3 — 5 — 5.4 ns

tAC2 CAS Latency = 2 — 6 — 6 ns

tCHI CLK HIGH Level Width 2 — 2.5 — ns

tCL CLK LOW Level Width 2 — 2.5 — ns

tOH3 Output Data Hold Time

(6)

CAS Latency = 3 2.5 — 2.7 — ns

tOH2 CAS Latency = 2 2.5 — 3 — ns

tLZ Output LOW Impedance Time 0 — 0 — ns

tHZ3 Output HIGH Impedance Time

(5)

CAS Latency = 3 — 5 — 5.4 ns

tHZ2 CAS Latency = 2 — 6 — 6 ns

tDS Input Data Setup Time 1.5 — 1.5 — ns

tDH Input Data Hold Time 0.8 — 0.8 — ns

tAS Address Setup Time 1.5 — 1.5 — ns

tAH Address Hold Time 0.8 — 0.8 — ns

tCKS CKE Setup Time 1.5 — 1.5 — ns

tCKH CKE Hold Time 0.8 — 0.8 — ns

tCKA CKE to CLK Recovery Delay Time

1CLK+3

—

1CLK+3

—ns

tCS Command Setup Time (CS, RAS, CAS, WE, DQM) 1.5 — 2.0 — ns

tCH Command Hold Time (CS, RAS, CAS, WE, DQM) 0.8 — 1 — ns

tRC Command Period (REF to REF / ACT to ACT) 60 — 63 — ns

tRAS Command Period (ACT to PRE) 42

100,000

tRP Command Period (PRE to ACT) 18 — 20 — ns

tRCD Active Command To Read / Write Command Delay Time 18 — 20 — ns

tRRD Command Period (ACT [0] to ACT[1]) 12 — 14 — ns

tDPL or Input Data To Precharge CAS Latency = 3 2CLK — 2CLK — ns

tWR Command Delay time

CAS Latency = 2 2CLK — 2CLK — ns

tDAL Input Data To Active / Refresh CAS Latency = 3

2CLK+tRP

—

2CLK+tRP

—ns

Command Delay time (During Auto-Precharge)

CAS Latency = 2

2CLK+tRP

—

2CLK+tRP

—ns

tTTransition Time 1 10 1 10 ns

tREF Refresh Cycle Time (4096) — 64 — 64 ms

Notes:

1. When power is first applied, memory operation should be started 200 µs after VDD and VDDQ reach their stipulated voltages.

Also note that the power-on sequence must be executed before starting memory operation.

2. Measured with tT = 1 ns.

3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL

(max.).

4. Access time is measured at 1.4V with the load shown in the figure below.

5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)

when the output is in the high impedance state.

6. If clock rising time is longer than 1ns, tr/2 - 0.5ns should be added to the parameter.

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Rev. E

11/21/07

IS42S16400D

AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)

I/O

50 Ω

+1.5V

50 pF

Input Load Output Load

2.0V

1.4V

0.8V

CLK

INPUT

OUTPUT

CHI

2.0V

1.4V

1.4V 1.4V

0.8V

OPERATING FREQUENCY / LATENCY RELATIONSHIPS

SYMBOL PARAMETER -6 -7 UNITS

— Clock Cycle Time 6 7 ns

— Operating Frequency 166 143 MHz

tCCD READ/WRITE command to READ/WRITE command 1 1 cycle

tCKED CKE to clock disable or power-down entry mode 1 1 cycle

tPED CKE to clock enable or power-down exit setup mode 1 1 cycle

tDQD DQM to input data delay 0 0 cycle

tDQM DQM to data mask during WRITEs 0 0 cycle

tDQZ DQM to data high-impedance during READs 2 2 cycle

tDWD WRITE command to input data delay 0 0 cycle

tDAL Data-in to ACTIVE command 5 5 cycle

tDPL Data-in to PRECHARGE command 2 2 cycle

tBDL Last data-in to burst STOP command 1 1 cycle

tCDL Last data-in to new READ/WRITE command 1 1 cycle

tRDL Last data-in to PRECHARGE command 2 2 cycle

tMRD LOAD MODE REGISTER command 2 2 cycle

to ACTIVE or REFRESH command

tROH Data-out to high-impedance from CL = 3 3 3 cycle

PRECHARGE command CL = 2 2 2 cycle

IS42S16400D

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Rev. E

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FUNCTIONAL DESCRIPTION

The 64Mb SDRAMs (1 Meg x 16 x 4 banks) are quad-bank

DRAMs which operate at 3.3V and include a synchronous

interface (all signals are registered on the positive edge of

the clock signal, CLK). Each of the 16,777,216-bit banks

is organized as 4,096 rows by 256 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed

(BA0 and BA1 select the bank, A0-A11

select the row)

. The address bits

(A0-A7)

registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.

The following sections provide detailed information covering

device initialization, register definition, command

descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner.

The 64M SDRAM is initialized after the power is applied

to VDD and VDDQ (simultaneously), and the clock is stable

with DQM High and CKE High.

A 100µs delay is required prior to issuing any command

other than a

COMMAND INHIBIT

or a

NOP

. The COMMAND

INHIBIT or NOP may be applied during the 100µs period and

continue should at least through the end of the period.

With at least one COMMAND INHIBIT or NOP command

having been applied, a PRECHARGE command should be

applied once the 100µs delay has been satisfied. All banks

must be precharged. This will leave all banks in an idle

state,

after which at least two AUTO REFRESH

cycles must

be performed. After the

AUTO REFRESH

cycles are com-

plete, the SDRAM is then ready for mode register program-

ming.

The mode register should be loaded prior to applying any

operational command because it will power up in an

unknown state. After the Load Mode Register command, at

least two NOP commands must be asserted prior to any

command.

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IS42S16400D

Mode Register

The mode register is used to define the specific mode of

operation of the SDRAM. This definition includes the

selection of a burst length, a burst type, a CAS latency, an

operating mode and a write burst mode, as shown in MODE

The mode register is programmed via the LOAD MODE

until it is programmed again or the device loses power.

Mode register bits M0-M2 specify the burst length, M3

specifies the type of burst

(sequential or interleaved)

, M4- M6

specify the CAS latency, M7 and M8 specify the operating

mode, M9 specifies the WRITE burst mode, and M10 and

M11 are reserved for future use.

The mode register must be loaded when all banks are idle,

and the controller must wait the specified time before

initiating the subsequent operation. Violating either of

these requirements will result in unspecified operation.

MODE REGISTER DEFINITION

Latency Mode

M6 M5 M4 CAS Latency

0 0 0 Reserved

0 0 1 Reserved

0 1 0 2

0 1 1 3

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

1. To ensure compatibility with future devices,

should program M11, M10 = "0, 0"

Write Burst Mode

M9 Mode

0 Programmed Burst Length

1 Single Location Access

Operating Mode

M8 M7 M6-M0 Mode

0 0 Defined Standard Operation

— — — All Other States Reserved

Burst Type

M3 Type

0 Sequential

1 Interleaved

Burst Length

M2 M1 M0 M3=0 M3=1

0 0 0 1 1

0 0 1 2 2

0 1 0 4 4

0 1 1 8 8

1 0 0 Reserved Reserved

1 0 1 Reserved Reserved

1 1 0 Reserved Reserved

1 1 1 Full Page Reserved

Reserved

Address Bus

Mode Register (Mx)

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

(1)

IS42S16400D

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BURST DEFINITION

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

2 0 0-1 0-1

1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

4 0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0-A7 Cn, Cn + 1, Cn + 2 Not Supported

Page Cn + 3, Cn + 4...

(y) (location 0-y) …Cn - 1,

Cn…

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as

shown in MODE REGISTER DEFINITION. The burst

length determines the maximum number of column loca-

tions that can be accessed for a given READ or WRITE

command. Burst lengths of 1, 2, 4 or 8 locations are

available for both the sequential and the interleaved burst

types, and a full-page burst is available for the sequential

type. The full-page burst is used in conjunction with the

BURST TERMINATE command to generate arbitrary

burst lengths.

Reserved states should not be used, as unknown opera-

tion or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of

columns equal to the burst length is effectively selected.

All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a

boundary is reached. The block is uniquely selected by

A1-A7 (x16) when the burst length is set to two; by A2-A7

(x16) when the burst length is set to four; and by A3-A7

(x16) when the burst length is set to eight. The remaining

(least significant) address bit(s) is (are) used to select the

starting location within the block. Full-page bursts wrap

within the page if the boundary is reached.

Burst Type

Accesses within a given burst may be programmed to be

either sequential or interleaved; this is referred to as the

burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by

the burst length, the burst type and the starting column

address, as shown in BURST DEFINITION table.

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Rev. E

11/21/07

IS42S16400D

DON'T CARE

UNDEFINED

CLK

COMMAND

READ NOP NOP NOP

CAS Latency - 3

tAC

tOH

DOUT

T0 T1 T2 T3 T4

tLZ

CLK

COMMAND

READ NOP NOP

CAS Latency - 2

tAC

tOH

DOUT

T0 T1 T2 T3

tLZ

CAS Latency

The CAS latency is the delay, in clock cycles, between the

registration of a READ command and the availability of the first

piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the

latency is

clocks, the data will be available by clock

edge

n +

m. The DQs will start driving as a result of the

clock edge one cycle earlier

(n + m

- 1), and provided that

the relevant access times are met, the data will be valid

by clock edge

n +

m. For example, assuming that the

clock cycle time is such that all relevant access times are

met, if a READ command is registered at T0 and the

latency is programmed to two clocks, the DQs will start

driving after T1 and the data will be valid by T2, as shown

in CAS Latency diagrams. The Allowable Operating

Frequency table indicates the operating frequencies at

which each CAS latency setting can be used.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and M8

to zero; the other combinations of values for M7 and M8 are

CAS Latency

Allowable Operating Frequency (MHz)

Speed CAS Latency = 2 CAS Latency = 3

6 133 166

7 133 143

reserved for future use and/or test modes. The programmed

burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with future

versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2

applies to both READ and WRITE bursts; when M9 = 1, the

programmed burst length applies to READ bursts, but

write accesses are single-location (nonburst) accesses.

IS42S16400D

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Rev. E

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CLK

CKE HIGH - Z

ROW ADDRESS

BANK ADDRESS

RAS

CAS

A0-A11

BA0, BA1

Activating Specific Row Within Specific Bank

DON'T CARE

CLK

COMMAND ACTIVE NOP NOP

tRCD

T0 T1 T2 T3 T4

READ or

WRITE

OPERATION

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to

a bank within the SDRAM, a row in that bank must be

“opened.”

This is accomplished via the ACTIVE command,

which selects both the bank and the row to be activated

(see

Activating Specific Row Within Specific Bank

After opening a row

(issuing an ACTIVE command)

, a READ

or WRITE command may be issued to that row, subject to

the tRCD specification. Minimum tRCD should be divided by

the clock period and rounded up to the next whole number

to determine the earliest clock edge after the ACTIVE

command on which a READ or WRITE command can be

entered. For example, a tRCD specification of 20ns with a

125 MHz clock (8ns period) results in 2.5 clocks, rounded

to 3. This is reflected in the following example, which

covers any case where 2 < [tRCD (MIN)/tCK] ≤ 3. (The

same procedure is used to convert other specification

limits from time units to clock cycles).

A subsequent ACTIVE command to a different row in the

same bank can only be issued after the previous active

row has been “closed” (precharged). The minimum time

interval between successive ACTIVE commands to the

same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be

issued while the first bank is being accessed, which

results in a reduction of total row-access overhead. The

minimum time interval between successive ACTIVE com-

mands to different banks is defined by tRRD.

Example: Meeting tRCD (MIN) when 2 <<

< [tRCD (min)/tCK] ≤≤

≤≤

≤ 3

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

CLK

CKE HIGH-Z

COLUMN ADDRESS

AUTO PRECHARGE

NO PRECHARGE

RAS

CAS

A0-A7

A10

BA0, BA1 BANK ADDRESS

A8, A9, A11

READ COMMANDREADS

READ bursts are initiated with a READ command, as

shown in the READ COMMAND diagram.

The starting column and bank addresses are provided with

the READ command, and auto precharge is either enabled

or disabled for that burst access. If auto precharge is

enabled, the row being accessed is precharged at the

completion of the burst. For the generic READ commands

used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the

starting column address will be available following the

CAS latency after the READ command. Each subsequent

data-out element will be valid by the next positive clock

edge. The CAS Latency diagram shows general timing

for each possible CAS latency setting.

Upon completion of a burst, assuming no other commands

have been initiated, the DQs will go High-Z. A full-page

burst will continue until terminated. (At the end of the page,

it will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a

subsequent READ command, and data from a fixed-length

READ burst may be immediately followed by data from a

READ command. In either case, a continuous flow of data

can be maintained. The first data element from the new

burst follows either the last element of a completed burst or

the last desired data element of a longer burst which is

being truncated.

The new READ command should be issued

cycles

before the clock edge at which the last desired data

element is valid, where

equals the CAS latency minus

one. This is shown in Consecutive READ Bursts for CAS

latencies of two and three; data element

+ 3 is either the

last of a burst of four or the last desired of a longer burst.

The 64Mb SDRAM uses a pipelined architecture and

therefore does not require the

rule associated with a

prefetch architecture. A READ command can be initiated

on any clock cycle following a previous READ command.

Full-speed random read accesses can be performed to the

same bank, as shown in Random READ Accesses, or each

subsequent READ may be performed to a different bank.

Data from any READ burst may be truncated with a

subsequent WRITE command, and data from a fixed-length

READ burst may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations).

The WRITE burst may be initiated on the clock edge

immediately following the last (or last desired) data

element from the READ burst, provided that I/O contention

can be avoided. In a given system design, there may be

a possibility that the device driving the input data will go

Low-Z before the SDRAM DQs go High-Z. In this case, at

least a single-cycle delay should occur between the last

read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown

in Figures RW1 and RW2. The DQM signal must be

asserted (HIGH) at least three clocks prior to the WRITE

command (DQM latency is two clocks for output buffers)

to suppress data-out from the READ. Once the WRITE

command is registered, the DQs will go High-Z (or remain

High-Z), regardless of the state of the DQM signal,

provided the DQM was active on the clock just prior to the

WRITE command that truncated the READ command. If

not, the second WRITE will be an invalid WRITE. For

example, if DQM was LOW during T4 in Figure RW2, then

the WRITEs at T5 and T7 would be valid, while the WRITE

at T6 would be invalid.

The DQM signal must be de-asserted prior to the WRITE

command (DQM latency is zero clocks for input buffers)

to ensure that the written data is not masked.

A fixed-length READ burst may be followed by, or truncated

with, a

PRECHARGE

command to the same bank

(provided

that auto precharge was not activated)

, and a full-page burst

may be truncated with a PRECHARGE command to the

same bank. The PRECHARGE command should be issued

cycles before the clock edge at which the last desired data

element is valid, where

equals the CAS latency minus one.

This is shown in the READ to PRECHARGE diagram for each

IS42S16400D

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Rev. E

11/21/07

DON'T CARE

UNDEFINED

CLK

COMMAND

READ NOP NOP NOP

CAS Latency - 3

tAC

tOH

DOUT

T0 T1 T2 T3 T4

tLZ

CLK

COMMAND

READ NOP NOP

CAS Latency - 2

tAC

tOH

DOUT

T0 T1 T2 T3

tLZ

CAS Latency

possible CAS latency; data element

+ 3 is either the last of

a burst of four or the last desired of a longer burst. Following

the PRECHARGE command, a subsequent command to the

same bank cannot be issued until tRP is met. Note that part

of the row precharge time is hidden during the access of the

last data element(s).

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the

optimum time (as described above) provides the same

operation that would result from the same fixed-length

burst with auto precharge. The disadvantage of the

PRECHARGE command is that it requires that the com-

mand and address buses be available at the appropriate

time to issue the command; the advantage of the

PRECHARGE command is that it can be used to truncate

fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the BURST

TERMINATE command, and fixed-length READ bursts

may be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The

BURST TERMINATE command should be issued

cycles

before the clock edge at which the last desired data

element is valid, where

equals the CAS latency minus

one. This is shown in the READ Burst Termination

diagram for each possible CAS latency; data element

3 is the last desired data element of a longer burst.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6

READ

NOP NOP NOP READ NOP NOP

OUT

n+1

OUT

n+2

OUT

n+3

OUT

BANK,

COL n BANK,

COL b

CAS Latency - 2

x = 1 cycle

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

READ

NOP NOP NOP READ NOP NOP NOP

DOUT n

DOUT n+1

DOUT n+2

DOUT n+3

DOUT b

BANK,

COL n BANK,

COL b

CAS Latency - 3

x = 2 cycles

Consecutive READ Bursts

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5

READ

NOP NOP

DOUT n

DOUT b

DOUT m

DOUT x

BANK,

COL n BANK,

COL b

CAS Latency - 2

BANK,

COL m BANK,

COL x

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6

READ

NOP NOP NOP

OUT

BANK,

COL n BANK,

COL b

CAS Latency - 3

BANK,

COL m BANK,

COL x

Random READ Accesses

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

DON'T CARE

CLK

DQM

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5

READ

NOP NOP NOP NOP WRITE

BANK,

COL n BANK,

COL b

DOUT n

DIN b

tDS

tHZ

CAS Latency - 3

RW1 - READ to WRITE

RW2 - READ to WRITE

DON'T CARE

CLK

DQM

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6

READ

NOP NOP NOP NOP NOP WRITE

BANK,

COL n

DIN b

tDS

tHZ

BANK,

COL b

CAS Latency - 2

DOUT n

DOUT

n+1 DOUT

n+2

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

READ

NOP NOP NOP NOP NOP ACTIVE

DOUT n

DOUT n+1

DOUT n+2

DOUT n+3

BANK a,

COL n BANK a,

ROW

BANK

(a or all)

CAS Latency - 2

x = 1 cycle

tRP

PRECHARGE

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

READ

NOP NOP NOP NOP NOP ACTIVE

DOUT n

DOUT n+1

DOUT n+2

DOUT n+3

BANK,

COL n BANK,

COL b

CAS Latency - 3

x = 2 cycles

tRP

BANK a,

ROW

PRECHARGE

READ to PRECHARGE

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6

READ

NOP NOP NOP NOP NOP

OUT

n+1

OUT

n+2

OUT

n+3

BANK a,

COL n

CAS Latency - 2

x = 1 cycle

BURST

TERMINATE

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

READ

NOP NOP NOP NOP NOP NOP

DOUT n

DOUT n+1

DOUT n+2

DOUT n+3

BANK,

COL n

CAS Latency - 3

x = 2 cycles

BURST

TERMINATE

READ Burst Termination

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

CLK

CKE HIGH - Z

COLUMN ADDRESS

AUTO PRECHARGE

BANK ADDRESS

RAS

CAS

A0-A7

A10

BA0, BA1

NO PRECHARGE

A8, A9, A11

WRITE Command

The starting column and bank addresses are provided with

the WRITE command, and auto precharge is either enabled

or disabled for that access. If auto precharge is enabled, the

row being accessed is precharged at the completion of the

burst. For the generic WRITE commands used in the

following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid

data-in

element will be

registered coincident

with the

WRITE

command.

Subsequent

data elements will be registered on each successive

positive clock edge. Upon completion of a fixed-length

burst, assuming no other commands have been initiated,

the DQs will remain High-Z and any additional input data will

be ignored (see WRITE Burst). A full-page burst will

continue until terminated. (At the end of the page, it will wrap

to column 0 and continue.)

Data for any WRITE burst may be truncated with a

subsequent WRITE command, and data for a fixed-length

WRITE burst may be immediately followed by data for a

WRITE command. The new WRITE command can be issued

on any clock following the previous WRITE command, and

the data provided coincident with the new command applies

to the new command.

An example is shown in WRITE to WRITE diagram. Data

+ 1 is either the last of a burst of two or the last desired of

a longer burst. The 64Mb SDRAM uses a pipelined architec-

ture and therefore does not require the

rule associated

with a prefetch architecture. A WRITE command can be

initiated on any clock cycle following a previous WRITE

command. Full-speed random write accesses within a page

can be performed to the same bank, as shown in Random

WRITE Cycles, or each subsequent WRITE may be per-

formed to a different bank.

Data for any WRITE burst may be truncated with a subse-

quent READ command, and data for a fixed-length WRITE

burst may be immediately followed by a subsequent READ

command. Once the READ command is registered, the

data inputs will be ignored, and WRITEs will not be ex-

ecuted. An example is shown in WRITE to READ. Data

1 is either the last of a burst of two or the last desired of a

longer burst.

Data for a fixed-length WRITE burst may be followed by, or

truncated with, a PRECHARGE command to the same bank

(provided that auto precharge was not activated), and a full-

page WRITE burst may be truncated with a PRECHARGE

command to the same bank. The PRECHARGE command

should be issued tWR after the clock edge at which the last

desired input data element is registered. The auto precharge

mode requires a tWR of at least one clock plus time,

regardless of frequency. In addition, when truncating a

WRITE burst, the DQM signal must be used to mask input

data for the clock edge prior to, and the clock edge coincident

with, the PRECHARGE command. An example is shown in

the WRITE to PRECHARGE diagram. Data

+1 is either the

last of a burst of two or the last desired of a longer burst.

Following the PRECHARGE command, a subsequent com-

mand to the same bank cannot be issued until tRP is met.

In the case of a fixed-length burst being executed to comple-

tion, a PRECHARGE command issued at the optimum time

(as described above)

provides the same operation that would

result from the same fixed-length burst with auto precharge.

The disadvantage of the

PRECHARGE

command is that it

requires that the command and address buses be available at

the appropriate time to issue the command; the advantage of

the PRECHARGE command is that it can be used to truncate

fixed-length or full-page bursts.

Fixed-length or full-page WRITE bursts can be truncated

with the BURST TERMINATE command. When truncating

a WRITE burst, the input data applied coincident with the

BURST TERMINATE command will be ignored. The last

data written (provided that DQM is LOW at that time) will

be the input data applied one clock previous to the BURST

TERMINATE command. This is shown in WRITE Burst

Termination, where data

is the last desired data element

of a longer burst.

WRITEs

WRITE bursts are initiated with a WRITE command, as

shown in WRITE Command diagram.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

CLK

COMMAND

ADDRESS

T0 T1 T2 T3

WRITE

NOP

DIN n

DIN n+1

BANK,

COL n

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2

WRITE

NOP

WRITE

DIN n

DIN n+1

DIN b

BANK,

COL n BANK,

COL b

DON'T CARE

WRITE Burst

WRITE to WRITE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3

WRITE

DIN n

DIN b

DIN m

DIN x

BANK,

COL n BANK,

COL b BANK,

COL m BANK,

COL x

Random WRITE Cycles

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

DON'T CARE

CLK

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5

WRITE

NOP

READ

NOP

NOP NOP

DIN n

DIN n+1

DOUT b

DOUT b+1

BANK,

COL n BANK,

COL b

CAS Latency - 2

WRITE to READ

WP1 - WRITE to PRECHARGE

DON'T CARE

CLK

DQM

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6

WRITE

NOP NOP ACTIVE NOP NOP

BANK a,

COL n BANK a,

ROW

BANK

(a or all)

tWR

tRP

PRECHARGE

DIN n

DIN n+1

CAS Latency - 2

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

CLK

COMMAND

ADDRESS

T0 T1 T2

WRITE

DIN n

( DATA )

BANK,

COL n

DON'T CARE

(ADDRESS)

BURST

TERMINATE

COMMAND

WRITE Burst Termination

DON'T CARE

CLK

DQM

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6

WRITE

NOP NOP NOP ACTIVE NOP

BANK a,

COL n BANK a,

ROW

BANK

(a or all)

tWR

tRP

PRECHARGE

DIN n

DIN n+1

CAS Latency - 3

WP2 - WRITE to PRECHARGE

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

CLK

CKE

HIGH - Z

ALL BANKS

BANK SELECT

BANK ADDRESS

RAS

CAS

A0-A9, A11

A10

BA0, BA1

DON'T CARE

CLK

CKE

COMMAND NOP NOP

ACTIVE

≥ tCKStCKS

All banks idle

Enter

power-down mode

Exit power-down mode

tRCD

tRAS

tRC

Input buffers gated

off

PRECHARGE Command

POWER-DOWN

Power-down occurs if CKE is registered LOW coincident

with a NOP or COMMAND INHIBIT when no accesses are

in progress. If power-down occurs when all banks are idle,

this mode is referred to as precharge power-down; if

power-down occurs when there is a row active in either

bank, this mode is referred to as active power-down.

Entering power-down deactivates the input and output

buffers, excluding CKE, for maximum power savings

while in standby. The device may not remain in the power-

down state longer than the refresh period (64ms) since no

refresh operations are performed in this mode.

The power-down state is exited by registering a NOP or

COMMAND INHIBIT and CKE HIGH at the desired clock

edge (meeting tCKS). See figure below.

PRECHARGE

The PRECHARGE command (see figure) is used to

deactivate the open row in a particular bank or the open

row in all banks. The bank(s) will be available for a

subsequent row access some specified time (tRP) after

the PRECHARGE command is issued. Input A10 deter-

mines whether one or all banks are to be precharged, and

in the case where only one bank is to be precharged,

inputs BA0, BA1 select the bank. When all banks are to be

precharged, inputs BA0, BA1 are treated as “Don’t Care.”

Once a bank has been precharged, it is in the idle state and

must be activated prior to any READ or WRITE com-

mands being issued to that bank.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

DON'T CARE

CLK

CKE

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5

NOP

WRITE

NOP NOP

BANK a,

COL n

n+1 D

n+2

INTERNAL

CLOCK

DON'T CARE

CLK

CKE

COMMAND

ADDRESS

T0 T1 T2 T3 T4 T5 T6

READ

NOP NOP NOP NOP NOP

BANK a,

COL n

DOUT n

OUT

n+1

OUT

n+2

OUT

n+3

INTERNAL

CLOCK

CLOCK SUSPEND

Clock suspend mode occurs when a column access/burst

is in progress and CKE is registered LOW. In the clock

suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled

LOW, the next internal positive clock edge is suspended.

Any command or data present on the input pins at the time

of a suspended internal clock edge is ignored; any data

present on the DQ pins remains driven; and burst counters

are not incremented, as long as the clock is suspended.

(See following examples.)

Clock suspend mode is exited by registering CKE HIGH;

the internal clock and related operation will resume on the

subsequent positive clock edge.

Clock Suspend During WRITE Burst

Clock Suspend During READ Burst

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

DON'T CARE

CLK

COMMAND

BANK n

BANK m

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

NOP NOP NOP NOP NOP NOP

OUT

a+1

OUT

b+1

BANK n,

COL a BANK m,

COL b

CAS Latency - 3 (BANK n)

CAS Latency - 3 (BANK m)

RP - BANK n

RP - BANK m

READ - AP

BANK n

READ - AP

BANK m

Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle

Page Active READ with Burst of 4 Precharge

Internal States

DON'T CARE

CLK

COMMAND

BANK n

BANK m

ADDRESS

DQM

T0 T1 T2 T3 T4 T5 T6 T7

NOP NOP NOP NOP NOP NOP

DOUT a

DIN b

DIN b+1

DIN b+2

DIN b+3

BANK n,

COL a BANK m,

COL b

CAS Latency - 3 (BANK n)

tRP - BANK n tRP - BANK m

WRITE - AP

BANK n

WRITE - AP

BANK m

READ with Burst of 4 Interrupt Burst, Precharge Idle

Page Active WRITE with Burst of 4 Write-Back

Internal States Page Active

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by programming

the write burst mode bit

(M9)

in the mode register to a logic 1.

In this mode, all

WRITE

commands result in the access of a

single column location (burst of one), regardless of the

programmed burst length. READ commands access

columns according to the programmed burst length and

sequence, just as in the normal mode of operation (M9 = 0).

CONCURRENT AUTO PRECHARGE

An access command (READ or WRITE) to another bank

while an access command with auto precharge enabled is

executing is not allowed by SDRAMs, unless the SDRAM

supports CONCURRENT AUTO PRECHARGE. ISSI

SDRAMs support CONCURRENT AUTO PRECHARGE.

Four cases where CONCURRENT AUTO PRECHARGE

occurs are defined below.

READ with Auto Precharge

1. Interrupted by a READ (with or without auto precharge):

A READ to bank m will interrupt a READ on bank n, CAS

latency later. The PRECHARGE to bank n will begin

when the READ to bank m is registered.

2. Interrupted by a WRITE (with or without auto precharge):

A WRITE to bank m will interrupt a READ on bank n

when registered. DQM should be used two clocks prior

to the WRITE command to prevent bus contention. The

PRECHARGE to bank n will begin when the WRITE to

bank m is registered.

Fig CAP 1 - READ With Auto Precharge interrupted by a READ

Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

DON'T CARE

CLK

COMMAND

BANK n

BANK m

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

NOP NOP NOP NOP NOP NOP

DIN a

DIN a+1

DOUT b

DOUT b+1

BANK n,

COL a BANK m,

COL b

CAS Latency - 3 (BANK m)

RP - BANK n

RP - BANK m

WRITE - AP

BANK n

READ - AP

BANK m

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4 Precharge

Internal States

- BANK n

DON'T CARE

CLK

COMMAND

BANK n

BANK m

ADDRESS

T0 T1 T2 T3 T4 T5 T6 T7

NOP NOP NOP NOP NOP NOP

BANK n,

COL a BANK m,

COL b

RP - BANK n

RP - BANK m

WRITE - AP

BANK n

WRITE - AP

BANK m

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4 Write-Back

Internal States

- BANK n

DIN a

DIN a+1 DIN a+2

DIN b

DIN b+1 DIN b+2 DIN b+3

WRITE with Auto Precharge

3. Interrupted by a READ (with or without auto precharge):

A READ to bank m will interrupt a WRITE on bank n when

registered, with the data-out appearing

CAS latency

later.

The PRECHARGE to bank n will begin after tWR is met,

where tWR begins when the READ to bank m is registered.

The last valid

WRITE

to bank n will be data-in registered

one clock prior to the READ to bank m.

4. Interrupted by a WRITE (with or without auto precharge):

WRITE

to bank m will interrupt a

WRITE

on bank n when

registered. The PRECHARGE to bank n will begin after

tWR is met, where tWR begins when the WRITE to bank

m is registered. The last valid data WRITE to bank n will

be data registered one clock prior to a WRITE to bank m.

Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ

Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

INITIALIZE AND LOAD MODE REGISTER(1)

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

tCH tCLtCK

tCMH tCMS tCMH tCMS tCMH tCMS

tCKS tCKH

T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3

tMRDtRCtRCtRP

ROW

BANK

tAS tAH

CODE

ALL BANKS

SINGLE BANK

ALL BANKS

AUTO

REFRESH AUTO

REFRESH Load MODE

T = 100µs Min.

Power-up: VCC

and CLK stable

Precharge

all banks

AUTO REFRESH Program MODE REGISTER

NOP

PRECHARGE

NOP NOP NOP ACTIVE

(2, 3, 4)

AUTO REFRESH

At least 2 Auto-Refresh Commands

Notes:

1. If CS is High at clock High time, all commands applied are NOP.

2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired.

3. JEDEC and PC100 specify three clocks.

4. Outputs are guaranteed High-Z after the command is issued.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

POWER-DOWN MODE CYCLE

CAS latency = 2, 3

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

tAS tAH

BANK

tCH

tCLtCK

tCMS tCMH

tCKS tCKH

PRECHARGE

NOP NOP NOP

ACTIVE

ALL BANKS

SINGLE BANK

ROW

BANK

tCKStCKS

Precharge all

active banks

All banks idle

Two clock cycles

Input buffers gated

off while in

power-down mode

All banks idle, enter

power-down mode

Exit

ower-down mode

T0 T1 T2 Tn+1 Tn+2

High-Z

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

CLOCK SUSPEND MODE

Notes:

1. CAS latency = 3, burst length = 2

2. A8, A9, and A11 = "Don't Care"

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

CMS

CMH

CKS

CKH

COLUMN m

(2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

READ NOP NOP NOP NOP NOP WRITE NOP

CKS

CKH

BANK BANK

COLUMN n

(2)

tOH

OUT

m D

OUT

m+1

tLZ

UNDEFINED

OUT

e+1

OUT

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

AUTO-REFRESH CYCLE

CAS latency = 2, 3

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

CKS

CKH

T0 T1 T2 Tn+1 To+1

ALL BANKS

SINGLE BANK

BANK

(s)

ROW

BANK

High-Z

PRECHARGE

NOP NOP NOP ACTIVE

Auto

Refresh

Auto

Refresh

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

SELF-REFRESH CYCLE

CAS latency = 2, 3

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

tAS tAH

BANK

tCL

tCHtCK

tCMS tCMH

tCKS tCKH

ALL BANKS

SINGLE BANK

tCKS

Precharge all

active banks

CLK stable prior to exiting

self refresh mode

Enter self

refresh

mode

Exit

self refresh

mode

(Restart refresh time base)

T0 T1 T2 Tn+1 To+1 To+2

High-Z

Auto

Refresh Auto

Refresh

PRECHARGE

NOP NOP NOP

tCKS

≥ t

RAS

XSR

DON'T CARE

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

READ WITHOUT AUTO PRECHARGE

DON'T CARE

UNDEFINED

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

ACTIVE NOP READ NOP NOP NOP

PRECHARGE

NOP ACTIVE

ROW

BANK

COLUMN m

(2)

CMS

CMH

CKS

CKH

BANK

RCD

CAS Latency

OUT

m+1

OUT

m+2 D

OUT

m+3

T0 T1 T2 T3 T4 T5 T6 T7 T8

DISABLE AUTO PRECHARGE

ROW

BANK

RAS

ALL BANKS

SINGLE BANK

BANK

Notes:

1. CAS latency = 2, burst length = 4

2. A8, A9, and A11 = "Don't Care"

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

READ WITH AUTO PRECHARGE

DON'T CARE

UNDEFINED

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE

ROW

BANK

COLUMN m

(2)

CMS

CMH

CKS

CKH

BANK

RCD

RAS

CAS Latency

OUT

m+1

OUT

m+2 D

OUT

m+3

T0 T1 T2 T3 T4 T5 T6 T7 T8

ENABLE AUTO PRECHARGE

ROW

BANK

Notes:

1. CAS latency = 2, burst length = 4

2. A8, A9, and A11 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

SINGLE READ WITHOUT AUTO PRECHARGE

DON'T CARE

UNDEFINED

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

ACTIVE NOP READ NOP NOP

PRECHARGE

NOP ACTIVE NOP

ROW

BANK

COLUMN m

(2)

CMS

CMH

CKS

CKH

BANK

RCD

RAS

CAS Latency

OUT

T0 T1 T2 T3 T4 T5 T6 T7 T8

DISABLE AUTO PRECHARGE

ROW

BANK

ALL BANKS

SINGLE BANK

BANK

Notes:

1. CAS latency = 2, burst length = 1

2. A8, A9, and A11 = "Don't Care"

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

SINGLE READ WITH AUTO PRECHARGE

DON'T CARE

UNDEFINED

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

ACTIVE NOP NOP NOP READ NOP NOP ACTIVE NOP

ROW

BANK

COLUMN m

(2)

CMS

CMH

CKS

CKH

BANK

RCD

RAS

CAS Latency

OUT

T0 T1 T2 T3 T4 T5 T6 T7 T8

ENABLE AUTO PRECHARGE

ROW

BANK

Notes:

1. CAS latency = 2, burst length = 1

2. A8, A9, and A11 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

ALTERNATING BANK READ ACCESSES

BANK 0 BANK 3 BANK 3 BANK 0

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

tCMS tCMH

tAS tAH

tRCD - BANK 0

CAS Latency - BANK 0

RCD

- BANK 0

tRAS - BANK 0

tRC - BANK 0

tCH

tCLtCK

tCMS tCMH

tCKS tCKH

ACTIVE

NOP READ NOP

ACTIVE

NOP READ NOP

ACTIVE

ROW

BANK 0

ROW ROW

tRRD tRCD - BANK 3

tRP - BANK 0

COLUMN m

(2)

ROW

COLUMN b

(2)

ROW

ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8

tAC

tOH tOH tOH tOH tOH

OUT

m D

OUT

tAC tAC tAC tAC tAC

tLZ

CAS Latency - BANK 3

Notes:

1. CAS latency = 2, burst length = 4

2. A8, A9, and A11 = "Don't Care"

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

READ - FULL-PAGE BURST

DON'T CARE

UNDEFINED

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

ACTIVE NOP READ NOP NOP NOP NOP NOP

BURST TERM NOP NOP

ROW

BANK

COLUMN m(2)

CMS

CMH

CKS

CKH

BANK

RCD

CAS Latency

tOH tOH tOH tOH tOH tOH

DOUT m DOUT m+

DOUT m+

DOUT m-

DOUT m DOUT m+

each row (x4) has

1,024 locations Full page

completion

Full-page burst not self-terminating.

Use BURST TERMINATE command.

T0 T1 T2 T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4

Notes:

1. CAS latency = 2, burst length = full page

2. A8, A9, and A11 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

READ - DQM OPERATION

DON'T CARE

UNDEFINED

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

ACTIVE NOP READ NOP NOP NOP NOP NOP NOP

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

ROW

BANK

RCD

CAS Latency

OUT

COLUMN m

(2)

BANK

CMS

CMH

CKS

CKH

T0 T1 T2 T3 T4 T5 T6 T7 T8

Notes:

1. CAS latency = 2, burst length = 4

2. A8, A9, and A11 = "Don't Care"

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

WRITE - WITHOUT AUTO PRECHARGE

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

tCMS tCMH

tAS tAH

tRCD

tRAS

tRC

tCH

tCLtCK

tCMS tCMH

tCKS tCKH

ACTIVE

NOP WRITE NOP NOP NOP

PRECHARGE

NOP

ACTIVE

tWR

(3)

tRP

COLUMN m

(2)

ROW

DISABLE AUTO PRECHARGE

ROW

BANK

tDS tDH tDS tDH tDS tDHtDS tDH

DIN m DIN m+1 DIN m+2 DIN m+3

BANK BANK BANK

ALL BANKS

SINGLE BANK

T0 T1 T2 T3 T4 T5 T6 T7 T8

Notes:

1. burst length = 4

2. A8, A9, and A11 = "Don't Care"

3. tRAS must not be violated

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

WRITE - WITH AUTO PRECHARGE

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

RCD

RAS

CMS

CMH

CKS

CKH

ACTIVE

NOP WRITE NOP NOP NOP NOP NOP NOP

ACTIVE

COLUMN m

(2)

ROW

BANK BANK

ENABLE AUTO PRECHARGE

ROW

BANK

m D

m+1 D

m+2 D

m+3

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

Notes:

1. burst length = 4

2. A8, A9, and A11 = "Don't Care"

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

SINGLE WRITE - WITHOUT AUTO PRECHARGE

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

RCD

RAS

CMS

CMH

CKS

CKH

ACTIVE NOP WRITE NOP

(4)

NOP

(4)

PRECHARGE

NOP

ACTIVE

NOP

(3)

DISABLE AUTO PRECHARGE

ROW

BANK

COLUMN m(2)

ROW

BANK BANK BANK

ALL BANKS

SINGLE BANK

T0 T1 T2 T3 T4 T5 T6 T7 T8

Notes:

1. burst length = 1

2. A8, A9, and A11 = "Don't Care"

3. tRAS must not be violated

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

SINGLE WRITE - WITH AUTO PRECHARGE

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

RCD

RAS

CMS

CMH

CKS

CKH

ACTIVE NOP

(3)

NOP

(3)

NOP

(3)

WRITE NOP NOP NOP ACTIVE NOP

COLUMN m

(2)

ROW

BANK BANK

ENABLE AUTO PRECHARGE

ROW

BANK

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

Notes:

1. burst length = 1

2. A8, A9, and A11 = "Don't Care"

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

ALTERNATING BANK WRITE ACCESS

BANK 0 BANK 1 BANK 1 BANK 0

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

RCD

- BANK 0

RCD

- BANK 0

- BANK 1

RAS

- BANK 0

CMS

CMH

CKS

CKH

ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE

m D

b D

ROW

BANK 0

ROW ROW

RRD

RCD

- BANK 1

- BANK 0 t

- BANK 0

COLUMN m

(2)

ROW

COLUMN b

(2)

ROW

ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

Notes:

1. burst length = 4

2. A8, A9, and A11 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

ACTIVE NOP WRITE NOP NOP NOP NOP

BURST TERM NOP

ROW

BANK

RCD

m D

m+1 D

m+2 D

m+3 D

m-1

COLUMN m(2)

CMS

CMH

CKS

CKH

BANK

Full page completed

T0 T1 T2 T3 T4 T5 Tn+1 Tn+2

WRITE - FULL PAGE BURST

Notes:

1. burst length = full page

2. A8, A9, and A11 = "Don't Care"

IS42S16400D

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

DON'T CARE

CLK

CKE

COMMAND

DQM/

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

CMS

CMH

ACTIVE NOP WRITE NOP NOP NOP NOP NOP

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

ROW

BANK

RCD

m D

m+2 D

m+3

COLUMN m(2)

BANK

CMS

CMH

CKS

CKH

T0 T1 T2 T3 T4 T5 T6 T7

WRITE - DQM OPERATION

Notes:

1. burst length = 4

2. A8, A9, and A11 = "Don't Care"

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

11/21/07

IS42S16400D

ORDERING INFORMATION

Commercial Range: 0°°

°°

°C to 70°°

°°

°C

Frequency Speed (ns) Order Part No. Package

166 MHz 6 IS42S16400D-6T 400-mil TSOP II

166 MHz 6 IS42S16400D-6TL 400-mil TSOP II, Lead-free

166 MHz 6 IS42S16400D-6BL 60-ball fBGA, Lead-free

143 MHz 7 IS42S16400D-7T 400-mil TSOP II

143 MHz 7 IS42S16400D-7TL 400-mil TSOP II, Lead-free

143 MHz 7 IS42S16400D-7BL 60-ball fBGA, Lead-free

Industrial Range: -40°°

°°

°C to 85°°

°°

°C

Frequency Speed (ns) Order Part No. Package

166 MHz 6 IS42S16400D-6TLI 400-mil TSOP II, Lead-free

166 MHz 6 IS42S16400D-6BLI 60-ball fBGA, Lead-free

143 MHz 7 IS42S16400D-7TI 400-mil TSOP II

143 MHz 7 IS42S16400D-7TLI 400-mil TSOP II, Lead-free

143 MHz 7 IS42S16400D-7BLI 60-ball fBGA, Lead-free

PACKAGING INFORMATION

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. D

02/16/06

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Mini Ball Grid Array

Package Code: B (60-Ball)

mBGA - 10.1mm x 6.4mm

MILLIMETERS INCHES

Sym. Min. Typ. Max. Min. Typ. Max.

No.

Leads 60

A — — 1.20 — — 0.047

A1 0.23 0.28 0.33 0.009 0.011 0.013

D 10.00 10.10 10.20 0.394 0.398 0.402

D1 — 9.10 — — 0.358 —

E 6.30 6.40 6.50 0.248 0.252 0.256

E1 — 3.90 — — 0.154 —

e — 0.65 — — 0.026 —

7 6 5 4 3 2 1

1 2 3 4 5 6 7

ø 0.40 + +/-0.05 (60X)

SEATING PLANE

Notes:

1. Controlling dimensions are in millimeters.

2. 0.65 mm Ball Pitch

PACKAGING INFORMATION

Integrated Silicon Solution, Inc.

Rev. D

03/13/07

Plastic TSOP 54–Pin, 86-Pin

Package Code: T (Type II)

Plastic TSOP (T - Type II)

Millimeters Inches

Symbol Min Max Min Max

Ref. Std.

No. Leads (N) 54

A — 1.20 — 0.047

A1 0.05 0.15 0.002 0.006

A2 — — — —

b 0.30 0.45 0.012 0.018

C 0.12 0.21 0.005 0.0083

D 22.02 22.42 0.867 0.8827

E1 10.03 10.29 0.395 0.405

E 11.56 11.96 0.455 0.471

e 0.80 BSC 0.031 BSC

L 0.40 0.60 0.016 0.024

L1 — — — —

ZD 0.71 REF

α0° 8° 0° 8°

SEATING PLANE

1N/2

N/2+1N

Lα

Notes:

1. Controlling dimension: millimieters,

unless otherwise specified.

2. BSC = Basic lead spacing between

centers.

3. Dimensions D and E1 do not include

mold flash protrusions and

should be

measured from the bottom of the

package

4. Formed leads shall be planar with

respect to one another within 0.004

inches at the seating plane.

Plastic TSOP (T - Type II)

Millimeters Inches

Symbol Min Max Min Max

Ref. Std.

No. Leads (N) 86

A — 1.20 — 0.047

A1 0.05 0.15 0.002 0.006

A2 0.95 1.05 0.037 0.041

b 0.17 0.27 0.007 0.011

C 0.12 0.21 0.005 0.008

D 22.02 22.42 0.867 0.8827

E1 10.03 10.29 0.395 0.405

E 11.56 11.96 0.455 0.471

e 0.50 BSC 0.020 BSC

L 0.40 0.60 0.016 0.024

L1 0.80 REF 0.031 REF

ZD 0.61 REF 0.024 BSC

α0° 8° 0° 8°