Application Note 1067
Sep. 2011 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
1
Application Notes for AP3770 System Solution
Prepared by Su Qing Hua
System Engineering Dept.
1. Introduction
The AP3770 uses Pulse Frequency Modulation (PFM)
method to realize Discontinuous Conduction Mode (DCM)
operation for FLYBACK power supplies. The principle of
PFM is different with that of Pulse Width Modulation
(PWM), so the design of transformer is also different.
The AP3770 can provide accurate constant voltage,
constant current (CV/CC) regulation by using Primary Side
Regulation (PSR). AP3770 has the special technique to
suppress the audio noise, internal line compensation to
reduce the number of system components, fixed cable
compensation to compensate the voltage drop on different
output cable for achieving good CV regulation.
The AP3770 can achieve low standby power less than
30mW.
Figure 1. 5V/1A Output for Battery Charger of Mobile Phone
Figure 1 is AP3770 typical application circuit, which is a
FLYBACK converter controlled by AP3770 with a
3-winding transformer---Primary winding (Np), Secondary
winding (Ns) and Auxiliary winding (Na). The AP3770
senses the auxiliary winding feedback voltage at FB pin
and obtains power supply at VCC pin.
Figure 2 is the typical operation waveforms of PFM
controller. In this figure, a series of relative idea operation
waveforms are given to illustrate some parameters used in
following design steps. And the nomenclature of the
parameters in Figure 2 is illustrated.
Vdri---A simplified driving signal of primary transistor
Ip---The primary side current
Is ---The secondary side current
VSEC---The voltage of secondary
tSW---The period of switching frequency
tONP ---The time of primary side “ON”
tONS ---The time of secondary side “ON”
tOFF ---The discontinuous time
tOFFS --- The time of secondary side “Off”
IPK---Peak current of primary side
IPKS---Peak current of secondary side
VS---the sum of Vo and forward voltage of rectification
diode
Application Note 1067
Sep. 2011 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
2
Figure 2. Operation Waveforms
2. Five Aspects for System Design
1. Low Standby Power Design
2. Switching Frequency Design
3. Transformer and Power Devices Design
4. Feedback Resistors Design
5. Line Compensation Design
2.1 Low Standby Power Design
In order to achieve low standby power, AP3770 decreases
the minimum operating voltage. And due to proprietary
Zero-Startup-Current technique, the startup up resistors
R3+R4 should be higher to 10M to 14MΩ to further lower
the power loss. The recommended value of dummy load
resistor R13 is 4.7KΩ to 10KΩ for an model with 5V
output voltage. The selection of dummy load resistor is a
tradeoff between standby power and I-V Curve.
2.2 Switching Frequency Design
Figure 3. Relationship Between VCPC, fSW and IO with Constant Peak Current
tONP
tONS
IPK
IPKS
tSW
VS
IP
IS
Vdri
tOFFS
VCPC
1.4V
fSW
47.6kHz
fSW
IO
20kHz
VCS_REF
VH=0.5V
42%IO
tOFF
VSEC
Application Note 1067
Sep. 2011 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
3
When the constant peak current is adopted, the voltage of
CPC pin is increased linearly with load increasing. The
maximum value of VCPC is equal to
V.V.VDD
t
t
SW
ONS 4153
10
4=⋅=⋅ (1)
The primary current ip(t) is sensed by a current sense
resistor RCS as shown in Figure 2. The power transferring
from input to output is given by:
SWpkPO fILP ⋅⋅⋅= 2
2
1 (2)
Where, the fSW is the switching frequency. When the peak
current IPK is constant, the output power depends on the
switching frequency fSW. fSW is linearly increased with load
increasing.
In AP3770, two-segmented peak current is used to realize
audio noise suppression. The peak current is about 0.5V
when IO>42%IOmax, and the peak current is about
0.5V/1.5 when IO<42%IOmax.
Figure 4. Relationship Between VCPC, fSW and IO with Variable Peak Current
So, the voltage of CPC pin and switching frequency has a
mutation at about 42% of load. At the mutation point, if the
peak current is changed from 0.5V( high IPK) to 0.33V(low
IPK), the voltage of CPC pin at low IPK will be increased to
1.5 times of VCPC at high IPK and the switching frequency
fSW at low IPK will be increased to 2.25 times of fSW at high
IPK. So the range of load working in the audio frequency is
suppressed.
Figure 5. Hysteresis at Conversion Between Low IPK and High IPK
VCS_REF
VH=0.5V
VL=0.5V/1.5
42%IO
39%IO IO
VCS
_
REF
VLOAD
VCPC
0.42хIO
_
MAX IO_MAX
VH=0.5V
VL=0.5V/1.5
f
SW
23.1kHz
3.85kHz
55kHz
52kHz
f
SW
IO_MAX
0.42хIO
_
MAX
20kHz
ISOURCE
IO_MAX
0.42хIO
_
MAX
2/3 * I SOURCE
Application Note 1067
Sep. 2011 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
4
In order to avoid oscillation, a hysteresis is added at the
conversion between low IPK and high IPK. Considering the
relationship between audio noise and flux density of
transformer, deltaB≤2500 gauss is better for audio noise
suppression.
The low limitation of maximum switching frequency is
given by audio noise suppression. And the upper limit of
the AP3770 can be up to 120kHz. But this is only the limit
of the IC; the finally designed maximum switching
frequency is determined by the tradeoff between the
efficiency, mechanical dimensions and thermal
performance.
2.3 Transformer and Power Devices Design
In Constant Current operation of AP3770, the CC loop
control function of AP3770 will keep a fixed proportion
between D1 (in Figure 1) on-time tONS and D1 off-time
tOFFS (in Figure 2) by discharging or charging a capacitor
embedded in the IC. The fixed proportion is
6
4
=
OFFS
ONS
t
t (3)
The relationship between the output constant-current and
secondary peak current IPKS is given by:
OFFSONS
ONS
pksO tt
t
II +
⋅⋅= 2
1 (4)
At the instant of D1 turn-on, the primary current transfers
to the secondary at an amplitude of:
pk
S
P
pks I
N
N
I⋅= (5)
Thus the output constant-current is given by:
pk
S
P
OFFSONS
ONS
pk
S
P
OI
N
N
tt
t
I
N
N
I⋅⋅=
+
⋅⋅⋅= 5
1
2
1 (6)
Design Steps:
Step 1, a reasonable IPK of FLYBACK with AP3770
should be designed
1-1. Calculate the Max. turn ratio of XFMR
The maximum turn ration of XFRM should be designed
first, which is to ensure that the system should work in
DCM in all working conditions, especially at the min. input
voltage and full load.
As we know, if the system can meet equation (7) at
minimum input voltage and full load, it can work in DCM
in all working conditions.
OFFSONSSW ttt
+
≥
(7)
For the primary side current,
indc
p
pkONP V
L
It ⋅= (8)
Where LP is the inductance of primary winding.
Vindc is the rectified DC voltage of input.
When Vindc is the minimum value, the maximum tONP can
be obtained. So,
min_indc
p
pkONP_MAX V
L
It ⋅= (9)
For the secondary side current,
S
S
pksONS V
L
It ⋅= (10)
In (10), LS is the inductance of secondary winding.
dOS VVV
+
=
, Vd is the forward voltage of secondary diode.
For (10), in CV regulation, the VS is a constant voltage, so
tONS is a constant value with different input voltage.
In FLYBACK converter, when the primary transistor turns
ON, the energy stored in the magnetizing inductance Lp.
So the power transferring from the input to the output is
given by,
inininininin IVPP
ηη
⋅⋅=⋅=
' (11)
SWpkpin fILP ⋅⋅⋅= 2
'
2
1 (12)
Here, '
in
Pis input power of transformer, not including the
all of the power loss at primary side (Rectifier, RCD
snubber, BJT and so on).
in
η
is definition to the input efficiency of system, which is
about 0.9.
Then,
inin
pkp
SW P
IL
t
η
⋅⋅
⋅
=2
2
(13)
tSW, tONP and tONS in (7) are replaced with (13), (9) and (10),
indc_min
p
pk
s
s
pks
inin
2
pkp
V
L
I
V
L
I
P2
IL ⋅+⋅≥
⋅⋅
⋅
η
(14)
Application Note 1067
Sep. 2011 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
5
Because the peak current and inductance of primary side
and secondary side have the following relationship,
ipkpks INI
η
⋅⋅= (15)
2
p
s
N
L
L=
(16)
Here, N is the turn ratio of primary and secondary sides.
With (14), (15) and (16), then,
inS
i
inin
pk
V
1
NVP2
I+
⋅
≥
⋅⋅
η
η
(17)
Because,
η
IV
POO
in
⋅
= (18)
η
is the system efficiency.
At full load, the system will work in the boundary of CC
regulation. IO can be given by,
pks
SW
ONS
OI
t
t
I⋅⋅= 2
1 (19)
Then, IPKS can be defined,
Opks IkI ⋅= (20)
In the design of AP3770,
5
t
t
k
ONS
SW =
⋅
=2 (21)
The following can be obtained,
)
VVV2
ηk
(VN
dO
i
iinO
indc_min +
−
⋅⋅⋅
⋅
⋅≤
η
ηη
(22)
1-2. Calculate the peak current of primary side and
current sensed resistor
IPK can be calculated by the output current.
N
Ik
N
I
IO
pks
pk
⋅
==⋅ i
η
(23)
Here, k=5, 9.0
i=
η
, which is the efficiency of IPK and IPKS.
N is the calculated value of Nmax.
In AP3770, 0.5V is an internal reference voltage. If the
sensed voltage VCS reaches 0.5V, the power transistor will
be shut down and tONP will be ended.
pk
CS I
0.5V
R= (24)
So RCS can be obtained from (24) and selected with a real
value from the standard resistor series. After RCS selected,
IPK should be modified based on the selected RCS.
From now on, IPK and RCS have been designed.
Step 2, Design Transformer
2-1. Calculate the inductance of primary side---LP
The primary side inductance LP is relative with the stored
energy. LP should be big enough to store enough energy, so
that PO_Max can be obtained from this system.
From formula (18), the output power can be given by,
in
SW
2
pkpO
η
fIL
2
1
P
η
⋅⋅⋅⋅= (25)
Where fSW was set by the user based on definite
requirement.
Then, LP can be gotten by,
η
η
in
SW
2
PK
O
PfI
P2
L⋅
⋅
⋅
= (26)
2-2. Re-calculate the turn ratio of primary and
secondary side---N
From formula (24), the turn ratio of primary and secondary
side N can be re-calculated.
)(k
I
Ik
N
pk
O5
i
=
⋅
⋅
=
η
(27)
2-3. Calculate the turns of primary, secondary and
auxiliary sides
First, the reasonable core-type and ∆Bshould be selected.
Then, the turns of 3-winding transformer can be obtained
respectively.
The turns of primary winding,
∆BAe
IL
NPKP
p⋅
⋅
= (28)
The turns of secondary winding,
N
N
NP
S= (29)
The turns of auxiliary winding,
S
AS
AV
VN
N
⋅
= (30)
Application Note 1067
Sep. 2011 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
6
Where VA=VCC+ Vda, VCC is the set IC supply voltage and
Vda is the voltage drop of the auxiliary diode.
For AP3770, the typical value of UVLO is decreased to
5.5V, so the supply voltage of IC，VCC can be set to a
typical value---12V.
VS is equal to VO+Vd.
Ae can be gotten automatically after core-type is selected.
2-4. Check the maximum duty cycle of primary side
After turn ratio of primary side and secondary side is
designed, the maximum duty cycle of primary side at low
line voltage can be calculated again.
Considering the Volt-second balance between magnetizing
and de-magnetizing, the formula of duty cycle is
indc
dO
V
NVV
D4.0)( ⋅⋅+
= (31)
Step 3, Select diode and primary transistor
3-1. Select diodes of secondary and auxiliary sides
Maximum reverse voltage of secondary side，
P
indc_m
dr N
NV
VV Sax
O
⋅
+= (32)
Maximum reverse voltage of auxiliary side,
P
Aindc_m
Ard N
NV
VV ⋅
+= ax
a (33)
In (32) and (33), the maximum DC input voltage should be
used.
3-2. Select the primary side transistor
S
PS
indc_maxdc_spikedc_max N
NV
VVV ⋅
++= (34)
Be careful that the value of Vdc_spike will be different with
different snubber circuit.
Design Example:
Specification:
Input voltage: 85VAC to 265VAC
Output voltage: VO=5.3V (Considering the cable
compensation)
Output current: IO=1.1A
Efficiency: 80%
It is higher than the total efficiency because the loss in the
input rectifier and the BJT are not included.
Other setting by users:
Switching frequency: fSW=54kHz (Should be equal to or
higher than 54kHz)
Forward voltage of secondary diode: Vd=0.4V
Forward voltage of auxiliary diode: Vda=1.1V
VCC voltage: VCC=12V
Core_type: EE16 (Ae=19.2mm2)
Set
∆
B:
∆
B<3000GS
Vdc_spike=100V (with snubber circuit)
Design Steps:
Step 1, a reasonable IPK of FLYBACK with AP3770
should be designed.
1-1. Calculate the maximum turn ratio of XFMR
))(k
VVV2
ηk
(VN
dO
i
iinO
indc_minMAX 5=
+
−
⋅⋅⋅
⋅
⋅=
η
ηη
(35)
402VV inac_minindc_min −⋅= , 0.75=
η
, 9.0=
in
η
, 9.0
=
i
η
22
≈
MAX
N (36)
The turn ratio is finally selected as: 18.5=N
1-2. Calculate the peak current of primary side and
current sensed resistor
N
Ik
N
I
IO
pks
pk
⋅
==⋅ i
η
( 9.0
i=
η
, which is the transfer
efficiency of Ipk and Ipks)
mAI pk_max 330
=
(37)
Sensed current resistor,
359m
max_
CS 0.5V
I
V
R
pk
CS == (38)
Ω
≈
1.5R CS (39)
Re-calculate peak current of primary side,
mAI pk_max 333
=
(40)
Step 2, Design Transformer
2-1. Calculate the inductance of primary side---LP
η
η
in
SW
2
PK
O
PfI
P2
L⋅
⋅
⋅
= (41)
mHLp2.035
=
(42)
Application Note 1067
Sep. 2011 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
7
2-2. Re-calculate the turn ratio of primary and
secondary side---N
)(k
I
Ik
N
pk
O5
i
=
⋅
⋅
=
η
(43)
18.3=N (44)
2-3. Calculate the turns of primary, secondary and
auxiliary sides
The turns of primary winding,
∆BAe
IL
NPKP
p⋅
⋅
= (45)
TNP811> (46)
The turns of secondary winding,
N
N
NP
S=
(47)
TNS7≈ (48)
Recalculate the primary winding,
N
SP ⋅= NN (49)
TNP128≈ (50)
The turns of auxiliary winding,
d
AS
AVV
VN
N+
⋅
=
o
(51)
TNA15≈ (52)
2-4. Check the maximum duty cycle of primary side
The maximum duty cycle of primary side is calculated as
following,
indc
dO
V
NVV
D4.0)(
⋅
⋅
+
=
(53)
0.528
80
4.08.31)4.03.5(4.0)(
|
min_
min_ =
⋅⋅+
=
⋅
⋅
+
=
indc
dO
VV
NVV
Dindc
(54)
Step 3, Select diode and primary tran si st or
3-1. Select diodes of secondary and auxiliary sides
Maximum reverse voltage of secondary side，
P
indc_m
dr N
NV
VV Sax
O
⋅
+=
(55)
2265V
ax ⋅=
indc_m
V (56)
28V
17
375
5.4 ≈+=
dr
V
(57)
Maximum reverse voltage of auxiliary side,
P
Aindc_m
Ard N
NV
VV
⋅
+= ax
a
(58)
VVdar 65
128
15375
12 ≈
⋅
+=
(59)
3-2. Select primary side transistor
S
PS
indc_maxdc_spikedc_max N
NV
VVV ⋅
++=
(60)
567V17*4.5375100
max_c ≈
+
+
=
d
V (61)
Design Results Summary:
1.Calculate the maximum peak current of primary side and RCS
IPK= 333 mA Peak current of primary side
RCS= 1.5
Ω Current sensed resistor
2.Design transformer
LP= 2 mH(+/-8%) Inductance of primary side
N= 17 Turn ratio of primary and secondary
NP= 128 T Turns of primary side
NS= 7 T Turns of secondary side
NA= 15 T Turns of auxiliary side
DMAX 0.52 Maximum duty cycle of primary side at VINDC=80V
3. Select diode and primary transistor
Vdr= 28 V Maximum reverse voltage of secondary diode
Vdar= 56 V Maximum reverse voltage of auxiliary diode
VdcMax= 567 V Voltage stress of primary transistor
Application Note 1067
Sep. 2011 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
8
2.4 Feedback Resistors Design
Figure 6. Feedback Resistors Circuit
From above Figure 6,
D
A
S
FB
FBFB
FBo V
N
N
R
)R(R
VV −⋅
+
⋅=
2
21
(62)
Through adjusting RFB1 and R FB2, a suitable output voltage
can be achieved. The recommended values of RFB1 and R
FB2 are within 5kΩ to 50kΩ.
2.5 Line Compensation Design
The internal line compensation function in AP3770 is
shown in Figure 7. S1 is closed when the primary switch is
“ON”. The line voltage can be detected from the FB pin.
The detected voltage internally compensates the peak
current. So the line compensation is determined by RLINE.
In different application, the value of RLINE is different.
Figure 7. Line Compensation Circuit
Application Note 1067
Sep. 2011 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
9
tSW
tOFF
tONP
FB
t
VN
Figure 8. Waveform of FB Pin
The negative voltage VN of FB pin (in Figure 8) is linear to
line voltage. The AP3770 samples VN to realize the line
compensation.
indc
p
a
FBFB
FB V
N
N
RR
R⋅⋅
+
=
21
2
N
V
(63)
The compensated voltage of line compensation (VCS_LINE)
can be calculated by the following formula,
indc
p
a
FBFB
FB
line
Nlinelinecs
V
N
N
RR
R
k
R
V
k
KRV
⋅⋅
+
⋅⋅⋅=
⋅⋅⋅=
21
2
_
670
1
8.0
670
1
(64)
So, RLINE can be adjusted to achieve excellent line
regulation of output current.
3. Summary
In order to get good performance of AP3770, it’s important
to design transformer, line compensation and feedback
resistance correctly. This application only gives a
preliminary design guideline about these aspects and
considers ideal conditions, so some parameters need to be
adjusted slightly on the basis of the calculated results.
