G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Features : Description : The GLT6200L08 is a low power CMOS Static RAM organized as 262,144 x 8 bits. Easy memory expansion is provided by an active LOW CE1 an Low-power consumption. -active: 30mA at 55ns. -stand by : 10 A (CMOS input / output) 2 A (CMOS input / output, SL) Single +2.7 to 3.3V power supply. active LOW OE , and Tri-state I/O's. This device has Equal access and cycle time. 55/70/85 ns access time. 1.0V data retention mode. TTL compatible, tri-state input/output. Automatic power-down when deselected. Industrial grade (-40C ~ 85C) available. Package available: 32-sTSOP. 48Ball CSP-BGA an automatic power-down mode feature when deselected. Writing to the device is accomplished by taking chip Enable 1 ( CE1 ) with Write Enable ( WE ) LOW. Reading from the device is performed by taking Chip Enable 1 ( CE1 ) with Output Enable ( OE ) LOW while Write Enable ( WE ) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected : the outputs are disabled during a write cycle. The GLT6200L08 comes with a 1V data retention feature and Lower Standby Power. The GLT6200L08 is available in a 32-pin sTSOP packages. Function Block Diagram : SENSE AMP ROW DECODER Row Address INPUT BUFFER Cell Array COLUMN DECODER I/O7 I/O1 CONTROL CIRCUIT OE WE CE1 CE2 Column Address G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -1- G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Pin Configurations : sTSOPI GLT6200L08 A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE A10 CE1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A0 A1 A2 A3 48 Ball fpBGA : 1 2 3 4 5 6 7 8 A B C D E F G H 1 A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9 2 A1 A2 NC NC NC NC 3 CE2 NC NC NC NC 4 A3 A4 A5 NC NC A17 A16 A12 5 A6 A7 NC NC NC NC A15 A13 6 A8 I/O0 I/O1 VCC VSS I/O2 I/O3 A14 WE OE CE Note : NC means no Ball. Pin Descriptions: Name A0 - A17 CE 1 and CE2 OE WE I/O0 - I/O7 VCC GND NC Function Address Inputs Chip Enable Input Output Enable Input Write Enable Input Data Input and Data Output 3V Power Supply Ground No Connection G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -2- A10 A11 G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Truth Table: CE1 WE OE Data Mode H X X X X X High-Z High-Z Standby Standby L L L H H L L H X Data Out High-Z Data Out Active, Read Active, Output Disable Active, Write *Key : X = Don't Care, L = Low, H = High Absolute Maximum Ratings* Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Power Dissipation Storage Temperature (Plastic) Temperature Under Bias Vt PT Tstg Tbias -0.5 -55 -40 Vcc+0.5 1.0 +150 +85 V W C C *Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions ( TA = -25C to + 85C) Parameter Symbol Min Typ Supply Voltage Input Voltage * VCC Gnd VIH VIL 2.7 0.0 2.0 -0.5* 3 0.0 - Max Unit 3.3 0.0 VCC+0.2 0.6 V V V V VIL min = -1.0V for pulse width less than tRC/2. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -3- G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) DC Operating Characteristics ( Vcc=2.7V to 3.3V, TA =-25C to + 85C) Parameter Input Leakage Current Sym. ILI Output Leakage Current ILO Operating Power Supply Current ICC Min VCC = Max, Vin = Gnd to VCC 70 Max 1 Min 85 Max 1 Min Unit Max 1 A 1 1 1 A 3 3 3 mA 30 30 25 mA 3 3 3 mA 0.5 0.5 0.5 mA 10 10 10 A 2 2 2 A 0.4 0.4 V CE1 =VIH VCC = Max, VOUT = Gnd to VCC CE1 =VIL , VIN=VIH or VIL, IOUT=0mA ICC1 Average Operating Current 55 Test Conditions CE1 =VIL , IOUT = 0mA, Min Cycle, 100% Duty ICC2 CE1 =0.2V IOUT = 0mA, Cycle Time=1s, 100% Duty Standby Power Supply ISB Current(TTL Level) Standby Power Supply ISB1 Current (CMOS Level) CE1 =VIH CE1 VCC0.2V or f=0 VIN 0.2V or VIN VCC-0.2V Output Low Voltage VOL IOL = 2 mA Output High Voltage VOH IOH = -1 mA 0.4 2.4 Data Retention Parameter Sym. VCC for Data retention VDR Data Retention Current ICCDR Chip Deselect to Data Retention Time tCDR (2) Operating Recovery Time 2.4 Test Conditions CE1 VCC -0.2V or VIN VCC -0.2V or VIN 0.2V tR 2.4 V Min. Max. Unit 1.0 - V - 2 A 0 - ns tRC - ns G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -4- G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Data Retention Waveform (TA = -25C to + 85C) Data Retention Mode Vcc 2.7V 2.7V VDR >= 1.0V tCDR CE tR VIH AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Level VIH VDR AC Test Loads and Waveforms 0.4V to 2.4V 5 ns CL* TTL 1.4V Output Load Condition CL = 30pf + 1TTL Load *Including Scope and Jig Capacitance Read Cycle (3,9)( Vcc=2.7V to 3.3V, TA =-25C to + 85C) Parameter 55 Symbol Min Read Cycle Time tRC 70 Max 55 Min 85 Max 70 Min Unit Note Max 85 ns Address Access Time tAA 55 70 85 ns Chip Enable Access Time tACE 55 70 85 ns Output Enable Access Time tOE 40 40 40 ns Output Hold from address Change tOH 10 10 10 ns Chip Enable to Output in Low-Z tCLZ 10 10 10 ns 4,5 Chip Disable to Output in High-Z tCHZ ns 4,5 Output Enable to Output in Low-Z tOLZ ns 4,5 Output Disable to Output in High-Z tOHZ ns 4,5 Power-Up Time tPU ns 5 Power-Down Time tPD ns 5 25 5 30 5 20 0 25 0 55 35 5 30 0 70 85 G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. 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IV, Science Based Industrial Park, Hsin Chu, Taiwan. -5- G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled) tRC Address tOH tAA Data Valid DOUT Timing Waveform of Read Cycle 2 (5,6,8,9) ( CE1 Controlled) CE1 tRC OE tOE tACE tOHZ tCHZ tOLZ DOUT Data Valid tCLZ tPD ICC tPU Supply Current 50% 50% ISB Write Cycle (3,11)( Vcc=2.7V to 3.3V, TA =-25C to + 85C) Parameter 55 Symbol Min 70 Max Min 85 Max Min Unit Note Max Write Cycle Time tWC 55 70 85 ns Chip Enable to Write End tCW 40 60 70 ns Address Setup to Write End tAW 40 60 70 ns Address Setup Time tAS 0 0 0 ns Write Pulse Width tWP 40 50 60 ns Write Recovering Time tWR 0 0 0 ns Data Valid to Write End tDW 25 30 35 ns Data Hold Time tDH 0 0 0 ns Write Enable to Output in High-Z tWZ Output Active from Write End tOW 25 5 30 5 35 5 ns 4,5 ns 4,5 G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -6- G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Timing Waveform of Write Cycle 1 (10,11) ( WE Controlled) tWC tAW tWR Address WE tWP tAS tDW DIN tDH Data Valid tWZ tOW DOUT Timing Waveform of Write Cycle 2 (10,11) ( CE1 Controlled) tWC tAW tWR Address tAS tCW CE1 tWP WE tWZ tDW DIN tDH Data Valid DOUT G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -7- G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Notes : 1. 2. 3. 4. 5. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition. This parameter is tested with CL = 5pF. Transition is measured 500mV from steady - state voltage. This parameter is guaranteed, but is not tested. 6. WE 7. CE1 and OE is HIGH for read cycle. are LOW and for read cycle. 8. Address valid prior to or coincident with CE1 transition LOW . 9. All read cycle timings are referenced from the last valid address to the first transition address. 10. CE1 or WE must be HIGH during address transition. 11. All write cycle timings are referenced from the last valid address to the first transition address. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -8- G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Ordering Information Part Number SPEED POWER PACKAGE GLT6200L08LL-55 ST GLT6200L08LL-70 ST GLT6200L08LL-85 ST GLT6200L08SL-55 ST GLT6200L08SL-70 ST GLT6200L08SL-85 ST GLT6200L08LLI-55 ST GLT6200L08LLI-70 ST GLT6200L08LLI-85 ST GLT6200L08SLI-55 ST GLT6200L08SLI-70 ST GLT6200L08SLI-85 ST GLT6200L08LL-55 FG GLT6200L08LL-70 FG GLT6200L08LL-85 FG GLT6200L08SL-55 FG GLT6200L08SL-70 FG GLT6200L08SL-85 FG GLT6200L08LLI-55 FG GLT6200L08LLI-70 FG GLT6200L08LLI-85 FG GLT6200L08SLI-55 FG GLT6200L08SLI-70 FG GLT6200L08SLI-85 FG 55ns 70ns 85ns 55ns 70ns 85ns 55ns 70ns 85ns 55ns 70ns 85ns 55ns 70ns 85ns 55ns 70ns 85ns 55ns 70ns 85ns 55ns 70ns 85ns Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L sTSOPI 32L fpBGA-48L fpBGA-48L fpBGA-48L fpBGA-48L fpBGA-48L fpBGA-48L fpBGA-48L fpBGA-48L fpBGA-48L fpBGA-48L fpBGA-48L fpBGA-48L G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. 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IV, Science Based Industrial Park, Hsin Chu, Taiwan. -9- G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Parts Numbers (Top Mark) Definition : GLT 6 200 L 08 LL I - 55 TS 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 64K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 VOLTAGE Blank : 5V L : 3.3V M : 2.5V N : 2.1V SPEED -SRAM 10 : 10ns 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) ST : sTSOP (Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP FG : 48-fpBGA I : Industrial Temperature LL : Low Low power L : Low power SL : Super Low power G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 10 - G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) Package Information 32 pin 8x13.4mm Small Outline J-form Package (sTSOP) G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 11 - G -LINK GLT6200L08 Ultra Low Power 256k x 8 CMOS SRAM Nov 2000(Rev. 1.0) GLT6200L08 fpBGA C aaa A A1 D D1 E A B C D E F G H 1 2 3 O O O O O O O O SYMBOL A A1 O O O O O O O O b e C O O O O O O O O 4 O O O O O O O O 5 O O O O O O O O 6 PACKAGE OUTLINE DWG. O O O O O O O O b E1 D D1 E E1 e aaa UNIT : MM 1.100.1 0.220.05 0.35 0.36TYP 8.000.10 5.25 6.000.10 3.75 0.75TYP 0.10 G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 12 -