G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features : Description :
∗ Low-power consumption.
-active: 30mA at 55ns.
-stand by :
10 µA (CMOS input / output)
2 µA (CMOS input / output, SL)
∗ Single +2.7 to 3.3V power supply.
∗ Equal access and cycle time.
∗ 55/70/85 ns access time.
∗ 1.0V data retention mode.
∗ TTL compatible, tri-state input/output.
∗ Automatic power-down when deselected.
∗ Industrial grade (-40°C ~ 85°C)
available.
∗ Package available: 32-sTSOP.
48Ball CSP-BGA
The GLT6200L08 is a low power CMOS Static
RAM organized as 262,144 x 8 bits. Easy memory
expansion is provided by an active LOW CE1 an
active LOW OE , and Tri-state I/O’s. This device has
an automatic power-down mode feature when
deselected.
Writing to the device is accomplished by taking
chip Enable 1 ( CE1 ) with Write Enable ( WE ) LOW.
Reading from the device is performed by taking Chip
Enable 1 ( CE1 ) with Output Enable ( OE ) LOW
while Write Enable ( WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance
state when the device is deselected : the outputs are
disabled during a write cycle.
The GLT6200L08 comes with a 1V data retention
feature and Lower Standby Power. The GLT6200L08
is available in a 32-pin sTSOP packages.
Function Block Diagram :
ROW DECODER
Cell
Array
SENSE AMP
INPUT BUFFER
COLUMN DECODER CONTROL
CIRCUIT
OE
WE
CE1
CE2
I/O7
I/O1
Column Address
Row Address
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
Pin Configurations :
sTSOPI GLT6200L08
A16
A7
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
26
25
24
23 GND
OE
A10
14
27
28 I/O7
I/O6
20 A0
7
WE
VCC
15
16
29
30
31
32A11
A9
A8
A13
CE2
A15
A14
A12
A6
A5
A4A3
A2
A1
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
CE1
A17
48 Ball fpBGA :
1 2345678 ABCDEFGH
¡
¡
¡
¡
¡
¡
¡
¡
1A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9
¡¡¡¡¡¡¡¡ 2A1 A2 NC NC NC NC OE A10
¡ ¡ ¡¡ ¡ ¡ ¡ ¡ 3CE2 WE NC NC NC NC CE A11
¡ ¡ ¡¡ ¡ ¡ ¡ ¡ 4A3 A4 A5 NC NC A17 A16 A12
¡ ¡ ¡¡ ¡ ¡ ¡ ¡ 5A6 A7 NC NC NC NC A15 A13
¡ ¡ ¡¡ ¡ ¡ ¡ ¡ 6A8 I/O0 I/O1 VCC VSS I/O2 I/O3 A14
Note : NC means no Ball.
Pin Descriptions:
Name
Function
A0 – A17 Address Inputs
CE
1 and CE2 Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0 – I/O7Data Input and Data Output
VCC 3V Power Supply
GND Ground
NC No Connection
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Truth Table:
CE1
WE
OE
Data Mode
X
High-Z
Standby
X
High-Z
Standby
L
Data Out
Active, Read
H
High-Z
Active, Output Disable
X
Data Out
Active, Write
*Key : X = Don’t Care, L = Low, H = High
Absolute Maximum Ratings*
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 Vcc+0.5 V
Power Dissipation PT-1.0 W
Storage Temperature (Plastic) Tstg -55 +150 °C
Temperature Under Bias Tbias -40 +85 °C
*Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any conditions outside those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions ( TA = -25°C to + 85°C)
Parameter Symbol Min Typ Max Unit
VCC 2.7 33.3 V
Supply Voltage Gnd 0.0 0.0 0.0 V
VIH 2.0 -VCC+0.2 V
Input Voltage VIL -0.5* -0.6 V
* VIL min = -1.0V for pulse width less than tRC/2.
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
DC Operating Characteristics ( Vcc=2.7V to 3.3V, TA =-25°C to + 85°C)
55 70 85
Parameter Sym. Test Conditions Min Max Min Max Min Max Unit
Input Leakage Current ILIVCC = Max,
Vin = Gnd to VCC 111µA
Output Leakage
Current ILOCE1 =VIH
VCC = Max, VOUT = Gnd to VCC
111µA
Operating Power
Supply Current ICC CE1 =VIL ,
VIN=VIH or VIL, IOUT=0mA
333mA
ICC1 CE1 =VIL ,
IOUT = 0mA,
Min Cycle, 100% Duty
30 30 25 mA
Average Operating
Current ICC2 CE1 =0.2V
IOUT = 0mA,
Cycle Time=1µs, 100% Duty
333mA
Standby Power Supply
Current(TTL Level)
ISB CE1 =VIH 0.5 0.5 0.5 mA
10 10 10 µA
Standby Power Supply
Current (CMOS Level) ISB1 CE1 ≥ VCC-
0.2V or f=0
VIN ≤ 0.2V or
VIN ≥ VCC-0.2V 2 2 2 µA
Output Low Voltage VOL IOL = 2 mA 0.4 0.4 0.4 V
Output High Voltage VOH IOH = -1 mA 2.4 2.4 2.4 V
Data Retention
Parameter Sym. Test Conditions Min. Max. Unit
VCC for Data retention VDR 1.0 -V
Data Retention Current ICCDR -2µA
Chip Deselect to Data Retention Time tCDR 0-ns
Operating Recovery Time(2) tR
CE1 ≥ VCC -0.2V or
VIN ≥ VCC -0.2V or
VIN ≤ 0.2V
tRC -ns
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
Data Retention Waveform (TA = -25°C to + 85°C)
Data Retention Mode
Vcc
CE VDR
VDR >= 1.0V
tRtCDR
2.7V
2.7V
VIH VIH
AC Test Conditions AC Test Loads and Waveforms
CL*TTL
Output Load Condition *Including Scope and Jig Capacitance
CL = 30pf + 1TTL Load
Read Cycle (3,9)( Vcc=2.7V to 3.3V, TA =-25°C to + 85°C)
55 70 85 Unit NoteParameter Symbol
Min Max Min Max Min Max
Read Cycle Time tRC 55 70 85 ns
Address Access Time tAA 55 70 85 ns
Chip Enable Access Time tACE 55 70 85 ns
Output Enable Access Time tOE 40 40 40 ns
Output Hold from address Change tOH 10 10 10 ns
Chip Enable to Output in Low-Z tCLZ 10 10 10 ns 4,5
Chip Disable to Output in High-Z tCHZ 25 30 35 ns 4,5
Output Enable to Output in Low-Z tOLZ 555ns 4,5
Output Disable to Output in High-Z tOHZ 20 25 30 ns 4,5
Power-Up Time tPU 000ns 5
Power-Down Time tPD 55 70 85 ns 5
Input Pulse Levels 0.4V to 2.4V
Input Rise and Fall Time
Input and Output Timing
Reference Level
5 ns
1.4V
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 6 -
Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled)
DOUT
tAA tOH
tRC
Data Valid
Address
Timing Waveform of Read Cycle 2 (5,6,8,9) ( CE1 Controlled)
t
OE
t
RC
Data Valid
CE1
t
OHZ
t
CHZ
t
PD
50%
50%
t
OLZ
t
ACE
t
CLZ
t
PU
Supply Current
OE
D
OUT
I
CC
I
SB
Write Cycle (3,11)( Vcc=2.7V to 3.3V, TA =-25°C to + 85°C)
55 70 85
Parameter Symbol Min Max Min Max Min Max Unit Note
Write Cycle Time tWC 55 70 85 ns
Chip Enable to Write End tCW 40 60 70 ns
Address Setup to Write End tAW 40 60 70 ns
Address Setup Time tAS 000ns
Write Pulse Width tWP 40 50 60 ns
Write Recovering Time tWR 000ns
Data Valid to Write End tDW 25 30 35 ns
Data Hold Time tDH 000ns
Write Enable to Output in High-Z tWZ 25 30 35 ns 4,5
Output Active from Write End tOW 555ns 4,5
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
Timing Waveform of Write Cycle 1 (10,11) ( WE Controlled)
tWP
tAW
WE
tWC tWR
tAS
tDW tDH
tOW
tWZ
Data Valid
Address
DIN
DOUT
Timing Waveform of Write Cycle 2 (10,11) ( CE1 Controlled)
tAW
WE
tWC tWR
tDW tDH
Data Valid
Address
DIN
tAS tCW
tWP
tWZ
CE1
DOUT
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 8 -
Notes :
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition.
4. This parameter is tested with CL = 5pF. Transition is measured ± 500mV from steady – state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW .
9. All read cycle timings are referenced from the last valid address to the first transition address.
10. CE1 or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 9 -
Ordering Information
Part Number SPEED POWER PACKAGE
GLT6200L08LL-55 ST
55ns
Normal
sTSOPI 32L
GLT6200L08LL-70 ST
70ns
Normal
sTSOPI 32L
GLT6200L08LL-85 ST
85ns
Normal
sTSOPI 32L
GLT6200L08SL-55 ST
55ns
Normal
sTSOPI 32L
GLT6200L08SL-70 ST
70ns
Normal
sTSOPI 32L
GLT6200L08SL-85 ST
85ns
Normal
sTSOPI 32L
GLT6200L08LLI-55 ST
55ns
Normal
sTSOPI 32L
GLT6200L08LLI-70 ST
70ns
Normal
sTSOPI 32L
GLT6200L08LLI-85 ST
85ns
Normal
sTSOPI 32L
GLT6200L08SLI-55 ST
55ns
Normal
sTSOPI 32L
GLT6200L08SLI-70 ST
70ns
Normal
sTSOPI 32L
GLT6200L08SLI-85 ST
85ns
Normal
sTSOPI 32L
GLT6200L08LL-55 FG
55ns
Normal
fpBGA-48L
GLT6200L08LL-70 FG
70ns
Normal
fpBGA-48L
GLT6200L08LL-85 FG
85ns
Normal
fpBGA-48L
GLT6200L08SL-55 FG
55ns
Normal
fpBGA-48L
GLT6200L08SL-70 FG
70ns
Normal
fpBGA-48L
GLT6200L08SL-85 FG
85ns
Normal
fpBGA-48L
GLT6200L08LLI-55 FG
55ns
Normal
fpBGA-48L
GLT6200L08LLI-70 FG
70ns
Normal
fpBGA-48L
GLT6200L08LLI-85 FG
85ns
Normal
fpBGA-48L
GLT6200L08SLI-55 FG
55ns
Normal
fpBGA-48L
GLT6200L08SLI-70 FG
70ns
Normal
fpBGA-48L
GLT6200L08SLI-85 FG
85ns
Normal
fpBGA-48L
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 10 -
Parts Numbers (Top Mark) Definition :
GLT 6 200 L 08 LL I - 55 TS
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 64K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
VOLTAGE
Blank : 5V
L : 3.3V
M : 2.5V
N : 2.1V
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
10 : 10ns
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
ST : sTSOP (Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
FG : 48-fpBGA
LL : Low Low power
L : Low power
SL : Super Low power
I : Industrial Temperature
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
Package Information
32 pin 8x13.4mm Small Outline J-form Package (sTSOP)
G-LINK GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Nov 2000(Rev. 1.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
GLT6200L08 fpBGA
ABCDEFGH
1
2
3
4
5
6
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OOOOOOOO
OOOOOOOO
OOOOOOOO
OOOOOOOO
OOOOOOOO
PACKAGE OUTLINE DWG.
SYMBOL UNIT : MM
A1.10±0.1
A1 0.22±0.05
∅b0.35
C0.36TYP
D8.00±0.10
D1 5.25
E6.00±0.10
E1 3.75
e0.75TYP
aaa 0.10
D1
D
E1
E
aaa
A1
C
A
∅b
e