HARRIS SEMICOND SECTOR i} HARRIS CMOS AND Gates High-Voltage Types (20-Volt Rating) CD40738B Triple 3-Input AND Gate CD4081B Quad 2-Input AND Gate CD40828 Dual 4-Input AND Gate @ C04073B, CD4081B and CD. 4082B AND gates provide the system de- signer with direct implementation of the AND function and supplement the existing family of CMOS gates. The CD4073B, CD4081B and CD40828 types are supplied in 14-lead dual-in- line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix), Features: MAXIMUM RATINGS, Absolute-Maximum Values: OC SUPPLY-VOLTAGE RANGE, (Vp) Voltages rataranced to Vgg Terminal} INPUT VOLTAGE RANGE, ALLINPUTS ... OCG INPUT CURRENT, ANY ONE INPUT POWER DISSIPATION PER PACKAGE (Pp): For Ta = -55C to +100C For Ta = +100C to +125C DEVICE DISSIPATION PER OUTPUT TRANSISTOR FOR Ta = FULL PACKAGE-TEMPERATURE RANGE {All Package Types)...........0...0c cece eee OPEAATING-TEMPERATURE RANGE (Ta) WOE D 4302271 0037509 & GRHAS CD4073B, CD4081B, CD4082B Types F< 3B-2/ Medium-Speed Operation tp_ yy, tee = S0ns (typ.) at Vop 2 10 V 100% tested for quiescent current at 20 V yw Maximum input current of 1 uA at 18 V over a full package-temperature range; 100 nA at bry 18 V and 25C ey Noise margin (full package-temperature range) = 1VatVpp=5V 2VatVpp=10V 2.5 V at Vpp = 15 V Standardized, symmetrical output characteristics 5-V,10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices a2es-2usas c04081B FUNCTIONAL DIAGRAM Yoo 100mW 55C to #125C ZTAnmmMPrOOD z STORAGE TEMPERATURE RANGE (Tgig).-.---. 22sec cence cece cece enna eect cent ee eee -65C to +150C LEAD TEMPERATURE (OURING SOLDERING): ss Atdislance 1/16 + 1/32 inch (1.59 + 0.79mm) from case for 10S MAX 6... se ceceeeeeeeeaeeeceeeease +285C __ 3268727570 cp40828 FUNCTIONAL DIAGRAM RECOMMENDED OPERATING CONDITIONS For maximum reliability, nominal operating conditions shauld be selected so that operation is always within the following ranges: LIMITS CHARACTERISTIC UNITS MIN. MAX. Supply-Voltage Range (For T, = Full Package 3 18 Vv Yoo Temperature Range) la C a DYNAMIC ELECTRICAL CHARACTERISTICS at Ta=25C, Input t,.t=20 ns, of and C,=50 pF, Ry, =200 kQ Al ALL TYPES ah ae TEST CONDITION E7 ro CHARACTERISTIC CONDI s LIMITS UNITS eS Vop Pa Volts TYP. MAX. tH tO Propagation Delay Time, 0 6 oO as s 5 PHL: PLH 15 45 90 a . . 5 100 200 9208-27575 Transition Time, 10 60 100 ns cD40738 THU: TLH 15 40 80 FUNCTIONAL DIAGRAM input Capacitance, Cyy Any Input - 5 75 pF 3-190HARRIS SEMICOND SECTOR 44E D MM 4302271 0037510 4 BHAS CD40738B, CD4081B, CD4082B Types 142-2) STATIC ELECTRICAL CHARACTERISTICS TEMPERATURE CONDITIONS LIMITS AT INDICATED TEMPERATURES (c) ] CHARACTER- t 3 ISTIC +25 UNITS z Vo | Vin |Yoo - 3 (v) (v) | (v) | -55 | 40 { +85 | +125 | Min. | Typ. | Max. Z 8 Quiescent Device - 05 5 0.25 | 0.25 7.5 75 - 0.01 0.25 5 & Current. - 010] 10} os | 05 15 1B | - 6.01 | os A 3 'DO Max. = {918} 18] 1 [a 7T 30 [| 3 f - [oo fa] * = G20] 20] 5 5 | 150 { 150] ~ 0.02 | 5 Output Low 0.4 0,5 5 | 064 | 0.61 0.42 | 0.36 | 0.51 1 - INPUT YOLTACE tjq} V (Sink)Current | 5 [oto] 10 [ 16] 15 | 1 | 09 |13a | 26 | ~ . ; ; mene tOL Min. 15 0.15] 15 42 A 78 24 34 68 ~ Fig. 3 Typical voltage transfer characteristics, Output High 4.6 0.5 | 5 | -0.64]-0.6) | -0.42 | -o.36|-0.51/] <1 - | ma {Source} 25 (05 { 5 | ~2 [-18 | -1.3 1-1.15]-1e [ 32 7 Tree ne (Tale 25 Current, 96 |o10[ 10 [-16/-15 |-11 | -o9 |-19] 26 | IOH Min 13.5 0.16] 15 |}-4.2 } -4 -28 | -2.4 }-3.4 | -6.8 - Output Voltage - 05 5 0.05 - 0 0.05 Low-Level ars . - 1 0.05 ~ 0 0.05 VOL Max. 0.10 o ES - 0.15] 15 0.05 = 0 0.05 v Leone < oes Output Voltage - as 5 4.95 4.95 5 - Ra High-Level, = [0,10] 10 9.95 995 | 10 [ 23 YOH Min. - ois] 15 14.95 95] is | ow J Input Low 0.5 ~ 5 15 - - 1.5 =f Voltage. 1 _ 10 3 _ _ 3 LOAD CAPACITANCE (CL) pF siescann 2 3 Vit, Max. 5 4 a wt > 15 = ] Vv Fig. 4 Typical propagation delay time S 3s Input High 0.5.4.5] - 5 35 3.5 - = as a function of load capacitance. 8 = Voltage. 19 - 10 7 7 _ ViH Min fi si35{ - | 15 " uf- [= Input Current + _ 5 (WN Max. 0,18} t8 | 20.1) +01 +] +1 +10 40.1] pA Yoo { | 2B p ot m1 2 DRAIN~TO-SOURCE VOLTAGE (Vogi-v guts 247.095 Fy a pf osseun Fig. 5 Typical output low {sink} Fy wt m current characteristics, He Un BAL 7 4 vsst SorecreD are sg CMOS PROTEC TION, NETWORK sacs-29zee Fig. 1 Schematic diagram for CD40818 {1 of 4 identical gates). M6, 8,13) a M400n 203, 9,:2) g2es- 29763 Fig. 2 Logic diagram for CD40818 (1 of 4 identical gates}. ORAIN~ T0-SOURCE VOLTAGE (Vp5) s2es-zansar Fig. 6 Minimum output low (sink) current characteristics. 3-191U4E D HARRIS SEMICOND SECTOR B@ 430ee7)1 0037511 6 EMHAS CD4073B, CD4081B, CD4082B Types 7T~73-2\ GRAIH~TO+SOURCE VOLTAGE (VpgI he eee an ae Le he = pd 4 pd k z Ys 3 Yoo | * ALL INPUTS aRE PROTECTED BY veer anon CMOS PROTECTION NETWORK Fig. 8 Typical output high (source) aval ata wy Yoo current characteristics. : an mr in pith | [Re .----A us | a A ORAIN-TO-SGUACE VOLTAGE {Yos} 1310 ] "he . t Fr jw L - zk <x 4 44 af : nl = v. 5 ss Lis Us : 2. Yes exc 29266 a Fig. 7 Schematic diagram for CD4082B (1 of 2 identical gates). 5 & 5 3 S2E Reka gzIAe Fig. 10 Minimum output high (source) current characteristics. s2es-2az67 Fig. 9 Logic diagram for CD40828 (1 of 2 identical gates). i oo ie = ra i io = * ig oO e F on KH fa & he 5 3 I BL = "I i #4512) ay 4 WS | re s m 4 2 oy 60 wan a LOAD CAPACITANCE (C,)pF azcs-20022 my t hie Fig. 12 Typi ition ti a . ypical transition time as a yy re E UE re function of load capacitance Yoo | +4 re 4 ha 7 b----A , Vss *ALL INPUTS ARE PROTECTED BY be 4 PROT! NET WO A A cuos JOTECTION NET WORK Ys 22e9-29288 Fig. 11 Schematic diagram for CD40738 {1 of 3 identical gates). 164,12) 83.) 906,101 s2cs-aszes. Fig. 13 ~ Logic diagram for CD40738 {1 of 2 identical gates}. 3-192 Ce - INPUT FREQUENCY (iz) iH: 9205-20903 Fig. 14 Typical dynamic power dissi- pation per gate as a function of frequency.HARRIS SEMICOND SECTOR WHE D 4302271 0037512 & BBHAS CD4073B, CD4081B, CD4082B Types 7-43A) Yoo INPUTS g ss WES pTageR: Fig. 15 ~ Quiescent device current test circuit. Yoo Ei : ~- o- . . LL : 4-10 nous | 1 (0.102-0.254) Yoo | NOTE 61-69. (t= = MEASURE INPUTS {1-549-1,753) 2 4 SEQUENTIALLY. Chip dimensions and pad layout S2C8-35100 s3 TO BOTH Von AND , CONNECT ALL ususeD for CD40818. 4 INPUTS TO EITHER: Vpn OF Yg5 10 20 30 40 50 60 Yss __ sees. 2race Fig. 16 input current test circuit. Qe So . o us 20 So ' az = INPUTS LourPyTs, ou ron Bs Noe he ~ 57-65 = x= ve ~ - 1448-85) ag _ i ~ : ox t NOTE vss TEST ANY COMBINATION OF INPUTS a2cs-2744.0 Fig. 17 Input-voltage test circuit. a TERMINAL ASSIGNMENTS ait asa | - : : : 57~65, a aE I (1.448-Lesi) ot a2 Spon Chip dimensions and pad layout 6 as ths for CD40828. | > a ' MG 5 OPE F 62 6 aR 9 10 20 30 40 - 50 i 2 ape 62| i I l I t I "OR Ea S a CD4081B 53-67 {1449-4.701) TOP view NC8NO CONNECTON 92c9-24537K2 CD4082B Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as in- dicated. Grid graduations are in 17 TL tg mils (10-3 inch}. oiiiied ei i 3 e 3 G 4-10 2 tbe (0.102-0.284) 4 . I . : q 5 sis nr Chip dimensions and pad layout +-. u aa9-Fs0n e2cs2ez76. pe ele sheiusaac for CD40738. . . vss 1h TOP EW secs cate C040738 3-193