ISL43141 - Intersil Corporation

FN6032

ISL43140, ISL43141, ISL43142

Low-Voltage, Single and Dual Supply,

High Performance, Quad SPST, Analog

Switches

The Intersil ISL43140–ISL43142 devices are CMOS,

precision, quad analog sw itch es desi gned to operate from a

single +2V to +12V supply or from a ±2V to ±6V su pply.

Targeted applications include battery powered equipment that

benefit from the devices’ low power cons umption (1µW), low

leakage currents (1nA max), and fast sw itch ing speed s

(tON = 30ns, tOFF = 18ns). A 12Ω maximum RON flatness

ensures signal fidelity , while channel-to-cha nnel mis match is

guaranteed to be less than 2.5Ω. The 3mm x 3m m Q uad N o-

Lead Flatpack (QFN) package all eviates board space

limitations, making this newest line of low-voltage switches an

ideal solutio n.

The ISL43140/ISL43141/ISL43142 are quad single-pol e/

single-throw (SPST) devices . The ISL43140 has four normally

closed (NC) switch es; the ISL43141 has four normally o pen

(NO) switches; the ISL43142 has tw o NO and two N C

switches and can be used as a dual SPDT, or a dual 2:1

multiplexer.

Table 1 summarizes the performance of this family .

TABLE 1. FEATURES AT A GLANCE

Features

• Fully Specified at ±5V, 12V , 5V, and 3V Supplies fo r 10%

Tolerances

• Four Separately Controlled SPST Switches

• Pin Compa tib le with DG411/DG41 2/D G 41 3

• ON Resistance (RON) . . . . . . . . . . . . . . . . . . . . . . . . 50Ω

•R

ON Matching Between Channels. . . . . . . . . . . . . . . . . . . 2Ω

• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max)

• Low Power Consumption (PD). . . . . . . . . . . . . . . . . . . .<1µW

• Low Leakage Current (Max at 85oC) . . . . . . . . . . . . . 5nA

• Fast Switchin g Action

-t

ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns

-t

OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18ns

• Guaranteed Break-Before-Make (ISL43142 only)

• Minimum 2000V ESD Protection per Method 3015.7

• TTL, CMOS Compatible

Applications

• Battery Powered, Handheld, and Portable Equipment

- Cellular/Mobile Phon es

- Pagers

- Laptops, Notebooks, Palmtops

• Comm uni ca tio ns Sys t em s

- Military Radios

- RF “Tee” Switches

• Test Equipm ent

- Ultrasound

- Electrocardiograph

• Heads-Up Displays

• Audio and Video Switching

• General Purpose Circuits

- +3V/+5V DACs and ADCs

- Digital Filters

- Operational Amplifier Gain Switching Networks

- High Frequency Analog Switching

- High Speed Multiplexing

Related Li terature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

ISL43140 ISL43141 ISL43142

Number of Switches 4 4 4

Configuration All NC All NO 2 NC / 2 NO

10.8V RON 50Ω50Ω50Ω

10.8V tON / tOFF 30ns / 18ns 30ns / 18ns 30ns / 18ns

±4.5V RON 50Ω50Ω50Ω

±4.5V tON / tOFF 40ns / 15ns 40ns / 15ns 40ns / 15ns

4.5V RON 110Ω110Ω110Ω

4.5V tON / tOFF 50ns / 20ns 50ns / 20ns 50ns / 20ns

2.7V RON 200Ω200Ω200Ω

2.7V tON / tOFF 120ns / 25ns 120ns / 25ns 120ns / 25ns

Packages 16 Ld SOIC (N), 16 Ld 3x3 QFN,

16 Ld TSSOP

Data Sheet November 2002

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

Pinouts (Note 1)

ISL43140 (SOIC, TSSOP)

TOP VIEW ISL43140 (QFN)

TOP VIE W

ISL43141 (SOIC, TSSOP)

TOP VIEW ISL43141 (QFN)

TOP VIE W

ISL43142 (SOIC, TSSOP)

TOP VIEW ISL43142 (QFN)

TOP VIE W

NOTE:

1. Switches Shown for Logic “0” Input.

IN1

COM1

NC1

V-

GND

NC4

IN4

COM4

IN2

NC2

V+

N.C.

NC3

COM3

IN3

COM2

NC1

V-

GND

NC4

COM1

IN1

IN2

COM2

16 14 13

6578

NC2

V+

N.C.

NC3

COM4

IN4

IN3

COM3

IN1

COM1

NO1

V-

GND

NO4

IN4

COM4

IN2

NO2

V+

N.C.

NO3

COM3

IN3

COM2

NO1

V-

GND

NO4

COM1

IN1

IN2

COM2

16 14 13

6578

NO2

V+

N.C.

NO3

COM4

IN4

IN3

COM3

IN1

COM1

NO1

V-

GND

NO4

IN4

COM4

IN2

NC2

V+

N.C.

NC3

COM3

IN3

COM2

NO1

V-

GND

NO4

COM1

IN1

IN2

COM2

16 14 13

6578

NC2

V+

N.C.

NC3

COM4

IN4

IN3

COM3

ISL43140, ISL43141, ISL43142

Truth Table

LOGIC

ISL43140 ISL43141 ISL43142

SW 1, 2, 3, 4 SW 1, 2, 3, 4 SW 1, 4 SW 2, 3

0ON OFFOFFON

1 OFF ON ON OFF

NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V.

Pin Descriptions

PIN FUNCTION

V+ Positive Power Supply Input

V- Negative Power Supply Input. Connect to GND for

Single Supply Configurations.

GND Ground Connection

IN Digital Control Input

COM Analog Switch Common Pin

NO Analog Switch Normally Open Pin

NC Analog Switch Normally Closed Pin

N.C. No Internal Connection

Ordering Information

PART NO.

(BRAND)

(NOTE 2) TEMP.

RANGE (oC) PACKAGE PKG. NO.

ISL43140IB -40 to 85 16 Ld SOIC (N) M16.15

ISL43140IR*

(140I) -40 to 85 16 Ld QFN L16.3x3

ISL43140IV -40 to 85 16 Ld TSSOP M16.173

ISL43141IB -40 to 85 16 Ld SOIC (N) M16.15

ISL43141IR*

(141I) -40 to 85 16 Ld QFN L16.3x3

ISL43141IV -40 to 85 16 Ld TSSOP M16.173

ISL43142IB -40 to 85 16 Ld SOIC (N) M16.15

ISL43142IR*

(142I) -40 to 85 16 Ld QFN L16.3x3

ISL43142IV -40 to 85 16 Ld TSSOP M16.173

NOTES:

2. Most surface mount devices are available on tape and reel; add

“-T” to suffix.

* In Development.

ISL43140, ISL43141, ISL43142

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V

V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V

All Other Pin s (No te 3). . . . . . . . . . . . . ((V-) - 0. 3 V) to (( V+) + 0.3V)

Continuous Current (Any Terminal). . . . . . . . . . . . . . . . . . . . . 10mA

Peak Current , IN, NO, NC, or COM

(Pulsed 1 ms, 1 0 % Duty Cyc l e , Max ) . . . . . . . . . . . . . . . . . . 20mA

ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV

Operating Conditions

Temperature Range

ISL4314XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

Thermal Resistance (Typical, Note 4) θJA (oC/W)

16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 115

16 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 75

16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC

Moisture Sensitivity (See Technical Brief TB363)

All Other Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1

QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2

Maximum Storage Temperature Range. . . . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC

(SOIC and TSSOP - Lead Tips Only)

CAUTION : Stresses above those listed i n “Absolut e Maximum Rat ings” may cause permanen t damage to the device. Thi s is a stress onl y rating and o peration of th e

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.

4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications: ±5V Supply Test Conditions VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),

Unless Otherwise Specified

PARAMETER TEST CONDITIONS TEMP

(oC) (NOTE 6)

MIN TYP (NOTE 6 )

MAX UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full V- - V+ V

ON Resistance, RON VS = ±4.5V, ICOM = 1.0mA, VNO or VNC = ±3V,

See Figure 5 25 - 50 65 Ω

Full - - 75 Ω

RON Matching Between Channels,

∆RON VS = ±4.5V, ICOM = 1.0mA, VNO or VNC = ±3V 25 - 2 2.5 Ω

Full - - 5 Ω

RON Flatness, RFLAT(ON) VS = ±4.5V, ICOM = 1.0mA, VNO or VNC = ±3V, Note 8 25 - 10 12 Ω

Full - - 13 Ω

NO or NC OFF Leakage Current,

INO(OFF) or INC(OFF) VS = ±5.5V, V COM = ±4.5V, VNO or VNC = +4.5V, Not e

725 -1 0.01 1 nA

Full -5 - 5 nA

COM OFF Leakage Current,

ICOM(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V, Not e

725 -1 0.01 1 nA

Full -5 - 5 nA

COM ON Leakage Current,

ICOM(ON) VS = ±5.5V, VCOM = VNO or VNC = ±4.5V, Note 7 25 -2 0.01 2 nA

Full -10 - 10 nA

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, VINH Full 2.4 1.6 - V

Input Voltage Low, VINL Full - 1.6 0.8 V

Input Current, IINH, I INL VS = ±5.5V, VIN = 0V or V+ Full -0.5 0.03 0.5 µA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,

VIN = 0 to 3V, See Figure 1 25 - 40 80 ns

Full - - 100 ns

Turn- OFF Ti me, tOFF VS = ±4.5V, VNO or VNC = ±3V, RL = 300 Ω, CL = 35pF,

VIN = 0 to 3V, See Figure 1 25 - 15 30 ns

Full - - 40 ns

Break-Before-Make Time Delay

(ISL43142), tDVS = ±5.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF,

VIN = 0 to 3V, See Figure 3 Full 5 20 - ns

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1 5 pC

NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF

COM OFF Capacitance,

CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF

COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 14 - pF

ISL43140, ISL43141, ISL43142

OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz,

VNO or VNC = 1VRMS, See Figures 4, 6, and 19 25 - >90 - dB

Crosstalk, Not e 9 25 - <-90 - dB

All Hostile Crosstalk RL = 50Ω, CL = 15pF, f = 10MHz,

VNO or VNC = 1VRMS, See Figure 19 25 - -60 - dB

Power Supply Rejection Ratio RL = 50Ω, CL = 15pF, f = 1MHz, See Figure 20 25 - 60 - dB

POWER SUPPLY CHARACTERISTICS

Power Supply Range Full ±2-±6V

Positive Supply Current, I+ VS = ±5.5V, VIN = 0V or V+, Switch On or Off 25 -1 0.05 1 µA

Full -1 - 1 µA

Negative Supply Current, I- 25 -1 0.05 1 µA

Full -1 - 1 µA

NOTES:

5. VIN = Input voltage to perform proper function.

6. The algebraic convention, whereby the most negative value is a m inimum and the most positive a maximum, is used in this data sheet.

7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC.

8. Flatness is defined as the delta between the maximum and minimum RON values over the specified voltage range.

9. Between any two switches.

Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, VINH = 5V, VINL = 0.8V (Note 5),

Unless Otherwise Specified

PARAMETER TEST CONDITIONS TEMP

(oC) (NOTE 6)

MIN TYP (NOTE 6)

MAX UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - V+ V

ON Resistance, RON V + = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V,

See Figure 5 25 - 50 65 Ω

Full - 60 75 Ω

RON Matching Between Channels,

∆RON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V 25 - 2 2.5 Ω

Full - - 5 Ω

RON Flatness, RFLAT(ON) V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V,

Note 8 25 - 8 12 Ω

Full - 9 13 Ω

NO or NC OFF Leakage Current,

INO(OFF) or INC(OFF) V+ = 13 .2V, VCOM = 1V, 10V, VNO or VNC = 10V, 1V,

Note 7 25 -1 - 1 nA

Full -5 - 5 nA

COM OFF Leakage Current,

ICOM(OFF) V+ = 13.2V, VCOM = 10V, 1V, VNO or VNC = 1V, 10V,

Note 7 25 -1 - 1 nA

Full -5 - 5 nA

COM ON Leakage Current,

ICOM(ON) V+ = 13.2V, VCOM = 1V, 10V, or VNO or VNC = 1V,

10V, Note 7 25 -2 - 2 nA

Full -10 - 10 nA

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, VINH Full 3.5 3.1 - V

Input Voltage Low, VINL Full - - 0.8 V

Input Current, IINH, I INL V+ = 13.2V, VIN = 0V or V+ Full -1 - 1 µA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,

VIN = 0 to 3.3V, See Figure 1 25 - 30 70 ns

Full - 34 100 ns

Turn- OFF Ti me, tOFF V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,

VIN = 0 to 3.3V, See Figure 1 25 - 18 50 ns

Full - 20 75 ns

Break-Before-Make Time Delay

(ISL43142), tDV+ = 13.2V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF,

VIN = 0 to 3.3V, See Figure 3 Full 0 8 - ns

Electrical Specifications: ±5V Supply Test Conditions VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS TEMP

(oC) (NOTE 6)

MIN TYP (NOTE 6 )

MAX UNITS

ISL43140, ISL43141, ISL43142

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 5 15 pC

OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz,

VNO or VNC = 1VRMS, See Figures 4, 6, and 19 25 - >90 - dB

Crosstalk, Not e 9 25 - <-90 - dB

All Hostile Crosstalk RL = 50Ω, CL = 15pF, f = 10MHz,

VNO or VNC = 1VRMS, See Figure 19 25 - -60 - dB

Power Supply Rejection Ratio RL = 50Ω, CL = 15pF, f = 1MHz, See Figure 20 25 - 60 - dB

NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF

COM OFF Capacitance,

CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF

COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 14 - pF

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 13.2V, VIN = 0V or V+, Switch On or Off 25 -1 0.05 1 µA

Full -1 - 1 µA

Negative Supply Current, I- 25 -1 0.05 1 µA

Full -1 - 1 µA

Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),

Unless Otherwise Specified

PARAMETER TEST CONDITIONS TEMP

(oC) MIN

(NOTE 6) TYP MAX

(NOT E 6)UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - V+ V

ON Resistance, RON V + = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V,

See Figure 5 25 - 110 120 Ω

Full - - 150 Ω

RON Matching Between Channels,

∆RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V 25 - 1.5 2 Ω

Full - - 5 Ω

RON Flatness, RFLAT(ON) V+ = 4. 5V, ICOM = 1.0mA, VNO or VNC = 1.5V to 4.5V,

Note 8 25 - 12 16 Ω

Full - - 20 Ω

NO or NC OFF Leakage Current,

INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V,

Note 7 25 -1 0.01 1 nA

Full -5 - 5 nA

COM OFF Leakage Current,

ICOM(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V,

Note 7 25 -1 0.01 1 nA

Full -5 - 5 nA

COM ON Leakage Current,

ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, Note 7 25 -2 - 2 nA

Full -10 - 10 nA

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, VINH Full 2.4 1.6 - V

Input Voltage Low, VINL Full - 1.6 0.8 V

Input Current, IINH, I INL V+ = 5.5V, VIN = 0V or V+ Full -0.5 0.03 0.5 µA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, C L = 35pF,

VIN = 0 to 3V, See Figure 1 25 - 50 100 ns

Full - - 150 ns

Turn- OFF Ti me, tOFF V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,

VIN = 0 to 3V, See Figure 1 25 - 20 50 ns

Full - - 75 ns

Break-Before-Make Time Delay

(ISL43142), tDV+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF,

VIN = 0 to 3V, See Figure 3 Full 10 30 - ns

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1 5 pC

OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz,

VNO or VNC = 1VRMS, See Figures 4, 6, and 19 25 - >90 - dB

Crosstalk, Not e 9 25 - <-90 - dB

Electrical Specifications: 12V Supply Test Conditions: V+ = +10.8V to +13.2V, V- = GND = 0V, VINH = 5V, VINL = 0.8V (Note 5),

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS TEMP

(oC) (NOTE 6)

MIN TYP (NOTE 6)

MAX UNITS

ISL43140, ISL43141, ISL43142

All Hostile Crosstalk RL = 50Ω, CL = 15pF, f = 10MHz,

VNO or VNC = 1VRMS, See Figure 19 25 - -60 - dB

Power Supply Rejection Ratio RL = 50Ω, CL = 15pF, f = 1MHz, See Figure 20 25 - 60 - dB

NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF

COM OFF Capacitance,

CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF

COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 14 - pF

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+, Switch On or Off 25 -1 0.05 1 µA

Full -1 - 1 µA

Negative Supply Current, I- 25 -1 0.05 1 µA

Full -1 - 1 µA

Electrical Specifications: 3V to 3.3V Supply Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V

(Note 5), Unless Otherwise Specified

PARAMETER TEST CONDITIONS TEMP

(oC) MIN

(NOTE 6) TYP MAX

(NOT E 6)UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - V+ V

ON Resistance, RON V + = 2.7V, ICOM = 1.0mA, VNO or VNC = 1V,

See Figure 5 25 - 200 250 Ω

Full - - 270 Ω

RON Matching Between Channels,

∆RON V+ = 2.7V, ICOM = 1.0mA, VNO or VNC = 1V 25 - 2 4 Ω

Full - - 6 Ω

RON Flatness, RFLAT(ON) V+ = 2. 7V, ICOM = 1.0mA, VNO or VNC = 0.5V to 1.5V,

Note 8 25 - 80 100 Ω

Full - - 120 Ω

NO or NC OFF Leakage Current,

INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 2.6V, VNO or VNC = 2.6V, 1V,

Note 7 25 -1 0.01 1 nA

Full -5 - 5 nA

COM OFF Leakage Current,

ICOM(OFF) V+ = 3.6V, VCOM = 1V, 2.6V, VNO or VNC = 2.6V, 1V,

Note 7 25 -1 0.01 1 nA

Full -5 - 5 nA

COM ON Leakage Current,

ICOM(ON) V+ = 3.6V, VCOM = 1V, 2.6V, Note 7 25 -2 - 2 nA

Full -10 - 10 nA

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, VINH Full 2.4 1.6 - V

Input Voltage Low, VINL Full - 1.6 0.8 V

Input Current, IINH, I INL V+ = 3.6V, VIN = 0V or V+ Full -0.5 0.03 0.5 µA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 300 Ω, CL = 35pF,

VIN = 0 to V+, See Figure 1 25 - 120 180 ns

Full - - 220 ns

Turn- OFF Ti me, tOFF V+ = 2. 7V, VNO or VNC = 1.5V, RL = 300Ω, C L = 35pF,

VIN = 0 to V+, See Figure 1 25 - 25 45 ns

Full - - 60 ns

Break-Before-Make Time Delay

(ISL43142), tDV+ = 3. 6V, VNO or VNC = 1.5V, RL = 300 Ω, CL = 35pF,

VIN = 0 to 3V, See Figure 3 25 15 50 - ns

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 0.5 5 pC

OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz,

VNO or VNC = 1VRMS, See Figures 4, 6, and 19 25 - >90 - dB

Crosstalk, Not e 9 25 - <-90 - dB

All Hostile Crosstalk RL = 50Ω, CL = 15pF, f = 10MHz,

VNO or VNC = 1VRMS, See Figure 19 25 - -60 - dB

Power Supply Rejection Ratio RL = 50Ω, CL = 15pF, f = 1MHz, See Figure 20 25 - 60 - dB

Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5),

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS TEMP

(oC) MIN

(NOTE 6) TYP MAX

(NOT E 6)UNITS

ISL43140, ISL43141, ISL43142

NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF

COM OFF Capacitance,

CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 7 - pF

COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 14 - pF

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+, Switch On or Off 25 -1 0.05 1 µA

Full -1 - 1 µA

Negative Supply Current, I- 25 -1 0.05 1 µA

Full -1 - 1 µA

Test Circuits and Waveforms

Logic input waveform is inverted for switches that have the opposite

logic sense.

FIGURE 1A. MEASUREMENT POINTS

Repeat test for all switches. CL includes fixture and stray

capacitance.

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

Logic input waveform is inverted for switches that have the opposite

logic sense.

FIGURE 2A. MEASUREMENT POINTS

Repeat test for all switches. CL includes fixture and stray

capacitance. FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

Electrical Specifications: 3V to 3.3V Supply Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V

(Note 5), Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS TEMP

(oC) MIN

(NOTE 6) TYP MAX

(NOT E 6)UNITS

50%

tr < 20ns

tf < 20ns

tOFF

90%

VNX

tON

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

90%

VOUT

VOUT V(NO or NC) RL

RLRON()

------------------------------=

SWITCH

INPUT

LOGIC

INPUT

VOUT

RL CL

COM

NO or NC

300Ω35pF

GND

V+ C

V- C

VNX

VOUT

∆VOUT

ON OFF ON

Q = ∆VOUT x CL

SWITCH

OUTPUT

LOGIC

INPUT

0V CL

VOUT

VGGND

COM

NO or NC

V+ C

LOGIC

INPUT

CV-

ISL43140, ISL43141, ISL43142

FIGURE 3A. MEASUREMENT POINTS

CL includes fixture and stray capacitance.

Reconfigure accordingly to test SW3 and SW4.

FIGURE 3B. TEST CIRCUIT

FIGURE 3. BREAK-BEF OR E-M AKE TIM E (ISL43142 ONLY)

Repeat test for all switches.

FIGURE 4. OFF ISOLATION TEST CIRCUIT

Repeat test for all switches.

FIGURE 5. RON TEST CIRCUIT

FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT

Test Circuits and Waveforms (Continued)

90%

LOGIC

INPUT

SWITCH

OUTPUT

SWITCH

OUTPUT

90%

VOUT1

VOUT2

90%

90% LOGIC

INPUT

IN1

COM1 RL1 CL1

VOUT1

300Ω

35pF

COM2

RL2 CL2

VOUT2 300Ω

35pF

NO1

NC2

GND

IN2

VNX

V+ C

V-

ANALYZER

SIGNAL

GENERATOR

V+ C

0V or 2.4V

NO or NC

COM

GND

V-

V+

0.8V or 2.4V

NO or NC

COM

GND

VNX

RON = V1/1mA

1mA

V-

0V or 2.4V

ANALYZER

V+

NO1 or NC1

SIGNAL

GENERATOR

RLGND

IN1

COM1

IN2

50Ω

0V or 2.4V

COM2 NO2 or NC2

V-

CONNECTION

V+

GND

NO or NC

COM

IMPEDANCE

ANALYZER

0V or 2.4V

V-

ISL43140, ISL43141, ISL43142

Detailed Descript ion

The IS L43140–ISL431 42 quad analog s witches offer p recise

switching capability from a bipolar ±2V to ±6V or a single 2V

to 12V supply with low on-resistance (50Ω) and high speed

switch ing (tON = 40ns, tOFF = 15ns). The devices are

especi ally we ll suited to portable battery po wered equip ment

thanks to the low operating supply voltage (2V), low power

consumption (1µW), low leakage currents (1nA max), and the

tiny QFN packa ging. High frequency applica t ions also benefit

from the wide bandwidth, and the very hi gh off isolatio n and

crosstalk rejection.

Supply Sequencing And Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might perm anently d amage the I C. All I/O p ins conta in

ESD protection diod es from the p in to V+ and to V- (see

Figure 8). To prevent forward biasing these diodes, V+ and

V- must be applie d befo re any input signa ls, a nd inp ut sig nal

voltage s must remain be tween V+ and V-. I f these condit ions

cannot be guaranteed, then one of the following two

protection methods should be employed.

Logic inputs can easily be protected by adding a 1kΩ

resistor in series with the input (see Figure 8). The resistor

limits the input current below the threshold that produces

permanent damage, and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

Adding a series resistor to the switch input defeats the

purpose of using a low R ON switch , so two small si gnal

diodes can be added i n ser ies with the supp ly pins to prov ide

overvoltage protection for all pins (see Figure 8). These

additio nal dio des l imit th e anal og signal from 1 V bel ow V+ to

1V above V-. The low leakage current performance is

unaffected by this approach, but the switch resistance may

increase, especially at low supply voltages.

Power-Supply Considerations

The ISL4314X construction is typical of most CMOS analog

switches, in that they have three supply pins: V+, V-, and

GND. V+ and V- drive the internal CMOS switches and set

their analog voltage limits, so there are no connections

between the analog signal path and GND. Unlike switches

with a 13V m aximum suppl y voltage, the ISL4314X 15V

maximum supply voltage provides plenty of room for the

10% tolerance of 12V supplies (±6V or 12V sing le sup ply),

as well as room for overshoot and noise spikes.

This fami ly of swit ches per forms equ all y well whe n operated

with bipolar or single voltage supplies. The addition of the

GND pin allows for asymmetrical bipolar supplies (e.g. +5V

and -3V). The minimum recommended supply voltage is 2V

or ±2V. It is important to note that the input signal range,

switching times, and on-resistance degrade at lower supply

voltages. Refer to the electrical specification tables and

Typical Performance Curves for deta ils .

V+ and GND power the internal logic (thus setting the digital

switching point) and level shifters. The level shifters convert

the logic levels to switched V+ and V- signals to drive the

analog switch gate terminals, so switch parameters -

especi ally RON - are strongly influenced by V-.

Logic-Level Thresholds

V+ and GND power the internal logic stages, so V- has no

affect on logic thresholds. This switch family is TTL

compatible (0.8V and 2.4V) over a V+ supply range of 2.5V

to 10V (see Figure 17). At 12V the VIH level is about 2.7V,

so for best results use a logic family the provides a VOH

greater than 3V.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

the digita l input si gnals from GND to V+ with a fast trans ition

time minimizes power dissipation.

High-Frequency Performance

In 50Ω system s, signa l respons e is reasonab ly flat even past

100MHz (see Figure 18). Figure 18 also illustrates that the

frequenc y response is very consiste nt over a wide V+ rang e,

and for varying analog signal levels.

An off switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal

feedthrough from a switch’s input to its output. Off Isolation

is the resistance to this feedthrough, while Crosstalk

indicates the amount of feedthrough from one switch to

another. Figure 19 details the high Off Isolation and

Crosstalk rejection provided by this family. At 10MHz, off

isolation is about 50dB in 50Ω systems, decr easing

approximately 20dB per decade as frequency increases.

Higher load impedances decrease Off Isolation and

Crosstalk rejection due to the voltage divider action of the

switch OFF impedance and the load impedance.

FIGURE 8. OVERVOLTAGE PROTECTION

V-

VCOM

VNO or NC

OPTIONAL PROTECTION

V+

INX

DIODE

OPTIONAL PROTECTION

DIODE

OPTIONAL

PROTECTION

RESISTOR

ISL43140, ISL43141, ISL43142

Leakage Considerations

Reverse ESD protection diodes are internally connected

betwee n eac h ana lo g-sig nal pin and bo th V+ and V- . One

of these di ode s con duc ts if any an alo g sig nal exce ed s V+

or V-.

Virtually all the anal og lea ka ge cu rrent comes from the ESD

diodes to V+ or V-. Although the ESD diodes on a given

signal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biased by either

V+ or V- and the analog signal. This means their leakages

will var y as the sign al varie s. The differ ence in the two diode

leakage s to th e V+ and V- pin s consti tutes t he anal og-si gnal-

path leakage current. All analog leakage current flows

betwee n each pin an d one o f the s upply termin als, n ot to th e

other switch terminal. This is why both sides of a given

switch can show leakage currents of the same or opposite

polarity . There is no conne cti on betw e en the analo g sign al

paths and GND.

Typical Performance Curves TA = 25oC, Unless Otherwise Specified

FIGUR E 9 . ON RE SISTANC E vs POSITIVE SUPPLY VOLTAGE FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE

FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE

RON (Ω)

V+ (V)

2 4 6 8 10 12

100

150

200

250

300

35791113

-40oC

85oC25oC

V- = 0V

100

120

100

V- = -3V

V- = -5V VCOM = (V+) - 1V

ICOM = 1mA

-40oC

85oC

25oC

-40oC

85oC

25oC

RON (Ω)

VCOM (V)

024681012

1357911

-40oC

85oCV+ = 12V

V- = 0V

115

135

100

150

200

250

25oC

V+ = 3V

V+ = 5V

25oC

-40oC

85oC

25oC

-40oC

85oC

V- = 0V

V- = 0V ICOM = 1mA

RON (Ω)

VCOM (V)

-4-2024

-5 -3 -1 1 3 5

VS = ±5V

100

120 VS = ±3V

100

140

180 ICOM = 1mA VS = ±2V

25oC

85oC

25oC

-40oC

85oC

25oC

-40oC

85oC

-40oC

Q (pC)

VCOM (V)

-5 0 5 10

-10

-5

-2.5 2.5 7.5 12.5

-7.5

-2.5

2.5

VS = ±5V V+ = 5V

V+ = 3V V+ = 12V

ISL43140, ISL43141, ISL43142

FIGURE 13. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 14. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE

FIGURE 15. TURN - ON TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 16. TURN - OFF TIME vs POSITIVE SUPPLY VOLTAGE

FIGURE 17. DIGITAL SWITCHING POINT vs

POSITIVE SUPPLY VOLTAGE FIGURE 18. FREQUENCY RESPONSE

Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)

tON (ns)

V+ (V)

24681012

100

150

200

250

300

357911

-40oC

85oC

25oC

V- = 0V

VCOM = (V+) - 1V

tOFF (n s)

V+ (V)

24681012

357911

-40oC

85oC

25oC

VCOM = (V+) - 1V

V- = 0V

100

150

200

250

tON (ns)

V+ (V)

100

150

200

250 VCOM = (V+) - 1V

24681012357911

-40oC

85oC

V- = -3V

V- = -5V

-40oC85oC

-40oC

25oC

-40oC

25oC

100

150

200

250

300

tOFF (ns)

V+ (V)

-40oC

85oC

100

125 VCOM = (V+) - 1V

V- = -3V

V- = -5V

-40oC85oC

-40oC

25oC

85oC

24681012357911

25oC

V+ (V)

VINH AND VINL (V)

24681012

0.5

1.5

2.5

3.5

357911

-40oC

85oC

-40oC

85oC

VINH

VINL

25oC

V- = 0V to -5V

FREQUENCY (MHz)

-3

NORMALIZED GAIN (dB)

GAIN

PHASE 0

135

180

PHASE (DEGREES)

1 10 100 600

RL = 50Ω

V+ = 2.7V (VIN = 2VP-P)

VS = ±2V (V IN = 3VP-P) or V+ = 5V (VIN = 4VP-P)

VS = ±2V (V IN = 3VP-P)

V+ = 5V ( VIN = 4VP-P)

VS = ±5V (VIN = 5VP-P)

V+ = 2.7V (VIN = 2VP-P)

ISL43140, ISL43141, ISL43142

FIGURE 19. CROSSTALK AND OFF ISOLATION FIGURE 20. ±PSRR vs FREQUENCY

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

V-

TRANSISTOR COUNT:

ISL43140: 188

ISL43141: 188

ISL43142: 188

PROCESS:

Si Gate CMOS

Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)

FREQUENCY (Hz)

1k 100k 1M 100M 500M10k 10M

-110

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

CROSSTALK (dB)

OFF ISOLATION (dB)

110

100

ISOLATION

ALL HOSTILE CROSSTALK

CROSSTALK

RL = 50Ω

VS = ±2V to ±5V

V+ = 3V to 12V or

PSRR (dB)

FREQUENCY (MHz)

0.3 1 10 100 1000

RL = 50Ω

VIN = 1VP-P

V+ = 3V to 12V or

VS = ±2V to ±5V

-PSRR, SWITCH ON

+PSRR, SWITCH ON

+PSRR, SWITCH OFF

-PSRR, SWITCH OFF

ISL43140, ISL43141, ISL43142

Small Outline Pla stic Packages (SOIC)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above

the seating plane, shall not exceed a maximum value of 0.61mm

(0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are

not necessarily exact.

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45o

0.25(0.010) BM M

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.3859 0.3937 9.80 10.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BS C 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N16 167

α0o8o0o8o-

Rev. 0 12/93

ISL43140, ISL43141, ISL43142

Thin Shrink Small Outline Plastic Packages (TSSOP)

INDEX

AREA E1

123

-B-

0.10(0.004) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004) c

E0.25(0.010) BM M

0.25

0.010

GAUGE

PLANE

NOTES:

1. These package dimensions are within allowable di mensions of

JEDEC MO- 153-AB , Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

0.05(0.002)

M16.173

16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.047 - 1.20 -

A1 0.002 0.006 0.05 0.15 -

A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.193 0.201 4.90 5.10 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N16 167

α0o8o0o8o-

Rev. 0 6/98

ISL43140, ISL43141, ISL43142

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Int ersil o r its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

Quad Flat No-Le ad Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP) L16.3x3

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDE C MO -220V EED-2 ISSUE C)

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

A 0.80 0.90 1.00 -

A1 - - 0.05 -

A2 - - 1.00 9

A3 0.20 REF 9

b 0.18 0.23 0.30 5, 8

D 3.00 BSC -

D1 2.75 BSC 9

D2 1.35 1. 50 1.65 7, 8

E 3.00 BSC -

E1 2.75 BSC 9

E2 1.35 1.50 1.65 7, 8

e 0.50 BSC -

k0.25 - - -

L 0.30 0.40 0.50 8

L1 - - 0.15 10

N162

Nd 4 3

Ne 4 3

P- -0.609

θ--129

Rev. 0 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized t erminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

ISL43140, ISL43141, ISL43142