MT28C3214P2FL-11BET - Micron

MT28C3214P2FL.p65 – Rev. 11/00

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE‡

‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE

SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S

PRODUCTION DATA SHEET SPECIFICATIONS.

FLASH AND SRAM

COMBO MEMORY MT28C3214P2FL

Low Voltage, Extended Temperature

FEATURES

• Flexible dual-bank architecture

• Support for true concurrent operations with no

latency:

Read bank b during program bank a and vice

versa

Read bank b during erase bank a and vice versa

• Organization: 2,048K x 16 (Flash)

256K x 16 (SRAM)

• Basic configuration:

Flash

Bank a (4Mb Flash for data storage)

– Eight 4K-word parameter blocks

– Seven 32K-word blocks

Bank b (28Mb Flash for program storage)

– Fifty-six 32K-word main blocks

SRAM

4Mb SRAM for data storage

– 256K-words

• F_VCC, VCCQ, F_VPP, S_VCC voltages

1.65V (MIN)/2.2V (MAX) F_VCC read voltage

1.65V (MIN)/2.2V (MAX) S_VCC read voltage

1.65V (MIN)/2.2V (MAX) VCCQ

1.8V (TYP) F_VPP (in-system PROGRAM/ERASE)

12V ±5% (HV) F_VPP (production programming

compatibility)

1.0V (MIN) S_VCC (SRAM data retention)

• Asynchronous access time

Flash access time: 95ns or 110ns @ 1.65V F_VCC

SRAM access time: 85ns @ 1.65V S_VCC

• Page Mode read access

Interpage read access: 95ns/110ns @ 1.65V F_VCC

Intrapage read access: 35ns/45ns @ 1.65V F_VCC

• Low power consumption

• Enhanced suspend options

ERASE-SUSPEND-to-READ within same bank

PROGRAM-SUSPEND-to-READ within same

bank

ERASE-SUSPEND-to-PROGRAM within same

bank

• Read/Write SRAM during program/erase of Flash

• Dual 64-bit chip protection registers for security

purposes

• Cross-compatible command set support

Extended command set

Common flash interface (CFI) compliant

• PROGRAM/ERASE cycles

100,000 WRITE/ERASE cycles per block

OPTIONS MARKING

• Timing

95ns -95

110ns -11

• Boot Block

Top T

Bottom B

• Operating Temperature Range

Commercial Temperature (0oC to +70oC) None

Extended Temperature (-40oC to +85oC) ET

Wireless Temperature (-25oC to +85oC) WT

• Package

66-ball FBGA (8 x 8 grid) FL

Part Number Example:

MT28C3214P2FL-95 TET

BALL ASSIGNMENT

66-Ball FBGA (Top View)

1 2 3 4 5 6 7 8 9 10 11 12

Top View

(Ball Down)

A14

DQ11

A15

A10

A19

S_OE#

A20

A16

F_WE#

S_V

F_WP#

S_LB#

A18

F_V

A12

S_WE#

DQ6

S_CE2

DQ10

DQ8

F_V

DQ14

DQ4

S_V

DQ2

DQ0

F_OE#

DQ7

DQ5

F_V

DQ3

DQ1

S_CE1#

A13

DQ15

DQ13

DQ12

DQ9

F_CE#

A11

F_RP#

F_V

S_UB#

A17

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Table 1

Cross Reference for Abbreviated Device Marks

PRODUCT SAMPLE MECHANICAL

PART NUMBER MARKING MARKING SAMPLE MARKING

MT28C3214P2FL-95 BET FW420 FX420 FY420

MT28C3214P2FL-95 TET FW421 FX421 FY421

MT28C3214P2FL-95 BWT FW423 FX423 FY423

MT28C3214P2FL-95 TWT FW422 FX422 FY422

MT28C3214P2FL-11 BET FW437 FX437 FY437

MT28C3214P2FL-11 TET FW431 FX431 FY431

MT28C3214P2FL-11 BWT FW435 FX435 FY435

MT28C3214P2FL-11 TWT FW434 FX434 FY434

DEVICE MARKING

Due to the size of the package, Micron’s standard

part number is not printed on the top of each device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross referenced to Micron part num-

bers in Table 1.

GENERAL DESCRIPTION

The MT28C3214P2FL, a combination of Flash and

SRAM memory, provides a compact, low-power

solution for systems where PCB real estate is at a pre-

mium. The dual-bank Flash is a high-performance,

high-density, nonvolatile memory device with a revo-

lutionary architecture that can significantly improve

system performance.

This new architecture features:

• A two-memory-bank configuration supporting

dual-bank burst operation;

• A high-performance bus interface providing a fast

page data transfer; and

• A conventional asynchronous bus interface.

The device also provides soft protection for blocks

by configuring soft protection registers with dedicated

command sequences. For security purposes, dual 64-

bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state

machine (WSM). The WSM simplifies these operations

and relieves the system processor of secondary tasks.

An on-chip status register, one for each bank, can be

used to monitor the WSM status to determine the

progress of a PROGRAM/ERASE command.

The erase/program suspend functionality allows

compatibility with existing EEPROM emulation soft-

ware packages.

The device takes advantage of a dedicated power

source for the Flash device (F_VCC) and a dedicated

power source for the SRAM device (S_VCC), both at

1.65V–2.20V for optimized power consumption and

improved noise immunity. The separate S_VCC pin for

the SRAM provides the data retention capability when-

ever required. The data retention S_VCC is specified as

low as 1.0V. The device supports two VPP voltages; in-

circuit VPP of 0.9V–2.2V and production compatibility of

12V ±5%. The 12V ±5% VPP is supported for a maximum

of 100 cycles and 10 cumulative hours.

The MT28C3214P2FL contains an asynchronous

4Mb SRAM organized as 256K-words by 16 bits. This

device is fabricated using an advanced CMOS process

and high-speed/ultra-low-power circuit technology.

The MT28C3214P2FL is packaged in a 66-ball FBGA

package with 0.80mm pitch.

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

BLOCK DIAGRAM

F_V

S_OE#

S_CE2

S_CE1#

S_WE#

DQ0

–

DQ15

A18

–

A20

–

A17

F_RP#

F_CE#

F_OE#

F_WE# F_V

F_WP#

F_V

FLASH

SRAM S_V

S_UB#

S_LB#

2,048K x 16

256K x 16

Bank a

Bank b

S_V

FLASH FUNCTIONAL BLOCK DIAGRAM

Address

Input

Buffer

X DEC

Y/Z DEC

Data Input

Buffer

Output

Multiplexer

Address

CNT/WSM

Output

Buffer

Status

Reg.

WSM

Program/

Erase

Pump Voltage

Generators

Address Latch

DQ0-DQ15

DQ0–DQ15

CSM

F_RST#

F_CE#

X DEC

Y/Z DEC

F_WE#

F_OE#

I/O Logic

A0–A20

Address

Multiplexer

Bank 2 Blocks

Y/Z Gating/Sensing

Data

Bank 1 Blocks

Y/Z Gating/Sensing

ID Reg.

RCR

Block Lock

Device ID

Manufacturer’s ID

OTP

Query

PR Lock

Query/OTP

PR Lock

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

BALL DESCRIPTIONS

66-BALL FBGA

NUMBERS SYMBOL TYPE DESCRIPTION

A3, A4, A5, A6, A0–A20 Input Address Inputs: Inputs for the addresses during READ and WRITE

A7, A8, B3, B4, operations. Addresses are internally latched during READ and WRITE

B5, B6, E5, G3, cycles. Flash: A0–A20; SRAM: A0–A17.

G4, G5, G6, G7,

G8, G9, H4, H5,

H7 F_CE# Input Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,

the device is disabled and goes into standby power mode.

H9 F_OE# Input Flash Output Enable: Enables flash output buffers when LOW. When

F_OE# is HIGH, the output buffers are disabled.

C3 F_WE# Input Flash Write Enable: Determines if a given cycle is a flash WRITE cycle.

F_WE# is active LOW.

D4 F_RP# Input Reset. When F_RP# is a logic LOW, the device is in reset, which drives

the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,

the device is in standard operation. When F_RP# transitions from logic

LOW to logic HIGH, the device resets all blocks to locked and defaults to

the read array mode.

E3 F_WP# Input Flash Write Protect. Controls the lock down function of the flexible

locking feature.

G10 S_CE1# Input SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level

deselects the SRAM and reduces the power consumption to standby

levels.

D8 S_CE2 Input SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level

deselects the SRAM and reduces the power consumption to standby

levels.

F5 S_OE# Input SRAM Output Enable: Enables SRAM output buffers when LOW. When

S_OE# is HIGH, the output buffers are disabled.

B8 S_WE# Input SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.

S_WE# is active LOW.

F3 S_LB# Input SRAM Lower Byte: When LOW, it selects the SRAM address lower byte

(DQ0–DQ7).

F4 S_ UB# Input SRAM Upper Byte: When LOW, it selects the SRAM address upper byte

(DQ8–DQ15).

B7, B9, B10, DQ0–DQ15 Input/ Data Inputs/Outputs: Input array data on the second CE# and WE#

C7, C8, C9, Output cycle during PROGRAM command. Input commands to the command

C10, D7, E6, user interface when CE# and WE# are active. Output data when CE#

E8, E9, E10, and OE# are active.

F7, F8, F9, F10

(continued on next page)

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

BALL DESCRIPTIONS (continued)

66-BALL FBGA

NUMBERS SYMBOL TYPE DESCRIPTION

E4 F_VPP Input/ Flash Program/Erase Power Supply: [0.9V–2.2V or 11.4V–12.6V]. Operates

Supply as input at logic levels to control complete device protection. Provides

backward compatibility for factory programming when driven to 11.4V–

12.6V. Lower F_VPP voltages are available; consult factory for availability.

D10, H3 F_VCC Supply Flash Power Supply: [1.65V–2.2V]. Supplies power for device operation.

A9, H8 F_ VSS Supply Flash Specific Ground: Do not float any ground pin.

D9 S_VCC Supply SRAM Power Supply: [1.65V–2.2V]. Supplies power for device operation.

D3 S_VSS Supply SRAM Specific Ground: Do not float any ground pin.

A10 VCCQ Supply I/O Power Supply: [1.65–2.2V]. This input should be tied directly to VCC.

A1, A2, A11, NC – No Connect: Lead is not internally connected; it may be driven or

A12, C4, H1, floated.

H2, H10, H11,

H12

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

NOTES: 1. Two devices may not drive the memory bus at the same time.

2. Allowable flash read modes include read array, read query, read configuration, and read status.

3. Outputs are dependent on a separate device controlling bus outputs.

4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.

5. The SRAM may be placed into data retention mode by lowering S_VCC to the VDR range, as specified.

6. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2.

7. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to

control the bus outputs at a time.

8. Data output on lower byte only; upper byte High-Z.

9. Data output on upper byte only; lower byte High-Z.

10. Data input on lower byte only.

11. Data input on upper byte only.

TRUTH TABLE – FLASH

FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT

MODES

F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#

MEMORY DQ0–DQ15 NOTES

BUS CONTROL

Read H L L H SRAM must be High-Z Flash DOUT 1, 2, 3

Write H L H L Flash DIN 1

Standby H H X X Other High-Z 4 , 5

Output Disable H L H H SRAM any mode allowable Other High-Z 4 , 6

Reset L X X X Other High-Z 4 , 7

TRUTH TABLE – SRAM

FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT

MODES

F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#

MEMORY DQ0–DQ15 NOTES

BUS CONTROL

Read

DQ0–DQ15 L H L H L L SRAM DOUT 1, 3

DQ0–DQ7 L H L H H L SRAM DOUT LB 8

DQ8–DQ15 Flash must be High-Z L H L H L H S R A M DOUT UB 9

Write

DQ0–DQ15 L H H L L L SRAM DIN 1, 3

DQ0–DQ7 L H H L H L SRAM DIN LB 1 0

DQ8–DQ15 L H H L L H SRAM DIN UB 11

Standby H X X X X X Other High-Z 4 , 5

Flash any mode allowable X L X X X X Other High-Z 4, 5

Output Disable L H X X X X Other High-Z 4 , 5

Data Retention Same as standby Other High-Z 4 , 6

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

ARCHITECTURE AND MEMORY

ORGANIZATION

The Flash memory device contains two separate

memory banks (bank a and bank b) for simultaneous

READ and WRITE operations. Bank a is 4Mb deep and

contains 8 x 4K-word parameter blocks and seven 32K-

word blocks. Bank b is 28Mb deep, is equally sectored,

and contains fifty-six 32K-word blocks.

Figures 1 and 2 show the top and bottom memory

organizations.

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Figure 1

Bottom Boot Block Device

Bank b = 28Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

70 64/32 1F8000h-1FFFFFh

69 64/32 1F0000h-1F7FFFh

68 64/32 1E8000h-1EFFFFh

67 64/32 1E0000h-1E7FFFh

66 64/32 1D8000h-1DFFFFh

65 64/32 1D0000h-1D7FFFh

64 64/32 1C8000h-1CFFFFh

63 64/32 1C0000h-1C7FFFh

62 64/32 1B8000h-1BFFFFh

61 64/32 1B0000h-1B7FFFh

60 64/32 1A8000h-1AFFFFh

59 64/32 1A0000h-1A7FFFh

58 64/32 198000h-19FFFFh

57 64/32 190000h-197FFFh

56 64/32 188000h-18FFFFh

55 64/32 180000h-187FFFh

54 64/32 178000h-17FFFFh

53 64/32 170000h-177FFFh

52 64/32 168000h-16FFFFh

51 64/32 160000h-167FFFh

50 64/32 158000h-15FFFFh

49 64/32 150000h-157FFFh

48 64/32 148000h-14FFFFh

47 64/32 140000h-147FFFh

46 64/32 138000h-13FFFFh

45 64/32 130000h-137FFFh

44 64/32 128000h-12FFFFh

43 64/32 120000h-127FFFh

42 64/32 118000h-11FFFFh

41 64/32 110000h-117FFFh

40 64/32 108000h-10FFFFh

39 64/32 100000h-107FFFh

38 64/32 0F8000h-0FFFFFh

37 64/32 0F0000h-0F7FFFh

36 64/32 0E8000h-0EFFFFh

35 64/32 0E0000h-0E7FFFh

34 64/32 0D800h-0DFFFFh

33 64/32 0D0000h-0D7FFFh

32 64/32 0C8000h-0CFFFFh

31 64/32 0C0000h-0C7FFFh

30 64/32 0B8000h-0BFFFFh

29 64/32 0B0000h-0B7FFFh

28 64/32 0A8000h-0AFFFFh

27 64/32 0A0000h-0A7FFFh

26 64/32 098000h-097FFFh

25 64/32 090000h-097FFFh

24 64/32 088000h-087FFFh

23 64/32 080000h-087FFFh

22 64/32 078000h-07FFFFh

21 64/32 070000h-077FFFh

20 64/32 068000h-067FFFh

19 64/32 060000h-067FFFh

18 64/32 058000h-05FFFFh

17 64/32 050000h-057FFFh

16 64/32 048000h-04FFFFh

15 64/32 040000h-047FFFh

Bank a = 4Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

14 64/32 038000h-03FFFFh

13 64/32 030000h-037FFFh

12 64/32 028000h-02FFFFh

11 64/32 020000h-027FFFh

10 64/32 018000h-01FFFFh

9 64/32 010000h-017FFFh

8 64/32 008000h-00FFFFh

7 8/4 007000h-007FFFh

6 8/4 006000h-006FFFh

5 8/4 005000h-005FFFh

4 8/4 004000h-004FFFh

3 8/4 003000h-003FFFh

2 8/4 002000h-002FFFh

1 8/4 001000h-001FFFh

0 8/4 000000h-000FFFh

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Figure 2

Top Boot Block Device

Bank b = 28Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

55 64/32 1B8000h-1BFFFFh

54 64/32 1B0000h-1B7FFFh

53 64/32 1A8000h-1AFFFFh

52 64/32 1A0000h-1A7FFFh

51 64/32 198000h-19FFFFh

50 64/32 190000h-197FFFh

49 64/32 188000h-18FFFFh

48 64/32 180000h-187FFFh

47 64/32 178000h-17FFFFh

46 64/32 170000h-177FFFh

45 64/32 168000h-16FFFFh

44 64/32 160000h-167FFFh

43 64/32 158000h-15FFFFh

42 64/32 150000h-157FFFh

41 64/32 148000h-14FFFFh

40 64/32 140000h-147FFFh

39 64/32 138000h-13FFFFh

38 64/32 130000h-137FFFh

37 64/32 128000h-12FFFFh

36 64/32 120000h-127FFFh

35 64/32 118000h-11FFFFh

34 64/32 110000h-117FFFh

33 64/32 108000h-10FFFFh

32 64/32 100000h-107FFFh

31 64/32 0F8000h-0FFFFFh

30 64/32 0F0000h-0F7FFFh

29 64/32 0E8000h-0EFFFFh

28 64/32 0E0000h-0E7FFFh

27 64/32 0D8000h-0DFFFFh

26 64/32 0D0000h-0D7FFFh

25 64/32 0C8000h-0CFFFFh

24 64/32 0C0000h-0C7FFFh

23 64/32 0B8000h-0BFFFFh

22 64/32 0B0000h-0B7FFFh

21 64/32 0A8000h-0AFFFFh

20 64/32 0A0000h-0A7FFFh

19 64/32 098000h-09FFFFh

18 64/32 090000h-097FFFh

17 64/32 088000h-08FFFFh

16 64/32 080000h-087FFFh

15 64/32 078000h-07FFFFh

14 64/32 070000h-077FFFh

13 64/32 068000h-06FFFFh

12 64/32 060000h-067FFFh

11 64/32 058000h-05FFFFh

10 64/32 050000h-057FFFh

9 64/32 048000h-04FFFFh

8 64/32 040000h-047FFFh

7 64/32 038000h-03FFFFh

6 64/32 030000h-037FFFh

5 64/32 028000h-02FFFFh

4 64/32 020000h-027FFFh

3 64/32 018000h-01FFFFh

2 64/32 010000h-017FFFh

1 64/32 008000h-00FFFFh

0 64/32 000000h-007FFFh

Bank a = 4Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

70 8/4 1FF000h-1FFFFFh

69 8/4 1FE000h-1FEFFFh

68 8/4 1FD000h-1FDFFFh

67 8/4 1FC000h-1FCFFFh

66 8/4 1FB000h-1FBFFFh

65 8/4 1FA000h-1FAFFFh

64 8/4 1F9000h-1F9FFFh

63 8/4 1F8000h-1F8FFFh

62 64/32 1F0000h-1F7FFFh

61 64/32 1E8000h-1EFFFFh

60 64/32 1E0000h-1E7FFFh

59 64/32 1D8000h-1DFFFFh

58 64/32 1D0000h-1D7FFFh

57 64/32 1C8000h-1CFFFFh

56 64/32 1C0000h-1C7FFFh

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

FLASH MEMORY OPERATING MODES

COMMAND STATE MACHINE

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-

ings. The CSM acts as an interface between external

microprocessors and the internal write state machine

(WSM). The available commands are listed in Table 2,

their definitions are given in Table 3 and their descrip-

tions in Table 4. Program and erase algorithms are au-

tomated by the on-chip WSM. Table 5 shows the CSM

transition states. Once a valid PROGRAM/ERASE com-

mand is entered, the WSM executes the appropriate

algorithm, which generates the necessary timing sig-

nals to control the device internally. A command is

valid only if the exact sequence of WRITEs is completed.

After the WSM completes its task, the write state ma-

chine status (WSMS) bit (SR7) (see Table 7) is set to a

logic HIGH level (VIH), allowing the CSM to respond to

the full command set again.

OPERATIONS

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional

microprocessor timings into an on-chip CSM through

I/O pins DQ0–DQ7. The number of bus cycles required

to activate a command is typically one or two. The first

operation is always a WRITE. Control pins F_CE# and

F_WE# must be at a logic LOW level (VIL), and F_OE#

and F_RP# must be at logic HIGH (VIH). The second

operation, when needed, can be a WRITE or a READ

depending upon the command. During a READ opera-

tion, control pins F_CE# and F_OE# must be at a logic

LOW level (VIL), and F_WE# and F_RP# must be at logic

HIGH (VIH).

Table 6 illustrates the bus operations for all the

modes: write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of opera-

tion. Changing the mode of operation requires that a

command code be entered into the CSM. For each one

of the two flash memory partitions, an on-chip status

toring of the progress of various operations that can

take place on a memory bank. One of the two status

registers is interrogated by entering a READ STATUS

ing an address within the memory partition boundary,

and reading the register data on I/O pins DQ0–DQ7

(cycle 2). Status register bits SR0-SR7 correspond to

DQ0–DQ7 (see Table 7).

COMMAND DEFINITION

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating

the necessary timing signals to program, erase, and

verify data. See Table 3 for the CSM command defini-

tions and data for each of the bus cycles.

STATUS REGISTER

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is

pending or complete. The status register is monitored

toggling F_OE#, F_CE#, and address lines by reading

the resulting status code on I/O pins DQ0–DQ7. The

high-order I/Os (DQ8–DQ15) are set to 00h internally,

Table 2

Command State Machine Codes For Device Mode Selection

COMMAND DQ0–DQ7 CODE ON DEVICE MODE

10h/40h Program setup/alternate program setup

20h Block erase setup

50h Clear status register

60h Protection configuration setup

70h Read status register

90h Read protection configuration register

98h Read query

B0h Program/erase suspend

C0h Protection register program/lock

D0h Program/erase resume - erase confirm

FFh Read array

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

so only the low-order I/O pins (DQ0–DQ7) need to be

interpreted. Address lines select the status register per-

tinent to the selected memory partition.

edge of F_OE# or F_CE#, whichever occurs first. The

latest falling edge of either of these two signals up-

dates the latch within a given READ cycle. Latching the

data prevents errors from occurring if the register input

changes during a status register read.

The status register provides the internal state of the

WSM to the external microprocessor. During periods

when the WSM is active, the status register can be polled

to determine the WSM status. Table 7 defines the sta-

tus register bits.

After monitoring the status register during a

PROGRAM/ERASE operation, the data appearing on

DQ0–DQ7 remains as status register data until a new

command is issued to the CSM. To return the device to

other modes of operation, a new command must be

issued to the CSM.

COMMAND STATE MACHINE OPERATIONS

The CSM decodes instructions for the commands

listed in Table 2. The 8-bit command code is input to

the device on DQ0–DQ7 (see Table 3 for command

definitions). During a PROGRAM or ERASE cycle, the

CSM informs the WSM that a PROGRAM or ERASE cycle

has been requested.

During a PROGRAM cycle, the WSM controls the

program sequences and the CSM responds to a PRO-

GRAM SUSPEND command only.

During an ERASE cycle, the CSM responds to an

ERASE SUSPEND command only. When the WSM has

completed its task, the WSMS bit (SR7) is set to a logic

HIGH level and the CSM responds to the full command

set. The CSM stays in the current command state until

the microprocessor issues another command.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when VPP is within its correct volt-

age range.

Table 3

Command Definitions

FIRST BUS CYCLE SECOND BUS CYCLE

COMMAND OPERATION ADDRESS DATA OPERATION ADDRESS DATA

READ ARRAY WRITE WA FFh

READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ IA ID

READ STATUS REGISTER WRITE BA 70h READ BA SRD

CLEAR STATUS REGISTER WRITE BA 50h

READ QUERY WRITE QA 98h READ QA QD

BLOCK ERASE SETUP WRITE BA 20h WRITE BA D0h

PROGRAM SETUP/ALTERNATE PROGRAM SETUP WRITE WA 40h/10h WRITE WA WD

PROGRAM/ERASE SUSPEND WRITE BA B0h

PROGRAM/ERASE RESUME - ERASE CONFIRM WRITE BA D0h

LOCK BLOCK WRITE BA 60h WRITE BA 01h

UNLOCK BLOCK WRITE BA 60h WRITE BA D0h

LOCK DOWN BLOCK WRITE BA 60h WRITE BA 2Fh

PROTECTION REGISTER PROGRAM WRITE PA C0h WRITE PA PD

PROTECTION REGISTER LOCK WRITE LPA C0h WRITE LPA FFFDh

NOTE: 1. W A: Word address of memory location to be written, or read

2. IA: Identification code address

3. B A: Address within the block

4. ID: Identification code data

5. SRD: Data read from the status register

6. QA: Query code address

7. QD: Query code data

8. W D: Data to be written at the location WA

9. PA: Protection register address

10. LPA: Lock protection register address

11. PD: Protection register data

FLASH

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2 MEG x 16 PAGE FLASH

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ADVANCE

Table 4

Command Descriptions

CODE DEVICE MODE BUS CYCLE DESCRIPTION

10h Alt. Program Setup First Operates the same as a PROGRAM SETUP command.

20h Erase Setup First Prepares the CSM for an ERASE CONFIRM command. If the next

command is not ERASE CONFIRM, the CSM will set both SR4 and SR5

of the status register to a “1,” place the device into read status

40h Program Setup First A two-cycle command: The first cycle prepares for a PROGRAM

operation, the second cycle latches addresses and data and initiates

the WSM to execute the program algorithm. The flash outputs status

occurs first.

50h Clear Status First The WSM can set the program status (SR4), and erase status (SR5) bits

this command clears those bits to “0.”

60h Protection First Prepares the CSM for changes to the block locking status. If the next

Configuration command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK

Setup DOWN, then the CSM will set both the program and erase status

70h Read Status First Places the device into read status register mode. Reading the device

address presented to the device. The device will automatically enter

this mode after a PROGRAM or ERASE operation has been initiated.

90h Read Protection First Puts the device into the read protection configuration mode so that

Configuration reading the device will output the manufacturer/device codes or

block lock status.

98h Read Query First Puts the device into the read query mode so that reading the device

will output common flash interface information.

B0h Program Suspend First Suspends the currently executing PROGRAM/ERASE operation. The

status register will indicate when the operation has been successfully

Erase Suspend First suspended by setting either the program suspend (SR2) or erase

suspend (SR6) and the WSMS bit (SR7) to a “1” (ready). The WSM

will continue to idle in the suspend state, regardless of the state of all

input control pins except F_RP#, which will immediately shut down

the WSM and the remainder of the chip if F_RP# is driven to VIL.

C0 h Program Device First Writes a specific code into the device protection register.

Protection Register

Lock Device First Locks the device protection register; data can no longer be changed.

Protection register

(continued on the next page)

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ADVANCE

Table 4

Command Descriptions (continued)

CODE DEVICE MODE BUS CYCLE DESCRIPTION

D0h Erase Confirm First If the previous command was an ERASE SETUP command, then the

CSM will close the address and data latches, and it will begin erasing

the block indicated on the address pins. During programming/erase,

the device will respond only to the READ STATUS REGISTER,

PROGRAM SUSPEND, or ERASE SUSPEND commands and will output

status register data on the falling edge of F_OE# or F_CE#, whichever

occurs last.

Program/Erase First If a PROGRAM or ERASE operation was previously suspended, this

Resume command will resume the operation.

F F h Read Array First During the array mode, array data will be output on the data bus.

01h Lock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock the block indicated on the

address bus.

2Fh Lock Down Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock down the block indicated on

the address bus.

D0h Unlock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and unlock the block indicated on the

address bus. If the block had been previously set to Lock Down, this

operation will have no effect.

00h Invalid/Reserved Unassigned command that should not be used.

CLEAR STATUS REGISTER

The internal circuitry can set, but not clear, the block

lock status bit (SR1), the VPP status bit (SR3), the pro-

gram status bit (SR4), and the erase status bit (SR5) of

the status register. The CLEAR STATUS REGISTER com-

mand (50h) allows the external microprocessor to clear

these status bits and synchronize to the internal op-

erations. When the status bits are cleared, the device

returns to the read array mode.

READ OPERATIONS

The following READ operations are available: READ

ARRAY, READ PROTECTION CONFIGURATION REG-

ISTER, READ QUERY and READ STATUS REGISTER.

READ ARRAY

The array is read by entering the command code

FFh on DQ0–DQ7. Control pins F_CE# and F_OE# must

be at a logic LOW level (VIL), and F_WE# and F_RP#

must be at a logic HIGH level (VIH) to read data from the

array. Data is available on DQ0–DQ15. Any valid ad-

dress within any of the blocks selects that address and

allows data to be read from that address. Upon initial

power-up, the device defaults to the read array mode.

READ CHIP PROTECTION IDENTIFICATION DATA

The chip identification mode outputs three types

of information: the manufacturer/device identifier, the

block locking status, and the protection register. Two

bus cycles are required for this operation: the chip iden-

tification data is read by entering the command code

90h on DQ0–DQ7 and the identification code address

on the address lines. Control pins F_CE# and F_OE#

must be at a logic LOW level (VIL), and F_WE# and F_RP#

must be at a logic HIGH level (VIH) to read data from the

protection configuration register. Data is available on

DQ0–DQ15. To return to read array mode, write the

read array command code FFh on DQ0–DQ7. See Table

9 for further details.

READ QUERY

The read query mode outputs common flash inter-

face (CFI) data when the device is read (see Table 13).

Two bus cycles are required for this operation. It is

possible to access the query by writing the read query

command code 98h on DQ0–DQ7. Control pins F_CE#

and F_OE# must be at a logic LOW level (VIL), and F_WE#

and F_RP# must be at a logic HIGH level (VIH) to read

data from the query. The CFI data structure contains

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

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ADVANCE

Table 5

Command State Machine Transition Table

)noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP noititrap

etatstneserP rehtoehtfo noititrap

hF2 -kcoL nwod mrifnoc

h10 kcoL mrifnoc

h0C PTO putes

h06 kcolnU/kcoL nwod-kcoL/

h89 daeR yreuq

h09 daeR ecived

h05 raelC sutats retsiger

h07 daeR sutats

h0B margorP esarE/ dnepsus

h0D ,mrifnocEB ,emuserE/P mrifnocBLU

h02 esarE putes

h04/h01 margorP putes

hFF daeR yarra 7RS ataD nehw daer etatSedoM

yarradaeR

kcoL daeR yreuq daeR DI daeR yarra daeR sutats

yarradaeR

1yarrAyarrA

daeR

1puteS

2ysuB

yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra

3eldI

yarradaeR yarradaeR 4 esarE dnepsus

yarradaeR5

.gorP dnepsus

yarradaeR

kcoL daeR yreuq daeR DI daeR yarra daeR sutats

yarradaeR

1IFCyreuQ

6puteS

7ysuB

yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra

8eldI

yarradaeR yarradaeR 9 esarE dnepsus

yarradaeR01.gorP dnepsus

yarradaeR

kcoL daeR yreuq daeR DI daeR yarra daeR sutats

yarradaeR

1DIeciveD DI

11puteS

21ysuB

yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra

31eldI

yarradaeR yarradaeR 41 esarE dnepsus

yarradaeR51.gorP dnepsus

yarradaeR

kcoL daeR yreuq daeR DI daeR yarra daeR sutats

yarradaeR

1sutatSsutatS

61puteS

71ysuB

yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra

81eldI

yarradaeR yarradaeR 91 esarE dnepsus

yarradaeR02.gorP dnepsus

ysubretsigernoitcetorP 1sutatSputeS P

12eldI

ysubretsigernoitcetorP 0sutatSysuB22eldI

yarradaeRkcoL daeR yreuq daeR DI daeR yarra daeR sutats yarradaeR1sutatSenoD 32puteS

42ysuB

yarradaeR PTO putes

kcoL daeR yreuq daeR DI daeR yarra daeR sutats

yarradaeR esarE putes margorP putes daeR yarra 1sutatSenoD

52eldI

yarradaeR

yarradaeR 62 esarE dnepsus

yarradaeR72.gorP dnepsus

(continued on next page)

FLASH

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2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Table 5

Command State Machine Transition Table (continued)

)noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP noititrap

foetatstneserP rehtoeht noititrap

hF2 -kcoL nwod mrifnoc

h10 kcoL mrifnoc

H0C PTO putes

h06 kcolnU/kcoL nwod-kcoL/

h89 daeR yreuq

h09 daeR DIecived

h05 raelC sutats retsiger

h07 daeR sutats

h0B margorP esarE/ dnepsus

h0D ,mrifnocEB ,emuserE/P mrifnocBLU

h02 esarE putes

h04/h01 margorP putes

hFF daeR yarra 7RS ataD nehw daer etatSedoM

BLU/BLkcoLLBLU/BLkcoL1sutatSputeS

kcoL

82 ynA etats

yarradaeR

kcoL daeR yreuq DIdaeR daeR yarra daeR sutats

yarradaeR

1sutatSrorrE

92puteS

03ysuB

yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra

13eldI

yarradaeR yarradaeR 23 esarE dnepsus

yarradaeR33.gorP dnepsus

yarradaeR

kcoL daeR yreuq DIdaeR daeR yarra daeR sutats

yarradaeR

1sutatS /kcoL kcolnU

43puteS

53ysuB

yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra

63eldI

yarradaeR yarradaeR 73 esarE dnepsus

yarradaeR83.gorP dnepsus

ysuBmargorP 1sutatSputeS

margorP

93 ynA etats

ysuBmargorPdaerSPysubmargorP0sutatSysuB04eldI

yarradaeR

kcoL daeR yreuq DIdaeR daeR yarra daeR sutats

yarradaeR

1sutatSenoD

14puteS

24ysuB

yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra

34eldI

yarradaeR yarradaeR 44 esarE dnepsus

yarradaeR54.gorP dnepsus

daerdnepsusmargorP yarra kcoL

margorP dnepsus daer yreuq

margorP dnepsus DIdaer

margorP dnepsus daer yarra

margorP dnepsus daer sutats

margorP dnepsus daer yarra

ysubmargorP daerdnepsusmargorP yarra 1sutatS daeR sutats margorP dnepsus

64puteS

74eldI

84 esarE dnepsus

(continued on next page)

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Table 5

Command State Machine Transition Table (continued)

)noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP noititrap

etatstneserP rehtoehtfo noititrap

hF2 -kcoL nwod mrifnoc

h10 kcoL mrifnoc

h0C PTO putes

h06 kcolnU/kcoL nwod-kcoL/

h89 daeR yreuq

h09 daeR DIecived

h05 raelC sutats retsiger

h07 daeR sutats

h0B margorP esarE/ dnepsus

h0D ,mrifnocEB ,emuserE/P mrifnocBLU

h02 esarE putes

h04/h01 margorP putes

hFF daeR yarra 7RS ataD nehw daer etatSedoM

daerdnepsusmargorP yarra kcoL

margorP dnepsus daer yreuq

margorP dnepsus DIdaer

margorP dnepsus daer yarra

margorP dnepsus daer sutats

margorP dnepsus daer yarra

ysubmargorP daerdnepsusmargorP yarra 1yarrA daeR yarra

margorP dnepsus

94puteS

05eldI

15 esarE dnepsus

daerdnepsusmargorP yarra kcoL

margorP dnepsus daer yreuq

margorP dnepsus DIdaer

margorP dnepsus daer yarra

margorP dnepsus daer sutats

margorP dnepsus daer yarra

ysubmargorP daerdnepsusmargorP yarra

DIdaeR

25puteS

35eldI

45 esarE dnepsus

daerdnepsusmargorP yarra kcoL

margorP dnepsus daer yreuq

margorP dnepsus DIdaer

margorP dnepsus daer yarra

margorP dnepsus daer sutats

margorP dnepsus daer yarra

ysubmargorP daerdnepsusmargorP yarra 1IFC daeR yreuQ

55puteS

65eldI

75 esarE dnepsus

BLU/BLrorreesarE esarE rorre ysubesarErorreesarE

1sutatSputeS

esarE

85eldI

yarradaeR

kcoL daeR yreuq DIdaeR daeR yarra daeR sutats

yarradaeR

sutatS

rorrE

95puteS

06ysuB

yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra

16eldI

yarradaeR yarradaeR 26 esarE dnepsus

yarradaeR36.gorP dnepsus

yarradaeR

kcoL daeR yreuq DIdaeR daeR yarra daeR sutats

yarradaeR

sutatS

enoD

46puteS

56ysuB

yarradaeR PTO putes yarradaeResarE margorP putes daeR yarra

66eldI

yarradaeR yarradaeR 76 esarE dnepsus

yarradaeR86.gorP dnepsus

ysubesarekcolB daerSE sutats ysubesarE0sutatSysuB96eldI

(continued on next page)

FLASH

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2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Table 5

Command State Machine Transition Table

)noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP noititrap etatstneserP rehtoehtfo noititrap

hF2 -kcoL nwod mrifnoc

h10 kcoL mrifnoc

h0C PTO putes

h06 kcolnU/kcoL nwod-kcoL/

h89 daeR yreuq

h09 daeR DIecived

h05 raelC sutats retsiger

h07 daeR sutats

h0B margorP esarE/ dnepsus

h0D ,mrifnocEB ,emuserE/P mrifnocBLU

h02 esarE putes

h04/h01 margorP putes

hFF daeR yarra 7RS ataD nehw daer etatSedoM

yarradaerdnepsusesarEkcoL

esarE dnepsus daer yreuq

esarE dnepsus DIdaer

esarE dnepsus daer yarra

esarE dnepsus daer sutats

daerSE yarra ysubesarE daerdnepsusesarE yarra

sutatS daeR

sutats

esarE dnepsus

07puteS

yarradaerdnepsusesarE 17ysuB

daerSE yarra ysubesarE SE daer yarra

.gorP putes

SE daer yarra 27eldI

yarradaerdnepsusesarE 37 .gorP dnepsus

yarradaerdnepsusesarEkcoL

esarE dnepsus daer yreuq

esarE dnepsus DIdaer

esarE dnepsus daer yarra

esarE dnepsus daer sutats

daerSE yarra ysubesarE daerdnepsusesarE yarra

1yarrA daeR arra

47puteS

yarradaerdnepsusesarE 57ysuB

daerSE yarra ysubesarE SE daer yarra

.gorP putes

SE daer yarra 67eldI

yarradaerdnepsusesarE 77 .gorP dnepsus

yarradaerdnepsusesarEkcoL

esarE dnepsus daer yreuq

esarE dnepsus DIdaer

esarE dnepsus daer yarra

esarE dnepsus daer sutats

daerSE yarra ysubesarE daerdnepsusesarE yarra

DI daeR DI

87puteS

yarradaerdnepsusesarE 97ysuB

daerSE yarra ysubesarE SE daer yarra

.gorP putes

SE daer yarra 08eldI

yarradaerdnepsusesarE 18 .gorP dnepsus

yarradaerdnepsusesarEkcoL

esarE dnepsus daer yreuq

esarE dnepsus DIdaer

esarE dnepsus daer yarra

esarE dnepsus daer sutats

daerSE yarra ysubesarE daerdnepsusesarE yarra

1IFC daeR yreuq

28puteS

yarradaerdnepsusesarE 38ysuB

daerSE yarra ysubesarE SE daer yarra

.gorP putes

SE daer yarra 48eldI

yarradaerdnepsusesarE 58 .gorP dnepsus

FLASH

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ADVANCE

ERASE OPERATIONS

An ERASE operation must be used to initialize all

bits in an array block to “1s.” After BLOCK ERASE con-

firm is issued, the CSM responds only to an ERASE

SUSPEND command until the WSM completes its task.

Block erasure inside the memory array sets all bits

within the address block to logic 1s. Erase is accom-

plished only by blocks; data at single address locations

within the array cannot be erased individually. The

block to be erased is selected by using any valid ad-

dress within that block. Block erasure is initiated by a

command sequence to the CSM: BLOCK ERASE setup

(20h) followed by BLOCK ERASE CONFIRM (D0h) (see

Table 3). A two-command erase sequence protects

against accidental erasure of memory contents.

When the BLOCK ERASE CONFIRM command is

complete, the WSM automatically executes a sequence

of events to complete the block erasure. During this

sequence, the block is programmed with logic 0s, data

is verified, all bits in the block are erased, and finally

verification is performed to ensure that all bits are cor-

rectly erased. Monitoring of the ERASE operation is

possible through the status register (see the Status

During the execution of an ERASE operation, the

ERASE SUSPEND command (B0h) can be entered to

direct the WSM to suspend the ERASE operation. Once

the WSM has reached the suspend state, it allows the

CSM to respond only to the READ ARRAY, READ STA-

TUS REGISTER, READ QUERY, READ CHIP PROTEC-

TION CONFIGURATION, PROGRAM SETUP, PRO-

GRAM RESUME, ERASE RESUME and LOCK SETUP

(see the Block Locking section). During the ERASE SUS-

PEND operation, array data must be read from a block

other than the one being erased. To resume the ERASE

operation, an ERASE RESUME command (D0h) must

be issued to cause the CSM to clear the suspend state

previously set (see Figure 6). It is also possible that an

ERASE in any bank can be suspended and a WRITE to

another block in the same bank can be initiated. After

the completion of a WRITE, an ERASE can be resumed

by writing an ERASE RESUME command.

information such as block size, density, command set,

and electrical specifications. To return to read array

mode, write the read array command code FFh on DQ0–

DQ7.

READ STATUS REGISTER

The status register is read by entering the command

code 70h on DQ0–DQ7. Two bus cycles are required for

this operation: one to enter the command code and a

second to read the status register. In a READ cycle, the

address is latched and register data is updated on the

falling edge of F_OE# or F_CE#, whichever occurs last.

PROGRAMMING OPERATIONS

There are two CSM commands for programming:

PROGRAM SETUP and ALTERNATE PROGRAM SETUP

(see Table 2).

After the desired command code is entered (10h or

40h command code on DQ0–DQ7), the WSM takes over

and correctly sequences the device to complete the

PROGRAM operation. The WRITE operation may be

monitored through the status register (see the Status

respond to a PROGRAM SUSPEND command until the

PROGRAM operation has been completed, after which

time all commands to the CSM become valid again.

The PROGRAM operation can be suspended by issuing

a PROGRAM SUSPEND command (B0h). Once the WSM

reaches the suspend state, it allows the CSM to re-

spond only to READ ARRAY, READ STATUS REGISTER,

READ PROTECTION CONFIGURATION, READ QUERY,

PROGRAM SETUP, or PROGRAM RESUME. During the

PROGRAM SUSPEND operation, array data should be

read from an address other than the one being pro-

grammed. To resume the PROGRAM operation, a PRO-

GRAM RESUME command (D0h) must be issued to

cause the CSM to clear the suspend state previously

set (see Figure 3 for programming operation and Figure

4 for program suspend and program resume).

Taking F_RP# to VIL during programming aborts the

PROGRAM operation.

FLASH

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ADVANCE

STATUS

BIT # STATUS REGISTER BIT DESCRIPTION

SR7 WRITE

STATE

MACHINE

STATUS

(WSMS) Check write state machine bit first to determine word

1 = Ready program or block erase completion, before checking

0 = Busy program or erase status bits.

SR6 ERASE SUSPEND STATUS (ESS) When ERASE SUSPEND is issued, WSM halts execution and

1 = BLOCK ERASE Suspended sets both WSMS and ESS bits to “1.” ESS bit remains set to

0 = BLOCK ERASE in “1” until an ERASE RESUME command is issued.

Progress/Completed

S R5 ERASE STATUS (ES) When this bit is set to “1,” WSM has applied the maximum

1 = Error in Block Erasure number of erase pulses to the block and is still unable to

0 = Successful BLOCK ERASE verify successful block erasure.

S R 4 PROGRAM STATUS (PS) When this bit is set to “1,” WSM has attempted but failed to

1 = Error in PROGRAM program a word.

0 = Successful PROGRAM

SR3 VPP STATUS (VPPS) The VPP status bit does not provide continuous indication

1 = VPP Low Detect, Operation Abort of the VPP level. The WSM interrogates the VPP level only

0 = VPP = OK after the program or erase command sequences have been

entered and informs the system if VPP has not been switched

on. The VPP level is also checked before the PROGRAM/ERASE

operation is verified by the WSM. A factory option allows

PROGRAM or ERASE at 0V, in which case SR3 is held at “0.”

SR2 PROGRAM SUSPEND STATUS (PSS) When PROGRAM SUSPEND is issued, WSM halts execution

1 = PROGRAM Suspended and sets both WSM and PSS bits to “1.” PSS bit remains set to

0 = PROGRAM in Progress/Completed “1” until a PROGRAM RESUME command is issued.

SR1 BLOCK LOCK STATUS (BLS) If a PROGRAM or ERASE operation is attempted to one of

1 = PROGRAM/ERASE Attempted on a the locked blocks, this is set by the WSM. The operation

Locked Block; Operation Aborted specified is aborted and the device is returned to read status

0 = No Operation to Locked Blocks mode.

S R 0 RESERVED FOR FUTURE This bit is reserved for future.

ENHANCEMENT

Table 7

Status Register Bit Definition

WSMS ESS ES PS VPPS PSS BLS R

76543210

Table 6

Bus Operations

MODE F_RP# F_CE# F_OE# F_WE# ADDRESS DQ0–DQ15

Read (array, status registers, VIH VIL VIL VIH XDOUT

device identification register, or

query)

Standby VIH VIH X X X High-Z

Output Disable VIH VIH X X X High-Z

Reset VIL X X X X High-Z

Write VIH VIL VIH VIL XDIN

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ADVANCE

Figure 3

Automated Word Programming

Flowchart

NOTE: 1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation

attempts.

BUS

OPERATION COMMAND COMMENTS

WRITE WRITE Data = 40h or 10h

PROGRAM Addr = Address of word to be

SETUP programmed

WRITE WRITE Data = Word to be

DATA programmed

Addr = Address of word to be

programmed

READ Status register data;

toggle OE# or CE# to update

status register.

Standby Check SR7

1 = Ready, 0 = Busy

Repeat for subsequent words.

Write FFh after the last word programming operation

to reset the device to read array mode.

BUS

OPERATION COMMAND COMMENTS

Standby Check SR1

1 = Detect locked block

Standby Check SR3

1 = Detect V

low

Standby Check SR4

1 = Word program error

YES

Full Status Register

Check (optional)

YES

PROGRAM

SUSPEND?

SR7 = 1?

Issue PROGRAM SETUP

Command and

Word Address

Start

Word Program Passed

Range Error

Word Program Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits

Issue Word Address

and Word Data

PROGRAM

SUSPEND Loop

YES

SR1 = 0?

YES

SR3 = 0?

YES

SR4 = 0?

Word Program

Completed

Read Status Register

Bits

PROGRAM Attempted

on a Locked Block

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ADVANCE

Issue READ ARRAY

Command

PROGRAM

Complete

Finished

Reading

Issue PROGRAM

RESUME Command

YES

SR2 = 1?

Start

PROGRAM Resumed

Read Status Register

Bits

Issue PROGRAM

SUSPEND Command

YES

SR7 = 1?

Figure 4

PROGRAM SUSPEND/

PROGRAM RESUME Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE PROGRAM Data = B0h

SUSPEND

READ Status register data;

toggle OE# or CE# to update

status register.

Standby Check SR7

1 = Ready

Standby Check SR2

1 = Suspended

WRITE READ Data = FFh

MEMORY

READ Read data from block other

than that being programmed.

WRITE PROGRAM Data = D0h

RESUME

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ADVANCE

YES

Full Status Register

Check (optional)

YES

ERASE

SUSPEND?

SR 7 = 1?

Start

BLOCK ERASE Passed

Range Error

BLOCK ERASE Failed

FULL STATUS REGISTER CHECK FLOW

Read Status Register

Bits ERASE

SUSPEND Loop

YES

SR1 = 0?

YES

BLOCK ERASE

Completed

Read Status Register

Bits

ERASE Attempted

on a Locked Block

SR3 = 0?

SR5 = 0?

Issue ERASE SETUP

Command and

Block Address

Issue BLOCK ERASE

CONFIRM Command

and Block Address

Figure 5

BLOCK ERASE Flowchart

NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

BUS

OPERATION COMMAND COMMENTS

WRITE WRITE Data =20h

ERASE Block Addr = Address

SETUP within block to be erased

WRITE ERASE Data =D0h

Block Addr = Address

within block to be erased

READ Status register data;

toggle OE# or CE# to

update status register.

Standby Check SR7

1 = Ready, 0 = Busy

Repeat for subsequent blocks.

Write FFh after the last BLOCK ERASE operation to

reset the device to read array mode.

BUS

OPERATION COMMAND COMMENTS

Standby Check SR1

1 = Detect locked block

Standby Check SR32

1 = Detect VPP block

Standby Check SR4 and SR5

1 = BLOCK ERASE

command error

Standby Check SR53

1 = BLOCK ERASE error

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ADVANCE

READ

PROGRAM

Issue READ ARRAY

Command PROGRAM

Loop

ERASE

Complete

READ or

PROGRAM?

YES

Issue ERASE

RESUME Command

READ or

PROGRAM

Complete?

YES

SR6 = 1?

Start

ERASE Continued

Read Status Register

Bits

Issue ERASE

SUSPEND Command

(Note 2)

YES

SR7 = 1?

Figure 6

ERASE SUSPEND/ERASE RESUME

Flowchart

NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure.

2. See Word Programming Flowchart for complete programming procedure.

BUS

OPERATION COMMAND COMMENTS

WRITE ERASE Data = B0h

SUSPEND

READ Status register data;

toggle OE# or CE# to

update status register.

Standby Check SR7

1 = Ready

Standby Check SR6

1 = Suspended

WRITE READ Data = FFh

MEMORY

READ Read data from block

other than that being

erased.

WRITE ERASE Data = D0h

RESUME

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ADVANCE

READ-WHILE-WRITE/ERASE

CONCURRENCY

It is possible for the device to read from one bank

while erasing/writing to another bank. Once a bank

enters the WRITE/ERASE operation, the other bank

automatically enters read array mode. For example,

during a READ CONCURRENCY operation, if a PRO-

GRAM/ERASE command is issued in bank a, then bank

a changes to the read status mode and bank b defaults

to the read array mode. The device will read from bank

b if the latched address resides in bank b (see Figure 7).

Similarly, if a PROGRAM/ERASE command is issued in

bank b, then bank b changes to read status mode and

bank a defaults to read array mode. When returning to

bank a, the device will read program/erase status if the

latched address resides in bank a. A correct bank ad-

dress must be specified to read status register after

returning from concurrent read in the other bank.

When reading the CFI area, or the chip protection

ported in Figure 8a and Figure 8b.

Figure 7

READ-While-WRITE Concurrency

Bank a

1 - Erasing/writing to bank a

2 - Erasing in bank a can be

suspended and a WRITE to

another block in bank a

can be initiated.

3 - After the WRITE in that sector

is complete, an ERASE can

be resumed by writing an

ERASE RESUME command.

1 - Reading bank a

Bank b

1 - Reading from bank b

1 - Erasing/writing to bank b

2 - Erasing in bank b can be

suspended and a WRITE to

another block in bank b

can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can

be resumed by writing an

ERASE RESUME command.

Figure 8a

Top Boot Block Device Figure 8b

Bottom Boot Block Device

BANK A BANK B

Reading the READ Not Not

CFI or Chip Supported Supported

Protection WRITE Not Not

BANK A BANK B

Reading the READ Not Supported

CFI or Chip Supported

Protection WRITE Not Supported

BLOCK LOCKING

The Flash memory of the MT28C3214P2FL provides

a flexible locking scheme which allows each block to be

individually locked or unlocked with no latency.

The device offers two-level protection for the blocks.

The first level allows software-only control of block lock-

ing (for data which needs to be changed frequently),

while the second level requires hardware interaction

before locking can be changed (code which does not

require a frequent updates).

Control pins F_WP#, DQ0, and DQ1 define the state

of a block; e.g., state [001] means F_WP# = 0, DQ0 = 0

and DQ1 = 1.

Table 8 defines all of the possible locking states.

NOTE: All blocks are software-locked upon comple-

tion of the power-up sequence.

LOCKED STATE

After a power-up sequence completion, or after a

reset sequence, all blocks are locked (states [001] or

[101]). This means full protection from alteration. Any

PROGRAM or ERASE operations attempted on a locked

block will return an error on bit SR1 of the status regis-

ter. The status of a locked block can be changed to

unlocked or lock down using the appropriate software

commands. Writing the lock command sequence, 60h

followed by 01h, can lock an unlocked block.

UNLOCKED STATE

Unlocked blocks (states [000], [100], [110]) can be

programmed or erased. All unlocked blocks return to

the locked state when the device is reset or powered

down. An unlocked block can be locked or locked down

using the appropriate software command sequence,

60h followed by D0h. (See Table 3.)

LOCKED DOWN STATE

Blocks locked down (state [011]) are protected from

PROGRAM and ERASE operations, but their protection

status cannot be changed using software commands

alone. A locked or unlocked block can be locked down

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ADVANCE

by writing the lock down command sequence, 60h fol-

lowed by 2Fh. Locked down blocks revert to the locked

state when the device is reset or powered down.

The LOCK DOWN function is dependent on the

F_WP# input pin. When F_WP# = 0, blocks in lock down

[011] are protected from program, erase, and lock sta-

tus changes. When F_WP# = 1, the LOCK DOWN func-

tion is disabled ([111]) and locked down blocks can be

individually unlocked by a software command to the

[110] state, where they can be erased and programmed.

These blocks can then be relocked [111] and unlocked

[110], as desired, as long as F_WP# remains HIGH.

When F_WP# goes LOW, blocks that were previously

locked down return to the lock down state [011] regard-

less of any changes made while F_WP# was HIGH. De-

vice reset or power-down resets all locks, including

those in lock down, to the locked state (see Table 8).

READING A BLOCK’S LOCK STATUS

The lock status of every block can be read in the

read device identification mode. To enter this mode,

write 90h to the device. Subsequent READs at block

address +00002 will output the lock status of that block.

The lowest two output pins, DQ0 and DQ1, represent

the lock status. DQ0 indicates the block lock/unlock

status and is set by the LOCK command and cleared by

the UNLOCK command. It is also automatically set

when entering lock down. DQ1 indicates lock down

status and is set by the LOCK DOWN command. It can

only be cleared by reset or power-down, not by soft-

Table 8

Block Locking State Transition

ERASE/PROGRAM LOCK

F_WP# DQ1 DQ0 NAME ALLOWED LOCK UNLOCK DOWN

0 0 0 Unlocked Yes T o [001] – To [011]

0 0 1 Locked (Default) No – To [000] To [011]

0 1 1 Lock Down No – – –

1 0 0 Unlocked Yes To [101] – To [111]

1 0 1 Locked No – To [100] To [111]

1 1 0 Lock Down Yes To [111] – To [111]

Disabled

1 1 1 Lock Down No – To [110] –

Disabled

ITEM ADDRESS DATA

Manufacturer Code (x16) 00000h 002Ch

Device Code 00001h

·Top boot configuration 44A2

·Bottom boot configuration 44A3

Block Lock Configuration2XX002h LOCK

·Block is unlocked DQ0 = 0

·Block is locked DQ0 = 1

·Block is locked down DQ1 = 1

Chip Protection Register Lock 80 PR-LOCK

Chip Protection Register 1 81-84 Factory Data

Chip Protection Register 2 85-88 User Data

NOTE: 1. Other locations within the configuration address space are reserved by

Micron for future use.

2. “XX” specifies the block address of lock configuration.

Table 9

Chip Protection Configuration Addressing1

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ADVANCE

ware. Table 8 shows the block locking state transition

scheme.

LOCKING OPERATIONS DURING ERASE

SUSPEND

Changes to block lock status can be performed dur-

ing an ERASE SUSPEND by using the standard locking

command sequences to unlock, lock, or lock down. This

is useful in the case when another block needs to be

updated while an ERASE operation is in progress.

To change block locking during an ERASE opera-

tion, first write the ERASE SUSPEND command (B0h),

then check the status register until it indicates that the

ERASE operation has been suspended. Next, write the

desired lock command sequence to block lock, and the

lock status will be changed. After completing any de-

sired LOCK, READ, or PROGRAM operations, resume

the ERASE operation with the ERASE RESUME com-

mand (D0h).

If a block is locked or locked down during an ERASE

SUSPEND on the same block, the locking status bits

will be changed immediately. When the ERASE is re-

sumed, the ERASE operation will complete.

A locking operation cannot be performed during a

PROGRAM SUSPEND.

STATUS REGISTER ERROR CHECKING

Using nested locking or program command se-

quences during ERASE SUSPEND can introduce ambi-

guity into status register results.

Following protection configuration setup (60h), an

invalid command will produce a lock command error

(SR4 and SR5 will be set to “1”) in the status register. If

a lock command error occurs during an ERASE SUS-

PEND, SR4 and SR5 will be set to “1” and will remain at

“1” after the ERASE SUSPEND command is issued.

When the ERASE is complete, any possible error during

the ERASE cannot be detected via the status register

because of the previous locking command error.

A similar situation happens if an error occurs during

a program operation error nested within an ERASE

SUSPEND.

CHIP PROTECTION REGISTER

A 128-bit protection register can be used to fullfill

the security considerations in the system (preventing

device substitution).

The 128-bit security area is divided into two 64-bit

segments. The first 64 bits are programmed at the

manufacturing site with a unique 64-bit number. The

other segment is left blank for customers to program as

desired. (See Figure 9).

READING THE CHIP PROTECTION REGISTER

The chip protection register is read in the device

identification mode, loading the 90h command. Once

in this mode, READ cycles from addresses shown in

Table 9 retrieve the specified information. To return to

the read array mode, write the READ ARRAY command

(FFh).

PAGE READ MODE

The initial portion of the page mode cycle is the

same as the asynchronous access cycle. Holding CE#

LOW and toggling addresses A0–A1 allows random ac-

cess of other words in the page.

The page size can be customized at the factory to

four or eight words as required; but if no specification is

made, the normal size is four words.

ASYNCHRONOUS READ CYCLE

When accessing adresses in a random order or when

switching between pages, the access time is given by

tAA.

When F_CE# and F_OE# are LOW, the data is placed

on the data bus and the processor can read the data.

Figure 9

Protection Register Memory Map

4 Words

Factory-Programmed

4 Words

User-Programmed

PR-Lock

88h

85h

84h

81h

80h

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ADVANCE

STANDBY MODE

Icc supply current is reduced by applying a logic

HIGH level on F_CE# and F_RP# to enter the standby

mode. In the standby mode, the outputs are placed in

High-Z. Applying a CMOS logic HIGH level on F_CE#

and F_RP# reduces the current to ICC2 (MAX). If the

device is deselected during an ERASE operation or dur-

ing programming, the device continues to draw cur-

rent until the operation is complete.

AUTOMATIC POWER SAVE MODE (APS)

Substantial power savings are realized during peri-

ods when the Flash array is not being read and the

device is in the active mode. During this time the de-

vice switches to the automatic power save (APS) mode.

When the device switches to this mode, ICC is reduced

to ICC2. The low level of power is maintained until an-

other operation is initiated. In this mode, the I/O pins

retain the data from the last memory address read un-

til a new address is read. This mode is entered auto-

matically if no address or control pins toggle.

VPP / VCC PROGRAM AND ERASE

VOLTAGES

The flash memory of the MT28C3214P2FL provides

in-system programming and erase with VPP in the

0.9V–2.2V range. This device also has a factory option

of in-system programming of F_VPP = 0V; consult fac-

tory for details. VPP at 12V ±5% is supported for a maxi-

mum of 100 cycles and 10 cumulative hours.

The device can withstand 100,000 WRITE/ERASE

operations, with VPP = VCC.

During WRITE and ERASE operations, the WSM

monitors the VPP voltage level. WRITE/ERASE opera-

tions are allowed only when VPP is within the ranges

specified in Table 10.

POWER-UP SEQUENCE

The following power-up sequence must be observed

to properly initialize the device:

• RST# must be at VIL.

• Power on VCC/VCCQ (VCC  VCCQ at all times).

• Wait 2µS after VCC reaches VCC (MIN).

• Take RST# from VIL to VIH.

• The RST# transition from VIL to VIH must be less

than 10µS.

Table 10

VPP RANGE (V)

MIN MAX

In-System 0 2.2

In-Factory 11.4 12.6

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ADVANCE

ABSOLUTE MAXIMUM RATINGS*

Voltage to Any Pin Except VCC and VPP

with Respect to VSS ....................... -0.5V to +2.45V

VPP Voltage (for BLOCK ERASE and PROGRAM

with Respect to VSS) ................. -0.5V to +13.5V**

VCC and VCCQ Supply Voltage

with Respect to VSS ....................... -0.3V to +2.45V

Output Short Circuit Current...............................100mA

Operating Temperature Range ..............-40oC to +85oC

Storage Temperature Range.................-55oC to +125oC

Soldering Cycle ........................................... 260oC for 10s

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

**Maximum DC voltage on VPP may overshoot to +13.5V

for periods <20ns.

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN MAX UNITS NOTES

Operating temperature tA -40 +85 oC

VCC supply voltage F_VCC, S_VCC 1.65 2.2 V

I/O supply voltage (VCC = 1.65V–2.2V) VCCQ 1.65 2.2 V

Supply voltage, when used as logic control VPP10.9 2.2 V

VPP in-factory programming voltage VPP211.4 12.6 V 1

Data retention supply voltage S_VDR 1.0 – V

Block erase cycling 100,000 – Cycles

Figure 10

Output Load Circuit

I/O 14.5K

30pF

14.5K

FLASH ELECTRICAL SPECIFICATIONS

NOTE: 1. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

FLASH

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ADVANCE

COMBINED DC CHARACTERISTICS

(Note: 1)

VCC = 1.65V–2.2V

VCCQ = 1.65V–2.2V

DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES

Input Low Voltage VIL -0.4 – 0.4 V

Input High Voltage VIH VCCQ - – VCCQ + V

0.4V 0.3V

Output Low Voltage VOL – – 0.10 V

IOL = 100µA

Output High Voltage VOH VCCQ - – – V

IOH = 100µA 0.1V

VPP Lock Out Voltage VPPLK – – 0.4 V

VPP During Program/Erase VPP10.9 – 2.2 V

Operations VPP211.4 – 12.6 V 2

VCC Program/Erase Lock Voltage VLKO 1.0 – – V

Input Leakage Current IL––1mA

Output Leakage Current IOZ ––1mA

F_VCC Asynchronous ICC1––15mA

Read Current at 95ns

F_VCC Page Mode ICC2––5mA

Read Current at 35ns

F_VCC plus S_VCC Standby Current ICC3–2570mA

F_VCC Program Current ICC4+IPP3––55mA

F_VCC Erase Current ICC5+IPP4––65mA

F_V

/S_V

Erase Suspend Current

ICC6––60mA

F_V

/S_V

Program Suspend ICC7––60mA

Current

Read-While-Write Current ICC8––95mA

S_VCC Read/Write Operating VIN = VIH or VIL ICC9–1225mA3

Supply Current – Page Access Chip Enabled, IOL = 0

Mode

S_VCC Read/Write Operating VIN = VIH or VIL ICC10 –38mA3

Supply Current – Word Access Chip Enabled, IOL = 0

Mode

NOTE: 1. All currents are in RMS unless otherwise noted.

2. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

3. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using

the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts.

Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page

access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must

add current required to drive output capacitance expected in the actual system.

(continued on the next page)

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ADVANCE

COMBINED DC CHARACTERISTICS (continued)

(Note: 1)

VCC = 1.65V–2.2V

VCCQ = 1.65V–2.2V

DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES

VPP Read Current VPP ≤ VCC IPP1––1mA

VPP ³ VCC – – 200 mA

VPP Standby Current VPP ≤ VCC IPP2––1mA

VPP ³ VCC – – 200 mA

VPP Erase Suspend Current VPP = VPP1IPP5––1mA

VPP = VPP2– – 200 mA

VPP Program Suspend Current VPP = VPP1IPP6––1mA

VPP = VPP2– – 200 mA

NOTE: 1. All currents are in RMS unless otherwise noted.

2. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

3. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using

the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts.

Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page

access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must

add current required to drive output capacitance expected in the actual system.

FLASH

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ADVANCE

FLASH WRITE CYCLE TIMING REQUIREMENTS

-95/-11

VCC = 1.65V–2.2V

PARAMETER SYMBOL MIN MAX UNITS

Reset HIGH recovery to WE# going LOW tRS 150 ns

CE# setup to WE# going LOW tCS 0 ns

Write pulse width tWP 70 ns

Data setup to WE# going HIGH tDS 70 ns

Address setup to WE# going HIGH tAS 70 ns

CE# hold from WE# HIGH tCH 0 ns

Data hold from WE# HIGH tDH 0 ns

Address hold from WE# HIGH tAH 9 ns

Write pulse width HIGH tWPH 30 ns

WP# setup to WE# going HIGH tRHS 200 ns

VPP setup to WE# going HIGH tVPS 200 ns

Write recovery before READ tWOS 50 ns

WP# hold from valid SRD tRHH 0 ns

VPP hold from valid SRD tVPH 0 ns

WE# HIGH to data valid tWB tAA+50 ns

FLASH READ CYCLE TIMING REQUIREMENTS1

-95 -11

VCC = 1.65V–2.2V VCC = 1.65V–2.2V

PARAMETER SYMBOL MIN MAX MIN MAX UNITS

Address to output delay tAA 95 110 ns

CE# LOW to output delay tACE 95 110 ns

Page address access tAPA 35 45 ns

OE# LOW to output delay tAOE 30 30 ns

F_RP# HIGH to output delay tRWH 150 150 ns

CE# or OE# HIGH to output High-Z tOD 25 25 ns

Output hold from address, CE# or OE# change tOH 0 0 ns

CE# HIGH between subsequent synchronous READs tCBPH 20 20 ns

READ Cycle Time tRC 100 110 ns

FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS

-95/-11

VCC = 1.65V–2.2V

PARAMETER TYP MAX UNITS

4KW parameter block program time 0.1 0.3 s

32KW parameter block program time 0.8 2.4 s

Word program time 8 185 µs

4KW parameter block erase time 1 4 s

32KW parameter block erase time 1.5 5 s

Program suspend latency 510µs

Erase suspend latency 520µs

FLASH

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ADVANCE

TWO-CYCLE PROGRAMMING/ERASE OPERATION

VALID ADDRESS VALID ADDRESS VALID ADDRESS

UNDEFINED

RHS

A0-A20

OE#

CE#

WE#

RP#

WP#

IPPLK

IPPH

WPH

WOS

CMD CMD/

DATA

DQ0-DQ15

RHH

VPS

VPPH

STATUS

High-Z

NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle.

-95/-11

VCC = 1.65V–2.2V

SYMBOL MIN MAX UNITS

WRITE TIMING PARAMETERS

-95/-11

VCC = 1.65V–2.2V

SYMBOL MIN MAX UNITS

tRS 150 ns

tCS 0 ns

tWP 70 ns

tDS 70 ns

tAS 70 ns

tCH 0 ns

tDH 0 ns

tAH 9 ns

tRHS 200 ns

tVPS 200 ns

tWOS 50 ns

tRHH 0 ns

tVPH 0 ns

tWB tAA+50 ns

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

SINGLE ASYNCHRONOUS READ OPERATION

READ TIMING PARAMETERS

-95 -11

VCC = 1.65V–2.2V VCC = 1.65V–2.2V

SYMBOL MIN MAX MIN MAX UNITS

tAA 95 110 ns

tACE 95 110 ns

tAOE 30 30 ns

tRWH 150 150 ns

VALID ADDRESS

UNDEFINED

ACE

A0-A20

OE#

CE#

WE#

RWH

DQ0-DQ15

RP#

VALID OUTPUT

High-Z

AOE

tOD 25 25 ns

tOH 0 0 ns

tRC 100 110 ns

-95 -11

VCC = 1.65V–2.2V VCC = 1.65V–2.2V

SYMBOL MIN MAX MIN MAX UNITS

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

ASYNCHRONOUS PAGE MODE READ OPERATION

VALID ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

UNDEFINED

ACE

APA

AOE

A0-A1

F_OE#

F_CE#

F_WE#

VALID ADDRESS

A2-A20 V

RMH

DQ0-DQ15

F_RP #

High-Z

READ TIMING PARAMETERS

-95 -11

VCC = 1.65V–2.2V VCC = 1.65V–2.2V

SYMBOL MIN MAX MIN MAX UNITS

tAA 95 110 ns

tACE 95 110 ns

tAPA 35 45 ns

tAOE 30 30 ns

tRWH 150 150 ns

tOD 25 25 ns

tOH 0 0 ns

-95 -11

VCC = 1.65V–2.2V VCC = 1.65V–2.2V

SYMBOL MIN MAX MIN MAX UNITS

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Table 13

CFI

OFFSET DATA DESCRIPTION

00 2Ch Manufacturer Code

01 A2h Top Boot Block Device Code

A3h Bottom Boot Block Device Code

02–0F reserved Reserved

10, 11 0051,0052 “QR”

12 0059 “Y”

13, 14 0003, 0000 Primary OEM Command Set

15, 16 0040, 0000 Address for Primary Extended Table

17, 18 0000, 0000 Alternate OEM Command Set

19, 1A 0000, 0000 Address for OEM Extended Table

1B 0016 VCC MIN for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

1C 0022 VCC MAX for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

1D 0009 VPP MIN for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD

1E 0022 VPP MAX for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD

1F 0003 Typical timeout for single byte/word program, 2n us, 0000 = not supported

20 0000 Typical timeout for maximum size multiple byte/word program, 2n us, 0000 = not

supported

21 0009 Typical timeout for individual block erase, 2n ms, 0000 = not supported

22 0000 Typical timeout for full chip erase, 2n ms, 0000 = not supported

23 000C Maximum timeout for single byte/word program, 2n us, 0000 = not supported

24 0000 Maximum timeout for maximum size multiple byte/word program, 2n us, 0000 = not

supported

25 000C Maximum timeout for individual block erase, 2n ms, 0000 = not supported

26 0000 Maximum timeout for full chip erase, 2n ms, 0000 = not supported

27 0016 Device size, 2n bytes

28 0001 Bus Interface x8 = 0, x16 = 1, x8/x16 = 2

29 0000 Flash device interface description 0000 = async

2A, 2B 0000, 0000 Maximum number of bytes in multi-byte program or page, 2n

2C 0003 Number of erase block regions within device (4K words and 32K words)

2D, 2E 0007, 0000 Erase block region information 1, 8 blocks …

2F, 30 0020, 0000 …..of 8KB

31, 32 0007, 0000 7 blocks of ….

33, 34 0000, 0001 ……64KB

35, 36 3800, 0000 56 blocks of

37, 38 0000, 0001 ……64KB

39, 3A 0050, 0052 “PR”

3B 0049 “I”

3C 0030 Major version number, ASCII

(continued on the next page)

FLASH

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

Table 13

CFI (continued)

OFFSET DATA DESCRIPTION

3D 0031 Minor Version Number, ASCII

3E 00E6 Optional Feature and Command Support

3 F 0003 Bit 0 Chip erase supported no = 0

40 0000 Bit 1 Suspend erase supported = yes = 1

41 0000 Bit 2 Suspend program supported = yes = 1

Bit 3 Chip lock/unlock supported = no = 0

Bit 4 Queued erase supported = no = 0

Bit 5 Instant individual block locking supported = yes = 1

Bit 6 Protection bits supported = yes = 1

Bit 7 Page mode read supported = yes = 1

Bit 8 Synchronous read supported = yes = 1

Bit 9 Simultaneous operation supported = yes = 1

42 0001 Program supported after erase suspend = yes

43, 44 0003,0000 Bit 0 Block Lock Status active = yes; Bit 1 Block Lock Down active = yes

45 0018 VCC supply optimum; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

46 0018 VPP supply optimum; Bit7–Bit4 Volts in Hex ; Bit3–Bit0 100mV in BCD

47 0001 Number of protection register fileds in JEDEC ID space

48, 49 0080,0000 Lock bytes low address, lock bytes high address

4A, 4B 0003,0003 2n factory programmed bytes, 2n user programmable bytes

4C 0002 Background Operation

0000 = Not used

0001 = 4% block split

0002 = 12% block split

0003 = 25% block split

0004 = 50% block split

4D 0000 Burst Mode Type

0000 = No burst mode

00x1 = 4 words max

00x2 = 8 words max

00x3 = 16 words max

001x = Linear burst, and/or

002x = Interleaved burst, and/or

004x = Continuous burst

4E 0001 Page Mode Type

0000 = No page mode

0001 = 4-word page

0002 = 8-word page

0003 = 16-word page

0004 = 32-word page

4F 0004 SRAM density, 4Mb (256K x 16)

SRAM

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

SRAM OPERATING MODES

SRAM READ ARRAY

The operational state of the SRAM is determined by

S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as

indicated in the Truth Table. In order to perform an

SRAM READ operation, S_CE1#, and S_OE#, must be at

VIL, and S_CE2 and S_WE# must be at VIH. When in this

state, S_UB# and S_LB# control whether the lower byte

is read (S_UB# VIH, S_LB# VIL), the upper byte is read

(S_UB# VIL, S_LB# VIH), both upper and lower bytes are

read (S_UB# VIL, S_LB# VIL), or neither are read (S_UB#

VIH, S_LB# VIH) and the device is in a standby state.

While performing an SRAM READ operation, cur-

rent consumption may be reduced by reading within a

16-word page. This is done by holding S_CE1# and

SRAM FUNCTIONAL BLOCK DIAGRAM

DQ0–DQ7

WORD

ADDRESS

DECODE

LOGIC

PAGE

ADDRESS

DECODE

LOGIC

CONTROL

LOGIC

16K-PAGE

x16 WORD

x16 BIT

RAM ARRAY

WORD

MUX DQ8–DQ15

INPUT/

OUTPUT

MUX

AND

BUFFERS

S_CE1#

A4–A17

A0–A3

S_OE#

S_UB#

S_LB#

S_CE2

S_WE#

S_OE# at VIL, S_WE# and S_CE2 at VIH, and toggling

addresses A0-A3. S_UB# and S_LB# control the data

width as described above.

SRAM WRITE ARRAY

In order to perform an SRAM WRITE operation,

S_CE1# and S_WE# must be at VIL, and S_CE2 and

S_OE# must be at VIH. When in this state, S_UB# and

S_LB# control whether the lower byte is written (S_UB#

VIH, S_LB# VIL), the upper byte is written (S_UB# VIL,

S_LB# VIH), both upper and lower bytes are written

(S_UB# VIL, S_LB# VIL), or neither are written (S_UB#

VIH, S_LB# VIH) and the device is in a standby state.

SRAM

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

TIMING TEST CONDITIONS

Input pulse levels .................... 0.1V VCC to 0.9V VCC

Input rise and fall times .................................... 5 ns

Input timing reference levels ......................... 0.5V

Output timing reference levels ..................... 0.5V

Operating Temperature ............... -40oC to +85oC

SRAM READ CYCLE TIMING

DESCRIPTION SYMBOL MIN MAX UNITS

Read Cycle Time tRC 85 ns

Address Access Time tAA 85 ns

Chip Enable to Valid Output tCO 85 ns

Output Enable to Valid Output tOE 35 ns

Byte Select to Valid Output tLB, tUB 85 ns

Chip Enable to Low-Z Output tLZ 0 ns

Output Enable to Low-Z Output tOLZ 0 ns

Byte Select to Low-Z Output tLBZ, tUBZ 0 ns

Chip Enable to High-Z Output tHZ 0 15 ns

Output Disable to High-Z Output tOHZ 0 15 ns

Byte Select Disable to High-Z Output tLBHZ, tUBHZ 0 15 ns

Output Hold from Address Change tOH 5 ns

SRAM WRITE CYCLE TIMING

DESCRIPTION SYMBOL MIN MAX UNITS

Write Cycle Time tWC 85 ns

Chip Enable to End of Write tCW 85 ns

Address Valid to End of Write tAW 85 ns

Byte Select to End of Write tLBW, tUBW 85 ns

Address Setup Time tAS 0 ns

Write Pulse Width tWP 50 ns

Write Recovery Time tWR 0 ns

Write to High-Z Output tWHZ 0 15 ns

Data to Write Time Overlap tDW 50 ns

Data Hold from Write Time tDH 0 ns

End Write to Low-Z Output tOW 0 ns

SRAM

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

tOLZ 0 ns

tHZ 0 15 ns

tOHZ 0 15 ns

tLBHZ, tUBHZ 0 15 ns

tOH 5 ns

DON’T CARE

ADDRESS

S_CE1#

S_CE2

S_OE#

S_LB#, S_UB#

DATA OUT

tRC

tAA tHZ (1, 2)

tCO

tLBLZ, tUBLZ tLBHZ, tUBHZ

DATA VALID

High-Z

tOE

tLZ(2)

tOLZ

tOHZ (1)

tLB, tUB

SYMBOL MIN MAX UNITS

READ CYCLE 1

(S_CE1# = S_OE# = VIL; S_CE2, S_WE# = VIH)

ADDRESS

DATA OUT

tRC

tAA

tOH

DATA VALID DATA VALID

READ CYCLE 2

(S_WE# = VIH)

READ TIMING PARAMETERS

SYMBOL MIN MAX UNITS

tRC 85 ns

tAA 85 ns

tCO 85 ns

tOE 35 ns

tLB, tUB 85 ns

tLZ 0 ns

SRAM

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

WRITE CYCLE

(S_WE# CONTROL)

DON’T CARE

ADDRESS

S_CE1#

S_CE2

DATA OUT

tWC

tAW tWR

tCW

tWHZ tOW

High-Z

S_LB#, S_UB#

tLBW, tUBW

S_WE#

DATA IN

tAS tWP

tDH

tDW

DATA VALID

High-Z

tWR 0 ns

tWHZ 0 15 ns

tDW 50 ns

tDH 0 ns

tOW 0 ns

SYMBOL MIN MAX UNITS

WRITE TIMING PARAMETERS

SYMBOL MIN MAX UNITS

tWC 85 ns

tCW 85 ns

tAW 85 ns

tLBW, tUBW 85 ns

tAS 0 ns

tWP 50 ns

SRAM

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

tWR 0 ns

tWHZ 0 15 ns

tDW 50 ns

tDH 0 ns

tOW 0 ns

WRITE CYCLE 2

(S_CE1# CONTROL)

DON’T CARE

ADDRESS

S_CE1#

DATA OUT

tWC

tAW tWR

tCW

tWHZ

tLZ

High-Z

S_LB#, S_UB#

S_WE#

DATA IN

tAS

tWP

tLBW, tUBW

tDH

tDW

DATA VALID

SYMBOL MIN MAX UNITS

WRITE TIMING PARAMETERS

SYMBOL MIN MAX UNITS

tWC 85 ns

tCW 85 ns

tAW 85 ns

tLBW, tUBW 85 ns

tAS 0 ns

tWP 50 ns

2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 MEG x 16 PAGE FLASH

256K x 16 SRAM COMBO MEMORY

ADVANCE

66-BALL FBGA

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag

SOLDER BALL PAD: Ø .27mm

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

1.40 MAX

0.80

(TYP)

8.800.80

(TYP)

0.40

8.00±0.10

0.40

12.0 ±0.10

4.40

±0.05 6.00

±0.05

+0.05

-0.10

66X Ø

0.35 BALL A12 BALL A1

BALL A1

PIN #1 ID

5.60

2.80±0.05

0.1

1.05±.075

SEATING PLANE

NOTE: 1. All dimensions in millimeters MAX or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.