1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8-lead PDIP
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8-lead SOIC
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOL
D
SCK
SI
8-lead TSSOP
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
8-lead Ultra Thin SAP
VCC
HOLD
SCK
S
I
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-ball dBGA2
Bottom View
Bottom View
Features
•Serial Peripheral Interface (SPI) Compatible
•Supports SPI Modes 0 (0,0) and 3 (1,1)
•Data Sheet Describes Mode 0 Operation
•Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
•20 MHz Clock Rate (5V)
•64-byte Page Mode and Byte Write Operation
•Block Write Protection
– Protect 1/4, 1/2, or Entire Array
•Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
•Self-timed Write Cycle (5 ms Max)
•High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
•8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-
lead Ultra Thin SAP Packages
•Lead-free/Halogen-free
•Available in Automotive
•Die Sales: Wafer Form, Waffle Pack, and Bumped Die
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro-
grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is available in
2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
3368J–SEEPR–06/07
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128A
AT25256A
Not
Recommended
for New Design
2
3368J–SEEPR–06/07
AT25128A_256A
Block Write protection is enabled by programming the status register with top ¼, top ½ or entire
array of write protection. Separate Program Enable and Program Disable instructions are pro-
vided for additional data protection. Hardware data protection is provided via the WP pin to
protect against inadvertent write attempts to the status register. The HOLD pin may be used to
suspend any serial communication without resetting the serial sequence.
Table 0-1. Pin Configurations
Pin Name Function
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP Write Protect
HOLD Suspends Serial Input
NC No Connect
1. Absolute Maximum Ratings*
Operating Temperature 55C to +125C*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature 65C to +150C
Voltage on Any Pin
with Respect to Ground 1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
3368J–SEEPR–06/07
AT25128A_256A
Figure 1-1. Block Diagram
Note: 1. This parameter is characterized and is not 100% tested.
16384/32768 x 8
Table 1-1. Pin Capacitance(1)
Applicable over recommended operating range from TA=25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT =0V
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN =0V
4
3368J–SEEPR–06/07
AT25128A_256A
Note: 1. VIL min and VIH max are reference only and are not tested.
Table 1-2. DC Characteristics
Applicable over recommended operating range from TAI =40°C to +85°C, VCC = +1.8V to +5.5V,
TAE =40C to +125C, VCC = +1.8V to +5.5V(unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V at 20 MHz, SO = Open,
Read 9.0 10.0 mA
ICC2 Supply Current VCC = 5.0V at 10 MHz,
SO = Open, Read, Write 5.0 7.0 mA
ICC3 Supply Current VCC = 5.0V at 1 MHz,
SO = Open, Read, Write 2.2 3.5 mA
ISB1 Standby Current VCC = 1.8V, CS = VCC 0.2 3.0 µA
ISB2 Standby Current VCC = 2.7V, CS = VCC 0.5 3.0 µA
ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 5.0 µA
IIL Input Leakage VIN =0VtoV
CC 3.0 3.0 µA
IOL Output Leakage VIN =0VtoV
CC,T
AC =0Cto70C3.0 3.0 µA
VIL
(1) Input Low-voltage 1.0 VCC x 0.3 V
VIH
(1) Input High-voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low-voltage 3.6 VCC 5.5V IOL = 3.0 mA 0.4 V
VOH1 Output High-voltage IOH =1.6 mA VCC 0.8 V
VOL2 Output Low-voltage 1.8V VCC 3.6V IOL = 0.15 mA 0.2 V
VOH2 Output High-voltage IOH =100 µA VCC 0.2 V
5
3368J–SEEPR–06/07
AT25128A_256A
Table 1-3. AC Characteristics
Applicable over recommended operating range from TAI =40Cto+85C, TAE =40C to +125C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
fSCK SCK Clock Frequency
4.55.5
2.75.5
1.85.5
0
0
0
20
10
5
MHz
tRI Input Rise Time
4.55.5
2.75.5
1.85.5
2
2
2
µs
tFI Input Fall Time
4.55.5
2.75.5
1.85.5
2
2
2
µs
tWH SCK High Time
4.55.5
2.75.5
1.85.5
20
40
80
ns
tWL SCK Low Time
4.55.5
2.75.5
1.85.5
20
40
80
ns
tCS CS High Time
4.55.5
2.75.5
1.85.5
100
100
200
ns
tCSS CS Setup Time
4.55.5
2.75.5
1.85.5
100
100
200
ns
tCSH CS Hold Time
4.55.5
2.75.5
1.85.5
100
100
200
ns
tSU Data In Setup Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tHData In Hold Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tHD Hold Setup Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tCD Hold Hold Time
4.55.5
2.75.5
1.85.5
5
10
20
ns
tVOutput Valid
4.55.5
2.75.5
1.85.5
0
0
0
20
40
80
ns
tHO Output Hold Time
4.55.5
2.75.5
1.85.5
0
0
0
ns
tLZ Hold to Output Low Z
4.55.5
2.75.5
1.85.5
0
0
0
25
50
100
ns
6
3368J–SEEPR–06/07
AT25128A_256A
Notes: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
tHZ Hold to Output High Z
4.55.5
2.75.5
1.85.5
25
50
100
ns
tDIS Output Disable Time
4.55.5
2.75.5
1.85.5
25
50
100
ns
tWC Write Cycle Time
4.55.5
2.75.5
1.85.5
5
5
5
ms
Endurance(1) 5.0V, 25C, Page Mode 1M Write Cycles
Table 1-3. AC Characteristics (Continued)
Applicable over recommended operating range from TAI =40Cto+85C, TAE =40C to +125C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
7
3368J–SEEPR–06/07
AT25128A_256A
2. Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128A/256A always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128A/256A, and the serial output pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25128A/256A is selected when the CS pin is low. When the device is not
selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a
high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128A/256A.
When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communi-
cation, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held
high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status reg-
ister are inhibited. WP going low while CS is still low will interrupt a write to the status register. If
the internal write cycle has already been initiated, WP going low will have no effect on any write
operation to the status register. The WP pin function is blocked when the WPEN bit in the status
register is “0”. This will allow the user to install the AT25128A/256A in a system with the WP pin
tied to ground and still be able to write to the status register. All WP pin functions are enabled
when the WPEN bit is set to “1”.
8
3368J–SEEPR–06/07
AT25128A_256A
Figure 2-1. SPI Serial Interface
AT25128A/256A
9
3368J–SEEPR–06/07
AT25128A_256A
3. Functional Description
The AT25128A/256A is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6800 type series of microcontrollers.
The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and their opera-
tion codes are contained in see Table 4-3. All instructions, addresses, and data are transferred
with the MSB first and start with a high-to-low CS transition.
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The Ready/Busy and Write Enable status of the device can be determined by
the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruction.
Table 3-1. Instruction Set for the AT25128A/256A
Instruction Name Instruction Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Register
READ 0000 X011 Read Data from Memory Array
WRITE 0000 X010 Write Data to Memory Array
Table 3-2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Table 3-3. Read Status Register Bit Definition
Bit Definition
Bit0(RDY) Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN) Bit1=0indicates the device is not write enabled. Bit 1 = “1” indicates
the device is write enabled.
Bit 2 (BP0) See Table 3-4 on page 10.
Bit 3 (BP1) See Table 3-4 on page 10.
Bits 4 6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 3-5 on page 10.
Bits 0 7 are “1”s during an internal write cycle.
10
3368J–SEEPR–06/07
AT25128A_256A
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25128A/256A is divided into four array segments. Top quarter
(1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any
selected segment will therefore be read only. The block write protection levels and correspond-
ing status register control bits are shown in Table 3-4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g. WREN, tWC, RDSR).
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-
protected sections in the memory array are disabled. Writes are only allowed to sections of the
memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
READ SEQUENCE (READ): Reading the AT25128A/256A via the SO pin requires the follow-
ing sequence. After the CS line is pulled low to select a device, the Read op-code is transmitted
via the SI line followed by the byte address to be read (see Table 3-6 on page 11). Upon com-
pletion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is
then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high
after the data comes out. The read sequence can be continued since the byte address is auto-
matically incremented and data will continue to be shifted out. When the highest address is
Table 3-4. Block Write Protect Bits
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25128A AT25256A
0 0 0 None None
1(1/4) 0 1 3000 – 3FFF 6000 – 7FFF
2(1/2) 1 0 2000 – 3FFF 4000 – 7FFF
3(All) 1 1 0000 – 3FFF 0000 – 7FFF
Table 3-5. WPEN Operation
WPEN WP WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
11
3368J–SEEPR–06/07
AT25128A_256A
reached, the address counter will roll over to the lowest address allowing the entire memory to
be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25128A/256A, two separate instruc-
tions must be executed. First, the device must be write enabled via the Write Enable (WREN)
Instruction. Then a Write instruction may be executed. Also, the address of the memory loca-
tion(s) to be programmed must be outside the protected address field location selected by the
Block Write Protection Level. During an internal write cycle, all commands will be ignored except
the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to select the
device, the Write op-code is transmitted via the SI line followed by the byte address and the data
(D7 - D0) to be programmed (see Table 3-6). Programming will start after the CS pin is brought
high. (The Low-to-High transition of the CS pin must occur during the SCK low time immediately
after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register
(RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has
ended. Only the Read Status Register instruction is enabled during the Write programming
cycle.
The AT25128A/256A is capable of a 64-byte Page Write operation. After each byte of data is
received, the six low order address bits are internally incremented by one; the high order bits of
the address will remain constant. If more than 64 bytes of data are transmitted, the address
counter will roll over and the previously written data will be overwritten. The AT25128A/256A is
automatically returned to the write disable state at the completion of a Write cycle.
NOTE: If the device is not write enabled (WREN), the device will ignore the Write instruction
and will return to the standby state, when CS is brought high. A new CS falling edge is required
to re-initiate the serial communication.
Table 3-6. Address Key
Address AT25128A AT25256A
ANA13 A0A14 A0
Don’t Care Bits A15 A14 A15
12
3368J–SEEPR–06/07
AT25128A_256A
4. Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 4-1. Synchronous Data Timing
Figure 4-2. WREN Timing
SO
V
OH
V
OL
HI-Z HI-Z
t
V
VALID IN
SI
V
IH
V
IL
t
H
t
SU
t
DIS
SCK
V
IH
V
IL
t
WH
t
CSH
CS
V
IH
V
IL
t
CSS
t
CS
t
WL
tHO
13
3368J–SEEPR–06/07
AT25128A_256A
Figure 4-3. WRDI Timing
Figure 4-4. RDSR Timing
Figure 4-5. WRSR Timing
CS
SCK
01234567891011121314
SI INSTRUCTION
SO
76543210
DATA OUT
MSB
HIGH IMPEDANCE
15
14
3368J–SEEPR–06/07
AT25128A_256A
Figure 4-6. READ Timing
Figure 4-7. WRITE Timing
Figure 4-8. HOLD Timing
SO
SCK
HOLD
t
CD
t
HD
t
HZ
t
LZ
t
CD
t
HD
CS
15
3368J–SEEPR–06/07
AT25128A_256A
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
2. “U” designates Green package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL788 for wafer form. Bumped die available upon request. Please Contact
Serial Interface Marketing.
5. AT25128A Ordering Information(1)
Ordering Code Package Operation Range
AT25128A-10PU-2.7(2)
AT25128A-10PU-1.8(2)
AT25128AN-10SU-2.7(2)
AT25128AN-10SU-1.8(2)
AT25128AW-10SU-2.7(2)
AT25128AW-10SU-1.8(2)
AT25128A-10TU-2.7(2)
AT25128A-10TU-1.8(2)
AT25128AU2-10UU-1.8(2)
AT25128AY7-10YH-1.8(2)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U2-1
8Y7
Lead-free/Halogen-free/
Industrial Temperature
(40Cto85C)
AT25128A-W1.8-11(3) Die Sale Industrial Temperature
(40Cto85C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U2-1 8-ball, die Ball Grid Array Package (dBGA2)
8A2 8-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP)
8Y7 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
2.7 Low-voltage (2.7V to 5.5V)
1.8 Low-voltage (1.8V to 5.5V)
16
3368J–SEEPR–06/07
AT25128A_256A
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
2. “U” designates Green package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL788 for wafer form. Bumped die available upon request. Please contact
Serial Interface Marketing.
AT25256A Ordering Information(1)
Ordering Code Package Operation Range
AT25256A-10PU-2.7(2)
AT25256A-10PU-1.8(2)
AT25256AN-10SU-2.7(2)
AT25256AN-10SU-1.8(2)
AT25256AW-10SU-2.7(2)
AT25256AW-10SU-1.8(2)
AT25256A-10TU-2.7(2)
AT25256A-10TU-1.8(2)
AT25256AU2-10UU-1.8(2)
AT25256AY7-10YH-1.8(2)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U2-1
8Y7
Lead-free/Halogen-free/
Industrial Temperature
(40Cto85C)
AT25256A-W1.8-11(3) Die Sale Industrial Temperature
(40Cto85C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U2-1 8-ball, die Ball Grid Array Package (dBGA2)
8A2 8-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP)
8Y7 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
2.7 Low-voltage (2.7V to 5.5V)
1.8 Low-voltage (1.8V to 5.5V)
17
3368J–SEEPR–06/07
AT25128A_256A
6. Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
A
–
–
0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005
–
–
3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
Top View
Side View
End View
18
3368J–SEEPR–06/07
AT25128A_256A
8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
3/17/05
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
θ 0˚ – 8˚
Ø
Ø
E
E
1
1
N
N
TOP VIEW
TOP VIEW
C
C
E1
E1
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
SIDE VIEW
19
3368J–SEEPR–06/07
AT25128A_256A
8S2 – EIAJ SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
10/7/03
8S2 C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
∅
0° 8°
e 1.27 BSC 4
End View
Side View
eb
A
A1
D
E
N
1
C
E1
∅
L
Top View
20
3368J–SEEPR–06/07
AT25128A_256A
8U2-1 – dBGA2
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
PO8U2-1
A
6/24/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
A 0.81 0.91 1.00
A1 0.15 0.20 0.25
A2 0.40 0.45 0.50
b 0.25 0.30 0.35 1
D 2.35 BSC
E 3.73 BSC
e 0.75 BSC
e1 0.74 REF
d 0.75 BSC
d1 0.80 REF
1. Dimension 'b' is measured at the maximum solder ball diameter.
This drawing is for general information only.
d
A
Side View
Top View
Bottom View
8 Solder Balls
1
A
B
C
D
2
(e1)
e
A1 BALL PAD CORNER
(d1)
1. b
A1
A2
D
A1 BALL PAD CORNER
E
21
3368J–SEEPR–06/07
AT25128A_256A
8A2 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
22
3368J–SEEPR–06/07
AT25128A_256A
8Y7 – UTSAP
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array
Package (UTSAP) Y7 B
8Y7
10/13/05
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN NOM MAX NOTE
A – – 0.60
A1 0.00 – 0.05
D 5.80 6.00 6.20
E 4.70 4.90 5.10
D1 3.30 3.40 3.50
E1 3.90 4.00 4.10
b 0.35 0.40 0.45
e 1.27 TYP
e1 3.81 REF
L 0.50 0.60 0.70
D1
PIN 1 ID
E1
L
b
e1
e
PIN 1 INDEX AREA
A
E
D
A1
A
23
3368J–SEEPR–06/07
AT25128A_256A
Revision History
Doc. Rev. Date Comments
3368J 6/2007 Changed 8Y4 to 8Y7 package
3368I 3/2007 Revision history implemented
Removed Pb product offering
3368J–SEEPR–06/07
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