GS76024AB
256K x 24
6Mb Asynchronous SRAM
8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
BGA
Commercial Temp
Industrial Temp
Rev: 1.02a 4/2011 1/12 © 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• Fast access time: 8, 10, 12 ns
• CMOS low power operation: 260/210/180 mA at minimum
cycle time
• Single 3.3 V ± 0.3V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40 to 85°C
• Package
B: 14 mm x 22 mm, 119-bump, 1.27 mm pitch BGA
GB: RoHS-compliant 119-bump BGA available
Description
The GS76024A is a high speed CMOS static RAM organized
as 262,144 words by 24 bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single
3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS76024A is available in a 119-bump BGA
package.
119-bump Ball Grid Array Package
Pin Descriptions
Symbol Description Symbol Description
A0 to A17 Address input DQ1 to DQ24 Data input/output
WE Write enable input OE Output enable input
CE Chip enable input
VDD +3.3V power supply VSS Ground
CE
WE
OE
Memory Array
Row
Decoder
Column
Decoder
Address
Input
Control I/O Buffer
A0
DQ1DQ24
A17
Block Diagram
1234567
ANCA
3A2A16 A1A0NC
BNCA
7A6CE A5A4NC
CDQ
13 NC VDD,
NC A17 VSS,
NC NC DQ12
DDQ14 VDD VSS VSS VSS VDD DQ11
EDQ15 NC VDD VSS VDD NC DQ10
FDQ16 VDD VSS VSS VSS VDD DQ9
GDQ17 NC VDD VSS VDD NC DQ8
HDQ18 VDD VSS VSS VSS VDD DQ7
JVDD VSS VDD VSS VDD VSS VDD
KDQ19 VDD VSS VSS VSS VDD DQ6
LDQ20 NC VDD VSS VDD NC DQ5
MDQ21 VDD VSS VSS VSS VDD DQ4
NDQ22 NC VDD VSS VDD NC DQ3
PDQ23 VDD VSS VSS VSS VDD DQ2
RDQ24 NC NC NC NC NC DQ1
TNCA11 A10 WE A9A8NC
UNCA
15 A14 OE A13 A12 NC
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 2/12 © 2003, GSI Technology
119-bump, 1.27 mm Pitch BGA Pad Out—Top View (Package B)
Note:
Bumps 3C and 5C are actually NCs but should be wired C3 = VDD and C5 = VSS to assure compatibility with future versions.
Truth Table
CE OE WE Mode DQ0 to DQ23 VDD Current
H X X Not selected High Z ISB1, ISB2
L L H Read Data Out
IDD
L X L Write Data In
L H H Output disable High Z
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 3/12 © 2003, GSI Technology
Note:
X: “H” or “L”
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply Voltage VDD –0.5 to +4.6 V
Input Voltage VIN
–0.5 to VDD +0.5
(≤ 4.6 V max.) V
Output Voltage VOUT
–0.5 to VDD +0.5
(≤ 4.6 V max.) V
Allowable BGA power dissipation PD 1.5 W
Storage temperature TSTG –55 to 150 oC
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply Voltage for -8/10/12 VDD 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 —VDD+0.3 V
Input Low Voltage VIL –0.3 —0.8 V
Ambient Temperature,
Commercial Range TAc 0 — 70 oC
Ambient Temperature,
Industrial Range TAi –40 —85 oC
Notes:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter Symbol Test Condition Max Unit
Input Capacitance CIN VIN = 0 V 10 pF
I/O Capacitance COUT VOUT = 0 V 7pF
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 4/12 © 2003, GSI Technology
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current IIL VIN = 0 to VDD –2 uA 2 uA
Output Leakage Current IOL
Output High Z, VOUT = 0
to VDD
–1 uA 1 uA
Output High Voltage VOH IOH = –4 mA 2.4 —
Output Low Voltage VOL IOL = +4 mA —0.4 V
DQ
VT = 1.4 V
50Ω30pF1
DQ
3.3 V
Output Load 1
Output Load 2
589Ω
434Ω
5pF1
Notes:
1. Includes scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ.
Parameter Conditions
Input high level VIH = 2.4 V
Input low level VIL = 0.4 V
Input rise time tr = 1 V/ns
Input fall time tf = 1 V/ns
Input reference level 1.4 V
Output reference level 1.4 V
Output load Fig. 1& 2
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 5/12 © 2003, GSI Technology
AC Test Conditions
Power Supply Currents
Parameter Symbol Test Conditions 0 to 70°C –40 to 85°C
8 ns 10 ns 12 ns 8 ns 10 ns 12 ns
Operating
Supply
Current
IDD
CE ≤ VIL
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
260 mA 210 mA 180 mA 280 mA 230 mA 200 mA
Standby
Current ISB1
CE ≥ VIH
All other inputs
≥ VIH or ≤VIL
Min. cycle time
60 mA 50 mA 50 mA 80 mA 70 mA 70 mA
Standby
Current ISB2
CE ≥ VDD - 0.2V
All other inputs
≥ VDD - 0.2V or ≤ 0.2V
20 mA 40 mA
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 6/12 © 2003, GSI Technology
AC Characteristics
Read Cycle
Parameter Symbol
-8 -10 -12
Unit
Min Max Min Max Min Max
Read cycle time tRC 8 — 10 —12 —ns
Address access time tAA — 8 — 10 —12 ns
Chip enable access time (CE) tAC — 8 — 10 —12 ns
Byte enable access time (UB, LB) tAB —3.5 — 4 — 5 ns
Output enable to output valid (OE) tOE —3.5 — 4 — 5 ns
Output hold from address change tOH 3 — 3 — 3 — ns
Chip enable to output in low Z (CE)t*3 — 3 — 3 — ns
Output enable to output in low Z (OE)t*0 — 0 — 0 — ns
Byte enable to output in low Z (UB, LB)t*0 — 0 — 0 — ns
Chip disable to output in High Z (CE)t*— 4 — 5 — 6 ns
Output disable to output in High Z (OE)t*—3.5 — 4 — 5 ns
Byte disable to output in High Z (UB, LB)t*—3.5 — 4 — 5 ns
* These parameters are sampled and are not 100% tested
tAA
tOH
tRC
Address
Data Out Previous Data Data valid
Read Cycle 1: CE = OE = VIL, WE = VIH
LZ
OLZ
BLZ
HZ
OHZ
BHZ
tAA
tRC
Address
tAC
tLZ
tOE
tOLZ
CE
OE
Data Out
tHZ
tOHZ
Data valid
High impedance
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 7/12 © 2003, GSI Technology
Read Cycle 2: WE = VIH
Write Cycle
Parameter Symbol
-8 -10 -12
Unit
Min Max Min Max Min Max
Write cycle time tWC 8 — 10 —12 —ns
Address valid to end of write tAW 5.5 — 7 — 8 — ns
Chip enable to end of write tCW 5.5 — 7 — 8 — ns
Byte enable to end of write tBW 5.5 — 7 — 8 — ns
Data set up time tDW 4 — 4.5 — 6 — ns
Data hold time tDH 0 — 0 — 0 — ns
Write pulse width tWP 5.5 — 7 — 8 — ns
Address set up time tAS 0 — 0 — 0 — ns
Write recovery time (WE)tWR 0 — 0 — 0 — ns
Write recovery time (CE)tWR1 0 — 0 — 0 — ns
Output Low Z from end of write tWLZ*3 — 3 — 3 — ns
Write to output in High Z tWHZ*—3.5 — 4 — 5 ns
* These parameters are sampled and are not 100% tested.
tWC
Address
CE
WE
Data In
OE
Data Out
tAW
tCW
tAS tWP
tWR
tDW tDH
tWLZ
tWHZ
Data valid
High impedance
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 8/12 © 2003, GSI Technology
Write Cycle 1: WE control
tWC
Address
CE
WE
Data In
OE
Data Out
tAW
tWP
tAS tCW
tWR1
tDW tDH
Data valid
High impedance
Write Cycle 2: CE control
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 9/12 © 2003, GSI Technology
Package Dimensions—119-Bump FPBGA (Package B, Variation 1)
(Date Code: yyww.31)
7 6 5 4 3 2 1
A1
BOTTOM VIEW
1.27
7.62
1.27
20.32
14±0.20
22±0.20
B
A
0.20(4x)
Ø0.10
Ø0.30
C
C A B
S
SØ0.60~0.90 (119x)
CSEATING PLANE
0.15 C
0.50~0.70
2.06.±0.13
0.90±0.10
0.15 C
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.56±0.05
SS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.70 REF
12.00
1 2 3 4 5 6 7
22±0.20
19.50
Pin #1 Corner
Ø1.00(3x) REF
30 TYP.
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 10/12 © 2003, GSI Technology
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
(Date Code: yyww.3H)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1 2 3 4 5 6 7 7 6 5 4 3 2 1
A1 TOP VIEW A1
BOTTOM VIEW
1.27
7.62
1.27
20.32
14±0.10
22±0.10
B
A
0.20(4x)
Ø0.10
Ø0.30
C
C A B
S
SØ0.60~0.90 (119x)
CSEATING PLANE
0.15 C
0.50~0.70
1.86.±0.13
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
SS
Ordering Information
Part Number1Package Access Time Temp. Range
GS76024AB-8 119-Bump BGA28 ns Commercial
GS76024AB-10 119-Bump BGA210 ns Commercial
GS76024AB-12 119-Bump BGA212 ns Commercial
GS76024AB-8I 119-Bump BGA28 ns Industrial
GS76024AB-10I 119-Bump BGA210 ns Industrial
GS76024AB-12I 119-Bump BGA212 ns Industrial
GS76024AB-8 RoHS-compliant119-Bump BGA28 ns Commercial
GS76024AB-10 RoHS-compliant119-Bump BGA210 ns Commercial
GS76024AB-12 RoHS-compliant119-Bump BGA212 ns Commercial
GS76024AB-8I RoHS-compliant119-Bump BGA28 ns Industrial
GS76024AB-10I RoHS-compliant119-Bump BGA210 ns Industrial
GS76024AB-12I RoHS-compliant119-Bump BGA212 ns Industrial
Notes:
1. Customers requiring Tape and Reel should add the character “T” to the end of the part number. For example: GS76024AB-12T.
2. Please see pages 9 and 10 for date code information for Variation 1 and Variation 2 of the 119-bump BGA.
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 11/12 © 2003, GSI Technology
Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content Page/Revisions/Reason
GS76024A_r1 • Creation of new datasheet
GS76024A_r1; GS76024A_r1_01 Content/Format • Updated format
• Added variation information to package mechanical
GS76024A_r1_01;
GS76024A_r1_02Content
• Added Variation 2 119 BGA to datasheet
• Added date codes to mechanicals
• (Rev1.02a: Added RoHS-compliant information)
GS76024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 4/2011 12/12 © 2003, GSI Technology
