64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Features Async/Page/Burst CellularRAM(R) 1.5 Memory MT45W4MW16BCGB Features Figure 1: * Single device supports asynchronous, page, and burst operations * VCC, VCCQ voltages: - 1.7-1.95V VCC - 1.7-3.3V VCCQ1 * Random access time: 70ns * Burst mode READ and WRITE access - 4, 8, 16, or 32 words or continuous burst - Burst wrap or sequential - MAX clock rate: 133 MHz1 (tCLK = 7.5ns) - Burst initial latency: 37.5ns (5 clocks) at 133 MHz - tACLK: 5.5ns at 133 MHz * Page mode read access - 16-word page size - Interpage read access: 70ns - Intrapage read access: 20ns * Low power consumption - Asynchronous READ: <25mA - Intrapage READ: <15mA - Initial access, burst READ: (37.5ns [5 clocks] at 133 MHz) <45mA - Continuous burst READ: <40mA - Standby: <50A (TYP at 25 C) - Deep power-down (DPD): <3A (TYP) * Low-power features - On-chip temperature-compensated refresh (TCR) - Partial-array refresh (PAR) - DPD mode Options PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__1.fm - Rev. F 9/07 EN 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CRE B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 A21 A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV# RFU RFU RFU Top view (Ball down) Options (continued) Designator * Standby power at 85C - Standard: 140A (MAX) - Low power: 120A (MAX) * Operating temperature range - Wireless (-30C to +85C) - Industrial (-40C to +85C) Designator * Configuration: 4 Meg x 16 VCC core voltage supply: 1.7-1.95V VCCQ I/O voltage supply: 1.7-3.3V1 * Package 54-ball VFBGA ("green") * Access time 70ns * Frequency: 133 MHz 104 MHz 80 MHz 54-Ball VFBGA Ball Assignment MT45W4MW16BC None L WT IT Notes: 1. The 3.3V I/O voltage and 133 MHz clock frequency exceed the CellularRAM 1.5 Workgroup specification. GB -70 13 1 8 Part Number Example: MT45W4MW16BCGB-701LWT 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Burst Wrap (BCR[3]) Default = No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .27 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Latency Counter (BCR[13:11]) Default = Three Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Initial Access Latency (BCR[14]) Default = Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Page Mode Operation (RCR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhzTOC.fm - Rev. F 9/07 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 56: 54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Functional Block Diagram - 4 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 READ Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 WRITE Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Page Mode READ Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Burst Mode READ (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Burst Mode WRITE (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Wired-OR WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Refresh Collision During Variable-Latency READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY . . . . . . . . . . . . . . . .19 Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation . . . . . . .20 Register READ, Asynchronous Mode Followed by READ ARRAY Operation . . . . . . . . . . . . . . . . . . . .21 Register READ, Synchronous Mode Followed by READ ARRAY Operation . . . . . . . . . . . . . . . . . . . . .22 Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Latency Counter (Variable Initial Latency, No Refresh Collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Latency Counter (Fixed Latency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Typical Refresh Current vs. Temperature (ITCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 AC Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 DPD Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Asynchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Single-Access Burst READ Operation - Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4-Word Burst READ Operation - Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Single-Access Burst READ Operation - Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4-Word Burst READ Operation - Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Burst READ at End-of-Row (Wrap Off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 WE#-Controlled Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Burst WRITE Operation - Variable Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Burst WRITE Operation - Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Burst WRITE at End of Row (Wrap Off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Burst READ Interrupted by Burst READ or WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode . . . . . . . . . . . . . . . . . .61 Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . .62 Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Asynchronous WRITE (ADV# LOW) Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .67 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhzLOF.fm - Rev. F 9/07 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Bus Operations - Asynchronous Mode (BCR[15] = 1; Default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Bus Operations - Burst Mode (BCR[15] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Variable Latency Configuration Codes (BCR [14] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Fixed Latency Configuration Codes (BCR[14] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 64Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Device Identification Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Partial-Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhzLOT.fm - Rev. F 9/07 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory General Description General Description Micron(R) CellularRAM(R) products are high-speed, CMOS memory devices developed for low-power, portable applications. The MT45W4MW16BCGB is a 64Mb DRAM core device, organized as 4 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three mechanisms to minimize standby current. Partialarray refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh (TCR) uses an onchip sensor to adjust the refresh rate to match the device temperature--the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system configurable refresh mechanisms are accessed through the RCR. This CellularRAM device is compliant with the industry-standard CellularRAM 1.5 feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, additional wrap options, and a device ID register (DIDR). PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory General Description Figure 2: Functional Block Diagram - 4 Meg x 16 A[21:0] Address decode logic 4,096K x 16 DRAM memory array Refresh configuration register (RCR) Input/ output MUX and buffers DQ[7:0] DQ[15:8] Device ID register (DIDR) Bus configuration register (BCR) CE# WE# OE# CLK ADV# CRE WAIT LB# UB# Control logic Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN Functional block diagrams illustrate simplified device operation. For detailed information, see ball descriptions in Table 1 on page 7; bus operations in Table 2 on page 8, Table 3 on page 9, and Table 2 on page 8; and timing diagrams starting on page 42. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory General Description Table 1: VFBGA Ball Descriptions VFBGA Assignment Symbol Type Description E3, H6, G2, H1, D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4, A3 J2 A[21:0] Input Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. CLK Input J3 ADV# Input A6 CRE Input B5 CE# Input A2 OE# Input G5 WE# Input A1 B2 G1, F1, F2, E2, D2, C2, C1, B1, G6, F6, F5, E5, D5, C6, C5, B6 J1 LB# UB# DQ[15:0] Input Input Input/ Output Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK must be static LOW during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. Address valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during asynchronous READ and WRITE operations. Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations access the RCR, BCR, or DIDR. Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby or DPD mode. Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write enable: Determines whether a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE either to a configuration register or to the memory array. Lower byte enable. DQ[7:0] Upper byte enable. DQ[15:8] Data inputs/outputs. WAIT Output J4, J5, J6 D6 E1 E6 D1 RFU VCC VCCQ VSS VSSQ - Supply Supply Supply Supply Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is asserted at the end of a row unless wrapping within the burst length. WAIT is asserted and should be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH. Reserved for future use. Device power supply (1.7-1.95V): Power supply for device core operation. I/O power supply (1.7-3.3V): Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will be asserted, but should be ignored during asynchronous and page mode operations. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory General Description Table 2: Bus Operations - Asynchronous Mode (BCR[15] = 1; Default) Mode Power CLK1 ADV# CE# OE# WE# CRE LB#/ UB# Read Write Standby No operation Configuration register write Configuration register read DPD Active Active Standby Idle Active L L L L L L L X X L L L H L L L X X X H H L X X L L L L L H L L X X X Low-Z Low-Z High-Z Low-Z Low-Z Data-out Data-in High-Z X High-Z Active L L L L H H L Low-Z Deep power-down L X H X X X X High-Z Config. reg. out High-Z Notes: WAIT2 DQ[15:0]3 Notes 4 4 5, 6 4, 6 7 1. CLK must be LOW during asynchronous read and asynchronous write modes and to achieve standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are enabled. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory General Description Table 3: Bus Operations - Burst Mode (BCR[15] = 0) Mode Power CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 Notes Asynchronous read Asynchronous write Standby No operation Initial burst read Active L L L L H L L Low-Z Data-out 4 Active L L L X L L L Low-Z Data-in 4 Standby Idle Active L L X X L H L L X X X X X H L L L X X L High-Z Low-Z Low-Z High-Z X X 5, 6 4, 6 4, 8 Initial burst write Active L L H L L X Low-Z X 4, 8 Burst continue Active H L X X X L Low-Z Data-in or data-out 4, 8 Burst suspend Configuration register write Active Active X L L L H H X L X H X X Low-Z Low-Z High-Z High-Z 4, 8 8, 9 Configuration register read Active L L L H H L Low-Z Config. reg. out X H X X X X High-Z DPD Deep power-down Notes: X L High-Z 8, 9 7 1. CLK must be LOW during asynchronous read and asynchronous write modes and to achieve standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only UB# is in the select mode, DQ[15:8] are enabled. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current. 7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to LOW and is held LOW for tDPDX. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). 9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated by WAIT). PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Part-Numbering Information Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densities (see Figure 3). Figure 3: Part Number Chart MT 45 W 4M W 16 BC GB -70 Micron Technology 8 WT ES Production Status Blank = Production Product Family ES = Engineering sample 45 = PSRAM/CellularRAM memory MS = Mechanical sample Operating Core Voltage Operating Temperature W = 1.7-1.95V WT = -30C to +85C IT = -40 to +85C Address Locations Standby Power Options M = Megabits Blank = Standard Operating Voltage L = Low power W = 1.7-3.3V1 Frequency 8 = 80 MHz Bus Configuration 1 = 104 MHz 16 = x16 13 = 133 MHz READ/WRITE Operation Mode Access/Cycle Time BC = Asynchronous/page/burst 70 = 70ns Package Codes GB = 54-ball VFBGA "green" (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) Valid Part Number Combinations After building the part number from the part numbering chart above, visit the Micron Web site at www.micron.com/support/designsupport/tools/fbga/decoder to verify that the part number is offered and valid. If the device required is not on this list, contact the factory. Device Marking Due to the size of the package, the Micron standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at www.micron.com/support/decoder. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, "Product Mark/ Label," at www.micron.com/support/designsupport/documents/csn. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Functional Description Functional Description In general, the MT45W4MW16BCGB device is a high-density alternative to SRAM and PSRAM products, popular in low-power, portable applications. The MT45W4MW16BCGB contains a 67,108,864-bit DRAM core, organized as 4,194,304 addresses by 16 bits. The device implements the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. Power-Up Initialization CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Figure 18 on page 25 and Figure 24 on page 31). VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150s to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 4: Power-Up Initialization Timing Vcc = 1.7V Vcc VccQ tPU > 150s Device ready for Device initialization normal operation Bus Operating Modes The MT45W4MW16BCGB CellularRAM product incorporates a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]). Asynchronous Mode CellularRAM products power up in the asynchronous operating mode. This mode uses the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations (Figure 5 on page 12) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 6 on page 12) occur when CE#, WE#, and LB#/UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can use the ADV input to latch the address or can drive ADV LOW during the entire READ/WRITE operation. During asynchronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is enabled, and its state should be ignored. WE# LOW time must be limited to tCEM. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Bus Operating Modes Figure 5: READ Operation (ADV# LOW) CE# OE# WE# Address Valid address Data Valid data LB#/UB# tRC = READ cycle time Don't Care Note: Figure 6: ADV must remain LOW for page mode operation. WRITE Operation (ADV# LOW) CE# OE# < tCEM WE# Address Data Valid address Valid data LB#/UB# tWC = WRITE cycle time Don't Care PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Bus Operating Modes Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed, and then adjacent addresses can be read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16address CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access time. Figure 7 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held LOW. CE# must be driven HIGH upon completion of a page mode access. WAIT will be driven while the device is enabled, and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode read accesses. Due to refresh considerations, CE# must not remain LOW longer than tCEM. Figure 7: Page Mode READ Operation (ADV# LOW) < tCEM CE# OE# WE# Address Data Add[0] Add[1] Add[2] Add[3] tAA tAPA D[0] tAPA D[1] tAPA D[2] D[3] LB#/UB# Don't Care Burst Mode Operation Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multiclock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge of the next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 8 on page 14) or a WRITE (WE# = LOW, Figure 9 on page 15). The size of a burst can be specified in the BCR either as a fixed-length or continuous. Fixed-length bursts consist of 4, 8, 16, or 32 words. Continuous bursts have the ability to start at a specified address and burst to the end of the 128-word row. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and the CellularRAM device. The initial latency for READ operations can be configured as fixed or variable PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Bus Operating Modes (WRITE operations always use fixed latency). Variable latency allows the CellularRAM to be configured for minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles. Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies. The WAIT output asserts when a burst is initiated and de-asserts to indicate when data is to be transferred into or out of memory. WAIT will again be asserted at the boundary of the 128-word row, unless wrapping within the burst length. To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active and, as a result, no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE# is taken LOW, and then CLK is restarted after valid data is available on the bus. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst should be restarted with a new CE# LOW/ADV# LOW cycle. Figure 8: Burst Mode READ (4-Word Burst) CLK A[21:0] Valid address ADV# CE# Latency code 2 (3 clocks) OE# WE# WAIT DQ[15:0] D0 D1 D2 D3 LB#/UB# READ burst identified (WE# = HIGH) Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN Don't Care Undefined Nondefault BCR settings for burst mode READ (4-word burst): fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. Figure 8 is representative of variable latency with no refresh collision or fixed-latency access. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Bus Operating Modes Figure 9: Burst Mode WRITE (4-Word Burst) CLK A[21:0] Valid address ADV# CE# Latency code 2 (3 clocks) OE# WE# WAIT DQ[15:0] D0 D1 D2 D3 LB#/UB# WRITE burst identified (WE# = LOW) Note: Don't Care Nondefault BCR settings for burst mode WRITE (4-word burst): fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. Mixed-Mode Operation The device supports a combination of synchronous READ and asynchronous READ and WRITE operations when the BCR is configured for synchronous operation. The asynchronous READ and WRITE operations require that the clock (CLK) remain LOW during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# can remain LOW when transitioning between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed tCEM. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 50 on page 63 for the "Asynchronous WRITE Followed by Burst READ" timing diagram. WAIT Operation The WAIT output on a CellularRAM device typically is connected to a shared, systemlevel WAIT signal (see Figure 10 on page 16). The shared WAIT signal is used by the processor to coordinate transactions with multiple memory devices on the synchronous bus. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Bus Operating Modes Figure 10: Wired-OR WAIT Configuration CellularRAM WAIT External pull-up/ pull-down resistor READY Processor WAIT WAIT Other device Other device When a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial latency may cause data corruption. When variable initial access latency is used (BCR[14] = 0), the WAIT output performs an arbitration role for READ operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has completed (see Figure 11 on page 17). When the refresh operation has completed, the READ operation will continue normally. WAIT will be asserted but should be ignored during asynchronous READ, WRITE, and PROGRAM operations. By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when valid data is available at the start of the burst and at the end of a row. If WAIT is not monitored, the controller must stop burst accesses at row boundaries on its own. LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be transferred to the RAM array, and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. LB#/UB# must be LOW during READ cycles. When both LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Bus Operating Modes Figure 11: CLK A[21:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Refresh Collision During Variable-Latency READ Operation VIH VIL VIH VIL Valid address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D0 VOL Additional WAIT states inserted to allow refresh completion Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN D1 D2 D3 Undefined Don't Care Nondefault BCR settings for refresh collision during variable-latency READ operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Low-Power Operation Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. Temperature-Compensated Refresh Temperature-compensated refresh (TCR) allows for adequate refresh at different temperatures. This CellularRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. Partial-Array Refresh Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start either at the beginning or the end of the address map (see Table 8 on page 32). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When reenabling additional portions of the array, the new portions are available immediately upon writing to the RCR. Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been reenabled by rewriting, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels but considerably lower than the active current specification. DPD can be enabled by writing to the RCR using CRE or the software access sequence; DPD starts when CE# goes HIGH. DPD is disabled the next time CE# goes LOW and stays LOW for at least 10s. Registers Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated any time the devices are operating in a standby state. The DIDR provides information on the device manufacturer, the CellularRAM generation, and the specific device configuration. The DIDR is read-only. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Access Using CRE The registers can be accessed either using a synchronous or an asynchronous operation when the control register enable (CRE) input is HIGH (see Figures 12 through 15). When CRE is LOW, a READ or WRITE operation will access the memory array. The configuration register values are written via addresses A[21:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care." The BCR is accessed when A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b. For reads, address inputs other than A[19:18] are "Don't Care," and register bits 15:0 are output on DQ[15:0]. Micron strongly recommends reading the memory array immediately after performing a configuration register READ and WRITE operation. Figure 12: Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY A[21:0] (except A[19:18]) OPCODE Address tAVH tAVS Select control register A[19:18]1 Address tAVS CRE tAVH tVPH ADV# tVP tCBPH Initiate control register access CE# tCW OE# tWP Write address bus value to control register WE# LB#/UB# DQ[15:0] Valid data Don't Care Notes: 1. A[19:18] = 00b to load RCR and A[19:18] = 10b to load BCR. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Figure 13: Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation CLK Latch control register value A[21:0] (except A[19:18]) OPCODE t tSP HD Address Latch control register address A[19:18]2 Address tSP CRE tSP ADV# tHD tHD tCBPH tCSP CE# Note 3 OE# tSP WE# tHD LB#/UB# WAIT tCEW High-Z High-Z Valid data DQ[15:0] Don't Care Notes: 1. Nondefault BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19:18] = 00b to load RCR and A[19:18] = 10b to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Figure 14: Register READ, Asynchronous Mode Followed by READ ARRAY Operation A[21:0] (except A[19:18]) Address tAVH tAVS Select register A[19:18]1 Address tAA tAVH tAVS CRE tAA tVPH ADV# tVP tAAVD tCBPH Initiate register access CE# tHZ tCO OE# tOHZ tOE tBA WE# tOLZ tLZ tBHZ LB#/UB# tLZ DQ[15:0] Valid CR Valid data Don't Care Notes: Undefined 1. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Figure 15: Register READ, Synchronous Mode Followed by READ ARRAY Operation CLK Latch control register value A[21:0] (except A[19:18]) Address Latch control register address tSP A[19:18]2 Address tHD tSP CRE tHD tSP ADV# tHD tABA tCBPH tCSP CE# Note 3 tHZ OE# tOHZ WE# tBOE tSP LB#/UB# tHD tCEW WAIT tOLZ tACLK High-Z High-Z Valid CR DQ[15:0] Valid data tKOH Don't Care Notes: Undefined 1. Nondefault BCR settings for synchronous mode register READ followed by READ ARRAY operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. 3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Software Access Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be modified, and all registers can be read using the software sequence. The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations (see Figure 16). The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 17 on page 24). The address used during all READ and WRITE operations is the highest address of the CellularRAM device being accessed (3FFFFFh for 64Mb); the contents of this address are not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, or the DIDR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is 0002h, the sequence will access the DIDR. During the fourth operation, DQ[15:0] transfer data into or out of bits 15:0 of the registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. Figure 16: Load Configuration Register Address READ READ WRITE WRITE Address (MAX) Address (MAX) Address (MAX) Address (MAX) XXXXh XXXXh CE# OE# WE# LB#/UB# Data CR value in RCR: 0000h BCR: 0001h PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 23 Don't Care Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Figure 17: Read Configuration Register Address READ READ WRITE READ Address (MAX) Address (MAX) Address (MAX) Address (MAX) XXXXh XXXXh CE# OE# WE# LB#/UB# Data CR value out RCR: 0000h BCR: 0001h DIDR: 0002h PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 24 Don't Care Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 18 defines the control bits in the BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b or through the register access software sequence with DQ = 0001h on the third cycle. Figure 18: Bus Configuration Register Definition A14 A13 A12 A11 A10 A[21:20] A[19:18] A[17:16] A15 21-20 19-18 17-16 Reserved Register Select Reserved 15 14 Initial Latency Operating Mode 13 12 11 Latency Counter Must be set to "0" All must be set to "0" BCR[14] 10 WAIT Polarity A9 9 Reserved A8 8 WAIT Configuration (WC) Must be set to "0" A6 A7 7 4 5 6 Reserved A4 A5 Drive Strength Reserved A3 A2 A1 A0 3 2 1 0 Burst Burst Wrap (BW)1 Length (BL)1 Must be set to "0" Setting is ignored (Default to "0") Initial Access Latency 0 Variable (default) 1 Fixed Burst Wrap (Note 1) BCR[3] BCR[13] BCR[12] BCR[11] 0 Burst wraps within the burst length 1 Burst no wrap (default) Latency Counter 0 0 0 Code 8 BCR[5] BCR[4] 0 0 1 Code 1-Reserved 0 0 Full 0 1 0 Code 2 0 1 1/2 (default) 0 1 1 Code 3 (Default) 1 0 1/4 1 0 0 Code 4 1 1 Reserved 1 0 1 Code 5 1 1 0 Code 6 1 1 1 Code 7-Reserved BCR[8] BCR[10] Drive Strength WAIT Configuration 0 Asserted during delay 1 Asserted one data cycle before delay (default) WAIT Polarity 0 Active LOW 1 Active HIGH (default) BCR[2] BCR[1] BCR[0] Burst Length (Note 1) 0 0 1 4 words Operating Mode 0 1 0 8 words 0 Synchronous burst access mode 0 1 1 16 words 1 Asynchronous access mode (default) 1 0 0 32 words 1 1 1 Continuous burst (default) BCR[15] Register Select BCR[19] BCR[18] 0 0 Select RCR 1 0 Select BCR 0 1 Select DIDR Notes: Others Reserved 1. Burst wrap and length apply both to READ and WRITE operations. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst length of 4, 8, 16, or 32 words. The device can also be set in continuous burst mode where data is accessed sequentially up to the end of the row. Burst Wrap (BCR[3]) Default = No Wrap The burst-wrap option determines whether a 4-, 8-, 16-, or 32-word READ or WRITE burst wraps within the burst length, or steps through sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses up to the end of the row. Sequence and Burst Length Table 4: Burst Wrap BCR[3] 0 WRAP Yes Starting Address 4-Word Burst Length 8-Word Burst Length 16-Word Burst Length Continuous Burst (Decimal) Linear Linear Linear Linear Linear 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-...-29-30-31 0-1-2-3-4-5-6-... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-...-30-31-0 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-...-31-0-1 2-3-4-5-6-7-8-... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-...-0-1-2 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-...-1-2-3 4-5-6-7-8-9-10-... 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-...-2-3-4 5-6-7-8-9-10-11-... 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-...-3-4-5 6-7-8-9-10-11-12-... 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-... 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-...-4-5-6 ... ... ... ... 14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-...-11-1213 14-15-16-17-18-19-20... 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-...-12-1314 15-16-17-18-19-20-21... ... ... ... 30 30-31-0-...-27-28-29 30-31-32-33-34-... 31 1 32-Word Burst Length 31-0-1-...-28-29-30 31-32-33-34-35-... 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-...--29-30-31 0-1-2-3-4-5-6-... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-...-30-31-32 1-2-3-4-5-6-7-... 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-...-31-32-33 2-3-4-5-6-7-8-... 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-...-32-33-34 3-4-5-6-7-8-9-... 4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-...-33-34-35 4-5-6-7-8-9-10-... 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-14-15-16-17-18-1920 5-6-7-...-34-35-36 5-6-7-8-9-10-11-... 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-15-16-17-18-19-2021 6-7-8-...-35-36-37 6-7-8-9-10-11-12-... 7 7-8-9-10-11-12-1314 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-...-36-37-38 7-8-9-10-11-12-13-... No ... ... ... ... 14 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-...-43-4445 14-15-16-17-18-19-20... 15 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-...-44-4546 15-16-17-18-19-20-21... ... ... ... 30 30-31-32-...-59-6061 30-31-32-33-34-35-36... 31 31-32-33-...-60-6162 31-32-33-34-35-36-37... PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured at half-drive strength during testing. See Table 5 for additional information. Table 5: Drive Strength BCR[5] BCR[4] Drive Strength 0 0 1 1 0 1 0 1 Full 1/2 (default) 1/4 Impedance Typ () Use Recommendation 25-30 50 100 CL = 30pF to 50pF CL = 15pF to 30pF, 104 MHz at light load CL = 15pF or lower Reserved WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (see Figures 19 and 21). When A8 = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid (see Figure 20 on page 28 and Figure 21 on page 28). WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. Figure 19: WAIT Configuration (BCR[8] = 0) CLK WAIT DQ[15:0] Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN High-Z Data 0 Data 1 Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 21 on page 28. 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Figure 20: WAIT Configuration (BCR[8] = 1) CLK WAIT DQ[15:0] Note: Figure 21: High-Z Data 0 Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 21 on page 28). WAIT Configuration During Burst Operation CLK BCR[8] = 0 Data valid in current cycle WAIT BCR[8] = 1 Data valid in next cycle WAIT DQ[15:0] D[0] D[1] D[2] D[3] Don't Care Note: Nondefault BCR setting: WAIT active LOW. Latency Counter (BCR[13:11]) Default = Three Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. For allowable latency codes, see Tables 6 and 7 on pages 29 and 30, respectively, and Figures 22 and 23 on pages 29 and 30, respectively. Initial Access Latency (BCR[14]) Default = Variable Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter (see Table 7 on page 30 and Figure 23 on page 30). Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit either selects synchronous burst operation or the default asynchronous mode of operation. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Table 6: Variable Latency Configuration Codes (BCR [14] = 0) BCR[13:11] Latency Configuration Code Latency1 Maximum Input CLK Frequency (MHz) Normal Refresh Collision -7013 -701 -708 010 011 100 2 (3 clocks) 3 (4 clocks)--default 4 (5 clocks) 2 3 4 4 6 8 66 (15.0ns) 104 (9.62ns) 133 (7.5ns) 66 (15.0ns) 52 (19.2ns) 104 (9.62ns) 80 (12.5ns) Others Reserved - - - - - Notes: Figure 22: CLK A[21:0] ADV# 1. Latency is the number of clock cycles from the initialization of a burst operation until data appears. Data is transferred on the next clock cycle. READ latency can range from the normal latency to the value shown for refresh collision. WRITE latency is fixed at the value shown for normal latency. Latency Counter (Variable Initial Latency, No Refresh Collision) VIH VIL VIH VIL Valid address VIH VIL Code 2 DQ[15:0] VOH Valid output VOL Code 3 DQ[15:0] Valid output Valid output Valid output Valid output Valid output Valid output Valid output Valid output (Default) VOH VOL Don't Care PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 29 Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Table 7: Fixed Latency Configuration Codes (BCR[14] = 1) Maximum Input CLK Frequency (MHz) Latency Configuration Code BCR[13:11] 010 011 100 101 110 000 Others Latency Count (N) -7013 -70 -708 2 3 4 5 6 8 - 33 (30ns) 52 (19.2ns) 66 (15ns) 75 (13.3ns) 104 (9.62ns) 133 (7.5ns) - 33 (30ns) 52 (19.2ns) 66 (15ns) 75 (13.3ns) 104 (9.62ns) 104 (9.62ns) - 33 (30ns) 52 (19.2ns) 66 (15ns) 75 (13.3ns) 80 (12.5ns) 80 (12.5ns) - 2 (3 clocks) 3 (4 clocks)--default 4 (5 clocks) 5 (6 clocks) 6 (7 clocks) 8 (9 clocks) Reserved Figure 23: Latency Counter (Fixed Latency) N-1 Cycles CLK Cycle N VIH VIL tAA A[21:0] VIH VIL Valid address tAADV ADV# CE# VIH VIL tCO VIH VIL tACLK VOH Valid output DQ[15:0] VOL (READ) tSP VOH Valid output Burst identified (ADV# = LOW) PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN Valid output Valid input Valid input Don't Care 30 Valid output tHD Valid input DQ[15:0] VOL (WRITE) Valid output Valid input Valid input Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure 24 describes the control bits used in the RCR. At power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b or through the register access software sequence with DQ = 0000h on the third cycle (see "Registers" on page 18). Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start either at the beginning or the end of the address map (see Table 8 on page 32). Figure 24: Refresh Configuration Register Mapping A[21:20] A[19:18] 21-20 19-18 Register Reserved Select A[17:8] 17-8 7 Reserved Page All must be set to "0" All must be set to "0" RCR[19] RCR[18] 6 A5 A4 5 4 Setting is ignored (Default 00b) 0 Select RCR 1 0 Select BCR 0 1 Select DIDR 2 Reserved Page mode disabled (default) 1 Page mode enable 31 1 0 Address Bus Must be set to "0" RCR[4] PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN A0 PAR RCR[2] RCR[1] RCR[0] Refresh Coverage 0 0 0 Full array (default) 0 0 1 Bottom 1/2 array 0 1 0 Bottom 1/4 array 0 1 1 Bottom 1/8 array 1 0 0 None of array 1 0 1 Top 1/2 array 1 1 0 Top 1/4 array 1 1 1 Top 1/8 array Page Mode Enable/Disable 0 A1 A2 3 DPD Reserved A3 Register Select 0 RCR[7] A6 A7 Deep Power-Down 0 DPD enable 1 DPD disable (default) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Table 8: 64Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die 000000h-3FFFFFh 000000h-1FFFFFh 000000h-0FFFFFh 000000h-07FFFFh 0 200000h-3FFFFFh 300000h-3FFFFFh 380000h-3FFFFFh 4 Meg x 16 2 Meg x 16 1 Meg x 16 512K x 16 0 Meg x 16 2 Meg x 16 1 Meg x 16 512K x 16 64Mb 32Mb 16Mb 8Mb 0Mb 32Mb 16Mb 8Mb Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been reenabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD can be enabled using CRE or the software sequence to access the RCR. Taking CE# LOW for at least 10s disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable DPD. BCR and RCR values (other than RCR[4]) are preserved during DPD. Page Mode Operation (RCR[7]) Default = Disabled The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Registers Device Identification Register The DIDR provides information on the device manufacturer, the CellularRAM generation, and the specific device configuration. Table 9 describes the bit fields in the DIDR. The DIDR is accessed with CRE HIGH and A[19:18] = 01b or through the register access software sequence with DQ = 0002h on the third cycle. Table 9: Bit Field Device Identification Register Mapping DIDR[15] DIDR[14:11] DIDR[10:8] DIDR[7:5] DIDR[4:0] Field name Row length Device version Device density CellularRAM generation Vendor ID Bit setting 0b Bit Setting Version 0000b 1st 0001b 2nd 0010b 3rd (etc.) (etc.) 010b 010b 00011b 64Mb CellularRAM 1.5 Micron Meaning 128 words Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN Vendors with 256-word row lengths for CellularRAM 1.5 devices will set DIDR[15] to 1b. 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Electrical Characteristics Electrical Characteristics Table 10: Absolute Maximum Ratings Parameter Rating -0.5V to (4.0V or VCCQ + 0.3V, whichever is less)1 -0.2V to +2.45V -0.2V to +4.0V -55C to +150C Voltage to any ball except VCC; VCCQ supply relative to VSS Voltage on VCC supply relative to VSS Voltage on VCCQ supply relative to VSS Storage temperature (plastic) Operating temperature (case) Wireless Industrial Soldering temperature and time 10s (solder ball only) Notes: -30C to +85C -40C to +85C +260C 1. This exceeds the CellularRAM Workgroup 1.5 specification of -0.3V to VCCQ + 0.3V. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Electrical Characteristics Table 11: Electrical Characteristics Wireless temperature (-30C < TC < +85C); Industrial temperature (-40C < TC < +85C) Description Conditions Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Notes: Table 12: IOH = -0.2mA IOL = +0.2mA VIN = 0 to VCCQ OE# = VIH or chip disabled 1. 2. 3. 4. Symbol VCC VCCQ VIH VIL VOH VOL ILI ILO Min Max Unit 1.7 1.7 VCCQ - 0.4 -0.2 0.8 VCCQ - - - 1.95 3.3 VCCQ + 0.2 0.4 - 0.2 VCCQ 1 1 V V V V V V A A Notes 1 2 3 4 4 VCCQ (MAX) exceeds the CellularRAM Workgroup specification of 1.95V. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions. BCR[5:4] = 01b (default setting of one-half drive strength). Operating Conditions Wireless temperature (-30C < TC < +85C); Industrial temperature (-40C < TC < +85C) Operating Current Conditions Asynchronous random READ/WRITE Asynchronous page READ Initial access, burst READ/WRITE Continuous burst READ Continuous burst WRITE Standby current Notes: Symbol -70 -70 133 MHz 104 MHz 80 MHz 133 MHz ICC3R 104 MHz 80 MHz 133 MHz ICC3W 104 MHz 80 MHz ISB Standard VIN = VCCQ or 0V CE# = VCCQ Low power (L) Typ VIN = VCCQ or 0V ICC1 chip enabled, ICC1P IOUT = 0 ICC2 50 Max Unit Notes 25 15 45 35 30 40 30 25 40 35 30 140 120 mA mA mA mA 1 1, 2 1 mA mA 1 mA mA 1 A 3, 4 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 2. Micron devices are fully compatible with the CellularRAM Workgroup specification for ICCP1: -70 MAX of 18mA. 3. ISB (MAX) values are measured with PAR set to full array and at +85C. To achieve low standby current, all inputs must be driven either to VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up or when entering standby mode. 4. ISB (TYP) is the average ISB at 25C, and VCC = VCCQ = 1.8V. This parameter is verified during characterization and is not 100 percent tested. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Electrical Characteristics Table 13: Partial-Array Refresh Specifications and Conditions Description Conditions Partial-array refresh standby current Symbol VIN = VCCQ or 0V, CE# = VCCQ IPAR Array Partition Max Unit Full 1/2 1/4 1/8 0 Full 1/2 1/4 1/8 0 140 120 110 105 95 120 105 95 90 85 A Standard power (no designation) Low-power option (L) Note: Figure 25: A IPAR (MAX) values are measured at 85C. IPAR might be slightly higher for up to 500ms after changes to the PAR array partition or when entering standby mode. To achieve low standby current, all inputs must be driven either to VCCQ or VSS. Typical Refresh Current vs. Temperature (ITCR) 80 PAR = Full array 70 PAR = 1/2 of array 60 PAR = 1/4 of array ISB (A) 50 40 PAR = 1/8 of array 30 PAR = None of array 20 10 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Table 14: Deep Power-Down Specifications Description Deep power-down Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN Conditions Symbol Typ Max Unit VIN = VCCQ or 0V; VCC, VCCQ = 1.95V; +85C IZZ 3 10 A IZZ (TYP) value applies across all operating temperatures and voltages. 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Electrical Characteristics Table 15: Capacitance Description Input capacitance Input/output capacitance (DQ) Notes: Figure 26: Conditions Symbol Min Max Unit Notes TC = +25C; f = 1 MHz; VIN = 0V CIN CIO 2.0 3.5 6 6 pF pF 1 1 1. These parameters are verified in device characterization and are not 100 percent tested. AC Input/Output Reference Waveform VCCQ Input 1 VCCQ/2 2 Test points 3 VCCQ/2 Output VSSQ Notes: Figure 27: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10 percent to 90 percent) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. AC Output Load Circuit Test point 50 VccQ/2 DUT 30pF Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN All tests are performed with the outputs configured for a default setting of half drive strength (BCR[5:4] = 01b). 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Requirements Timing Requirements Table 16: Asynchronous READ Cycle Timing Requirements All tests are performed with outputs configured for default setting of one-half drive strength (BCR[5:4] = 01b). 70ns Parameter Symbol Address access time ADV# access time Page access time Address hold from ADV# HIGH Address setup to ADV# HIGH LB#/UB# access time LB#/UB# disable to DQ High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width CE# LOW to WAIT valid Chip select access time CE# LOW to ADV# HIGH Chip disable to DQ and WAIT High-Z output Chip enable to Low-Z output Output enable to valid output Output hold from address change Output disable to DQ High-Z output Output enable to Low-Z output PAGE cycle time READ cycle time ADV# pulse width LOW Notes: t AA AADV t APA t AVH t AVS t BA tBHZ tBLZ tCEM tCEW tCO tCVS tHZ tLZ tOE tOH tOHZ tOLZ tPC tRC tVP t Min Max Unit - - - 2 5 - - 10 - 1 - 7 - 10 - 5 - 3 20 70 5 70 70 20 - - 70 8 - 4 7.5 70 - 8 - 20 - 8 - - - - ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 2 3 1 2 1 2 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2. 2. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward VOH or VOL. 3. Page mode enabled only. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Requirements Table 17: Burst READ Cycle Timing Requirements All tests are performed with outputs configured for default setting of one-half drive strength (BCR[5:4] = 01b) -7013 (133 MHz) Parameter Symbol Address access time (fixed latency) ADV# access time (fixed latency) Burst to READ access time (variable latency) CLK to output Variable LC = 4 delay Fixed LC = 8 All other LCs Address hold from ADV# HIGH (fixed latency) Burst OE# LOW to output delay CE# HIGH between subsequent burst or mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT valid CLK period Chip select access time (fixed latency) CE# setup time to active CLK edge Hold time from active CLK edge Chip disable to DQ and WAIT High-Z output CLK rise or fall time CLK to WAIT Variable LC = 4 valid Fixed LC = 8 All other LCs Output hold from CLK CLK HIGH or LOW time Output disable to DQ High-Z output Output enable to Low-Z output Setup time to active CLK edge Notes: t AA AADV t ABA t ACLK t t AVH tBOE tCBPH tCEM tCEW tCLK tCO tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ t OLZ t SP -701 (104 MHz) -708 (80 MHz) Min Max Min Max Min Max Unit - - - - 70 70 35.5 5.5 - - - - 70 70 35.9 7 - - - - 70 70 46.5 9 ns ns ns ns - 2 - 5 7 - 20 - - 2 - 5 7 - 20 - - 2 - 6 9 - 20 - ns ns ns ns - 1 7.5 - 2.5 1.5 - - - 4 7.5 - 70 - - 7 1.2 5.5 - 1 9.62 - 3 2 - - - 4 7.5 - 70 - - 7 1.6 7 - 1 12.5 - 4 2 - - - 4 7.5 - 70 - - 7 1.8 9 s ns ns ns ns ns ns ns ns - 2 3 - 3 2 7 - - 7 - - - 2 3 - 3 3 7 - - 7 - - - 2 4 9 - - 7 - - ns ns ns ns ns ns 3 3 Notes 1 2 2 4 3 4 1. Values are valid for tCLK (MIN) with no refresh collision: LC = 4 for -7013; LC = 3 for -701 and -708. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. 3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2. 4. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward VOH or VOL. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Requirements Table 18: Asynchronous WRITE Cycle Timing Requirements 70ns Parameter Symbol t AS AVH t AVS t AW tBW t CEW t CPH tCVS tCW t DH tDW tHZ tLZ tOW tVP tVS tWC tWHZ tWP tWPH tWR Address and ADV# LOW setup time Address hold from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# LOW to WAIT valid CE# HIGH between subsequent asynchronous operations CE# LOW to ADV# HIGH Chip enable to end of WRITE Data hold from WRITE time Data WRITE setup time Chip disable to WAIT High-Z output Chip enable to Low-Z output End WRITE to Low-Z output ADV# pulse width ADV# setup to end of WRITE WRITE cycle time WRITE to DQ High-Z output WRITE pulse width WRITE pulse width HIGH WRITE recovery time Notes: t Min Max Unit 0 2 5 70 70 1 5 7 70 0 20 - 10 5 5 70 70 - 45 10 0 - - - - - 7.5 - - - - - 8 - - - - - 8 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 2 2 1 3 1. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2. 2. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 37. The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward VOH or VOL. 3. WE# LOW time must be limited to tCEM (4s). PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Requirements Table 19: Burst WRITE Cycle Timing Requirements Parameter Symbol Address and ADV# LOW setup time Address hold from ADV# HIGH (fixed latency) CE# HIGH between subsequent burst or mixedmode operations Maximum CE# pulse width CE# LOW to WAIT valid Clock period CE# setup to CLK active edge Hold time from active CLK edge Chip disable to WAIT High-Z output CLK rise or fall time CLK to WAIT valid Variable LC = 4 Fixed LC = 8 All other LCs CLK HIGH or LOW time Setup time to active CLK edge tAS Notes: t t -7013 (133 Mhz) -701 (104 MHz) Min Max Min Max Min Max Unit Notes 0 2 5 - - - 0 2 5 - - - 0 2 6 - - - ns ns ns 1 - 1 7.5 2.5 1.5 - - - 4 7.5 - - - 7 1.2 5.5 - 1 9.62 3 2 - - - 4 7.5 - - - 8 1.6 7 - 1 12.5 4 2 - - - 4 7.5 - - - 8 1.8 9 s ns ns ns ns ns ns ns 2 - 3 2 7 - - - 3 3 7 - - - 4 3 9 - - ns ns ns AVH CBPH tCEM t CEW CLK t CSP tHD tHZ tKHKL tKHTL t tKP tSP -708 (80 MHz) 2 3 1. tAS is required if tCSP > 20ns. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. 3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 37. The High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Timing Diagrams Figure 28: Initialization Period Vcc (MIN) Vcc, VccQ = 1.7V Figure 29: tPU Device ready for normal operation DPD Entry and Exit Timing tDPD tDPDX tPU DPD enabled DPD exit Device initialization CE# Write RCR[4] = 0 Table 20: Device ready for normal operation Initialization Timing Parameters 70ns Parameter Symbol Time from DPD entry to DPD exit CE# LOW time to exit DPD Initialization period tDPD Notes: tDPDX tPU Min Max Unit Notes 10 10 - - - 150 s s s 1 1. The CellularRAM Workgroup 1.5 specification for tDPD is a minimum of 150s. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 30: Asynchronous READ tRC VIH A[21:0] Valid address VIL tAA ADV# VIH VIL tHZ CE# VIH VIL tCO tBHZ tBA LB#/UB# VIH VIL tOE OE# WE# tOHZ VIH VIL VIH tOLZ tBLZ VIL tLZ VOH DQ[15:0] VOL High-Z Valid output tCEW tHZ VIH WAIT VIL High-Z High-Z Don't Care PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 43 Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 31: Asynchronous READ Using ADV# A[21:0] VIH Valid address VIL tAVS tVPH tAA tAVH VIH ADV# VIL tAADV tVP CE# VIL tCO tBA VIH LB#/UB# tHZ tCVS VIH tBHZ VIL tOE tOHZ VIH OE# VIL VIH WE# tOLZ VIL tBLZ tLZ DQ[15:0] VOH High-Z Valid output VOL tCEW WAIT tHZ VIH VIL High-Z High-Z Don't Care PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 44 Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 32: Page Mode READ tRC A[21:4] VIH Valid address VIL VIH A[3:0] ADV# Valid address Valid address VIL tAA VIH Valid address Valid address tPC VIL tCEM tCO tHZ VIH CE# VIL tBHZ tBA LB#/UB# VIH VIL tOHZ tOE VIH OE# VIL VIH WE# tOLZ tBLZ VIL VOH DQ[15:0] VOL tAPA tOH tLZ Valid Output High-Z Valid output Valid output Valid output tHZ tCEW VOH WAIT VOL High-Z High-Z Don't Care PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 45 Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 33: Single-Access Burst READ Operation - Variable Latency tKP tCLK tKP VIH CLK A[21:0] VIL VIH VIL VIH ADV# CE# tKHKL tSP tHD Valid address tSP tHD tHD VIL VIH tCEM tABA tCSP tHZ VIL tOHZ tBOE VIH OE# VIL tSP WE# tHD tOLZ VIH VIL tSP tHD VIH LB#/UB# VIL VOH WAIT tKHTL tCEW High-Z High-Z VOL DQ[15:0] tACLK VOH VOL High-Z READ burst identified (WE# = HIGH) Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN tKOH Valid output Don't Care Undefined Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 34: 4-Word Burst READ Operation - Variable Latency tKHKL CLK ADV# CE# tKP VIL tSP A[21:0] tKP tCLK VIH tHD VIH VIL Valid address tSP tHD VIH VIL VIH tCEM tHD tABA tCSP VIL tCBPH tHZ tBOE OE# VIH VIL tSP WE# tHD tOHZ tOLZ VIH VIL tHD tSP LB#/UB# VIH VIL tKHTL tCEW WAIT VOH VOL High-Z High-Z tKOH tACLK DQ[15:0] VOH Valid output VOL READ burst identified (WE# = HIGH) Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN Valid output Valid output Valid output Don't Care Undefined Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 35: Single-Access Burst READ Operation - Fixed Latency CLK A[21:0] VIL tKP tKHKL tSP VIH Valid address VIL tAVH tSP VIH ADV# tKP tCLK VIH tAA tHD VIL tAADV tHD tCEM CE# tHZ tCSP VIH VIL tCO OE# VIL tSP WE# tOHZ tBOE VIH tOLZ tHD VIH VIL tHD tSP VIH LB#/UB# VIL WAIT VOL DQ[15:0] tKHTL tCEW VOH High-Z High-Z tKOH VOH High-Z VOL Valid output READ burst identified (WE# = HIGH) Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN Don't Care Undefined Nondefault BCR settings: fixed latency; latency code 4 (5 clocks); WAIT active LOW; WAIT asserted during delay. 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 36: 4-Word Burst READ Operation - Fixed Latency tKHKL CLK A[21:0] tKP tKP tCLK VIH VIL tSP VIH VIL Valid address tAVH tAA tSP ADV# tHD VIH VIL tAADV tCEM CE# VIH tHD tCSP VIL tHZ tCO OE# WE# LB#/UB# tBOE VIH VIL tCBPH tSP tHD tOHZ tOLZ VIH VIL tSP tHD VIH VIL tKHTL tCEW WAIT VOH VOL High-Z High-Z tKOH DQ[15:0] VOH High-Z VOL Valid output READ burst identified (WE# = HIGH) Note: PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN Valid output Valid output Valid output tACLK Don't Care Undefined Nondefault BCR settings: fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 37: READ Burst Suspend tCLK Note 2 VIH CLK VIL tSP VIH A[21:0] VIL tHD Valid address Valid address tSP tHD VIH ADV# VIL tCBPH tHZ tCEM VIH tCSP CE# VIL tOHZ VIH OE# VIL tOHZ Note 3 tSP tHD VIH WE# VIL tHD tSP VIH LB#/UB# VIL VOH tOLZ WAIT VOL High-Z tBOE High-Z tKOH tOLZ VOH DQ[15:0] VOL High-Z Valid output Valid output Valid output tACLK Valid output tBOE Valid output Valid output Don't Care Notes: Undefined 1. Nondefault BCR settings for READ burst suspend: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. CLK can be stopped LOW or HIGH but must be static, with no LOW-to-HIGH transitions during burst suspend. 3. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 38: CLK Burst READ at End-of-Row (Wrap Off) VIH VIL tCLK A[21:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# Note 2 VIH VIL OE# VIH VIL WE# VIH VIL tHZ tKHTL WAIT tHZ VOH High-Z VOL DQ[15:0] VOH Valid output VOL Valid output End of row Don't Care Notes: 1. Nondefault BCR settings for burst READ at end of row: fixed or variable latency; WAIT active LOW; WAIT asserted during delay. 2. For burst READs, CE# must go HIGH before the third CLK after the WAIT period begins (before the third CLK after WAIT asserts with BCR[8] = 0 or before the fourth CLK after WAIT asserts with BCR[8] = 1). Micron devices are fully compatible with the CellularRAM Workgroup specification that requires CE# to go HIGH 1 cycle sooner than shown here. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 39: CE#-Controlled Asynchronous WRITE tWC A[21:0] VIH Valid address VIL tAW tAS tWR VIH ADV# VIL tCW CE# tCPH VIH VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP VIH WE# VIL tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL tLZ WAIT tDH Valid input tWHZ VOL VOH VOL tHZ tCEW High-Z High-Z Don't Care PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 40: LB#/UB#-Controlled Asynchronous WRITE tWC A[21:0] VIH Valid address VIL tAW tWR tAS ADV# CE# VIH VIL tCW VIH VIL tBW LB#/UB# OE# VIH VIL VIH VIL tWP tWPH VIH WE# VIL tDW DQ[15:0] IN VIH DQ[15:0] OUT VOH High-Z VIL Valid input tWHZ tLZ VOL tHZ tCEW WAIT tDH VOH VOL High-Z High-Z Don't Care PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 41: WE#-Controlled Asynchronous WRITE tWC VIH A[21:0] Valid address VIL tAW tWR VIH ADV# VIL tCW VIH CE# VIL tBW VIH LB#/UB# VIL VIH OE# VIL tAS tWP tWPH VIH WE# VIL tDW DQ[15:0] IN High-Z VIL Valid input tOW tWHZ tLZ DQ[15:0] OUT tDH VIH VOH VOL tCEW tHZ VOH WAIT VOL High-Z High-Z Don't Care PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 42: WE#-Controlled Asynchronous WRITE Using ADV# A[21:0] VIH Valid address VIL tAVS tVS tVPH ADV# tVP tAS VIH VIL tAVH tAS tAW tCVS tCW VIH CE# VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP WE# VIH VIL tDW DQ[15:0] VIH IN VIL Valid input High-Z tLZ tDH tOW tWHZ DQ[15:0] VOH OUT VOL tCEW WAIT tHZ VIH VIL High-Z High-Z Don't Care PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 43: Burst WRITE Operation - Variable Latency Mode tCLK CLK tKP tKP tKHKL VIH VIL tSP A[21:0] VIL ADV# Valid address tAS3 tSP VIH VIL LB#/UB# tHD VIH tHD tAS3 tSP tHD VIH VIL tCEM CE# tHD tCSP VIH tCBPH VIL OE# VIH VIL tSP WE# tHD VIH VIL tKHTL tCEW tHZ VOH WAIT High-Z VOL High-Z Note 2 tHD tSP VIH DQ[15:0] D0 VIL WRITE burst identified (WE# = LOW) Notes: D1 D2 D3 Don't Care 1. Nondefault BCR settings for burst WRITE operation in variable latency mode: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay; burst length 4; burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]). 3. tAS required if tCSP > 20ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 44: Burst WRITE Operation - Fixed Latency Mode tCLK CLK tKP tKP tKHKL VIH VIL tSP A[21:0] VIH Valid address VIL tAVH tAS3 ADV# VIH VIL LB#/UB# tSP tHD tAS3 tSP tHD VIH VIL tCEM CE# tCSP VIH tHD tCBPH VIL OE# VIH VIL tSP WE# tHD VIH VIL tKHTL tCEW tHZ VOH WAIT High-Z VOL High-Z Note 2 tSP tHD VIH DQ[15:0] D0 VIL WRITE burst identified (WE# = LOW) Notes: D1 D2 D3 Don't Care 1. Nondefault BCR settings for burst WRITE operation in fixed latency mode: fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay; burst length 4; burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]). 3. tAS required if tCSP > 20ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 45: CLK Burst WRITE at End of Row (Wrap Off) VIH VIL tCLK A[21:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# Note 2 VIH Note 4 VIL VIH WE# VIL VIH OE# VIL tHZ WAIT tKHTL tHZ VOH High-Z VOL tSP Note 3 tHD VIH DQ[15:0] Valid input VIL Valid input End of row (A[6:0] = 7Fh) Don't Care Notes: 1. Nondefault BCR settings for burst WRITE at end of row: fixed or variable latency; WAIT active LOW; WAIT asserted during delay. 2. For burst WRITEs, CE# must go HIGH before the third CLK after the WAIT period begins (before the third CLK after WAIT asserts with BCR[8] = 0 or before the fourth CLK after WAIT asserts with BCR[8] = 1). Micron devices are fully compatible with the CellularRAM Workgroup specification that requires CE# to go HIGH 1 cycle sooner than shown here. 3. Devices from different CellularRAM vendors can assert WAIT so that the end-of-row data is input 1 cycle before the WAIT period begins (as shown, solid line) or the same cycle that asserts WAIT. This difference in behavior will not be noticed by controllers that monitor WAIT or that use WAIT to abort on an end-of-row condition. 4. Micron devices are fully compatible with the CellularRAM Workgroup specification that requires CE# to go HIGH 1 cycle sooner than shown here. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 46: Burst WRITE Followed by Burst READ tCLK CLK VIH VIL tSP tSP tHD VIH A[21:0] VIL Valid address Valid address tHD tSP tSP tHD ADV# VIH VIL tHD tSP VIH LB#/UB# VIL tCSP CE# OE# VIL tCBPH tOHZ Note 2 tCSP tHD tSP VIH WE# VIL WAIT tHD VIH VIL VIH tHD tSP tHD VOH VOL DQ[15:0] VIH IN/OUT VIL tBOE High-Z tSP tHD tACLK High-Z tKOH VOH High-Z D0 D1 D2 D3 VOL High-Z Valid output Valid output Valid output Don't Care Notes: Valid output Undefined 1. Nondefault BCR settings for burst WRITE followed by burst READ: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. CE# can stay LOW between burst READ and burst WRITE operations, but CE# must not remain LOW longer than tCEM. See burst interrupt diagrams (Figures 47 through 49 on pages 60 through 62) for cases where CE# stays LOW between bursts. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 47: Burst READ Interrupted by Burst READ or WRITE tCLK VIH CLK VIL VIH A[21:0] VIL ADV# VIH VIL VIH CE# VIL tSP READ burst interrupted with new READ or WRITE. See Note 2. tSP tHD Valid address tHD tSP tHD tSP tCEM (Note 3) tCSP tHD tSP tHD tSP tHD VIH WE# VIL WAIT tHD Valid address VOH tKHTL tBOE tBOE High-Z VOL tOHZ tOHZ OE# VIH 2nd cycle READ VIL tCEW LB#/UB# VIH 2nd cycle READ VIL tACLK DQ[15:0] OUT VOH 2nd cycle READ VOL High-Z tKOH tKOH Valid output High-Z Valid output Valid output Valid output D2 D3 tACLK OE# VIH 2nd cycle WRITE VIL LB#/UB# VIH 2nd cycle WRITE VIL DQ[15:0] IN VIH 2nd cycle WRITE VIL Valid output tSP tHD High-Z D0 D1 Don't Care Notes: Undefined 1. Nondefault BCR settings for burst READ interrupted by burst READ or WRITE: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision. 2. Burst interrupt shown on first allowable clock (such as after the first data received by the controller). PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 48: Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode WRITE burst interrupted with new WRITE or READ. See Note 2. tCLK CLK VIH VIL tSP tHD VIH A[21:0] VIL tSP tHD tSP tSP tHD VIH ADV# VIL tCEM (Note 3) tCSP VIH CE# VIL tHD tSP tHD VIH WE# VIL WAIT tSP tHD Valid address tKHTL VOH VOL tHD Valid address Valid address High-Z High-Z tCEW OE# VIH 2nd cycle WRITE VIL tSP tHD LB#/UB# VIH 2nd cycle WRITE VIL tSP tSP tHD DQ[15:0] IN VIH 2nd cycle WRITE VIL High-Z D0 OE# VIH 2nd cycle READ VIL LB#/UB# VIH 2nd cycle READ VIL tHD D1 D0 D2 tHD tSP tACLK DQ[15:0] OUT VOH 2nd cycle READ VOL VOH VOL High-Z tKOH Valid output Valid output Valid output Don't Care Notes: D3 tOHZ tBOE Valid output Undefined 1. Nondefault BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision. 2. Burst interrupt shown on first allowable clock (such as after first data word written). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 49: Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode WRITE burst interrupted with new WRITE or READ. See Note 2. tCLK CLK VIH VIL ADV# VIH VIL CE# VIH VIL WE# VIH VIL WAIT tSP tSP VIH A[21:0] VIL Valid address Valid address tAVH tAVH tSP tHD tCEM (Note 3) tHD tCSP tSP tHD tSP tHD Valid address tKHTL VOH VOL tHD tSP High-Z High-Z tCEW OE# VIH 2nd cycle WRITE VIL tSP tHD LB#/UB# VIH 2nd cycle WRITE VIL tSP tSP tHD DQ[15:0] IN VIH 2nd cycle WRITE VIL High-Z OE# VIH 2nd cycle READ VIL D0 D1 D2 D3 tOHZ tBOE tSP tHD LB#/UB# VIH 2nd cycle READ VIL DQ[15:0] OUT VOH 2nd cycle READ VOL VOH VOL tKOH High-Z tACLK Notes: tHD D0 Valid output Valid output Valid output Don't Care Valid output Undefined 1. Nondefault BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed latency mode: fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. Burst interrupt shown on first allowable clock (such as after first data word written). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 62 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 50: Asynchronous WRITE Followed by Burst READ tCLK VIH CLK VIL tWC VIH A[21:0] VIL Valid address tAVS ADV# VIH VIL VIH LB#/UB# VIL CE# VIH VIL tWC tVPH tSP Valid address tHD tSP Valid address tAVH tVP tAW tWR tVS tBW tCVS tCW tSP tCBPH tAS tHD tHD tCSP Note 2 tOHZ VIH OE# VIL VIH WE# VIL WAIT tAS tWC tWP tWPH tSP tHD tCEW VOH VOL DQ[15:0] VIH IN/OUT VIL tBOE High-Z Data Data tDH Notes: VOH VOL High-Z tKOH tACLK High-Z tDW Valid output Valid output Valid output Don't Care Valid output Undefined 1. Nondefault BCR settings for asynchronous WRITE followed by burst READ: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 63 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 51: Asynchronous WRITE (ADV# LOW) Followed by Burst READ tCLK CLK VIH VIL A[21:0] VIH VIL ADV# LB#/UB# CE# OE# WE# WAIT DQ[15:0] IN/OUT tWC tWC Valid address Valid address tAW tSP Valid address tWR tSP tHD VIH VIL tBW VIH tHD tHD tSP VIL VIH tCW tCBPH VIL tCSP Note 2 tOHZ VIH tWC tWP tWPH VIL VIH tSP tHD VIL tCEW VOH tBOE VOL VIH VIL High-Z Data tDH Notes: Data VOH VOL High-Z tKOH tACLK High-Z tDW Valid output Valid output Valid output Valid output Don't Care Undefined 1. Nondefault BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 64 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 52: Burst READ Followed by Asynchronous WRITE (WE#-Controlled) tCLK VIH CLK A[21:0] VIL VIH VIL VIH ADV# CE# tSP tHD tWC Valid address Valid address tSP tHD VIL VIH tCSP WE# VIH tCW Note 2 VIL VIL tCBPH tHZ tBOE VIH OE# tWR tAW tHD tSP tHD tOHZ tAS tOLZ tWP tWPH VIL VIH tHD tSP tBW LB#/UB# VIL VOH WAIT VOL DQ[15:0] tKHTL tCEW tCEW High-Z High-Z tKOH tACLK VOH High-Z VOL tDH tDW Valid output READ burst identified (WE# = HIGH) Notes: tHZ Valid input Don't Care Undefined 1. Nondefault BCR settings for burst READ followed by asynchronous WE#-controlled WRITE: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 53: CLK A[21:0] CE# tCLK VIH VIL VIH VIL ADV# Burst READ Followed by Asynchronous WRITE Using ADV# VIH tHD tSP Valid address tHD tSP tVPH tHD VIL VIH tCSP WE# VIH VIL VIH tAS tCW Note 2 VIL VIL tAW tCBPH tHZ tOHZ tBOE VIH OE# Valid address tAVH tAVS tVS tVP tSP tHD tAS tOLZ tHD tSP tWP tWPH tBW LB#/UB# VIL VOH WAIT VOL tKHTL tCEW tCEW High-Z High-Z tACLK DQ[15:0] VOH High-Z VOL tKOH tDW tDH Valid input Valid output READ burst identified (WE# = HIGH) Notes: tHZ Don't Care Undefined 1. Nondefault BCR settings for burst READ followed by asynchronous WRITE using ADV#: fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH or b) CE# HIGH for longer than 15ns. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 66 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 54: A[21:0] Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW VIH VIL Valid address Valid address tAW Valid address tAA tWR VIH ADV# LB#/UB# CE# VIL tBW VIH tBLZ tBHZ VIL tCPH tCW VIH tHZ Note 1 VIL tLZ OE# VIH WAIT tWC tWPH VIL tAS WE# tOHZ tOE tWP VIH VIL tHZ tHZ VOH VOL tOLZ DQ[15:0] VIH IN/OUT VIL High-Z Data tDH Notes: Data High-Z VOH Valid output VOL Don't Care tDW Undefined 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 67 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Timing Diagrams Figure 55: Asynchronous WRITE Followed by Asynchronous READ A[21:0] ADV# LB#/UB# CE# VIH Valid address VIL VIH tAVS tVPH tVP Valid address tAVH tAW tVS VIL VIL WE# WAIT tHZ tCPH tCW VIH tBHZ tBLZ tBW tCVS VIH VIL Note 1 tAS OE# Valid address tAA tWR tLZ tOHZ VIH VIL tAS tWP VIH tWC tWPH tOLZ VIL VOH VOL DQ[15:0] VIH IN/OUT VIL tOE High-Z Data tDH VOH Data tDW VOL High-Z Valid output Don't Care Notes: Undefined 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 68 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved. 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory Package Information Package Information Figure 56: 54-Ball VFBGA 0.70 0.05 Seating plane Solder ball material: 96.5% Sn, 3% Ag, 0.5% Cu Solder ball pad: O0.30 solder mask defined A 0.10 A Substrate material: plastic laminate 54X O0.37 Solder ball diameter refers to post-reflow condition. The pre-reflow diameter is 0.35. 3.75 Mold compound: epoxy novolac 0.75 TYP Ball A1 ID Ball A1 ID 4.00 0.05 Ball A6 Ball A1 8.00 0.10 6.00 3.00 0.75 TYP 1.875 3.00 0.05 1.00 MAX 6.00 0.10 Notes: 1. All dimensions are in millimeters; MAX/MIN or typical (TYP) where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W4MW16BCGB uses "green" packaging. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Qimonda AG outside the U.S. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef8247bd51/Source: 09005aef8247bd83 64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN 69 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2005 Micron Technology, Inc. All rights reserved.