MCP2021P-500E/SN - Microchip Technology

MCP2021/2/1P/2P

Features

• The MCP2021/2/1P/2P are compliant with LIN

Bus Specifications 1.3, 2.0, and 2.1 and are

compliant to SAE J2602

• Support Baud Rates up to 20 Kbaud with

LIN-compatible output driver

• 43V Load dump protected

• Very low EMI meet s stri ng ent OEM requi rem ents

• Wide supply voltage, 6.0V - 18.0V continuous:

- Maximum input voltage of 30V

• Extended Temperature Range: -40 to +125°C

• Interface to PIC EUSART and standard USARTs

• Local Interconnect Network (LIN) bus pin:

- Internal pull-up resistor and diode

- Protected again st grou nd sho rts

- Protected again st los s of groun d

- High current drive

• Automatic thermal shutdown

• On-Chip Voltage Regula tor:

- Output voltage of 5.0V with tolerances of

±3% overtemperature range

- Available with alternate output voltage of

3.3V with tolerances of ±3% overtemperature

range

- Maximum continuous input voltage of 30V

- Internal thermal overload protection

- Internal short circuit current limit

- External components limited to filter capacitor

only and load c apacitor

• Two low-power modes:

- Receiver on, Transmitter off, voltage

regulator on (≅85 µA)

- Receiver monitoring bus, Transmitter off,

voltage regulator off (≅16 µA)

Description

The MCP2021/2/1P/2P provides a bidirectional, half-

duplex communi catio n physic al interfa ce to auto motive

and industrial LIN systems that meets the LIN bus

specification Revision 2.0. The devices incorporate a

voltage regulator with 5V at 50 mA or 3.3V at 50 mA

regulated power-supply outputs.

The regul ator is short-circuit prot ected, and is p rotected

by an interna l thermal shut down circuit. The de vice has

been s pecifica lly des igned to operate in the a utomotiv e

operating environment and will survive all specified

transient conditions while meeting all of the stringent

quiescent current requirements.

The MCP2021/2/1P/2P family of devices includes the

following packa ges.

8-pin PDIP, DFN and SOIC packages:

• MCP202 1-3 30, LIN -c om p a tibl e d r iv er, 8-p in, 3.3 V

regulator, wake up on dominant level of LBUS

• MCP202 1-5 00, LIN -c om p a tibl e d r iv er, 8-p in, 5.0 V

regulator, wake up on dominant level of LBUS

• MCP202 1P-3 30, LIN- com p atible driver, 8-pin,

3.3V regulator, wake up at falling edge of LBUS

voltage

• MCP202 1P-5 00, LIN- com p atible driver, 8-pin,

5.0V regulator, wake up at falling edge of LBUS

voltage

14-pin PDIP, TSSOP and SOIC pack ages wit h RESET

output:

• MCP2022-330, LIN-compatible driver, 14-pin,

3.3V regulator, RESET output, wake up on domi-

nant level of LBUS

• MCP2022-500, LIN-compatible driver, 14-pin,

5.0V regulator, RESET output, wake up on domi-

nant level of LBUS

• MCP202 2P-3 30, LIN- c omp atible driver, 14-pin,

3.3V regulator, RESET output, wake up at falling

edge of LBUS voltage

• MCP202 2P-5 00, LIN- c omp atible driver, 14-pin,

5.0V regulator, RESET output, wake up at falling

edge of LBUS voltage

LIN Transceiver with Voltage Regulator

MCP2021/2/1P/2P

Package Types

MCP2021/2 Block Diagram

MCP2021

DFN-8, PDIP-8, SOIC-8

MCP2022

PDIP-14, SOIC-14, TSSOP-14

RXD

CS/LWAKE

VREG

TXD

FAULT/TXE

VBB

LBUS

VSS

RXD

CS/LWAKE

VREG

TXD

RESET

FAULT/TXE

VBB

LBUS

VSS

MCP2021P MCP2022P

Voltage

Regulator Ratiometric

Reference

Thermal

Protection

Internal Circuits

VREG

FAULT/TXE

RXD

TXD

VBB

LBUS

VSS

~30 kΩ

CS/LWAKE

Wake-Up

Logic and

Power Control

RESET

Short Circuit

Protection

Short Circuit

Protection

Thermal

Protection

(MCP2022 ONLY)

–

MCP2021/2/1P/2P

MCP2021P/2P Block Diagram

Ratiometric

Reference

Internal Circuits

VREG

RXD

TXD

VBB

VSS

~30

Wake-Up

Logic and

Power Control

RESET

Thermal

Protection

kΩ

(MCP2022P ONLY)

LBUS

Short-Circuit

Prot ection

CS/LWAKE

FAULT/TXE

–

Voltage

Regulator

Short-Circuit

Protection

Thermal

Short-Circuit

Protection

and

MCP2021/2/1P/2P

NOTES:

MCP2021/2/1P/2P

1.0 DEVICE OVERVIEW

The MCP2021/2/1P/2P provides a physical interface

betwee n a mi crocon troller and a LI N hal f-duple x bus . It

is intended for automotive and industrial applications

with serial bus speeds up to 20 Kbaud.

The MCP2021 /2/1P/2P prov ides a half-du plex, bidire c-

tional communications interface between a microcon-

troller and the serial network bus. This device will

translate the CMOS/TTL logic levels to LIN-level logic,

and vice ver sa.

The LIN specification 2.0 requires that the trans-

ceiver(s) of all nodes in the system be connected via

the LI N pin, refer enced to g round, and wit h a maxi mum

external termination resistance load of 510Ω from LIN

bus to batt ery supply. The 510Ω cor resp onds to 1 Ma s-

ter and 16 Slave nodes.

The MCP2021/2/1P/2P-500 provides a +5V, 50 mA,

regulated power output. The regulator uses an LDO

design, is short-circuit protected, and will turn the

regulator output off if it falls below 3.5V.

The MCP2021/2/1P/2P also includes thermal-

shutdown protection.

The regulator is specifically designed to operate in the

automotive environment and will survive +43V load

dump transients, double-battery jumps, and reverse

battery connections when a reverse blocking diode is

used. The other members of the MCP2021/2/1P/2P-

330 fami ly output +3.3V at 50 mA with a turn-off volt age

of 2.5V. (See Section 1.6 “Internal Voltage

Regulator”).

MCP2021/2 wakes from Power-Down mode on a

dominant level on LBUS. MCP2021P/2P wakes at a

transition from recessive level to dominant level on

LBUS.

1.1 Optional External Protection

1.1.1 REVERSE BATTERY PROTECTION

An external reverse-battery-blocking diode should be

used to provide polarity protection (see Figure 1-6).

1.1.2 TRANSIENT VOLTAGE

PROTECTION (LOAD DUMP)

An external 43V transient suppressor (TVS) diode,

between VBB and ground, with a 50Ω tran s ie nt pr o t ec -

tion resistor (RTP) in series with the battery supply and

the VBB pin protect the device from power transients

(see Figure 1-6) and ESD eve nts . While this pro tectio n

is optional, it is considered good engineering practice.

The resi stor value is chosen ac cording to Equation 1-1.

EQUATION 1-1:

1.2 Internal Protection

1.2.1 ESD PROTECTION

For component-level ESD ratings, please refer to the

Section 2.1 “Absolute Maximum Ratings†”.

1.2.2 GROUND LOSS PROTECTION

The LIN Bus specification states that the LIN pin must

transiti on to the rec essive st ate when ground is discon-

nected. Therefore, a loss of ground effectively forces

the LIN line to a hi-impedance level.

1.2.3 THERMAL PROTECTION

The thermal protection circuit monitors the die temper-

ature and is able to shut down the LIN transmitter and

voltage regulator if it detects a thermal overload.

There are three causes for a thermal overload. A ther-

mal shut down can be triggered by any one, or a com-

bination of, the following thermal overload conditions:

• Voltage regu lator overload

• LIN bus output overload

• Increase in die temperature due to increase in

environmental temperature

Driving the TXD and checking the RXD pin makes it

possib le to determine whether there is a bus co ntention

(i.e., Rx = low, Tx = high) or a thermal overload condi-

tion (i.e., Rx = high, Tx = low).

RTP <= ( VBBmin - 5.5) / 250 mA.

5.5V = VUVLO + 1.0V,

250 mA is the peak current at Power-On when

VBB = 5.5V

MCP2021/2/1P/2P

FIGURE 1-1: Thermal Shutdown State Diagrams.

1.3 Modes of Operation

For an overview of all operational modes, please refer

to Table 1-1.

1.3.1 POWER-ON RESET MODE

Upon application of VBB, the device enters Power-on

Reset mode (POR). During this mode, the part main-

ta ins the digit al se ction i n a Res et mode and wa its until

the voltage on pin VBB rises above the “ON” threshold

(Typ. 5.75V) to enter to the Ready mode. If during the

operat ion, the vo lta ge on pin VBB fal ls below the “OFF”

threshold (T yp. 4.25V), the part comes back to the POR

mode.

1.3.2 POWER-DOWN MODE

In the Power-Down mode, the transmitter and the

voltage regulator are off. Only the receiver wake-up

from LIN bus section, and the CS/LWAKE pin wake-up

circuit s are in operation. This is the lowest p ower mode.

If pin CS/LWAKE goes to a high level during Power-

Down mode, the device immediately enters Ready

mode and enables the voltage regulator; and after the

output has stabili zed (app roximately 0.3 m s to 1.2 ms),

the device goes to Operation mode or Transmitter-Off

mode (see Figure 1-2 for MCP2021/2 and Figure 1-3

for MCP2021P/2P).

LIN bus activity will also change the device from

Power-Down mode to Ready mode. MCP2021/2

wakes up on dominant level of LIN bus, and

MCP2021P/2P on a falling edge that follows a domi-

nant level lasting 20 µs of time.

The Pow er-Dow n mo de can be rea che d th rou gh either

Operation mode or Transmitter-Off mode.

1.3.3 READY MODE

Upon entering Ready mode, the voltage regulator and

receiver-threshold-detect circuit are powered up. The

tran smitt er remai ns i n off sta te. T he d evi ce is r ead y to

receive data as soon as the regulator is stabilized, but

not to transmit. If a microcontroller is being driven by

the voltage regulator output, it will go through a POR

and initi ali zatio n seque nce. Th e LIN pin is in the re ces-

sive state for MCP2021/2 and in floating state for

MCP2021P/2P.

The device will stay in Ready mode until the output of

the volt age regulato r has sta bilized and the C S/L W AKE

pin is true (‘1’). After VREG is stable and CS/LWAKE is

high, MCP2021/2 will enter Operation mode; and

MCP2021P/2P will enter either Operation mode or

Transmitter-Off mode, depending on the level of the

FAULT/TXE pin (refer to Figure 1-3).

1.3.4 OPERATION MODE

In this mode, all internal modules are operational.

The device will go into the Power-Down mode on the

falling edge of CS/LWAKE.

For the MCP2021P/2P devices, the pull-up resistor is

switched on only in this mode.

Operation

Mode Transmitter

Shutdown

LIN B us

Voltage

Shutdown

Regulator

Output

Temperature <SHUTDOWN

TEMP

Overload

to V

Overload

Temperat ure <SHUTDOWN

TEMP

Note: The ab ov e tim e in terv al <1.2 ms as su me s

12V VBB input and no thermal shutdown

event.

MCP2021/2/1P/2P

1.3.5 TRANSMITTER-OFF MODE

Whenever the FAULT/TXE signal is low, or permanent

dominant on TXD/LBUS is detected, the LBUS

transmitter is of f.

The transmitter may be re-enabled whenever the

FAULT/TXE signal returns hi gh, eithe r by removing the

internal fault condition or when the CPU returning the

FAULT/TXE high. The tran sm itt er wi ll not be ena bl ed if

the FAULT/TXE pin is brought high when the internal

fault is still present.

If TX-OFF mode is caused by TXD/LBUS permanent

dominant level, the transmitter can recover when the

permanent dominant status disappears.

The transm it ter is als o turn ed o ff whenev er th e vol t ag e

regulator is unstable or recovering from a fault. This

prevents unwanted disruption of the b us during times of

uncertain operation.

1.3.6 WAKE-UP

The Wake-Up sub-module observes the LBUS in order

to detect bus activity. Bus activity is detected when the

volt age on th e LBUS st ay s belo w a thresh old of ap pro x-

imately 0.4VBB for at least a typical duration of 20 µs.

The MCP2021/2 device is level sensitive to LBUS. Dom-

inant level longer than 20 µs will cause the device to

leave the Power-Down mode. The MCP2021P/2P

device is falling-edge sensitive to LBUS. Only the LBUS

transition from recessive to dominant followed by at

least 20 µs dominant level can wake up the device.

Putting CS/LWAKE to high level also wakes up the

device. Refer to Figure 1-2 and Figure 1-3.

1.3.7 DIFFERENCE DETAILS BETWEEN

MCP2021/2 AND MCP2021P/2P

The MCP202xP is a minor variation of the MCP202x

device that adds improved state machine control as

well as the ability to disconnect the internal 30kΩ pull-

up between LIN and VBB in all modes except normal

operation. These changes allow the system designer

to better handle fault conditions and reduce the overall

system current consumption. The differences between

the two device versions are as follows:

1. Switchable LIN-VBB Pull-Up Resistor:

On the MCP202xP device, the internal 30kΩ

pull-up resistor is disconnected in all modes

except Operation Mode. On the MCP202x

device , this pull-up resistor is a lways conne cted.

(See the MCP2021/2 Block Diagram and the

MCP2021P/2P Block Diagram for details.)

2. Power Down Wake-up on LIN Traffic:

The MCP202xP device requires a LIN falling

edge to generate a valid Wake condition due to

bus traffic. The MCP202x device will generate a

Wake anytime LIN is at a valid dominant level.

Because of this, if the LIN bus becomes perma-

nently shorted, it becomes impossible to place

the MCP202x in a low power state.

3. State Machine Options:

The MCP202xP device is able to enter Trans-

mitter Off Mode from Ready Mode without tran-

sitioning through Operation Mode. The

MCP202x device must enter Operation Mode

from Ready Mode. (See State Machine Dia-

grams, Figure 1-2 and Figure 1-3 for details).

This capability allows the system designer to

monitor the bus in Ready Mode to determine if

the syste m should transiti on to normal operatio n

and connect the internal pull-up or if Ready

Mode was reached due to an invalid condition.

In the case of an invalid condition, the

MCP202xP device can be placed into Power

Down m ode wit hout connec ting the interna l pull-

up and waking other nodes on the LIN Bus net-

work.

To properly take advantage of the device differences

will require the system designer to implement some

microc ontroller co de to the power-up routi ne. This c ode

will monitor the status of the LIN bus to determine how

the dom inant signa l sho uld be respo nded t o. I t will a lso

determine if the local LI N node need s to respond or can

‘Listen Only’. If the local LIN node does not need to

respond , it can enter T ransmitter Off Mode, disconnect-

ing the 3 0kΩ pull- up, reducing mod ule current while still

maintaining the ability to properly receive all valid LIN

messages.

Note: To enter Transmitter Off, the system must

set TXE ‘low’ before pulling CS high (see

Figur e 1-5). Oth erwise, if CS is p ulled hig h

first, the MCP202xP will enter Operation

Mode due to the internal pull-up on TXE.

MCP2021/2/1P/2P

FIGURE 1-2: MCP2021/2 Operational Modes State Diagrams.

FIGURE 1-3: MCP2021P /2P Operati on al Mod es State Diag ra ms.

Power-Down

TX: OFF

RX: OFF

VREG: OFF

CS/LWAKE=0

Transmitter Off

TX: OFF

RX: ON

VREG: ON

POR

TX: OFF

RX: OFF

VREG: OFF

Operation

TX: ON

RX: ON

VREG: ON

Ready

TX: OFF

RX: ON

VREG: ON

VBAT>5.75V

CS/LWAKE=1&

VREG_OK=1

CS/LWAKE=0

FAULT/TXE=0

Or Faults*

FAULT/TXE=1

&No Faults*

CS/LWAKE=1

or dominant level on LBUS

Start

*Fault: thermal shutdown and TXD/LBUS permanent dominant

Note: While the device is in shutdown, TXD should not be actively driven high or it may power internal logic

through the ESD diodes and may damage the device.

Power-Down

TX: OFF

RX: OFF

VREG: OFF

CS/LWAKE=0

Transmitter Off

TX: OFF

RX: ON

VREG: ON

POR

TX: OFF

RX: OFF

VREG: OFF

Operation

TX: ON

RX: ON

VREG: ON

Ready

TX: OFF

RX: ON

VREG: ON

VBAT>5.75V

CS/LWAKE=1&

VREG_OK=1&

FAULT/TXE=1

CS/LWAKE=0

FAULT/TXE=0

Or Faults*

FAULT/TXE=1

&No Faults*

CS/LWAKE=1

or Falling edge on LBUS

Start

*Fault: thermal shutdown and TXD/LBUS permanent dominant

CS=1&VREG_OK=1

&FAULT/TXE=0

MCP2021/2/1P/2P

FIGURE 1-4: MCP2021P/2P Wake-Up Due to Bus Disconnecting.

Ready

State

Sleep

LBUS

nFAULT_TXE

VREG

CS_LWAKE

MCP2021/2/1P/2P

FIGURE 1-5: Forced Power-Down Mode Sequence for MCP2021P/2P.

CS/LWAKE

VREG

FAULT/TXE

LBUS

Operation Mode Transmitter-Off

Mode Power-Down

Mode

tCSactive> = 2S

FAULT/TXE = 1

Forced internally

FAULT/TXE = 0

Forced exte rnally

LBUS disconnected;

e.g., Master pull-up &

internal resistor off;

LBUS floating.

Forced Power-Down Mode after BUS-OFF

instruction or a longer LIN-Bus inactivity

( > = 4 sec according to LIN specification)

STATE

MCP2021/2/1P/2P

TABLE 1-1: OVERVIEW OF OPERATIONAL MODES

State Transmitter Receiver Voltage

Regulator Operation Comments

POR OFF OFF OFF Read VBB; if VBB>5.75V, enter Ready

mode

Ready OFF ON ON MCP2021/2:

If CS/LWAKE is high level, then Operation

mode.

MCP2021P/2P:

If CS/LWAKE is high level and FAULT/TXE

is high level, then Operation mode.

If CS/LWAKE is high level and FAULT/TXE

is low level, then TXOFF mode.

Bus Off state

Operation ON ON ON If CS/LWAKE is low level, then Power-

Down mode.

If FAULT/TXE is low level or T XD/LBUS

permanent dominant is detected, then

Transmitter-Off mode.

Normal

Operation

mode

Power-Down OFF Activity

Detect OFF On LIN bus falling, go to Ready mode. On

CS/LWAKE high level, go through Ready

mode; then, to either operation or

Transmitter-Off mode (refer to Figure 1-2

and Figure 1-3).

Low Power

mode

Transmitter-Off OFF ON ON If CS/LWAKE is low level, then Power-

Down mode.

If FAULT/TXE is high, then Operation

mode.

MCP2021/2/1P/2P

1.4 Pin Descriptions

TABLE 1-1: PINOUT DESCRIPTIONS

1.4.1 POWER OU TP UT (VREG)

Positive Supply Voltage Regulator Output pin.

1.4.2 GROUND (VSS)

Ground pin .

1.4.3 BATTERY (VBB)

Battery Pos itive Supply Volt age pin. This pin is also the

input for the internal voltage regulator.

1.4.4 TRANSMIT DATA INPUT (TXD)

The Transmit Data Input pin has an internal pull-up to

VREG. Th e LI N p i n i s l o w ( dom i nan t ) wh en T XD is lo w,

and high (recessive) when TXD is high.

For extra bus security, TXD is internally forced to ‘1’

when VREG is less than 1.8V (typ.).

If the thermal protection detects an over-temperature

condition while the signal TXD is low, the transmitter is

shut dow n. The recov ery from the the rma l shu t do w n is

equal to adequate cooling time.

1.4.5 RECEIVE DATA OUTPUT (RXD)

The Receive Data Output pin is a standard CMOS

output and follows the state of the LIN pin.

1.4.6 LIN BUS

The bidirec tiona l LIN bus Int erface pin is the driver unit

for the LIN pin and i s co ntro ll ed by the sig nal TXD. LIN

has an open collector output with a current limitation.

To reduce EMI, the edges during the signal changes

are slope-controlled. To further reduce radiated emis-

sions, the LBUS pin has corner-rounding control for both

falling and rising edges.

The intern al LIN recei ver obs erves the ac tiv iti es o n th e

LIN bus, and generates output signal RXD that follows

the state of the LBUS. A 1st degree with 1 µS time con-

stant (160KhZ), low-pass input filter is placed to

maintain EMI immunity.

1.4.7 CS/LWAKE

Chip Sele ct In put pin . A i nter nal pull- dow n re sisto r wi ll

keep the CS/LWAKE pin low. This is done to ensure

that no disruptive data will be present on the bus while

the microcontroller is executing a POR and I/O initial-

ization sequence. The pin must see a high level to

activate the transmitter.

If CS/LWAKE= ‘0’ when the VBB supply is turned on,

the device stays in Ready mode (Low-Power mode). In

Ready mode, both the receiver and the voltage

regulator are on and the LIN transmitter driver is off.

If CS/LWAKE = ‘1’ when the VBB supply is turned on,

the devic e will pro ceed to either Operation or T ransmit-

ter-Off mode (refer to Figure 1-2 and Figure 1-3) after

the VREG output has stabilized.

This pin may also be used as a local wake-up input

(see Figure 1-6). In this implementation, the microcon-

troller will set the I/O pin that controls the CS/LWAKE

as an high-impedance input. The internal pull-down

resistor will keep the input low. An external switch, or

other source, can then wa ke up the transcei ver and th e

microcontroller.

Name

Devices

Type

Function

8-Pin

DFN,

PDIP,

SOIC

14-Pin

PDIP,

SOIC,

TSSOP

Normal Operation

VREG 3 3 O Power Output

VSS 5 11 P Ground

VBB 7 13 P Battery Supply

TXD 4 4 I Transmit Data Input (TTL)

RXD 1 1 O Receive Data Output (CMOS)

LBUS 6 1 2 I/O LIN bus (bidir ec tion al )

CS/LWAKE 2 2 TTL Chip Select (TTL)

FAULT/TXE 8 14 OD Fault Detect Output, Transmitter Enable (OD)

RESET — 5 OD RESET signal Output (OD)

Legend: O = Output, P = Power, I = Input, TTL = TTL input buffer, OD = Open-Drain output

Note: CS/LWAKE should not be tied directly to

VREG as this could force the MCP2 02x into

Operation mode before the

microcontroller is initialized.

MCP2021/2/1P/2P

1.4.8 FAULT/TXE

Fault Detect Output and Transmitter Enable Input

bidirectional pin.

This pin is an open-drain output. Its state is defined as

shown in Table 1-2. The transmitter driver is disabled

whenever this pin is low (‘0’), either from an internal

fault condition or by external drive. This allows the

transmi tter to be place d in an off st ate and st ill allow the

voltage regulator to operate. Refer to Table 1-1.

The FAULT/TXE also signals a mismatch between the

TXD input and the LBUS level. This can be used to

detect a bus contention. Since the bus exhibits a

propagation delay, the sampling of the internal

compare is debounced to eliminate false faults.

This pin has an internal pull-up resistor of

approximately 750 kΩ.

The F AUL T/TXE pin sampled at a rate faster than e very

10 µs.

TABLE 1-2: FAULT/TXE TRUTH TABLE

1.4.9 RESET

RESET is an open-drain output pin. This pin reflects an

internal signal that tracks the internal system voltage

has reached a valid, stable level.

As long as the in ternal volt age is valid, this pi n will keep

high im pedance. When the system vol tage drops below

the minimum required, the voltage regulator will shut

down and immediately convert the RESET output to

short to GND. A pull-up resistor is needed to change

the output to high/low voltage. When connected to a

micro-controller input, this can provide a warning that

the volt age regulator is shut ting down (see Figure 1-2).

Alternately, it can act as an external brown-out by con-

necting the RESET output to MCLR (see Figure 1-2). In

addition to monitoring the internal voltage, RESET is

asserted immediately upon entering the Power-Down

mode.

Note 1: The FAULT/TXE pi n is tr ue (0) whenev er

the internal circuits have detected a short

or thermal excursion and have disabled

the LBUS outp ut driv er.

2: FAULT/TXE is true ( 0) when VREG not OK

and has disabled the LBUS output driver.

TXD

In RXD

Out LINBUS

I/O Thermal

Override

FAULT/TXE

Definition

External

Input Driven

Output

LHV

BB OFF H L FAULT, TXD d riven low, LINBUS shorted to

VBB (Note 1)

HHV

BB OFF H H OK

LLGND OFF H HOK

HLGND OFF H HOK, data is being received from the LINBUS

xxVBB ON H L FAULT, transceiver in thermal shutdown

xxV

BB xLxNO F AULT, the CPU is commanding the

transceiver to turn off the transmitter driver

Legend: x = don’t care

Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault

reporting during bus propagation delays.

MCP2021/2/1P/2P

1.5 Typical Application s

FIGURE 1-6: Typical MCP202 1/MC P2021P Applic ati on.

LIN Bus

27V(4)

VBB

LBUS

VREG

TXD

RXD

VSS

VDD

TXD

RXD

+12

CS/LWAKE

I/O

FAULT/TXEI/O

43V(5)

1kΩ

+12

Master Node Only

+12

220 kΩ

WAKE-UP

Note 1: See Figure 2-3 for correct capacity and ESR for stable operation..

2: CF is the filter capacitor for the external voltage supply.

3: This diode is only needed if CS/LWAKE is connected to a 12V supply.

4: Transient suppressor diode. Vclamp L = 43V.

5: These components are required for additional load dump protection above 43V.

(3)

RTP(5)

100 pF

MCP2021/2/1P/2P

FIGURE 1-7: Typical MCP202 2/MC P2022P Applic ati on.

FIGURE 1-8: Typical LIN Network Configuration.

LIN Bus

27V(4)

VBB

LBUS

VREG

TXD

RXD

VSS

VDD

TXD

RXD

+12

CS/LWAKE

I/O

FAULT/TXE

I/O

43V(5)

1kΩ

+12

Master Node Only

+12

220 kΩ

WAKE-UP

Note 1: See Figure 2-3 for correct capacity and ESR for stable operation.

2: CF is the filter capacitor for the external voltage supply.

3: This diode is only needed if CS/LWAKE is connected to a 12V supply.

4: Transient suppressor diode. Vclamp L = 43V.

5: These components are required for additional load dump protection above 43V.

6: Required if CPU does not have internal pull-up.

(3)

RTP(5)

100 pF

INT or MCLR RESET

VDD(6)

LIN bus

MCP202X

Master

µC

1kΩ

VBB

Slave 1

µC Slave 2

µC Slave n <16

µC

40m

+ Return

LIN bus

MCP202X LIN bus

MCP202X

MCP2021/2/1P/2P

1.6 Internal Voltage Regulator

1.6.1 5.0V REGULATOR

The MCP20 21 has a low-drop-out volt age, positive reg-

ulator capable of supplying 5.00 VDC ±3% at up to

50 mA of load cur rent over the entir e operating temp er-

ature range of -40°C to +125°C. With a load current of

50 mA, the minimum i npu t to output vol tage differential

required for the output to remain in regulation is typi-

cally + 0.5 V (+1V m ax imum ov er th e ful l o pera tin g tem -

perature range). Quiescent current is less than 100 µA

with a full 50 mA load current when the input to output

voltage differential is greater than +3.00V.

The regulator requires an external output bypass

capacitor for stability. See Figure 2-3 for correct

capacity and ESR for stable operation.

Desig ned for autom otive applica tions, the reg ulator will

prote ct itself from doubl e-batter y jumps and up to +43V

load dump transients. The voltage regulator has both

short-circuit and thermal-shut-down protection built in.

Regard ing th e correlatio n b etwee n VBB, VREG and IDD,

please refer to Figure 1-10 throughFigure 1-12. When

the input voltage (VBB) drops below the differential

needed to provide stable regulation, the output VREG

will track the input down to approximately 3.5V, at

which point the regulator will turn off. This will allow

microcontrollers with internal POR circuits to generate

a clean arming of the POR trip point . The MCP202 1 will

then monitor VBB and turn on the regulator when VBB

rises above 5.75, again.

When the input vo lt ag e (V BB) dro p s bel ow t he d ifferen-

tial needed to provide stable regulation, the output

VREG) will track the input down to approximately

+4.25V. The regulator will turn off the output at this

point. Th is will al low PIC® microcontrollers with internal

POR circuit s to generate a clean arming of the POR trip

point. The regulator output will stay off until VBB is

above +5.75 VDC.

In the st art phase, the device must detect at le ast 5.75V

to initiate operation during power up. In the Power-

Down mode, the VBB monitor will be turned off.

The regulator has a thermal shutdown. If the thermal

protecti on circuit detects an overtem perature co ndition,

and the signals TXD and RXD are LOW , or TXD is HIGH,

the regulator will shut down. The recovery from the

thermal shutdown is equal to adequate cooling time.

FIGURE 1-9: Voltage Regulator Block Diagram.

Note: The regulator has an overload current

limitin g of approximately 100 mA. Durin g a

short circuit, the VREG is monitored. If

VREG is lower than 3.5V, the VREG will turn

off. After a recovery time of about three

milliseconds, the VREG will be checked

again. If there is no short circuit (VREG

>3.5V), the VREG will be switched back on.

Pass

Element

Sampling

Network

Buffer

VREG VBB

VSS

Fast

Transient

Loop

VREF

MCP2021/2/1P/2P

1.6.2 3.3V REGULATOR

A metal option provides for a alternate 3.30 VDC ±3%

at up to 5 0 mA of loa d curre nt over the ent ire oper atin g

temperature range of -40°C to +125°C. All

specif icatio ns gi ven a bove for the 5.0V opera tion a pply

except for any difference noted here.

The same input tracking of 4.25V applies the 3.3V

regulator.

FIGURE 1-10: Voltage Regulator Output on POR.

Note: The regulator has an overload current

limiting of approximately 100 mA. If VREG

is lower than 2.5V, the VREG will turn off.

Note 1: Start-up, VBB < 5.75V, regulato r off.

2: VBB > 5.75V, regulator on.

3: VBB ≤ 5.5V, regulator tracks VBB.

4: VBB < 4.25V, regulator will turn off.

5.0

3.5

(1) (2) (3)

VBB

VREG

MCP2021/2/1P/2P

FIGURE 1-11: Voltage Regulator Output on Power Dip.

Note 1: Voltage regulator on.

2: VBB ≤ 5.5V, regulator tracks VBB until VBB < 4.25V.

3: VREG < 3.5V, regulator is off.

4: VBB > 5.75V, regulator on.

3.5

(1) (2) (3)

3.5

(4)

VBB

VREG

MCP2021/2/1P/2P

FIGURE 1-12: Voltage Regulator Output on Overcurrent Situation.

1.7 ICSP™ Considerations

The following should be considered when the

MCP2021/2/1P/2P is connected to pins supporting

in-circuit pro g r am mi ng:

• Pow er u sed for progra mming the microcontroller

can be supplied from the programmer or from the

MCP2021/2/1P/2P.

• The voltage on VREG should not exceed the

maximum output voltage of VREG.

Note 1: IREG less than 50 mA, regulator on.

2: After IREG exceeds IREGmax, voltage regulator output will be reduced until VREG off is reached.

5.0

3.5

(1) (2)

IREG

VREG

MCP2021/2/1P/2P

NOTES:

MCP2021/2/1P/2P

2.0 ELECTRICAL CHARACTERISTICS

2.1 Absolute Maximum Ratings†

VIN DC Voltage on RXD and TXD........................................................................................................-0.3 to VREG+0.3V

VIN DC Voltage on FAULT and RESET.........................................................................................................-0.3 to +5.5V

VIN DC Voltage on CS/LWAKE.......................................................................................................................-0.3 to +43V

VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) .....................................-0.3 to +43V

VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-200V

VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V

VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-300V

VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V

VBB Battery Voltage, continuous....................................................................................................................-0.3 to +30V

VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V

VLBUS Bus Voltage, transient (Note 1)............................................................................................................-27 to +43V

ILBUS Bus Short Circuit Current Limit....................................................................................................................200 mA

ESD protection on LIN, VBB (IEC 61000-4-2, 330 Ohm, 150 pF) (Note 3)...................... ...... ..... ...... ...... . mi nimum ±9 kV

ESD protection on LIN, VBB (Charge Device Model) (Note 2)..............................................................................±1500V

ESD protection on LIN, VBB (Human Body Model, 1 kOhm, 100 pF) (Note 4).......................................................±8 kV

ESD protection on LIN, VBB (Machine Model) (Note 2)..........................................................................................±800V

ESD protection on all other pins (Human Body Model) (Note 2)............................................................................> 4 kV

Maximum Junction Temperature.............................................................................................................................150°C

Storage Temperature ..................................................................................................................................-55 to +150°C

Note 1: ISO 7637/1 load dump compliant (t < 500 ms).

2: According to JESD22-A114-B.

3: According to IBEE, without bus filter.

4: Limited by Test Equipment.

† NOTICE: Stresses abov e th os e l ist ed u nd er “M ax im um Ratings” ma y c au se permanent dam ag e to the dev ic e. Thi s

is a stres s ratin g on ly and func ti onal operat ion of the dev ic e a t thos e or any oth er co nd itio ns abo ve those indi cated in

the opera tional listi ngs of this specificati on is not impli ed. Exposure to maximum rat ing conditio ns for extend ed periods

may affect device reliability.

MCP2021/2/1P/2P

2.2 DC Specifications

DC Specifications

Electri cal Characteristics:

Unless otherwise indicated, all limits are specified for:

VBB = 6.0V to 18.0V

TA = -40°C to +125°C

CLOADREG = 10 µF

Parameter Sym Min. Typ. Max. Units Conditions

Power

VBB Quies cent Operati ng

Current IBBQ 115 210 µA IOUT = 0 mA,

LBUS recessive

— 120 215 µA VOUT = 3.3V

VBB Transmi tte r-off

Current IBBTO — 90 190 µA With VREG on, transmitter

off, receiver on, F AULT/TXE

= VIL, CS = VIH

—95210µAVOUT = 3.3V

VBB Power-Down Current IBBPD —16 26µAWith VREG powered-off,

receiver on and transmitter

off, FAULT/TXE = VIH,

TXD = VIH, CS = VIL)

VBB Current with VSS

Floating IBBNOGND -1 —1mAVBB = 12V, GND to VBB,

VLIN = 0-18V

Microcontroller Interface

High Level Input Voltage

(TXD, FAULT/TXE) VIH 2.0 or

(0.25VREG

+0.8)

—VREG

+0.3 V

Low Level Input Voltage

(TXD, FAULT/TXE) VIL -0.3 —0.15 VREG V

High Level Input Current

(TXD, FAULT/TXE) IIH -2.5 ——µA Input voltage = 0.8*VREG

Low Level Input Current

(TXD, FAULT/TXE) IIL -10 ——µA Input voltage = 0.2*VREG

Pull-up Current on Input

(TXD) IPUTXD -3.0 ——µA ~800 kΩ internal pull-up to

VREG @ VIH = 0.7*VREG

High Level Input Voltage

(CS/LWAKE) VIH 0.7VREG —VBB V Through a curr ent- limitin g

resistor

Low Level Input Voltage

(CS/LWAKE) VIL -0.3 —0.3VREG V

High Level Input Current

(CS/LWAKE) IIH ——7.0 µA Input voltage = 0.8*VREG

Low Level Input Current

(CS/LWAKE) IIL ——3.0 µA Input voltage = 0.2*VREG

Pull-down Current on

Input (CS/LWAKE) IPDCS ——6.0 µA ~1.3MΩ internal pull-down

to VSS @ VIH = 3.5V

Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).

2: For design guidance only, not tested.

3: Node has to sustain the current that can flow under this condition; bus must be operational under this

condition.

MCP2021/2/1P/2P

Bus Interface

High Level Input Voltage VIH(LBUS)0.6 VBB —18 V Recessive state

Low Level Input Voltage VIL(LBUS)-8

—0.4 VBB V Dominant state

Input Hysteresis VHYS ——

0.175 VBB VVIH(LBUS) - VIL(LBUS)

Low L eve l O u tput C urre nt IOL(LBUS)40

—200 mA Output voltage = 0.1 VBB,

VBB = 12V

Pull-up Current on Input IPU(LBUS)5

—180 µA ~30 kΩ internal pull-up

@ VIH (LBUS) = 0.7 VBB

Short Circuit Current

Limit ISC 50 —200 mA (Note 1)

High Level Outp ut

Voltage VOH(LBUS)0.8 VBB —VBB VVOH(LBUS) must be at least

0.8 VBB

Low Level Output Voltage VOLLO

(LBUS)——0.2 VBB V

Input Leakage Current (at

the receiver during

dominant bus level)

IBUS_PAS_DOM -1 —— mA Driver off,

VBUS = 0V,

VBAT = 12V

Leakage Current

(disconnected from

ground)

IBUS_NO_GND -1 —+1 mA GNDDEVICE = VBAT,

0V < VBUS < 18V,

VBAT = 12V

Leakage Current

(disconnected from V BAT)IBUS ——10 µA VBAT = GND,

0 < VBUS < 18V,

TA = -40°C to +85°C

(Note 3)

50 µA TA = +85°C to +125°C

Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5

VBB 0.525 VBB VVBUS_CNT = ( VIL (LBUS) +

VIH (LBUS))/2

Slave Termination Rslave 20 30 47 kΩ

2.2 DC Specifications (Continued)

DC Specifications

Electri cal Characteristics:

Unless otherwise indicated, all limits are specified for:

VBB = 6.0V to 18.0V

TA = -40°C to +125°C

CLOADREG = 10 µF

Parameter Sym Min. Typ. Max. Units Conditions

Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).

2: For design guidance only, not tested.

3: Node has to sustain the current that can flow under this condition; bus must be operational under this

condition.

MCP2021/2/1P/2P

2.2 DC Specification (Continued)

FIGURE 2-1: MCP2021-500 Safe Operating Range.

DC Specifications

Electri cal Characteristics:

Unless otherwise indicated, all limits are specified for:

VBB = 6.0V to 18.0V

TA = -40°C to +125°C

CLOADREG = 10 µF

Parameter Sym Min. Typ. Max. Units Conditions

Voltage Regu lator - 5.0V

Output Volt age VOUT 4.85 5.00 5.15 V 0 mA < IOUT < 50 mA,

Load Regulation ΔVOUT2—1050mV5mA < IOUT < 50 mA

refer to Section 1.6

“Internal Voltage

Regulator”

Quiescent Current IVRQ —— 25µAIOUT = 0 mA, (Note 2)

Power Supply Ripple

Reject PSRR — — 50 dB 1 VPP @10-20 kHz

CLOAD = 10 µf,

ILOAD = 5 0 mA

Output Nois e Voltage eN — — 100 µVRMS 10 Hz – 40 MHz

CFILTER = 10 µf,

CBP = 0.1 µf, CLOAD 10 µf,

ILOAD = 5 0 mA

Shutdown Voltage VSD 3.5 — 4.0 V See Figure 1-8

Input Voltage to Maintain

Regulation VBB 6.0 — 18.0 V

Input Voltage to Turn Off

Output VOFF 4.0 — 4.5 V

Input Voltage to Turn On

Output VON 5.5 — 6.0 V

Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).

2: For design guidance only, not tested.

3: Node has to sustain the current that can flow under this condition; bus must be operational under this

condition.

-40

-34

-28

-22

-16

-10

-4

104

110

116

122

Temperatu re (°C)

Vol tage R egulator Load (mA )

18V DFN

18V SOIC

12V SOI C

12V DF N

MCP2021/2/1P/2P

2.2 DC Specification (Continued)

FIGURE 2-2: MCP2021-330 Safe Operating Range.

DC Specifications

Electri cal Characteristics:

Unless otherwise indicated, all limits are specified for:

VBB = 6.0V to 18.0V

TA = -40°C to +125°C

CLOADREG = 10 µF

Parameter Sym Min. Typ. Max. Units Conditions

Voltage Regu lator - 3.3V

Output Volt age VOUT 3.20 3.30 3.40 V 0 mA < IOUT < 50 mA

Line Regulation ΔVOUT1—1050mVIOUT = 1 mA,

6.0V < VBB < 18V

Load Regulation ΔVOUT2—1050mV5mA < IOUT < 50 mA

Refer to Section 1.6

“Internal Voltage

Regulator”

Quiescent Current IVRQ —— 25µAIOUT = 0 mA, (Note 2)

Power Supply Ripple

Reject PSRR — — 50 dB 1 VPP @10-20 kHz

CLOAD = 10 µf,

ILOAD = 5 0 mA

Output Nois e Voltage eN — — 100 µVRMS

/√Hz 10 Hz – 40 MHz

CFILTER = 10 µf, CBP =

0.1 µf CLOAD = 10 µf,

ILOAD = 5 0 mA

Shutdown Vol tage VSD 2.5 — 2.7 V See Figure 1-8

Input Voltage to Maintain

Regulation VBB 6.0 — 18.0 V

Input Voltage to Turn Off

Output VOFF 4.0 — 4.5 V

Input Voltage to Turn On

Output VON 5.5 — 6.0 V

Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).

2: For design guidance only, not tested.

3: Node has to sustain the current that can flow under this condition; bus must be operational under this

condition.

-40

-34

-28

-22

-16

-10

-4

104

110

116

122

Temp er at u r e (°C)

Voltage Regulator Load (mA)

18V DF N

18V SOIC

12V SOIC

12V DF N

MCP2021/2/1P/2P

FIGURE 2-3: ESR Curves for Load Capacitor Selection.

Load Capacitor [uF]

ESR Curves

ESR [ohm]

0.1

0.01

0.001

10 100 1000

10.1

Instable

Stable only

with Tantalum or

Electrolytic cap.

Stable with

Tantalum,

Electrolytic and

Ceramic cap.

MCP2021/2/1P/2P

2.3 AC Specification

AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40°C to +125°C

Parameter Sym Min. Typ. Max. Units Test Conditions

Bus Interface - Constant Slope Time Parameters

Slope rising and falling

edges tSLOPE 3.5 — 22.5 µ s 7.3V <= VBB <= 18V

Propagation Delay of

Transmitter tTRANSPD ——4.0µstTRANSPD = max (tTRANSPDR or

tTRANSPDF)

Propagation Delay of

Receiver tRECPD ——6.0µstRECPD = max (tRECPDR or

tRECPDF)

Sym m etry of Pr opagation

Delay of Receiver rising

edge w.r.t. falling edge

tRECSYM -2.0 — 2.0 µs tRECSYM = max (tRECPDF -

tRECPDR)

Sym m etry of Pr opagation

Delay of Transmitter rising

edge w.r.t. falling edge

tTRANSSYM -2.0 — 2.0 µs tTRANSSYM = max (tTRANSPDF -

tTRANSPDR)

Time to sample of FAULT/

TXE for bu s con f li ct re port ing tFAULT ——32.5µstFAULT = max (tTRANSPD +

tSLOPE + tRECPD)

Duty Cycl e 1 @20.0 kbit/sec 39.6 — — %tBIT CBUS;RBUS conditions:

1nF; 1kΩ | 6.8 n F; 66 0Ω |

10 nF; 500Ω

THREC(MAX) = 0.744 x VBB,

THDOM(MAX) = 0.581 x VBB,

VBB =7.0V - 18V; tBIT = 50 µs.

D1 = tBUS_REC(MIN) / 2 x tBIT)

Duty Cycle 2 @20.0 kbit/sec — — 58.1 %tBIT CBUS;RBUS conditions:

1nF; 1kΩ | 6.8 n F; 66 0Ω |

10 nF; 500Ω

THREC(MAX) = 0.284 x VBB,

THDOM(MAX) = 0.422 x VBB,

VBB =7.6V - 18V; tBIT = 50 µs.

D2 = tBUS_REC(MAX) / 2 x tBIT)

Duty Cycl e 3 @10.4 kbit/sec 41.7 — — %tBIT CBUS;RBUS conditions:

1nF; 1kΩ | 6.8 n F; 66 0Ω |

10 nF; 500Ω

THREC(MAX) = 0.778 x VBB,

THDOM(MAX) = 0.616 x VBB,

VBB =7.0V - 18V; tBIT = 96 µs.

D3 = tBUS_REC(MIN) / 2 x tBIT)

Duty Cycle 4 @10.4 kbit/sec — — 59.0 %tBIT CBUS;RBUS conditions:

1nF; 1kΩ | 6.8 n F; 66 0Ω |

10 nF; 500Ω

THREC(MAX) = 0.251 x VBB,

THDOM(MAX) = 0.389 x VBB,

VBB =7.6V - 18V; tBIT = 96 µs.

D4 = tBUS_REC(MAX) / 2 x tBIT)

MCP2021/2/1P/2P

2.4 Thermal S pecifications

Voltage Regula tor

Bus Activity Debounce Time tBDB 5 10 20 µs Bus debounce time

Bus Activity to Voltage

Regulator Enabled tBACTVE 100 250 500 µs After bus debounce time

Voltage R egu lato r Enabl ed

to Ready tVEVR — — 1200 µs (Note 1)

Chip Select to Operation

Ready tCSOR — — 500 µs (Note 1)

Chip Select to Power-Down tCSPD ——80µs

Short-Circuit to Shut-Down tSHUTDOWN 20 — 100 µs

RESET Timing

VREG OK Detect to RESET

Inactive tRPU ——10.0µs

VREG OK Detect to RESET

Active tRPD ——10.0µs

Note 1: Time depends on external capacitance and load.

THERMAL CHARACTERISTICS

Parameter Symbol Typ Max Units Test Conditions

Recovery Temperature θRECOVERY +140 —°C

Shutdown Temperature θSHUTDOWN +150 —°C

Short Circuit Recovery Time tTHERM 1.5 5.0 ms

Thermal Package Resistances

Thermal Resistance, 8L-DFN θJA 35.7 —°C/W

Thermal Resistance, 8L-PDIP θJA 89.3 —°C/W

Thermal Resistance, 8L-SOIC θJA 149.5 —°C/W

Thermal Resistance, 14L-PDIP θJA 70 —°C/W

Thermal Resistance, 14L-SOIC θJA 95.3 —°C/W

Thermal Resistance, 14L-TSSOP θJA 100 —°C/W

Note 1: The maximum power dissipation is a function of TJMAX, ΘJA and ambient temperature TA. Th e maximum

allowable power dissipation at an ambient temperature is PD = (TJMAX - TA) ΘJA. If this dissipation is

exceeded, the die temperature will rise above 150°C and the MCP2021 will go into thermal shutdown.

2.3 AC Specification (Continued)

AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40°C to +125°C

Parameter Sym Min. Typ. Max. Units Test Conditions

MCP2021/2/1P/2P

2.5 Timing Diagrams and Specifications

FIGURE 2-4: Bus Timing Diagram.

FIGURE 2-5: Regulator CS/LWAKE Timing Diagram.

.95VLBUS

.0.4VBB

TTRANSPDR

TRECPDR

TTRANSPDF

TRECPDF

TXD

LBUS

RXD

Internal TXD/RXD

Compare

FAULT Sampling

TFAULT TFAULT

FAULT/TXE Output Stable Stable

Stable

Match Match

Match Match Match

Hold

Value

Hold

Value

50%

.50VBB

50%

0.0V

TCSPD

TCSOR

CS/LWAKE

VOUT

VREG

MCP2021/2/1P/2P

FIGURE 2-6: Regulator BUS WAKE Timing Diagram.

FIGURE 2-7: RESET Timing Diagram .

VOUT

LBUS

0.4VBB

TVEVR

VREG

TBDB + TBACTVE

RESET

VBB

6.0V

VREG

5.0V

4.0V

3.5V

TRPU

TRPD

TRPU

MCP2021/2/1P/2P

FIGURE 2-8: CS/LWAKE to RESET Timing Diagram.

FIGURE 2-9: Typical IBBQ vs. Temperature.

TCSPD

TCSOR

CS/LWAKE

VOUT

VREG

RESET

TRPU

0.05

0.1

0.15

0.2

-40C 25C 85C 125C

Temp erature ( °C)

Ibbq mA

Vbb = 6V

Vbb = 7.3V

Vbb = 12V

Vbb = 14.4V

Vbb = 18V

MCP2021/2/1P/2P

FIGURE 2-10: Typical IBBTO vs Temperature.

FIGURE 2-11: Typical IBBPD vs. Temperature.

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

-40C 25C 85C 125C

Temperature (°C)

Vbb = 6V

Vbb = 7. 3V

Vbb = 12V

Vbb = 14. 4V

Vbb = 18V

0.005

0.01

0.015

0.02

0.025

-40C 25C 85C 125C

Temperature (°C )

Ipd (mA)

Vbb = 6V

Vbb = 7. 3V

Vbb = 12V

Vbb = 14. 4V

Vbb = 18V

MCP2021/2/1P/2P

3.0 PACKAGING INFORMATION

3.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanu me ric trac ea bility code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the even t the full M icroc hip p art numb er cann ot be mark ed on one line, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

PIN 1

NNN

PIN 1

8-Lead DFN-S (6x5x0.9 mm) Example

8-Lead DFN (4x4x0.9 mm) Example

YYWW

NNN

XXXXXX

PIN 1 PIN 1

MCP2021

202150

8-Lead PDIP (300 mil) Example

XXXXXXXX

XXXXXNNN

YYWW

MCP2021 MCP2021P

2021500 2021P500

202150

E/MD

1033

256

2021500

E/MF

1033

256

2021500

E/P 256

1033

MCP2021 MCP2021P

2021500 2021P50

MCP2021/2/1P/2P

3.1 Package Marking Information (Continued)

MCP2022 MCP2022P

MCP2022-500 2022P-500

MCP2022 MCP2022P

MCP2022-500 MCP2022P-500

8-Lead SOIC (3.90 mm) Example

NNN

MCP2021 MCP2021P

2021500E 2021P50E

2021500E

SN 1033

256

14-Lead PDIP (300 mil) Example

14-Lead SOIC (3.90 mm) Example

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanu me ric trac ea bility code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the even t the fu ll Microc hip p art numb er ca nnot be mark ed on one line, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

MCP2022-500

E/P

1033256

MCP2022-500

E/SL

1033256

MCP2021/2/1P/2P

3.1 Package Marking Information (Continued)

14-Lead TSSOP (4.4 mm) Example

YYWW

NNN

XXXXXXXX

MCP2022 MCP2022P

2022500E 2022P50E

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanu me ric trac ea bility code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the even t the fu ll Microc hip p art numb er ca nnot be mark ed on one line, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

2022500E

1033

256

MCP2021/2/1P/2P

8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Package is saw singulated.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.80 BSC

Overall Height A 0.80 0.90 1.00

Standoff A1 0.00 0.02 0.05

Contact Thickness A3 0.20 REF

Overall Length D 4.00 BSC

Exposed Pad Width E2 0.00 2.20 2.80

Overall Width E 4.00 BSC

Exposed Pad Length D2 0.00 3.00 3.60

Contact Width b 0.25 0.30 0.35

Contact Length L 0.30 0.55 0.65

Contact-to-Exposed Pad K 0.20 – –

NOTE 1

NOTE 2

NOTE 1

EXPOSED

PAD

TOP VIEW BOTTOM VIEW

Microchip Technology Drawing C04-131C

MCP2021/2/1P/2P

D !"#$

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MCP2021/2/1P/2P

8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Package is saw singulated.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A 0.80 0.85 1.00

Standoff A1 0.00 0.01 0.05

Contact Thickness A3 0.20 REF

Overall Length D 5.00 BSC

Overall Width E 6.00 BSC

Exposed Pad Length D2 3.90 4.00 4.10

Exposed Pad Width E2 2.20 2.30 2.40

Contact Width b 0.35 0.40 0.48

Contact Length L 0.50 0.60 0.75

Contact-to-Exposed Pad K 0.20 – –

NOTE 2

NOTE 112

EXPOSED PAD

NOTE 1

BOTTOM VIEW

TOP VIEW

Microchip Technology Drawing C04-122

MCP2021/2/1P/2P

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MCP2021/2/1P/2P

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .348 .365 .400

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018B

MCP2021/2/1P/2P

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff §A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 4.90 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057B

MCP2021/2/1P/2P

& '(&))*+ !"#&',-$

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MCP2021/2/1P/2P

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .735 .750 .775

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .045 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

123

Microchip Technology Drawing C04-005B

MCP2021/2/1P/2P

14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff § A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 8.65 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

123

hα

Microchip Technology Drawing C04-065B

MCP2021/2/1P/2P

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MCP2021/2/1P/2P

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 4.90 5.00 5.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-087B

MCP2021/2/1P/2P

APPENDIX A: REVIS ION HISTORY

Revision F (January 2012)

The following modifications were made to this data

sheet:

Added the MCP2021P and MCP2022P options

and related information throughout the

document.

Revision E (February 2009)

The following is the list of modifications.

1. Added Example 1-7 and Exampl e 1-8.

2. Updated Section 1.4.9 “RESET”.

3. Updated Section 1.7 “ICSP™ Consider-

ations”.

4. Updated Section 2.1 “Absolute Maximum

Ratings†”.

5. Updated Section 2.2 “DC Specification s” and

Section 2.3 “AC Specification”.

6. Added FIGURE 2-3: “ESR Curves for Load

Capacitor Selection.”.

7. Updated the Product Identification System

section.

Revision D (July 2008)

The following is the list of modifications.

1. Updated ESD specs under ‘Absolute DC’.

2. U pdated notes in Example 1-1.

3. Updated Package Outline Drawings.

Revision C (April 2008)

The following is the list of modifications.

1. Added LIN2.1 and J2602 compliance statement

to Features section.

2. Added recommended RC network for CS/

LWAKE in Example 1-1.

3. Updated 2.1 Absolute Maximum Ratings to

reflect current test results.

4. Updated 2.2 DC Specifications and 2.3 AC

Specifications to reflect current production

device.

5. Added 8-Lead SOIC Landing Pattern Outline

drawing.

Revision B (August 2007)

The following is the list of modifications:

1. Modified Block Diagram on page 2.

2. Section 1.3.5 “Transmitter-OFF Mode”:

Delete d text in 1st pa ragraph.

3. Example 1-6: Removed +5V notation.

4. Section 1.4 “Pin Descriptions”: Re moved 10-

pin DFN, MSOP column from table.

5. Section 1.4.8 “Fault/TXE”: Deleted text from

2nd paragraph.

6. Section 3.0 “Packaging Information”: Added

8-lead 4x4 and 6x5 DFN and 14-lead TSSOP

packages. Updated package outline drawings

and adde d drawings for 8-lead DF N and 14-lead

TSSOP drawings.

Revision A (November 2005)

Original Release of this Document.

MCP2021/2/1P/2P

NOTES:

MCP2021/2/1P/2P

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP2021: LIN Transceiver with Voltage Regulator; wakes up on

dominant level of LIN bus.

MCP2021T: LIN Transceiver with Voltage Regulator; wakes up on

dominant level of LIN bus.

(Tape and Reel) (SOIC only)

MCP2022: LIN Transceiver with V oltage Regulator, and RESET

pin; wakes up on dominant level of LIN bus.

MCP2022T: LIN Transc eive r with Voltage Regulator, and RESET

pin; wakes up on dominant level of LIN bus.

(Tape and Reel) (SOIC only)

MCP2021P: LIN Transceiver with V oltage Regulator; wakes up at a

falling edge of LIN bus level.

MCP2021PT: LIN Transceiver with V oltage Regulator; wakes up at a

falling edge of LIN bus level

(Tape and Reel) (SOIC only)

MCP2022P: LIN Transc eive r with Voltage Regulator, and RESET

pin; wakes up at a falling edge of LIN bus level.

MCP2022PT: LIN Transceiver with Voltage Regulator, and RESET

pin; wakes up at a falling edge of LIN bus level.

(Tape and Reel) (SOIC only)

Temperature

Range: E = -40°C to +125°C

Package: MD = Plastic Micro Small Outline (4x4), 8-lead

MF = Plastic Micro Small Outline (6x5), 8-lead

P = Plastic DIP ( 300 mil Body), 8- lead, 14-lead

SN = Plastic SOIC, (150 mil Body), 8-lead

SL = Plastic SOIC, (150 mil Body), 14-lead

ST = Plastic Thin Shrink Small Outline, 14-lead

PART NO. –X /XX

PackageTemperature

Range

Device

Examples:

a) MCP2021-330E/SN: 3.3V, 8L-SOIC pkg.

b) MCP2021-330E/P: 3.3V, 8L-PDIP pkg.

c) MCP2021-500E/MF: 5.0V, 8L-DFN-S pkg.

d) MCP2021-500E/SN: 5.0V, 8L-SOIC pkg.

e) MCP2021-500E/MD: 5.0V, 8L-DFN pkg.

f) MCP2021-330E/P: 5.0V, 8L-PDIP pkg.

g) MCP2021T-330E/SN: Ta pe and Reel,

3.3V, 8L-SOIC pkg.

h) MCP2021T-500E/MD: Tape and Reel,

5.0V, 8L-D FN pkg.

i) MCP2021T-500E/SN: Tape and Reel,

5.0V, 8L-SOIC pkg.

a) MCP2022-330E/SL: 3.3V, 14L-SOIC pkg.

b) MCP2022-330E/P: 3.3V, 14L-PDIP pkg.

c) MCP2022-500E/SL: 5.0V, 14L-SOIC pkg.

d) MCP2022-500E/P: 5.0V, 14L-PDIP pkg.

e) MCP2022T-330E/SL: Tape and Reel,

3.3V, 14L-SOIC pkg.

f) MCP2022T-500E/SL: Tape and Reel,

5.0V, 14L-SOIC pkg.

g) MCP2022T-500E/ST: Tape and Reel,

5.0V, 14L-TSSOP pkg.

MCP2021/2/1P/2P

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is provided only f or yo ur convenience

and may be supers ed ed by u pda t es . It is y our responsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI C START,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-884-0

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in t he

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

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Technical Support:

http://www.microchip.com/

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Web Address:

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Tel: 91-80-3090-4444

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Tel: 91-11-4160-8631

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Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Taiwan - Kaohs iung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921- 5820

Worldwide Sales and Service

11/29/11