KA3842 - Fairchild Semiconductor

www.fairchildsemi.com

Rev. 5.0

Features

• Low Start Up Current

• Maximum Duty Clamp

• UVLO With Hysteresis

• Ope ratin g Fre quency Up To 500KHz

Description

The KA3842B/KA3843B/KA3844B/KA3845B are fixed

frequency current-mode PWM controller. They are spe -

cially designed for Off - Line and DC-to-DC converter

applications with minimum external components. These

integrated circuits feature a trimmed oscillator for precise

duty cycle control, a temperatur e compen sated r eference,

high gain error am plif ier. current sensing comparator, and a

high current totempole output Ideally suited fo r dr iving a

power MOSFET. Protection circuity Includes built in

under - volt age lockout and cu r rent li miti n g. Th e KA3 84 2B

and KA384 4B ha ve UVL O thresholds of 16V (on) and

10V (off) The KA3843B and KA3845B are 8.5V (on) and

7.9V ( off) The KA38 42B an d K A 38 43 B c an op er at e wi t hin

100% duty cycle. The KA3844B and KA3845B can operate

with 50% duty cycle.

8-DIP

14-SOP

KA3842B/KA3843B/KA3844B/KA3845B

SMPS Controller

KA3842B/KA3843B/KA3844B/KA3845B

Internal Block Diagram

Absolute Maximum Ratings

Parameter Symbol Value Unit

Supply Voltage VCC 30 V

Output Current IO±1A

Analog Inputs (Pin 2.3) V(ANA) -0.3 to 6.3 V

Error Amp Output Sink Current ISINK (E.A) 10 mA

Power Dissipation (TA = 25°C) PD1W

KA3842B/KA3843B/KA3844B/KA3845B

Electrical Characteristics

(VCC=15V, RT=10KΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)

Parameter Symbol Conditions Min. Typ. Max. Unit

REFERENCE SECTION

Reference Output Voltage VREF TJ = 25°C, IREF = 1mA 4.90 5.00 5.10 V

Line Regulation ∆VREF 12V≤VCC≤25V - 6 20 mV

Load Regulation ∆VREF 1mA≤IREF≤20mA - 6 25 mV

Short Circuit Output Current ISC TA = 25°C - -100 -180 mA

OSCILLATOR SECTION

Oscillation Frequency f TJ = 25°C475257KHz

Frequency Change with Voltage ∆f/∆VCC 12V≤VCC≤25V - 0.05 1 %

Oscillator Amplitude VOSC --1.6-V

P-P

ERROR AMPLIFIER SECTION

Input Bias Current IBIAS ---0.1-2µA

Input Voltage VI(E>A) V1 = 2.5V 2.42 2.50 2.58 V

Open Loop Voltage Gain GVO 2V≤ VO ≤4V 65 90 - dB

Power Supply Rejection Ratio PSRR 12V≤ VCC ≤25V 60 70 - dB

Output Sink Current ISINK V2 = 2.7V, V1 = 1.1V 2 7 - mA

Output Source Current ISOURCE V2 = 2.3V, V1 = 5V -0.6 -1.0 - mA

High Output Voltage VOH V2 = 2.3V, RL = 15KΩ to GND 5 6 - V

Low Output Voltage VOL V2 = 2.7V, RL = 15KΩ to Pin 8 - 0.8 1.1 V

CURRENT SENSE SECTION

Gain GV (Note 1 & 2) 2.85 3 3.15 V/V

Maximum Input Signal VI(MAX) V1 = 5V(Note 1) 0.9 1 1.1 V

Power Supply Rejection Ratio PSRR 12V≤ VCC ≤25V (Note 1) - 70 - dB

Input Bias Current IBIAS ---3-10µA

OUTPUT S ECTION

Low Output Voltage VOL

ISINK = 20mA - 0.08 0.4 V

ISINK = 200mA - 1.4 2.2 V

High Output Voltage

VOH ISOURCE = 20mA 13 13.5 - V

ISOURCE = 200mA 12 13.0 - V

Rise Time tR TJ = 25°C, CL= 1nF (Note 3) - 45 150 ns

Fall Time tF TJ = 25°C, CL= 1nF (Note 3) - 35 150 ns

UNDER-VOLTAGE LOCKOUT SECTION

Start Threshold

VTH(ST) KA3842B/KA3844B 14.5 16.0 17.5 V

KA3843B/KA3845B 7.8 8.4 9.0 V

Min. Operating Voltage

(After Turn O n) VOPR(MIN) KA3842B/KA3844B 8.5 10.0 11.5 V

KA3843B/KA3845B 7.0 7.6 8.2 V

KA3842B/KA3843B/KA3844B/KA3845B

Electrical Characteristics (Continued)

(VCC=15V, RT=10KΩ, CT=3.3nF, TA= 0°C to +70°C unless otherwise specified)

Adjust VCC above the start threshould before setting at 15V

Note:

1. Parameter measured at trip point of latch

2. Gain def ine d as:

3.These parameters, although guaranteed, are not 100 tested in production.

Figure 1. Open Loop Test Ci rcuit

High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors

should be connected clos e to pin 5 in a single point ground. T he tr ansistor and 5KΩ potentiometer are us ed to sample the

oscillator waveform and apply an adjustable ramp to pin 3.

Parameter Symbol Conditions Min. Typ. Max. Unit

PWM SECTION

Max. Duty Cycle

D(max) KA3842B/KA3843B 95 97 100 %

D KA3844B/KA3845B 47 48 50 %

Min. Duty Cycle D(MIN) ---0%

TOTAL STANDBY CURRENT

Start-Up Current IST --0.451mA

Operating Supply Current ICC(OPR) V3=V2=ON - 14 17 mA

Zener Voltage VZ ICC = 25mA 30 38 - V

A∆V1

∆V3

----------=,0 ≤ V3 ≤ 0.8V

KA3842B/KA3843B/KA3844B/KA3845B

Figure 2. Under Voltage Lockout

During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground

with a bleeder resistor to prevent activating the power switch with output leakage curren t.

Figure 3. Error Amp Configuration

Figure 4. Current Sense Circuit

Peak current (IS) is determ ined by the formula:

A small RC filter may be required to suppress switch transients.

ISMAX()

1.0V

------------=

KA3842B/KA3843B/KA3844B/KA3845B

Figure 5. Oscillator Waveforms and Maximum Duty Cycle

Oscillator timing capacitor, CT, is charged by VREF through RT, and discharged by an internal current source. During the dis-

charge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines both

oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:

tc = 0.55 RT CT

Frequency, then, is: f=(tc + td)-1

Figure 8. Shutdown Techniques

Figure 6. Oscillator Dead Time & Frequency Figure 7. Timing Resistance vs Frequency

tDRTCTIn0.0063RT2.7–

0.0063RT4–

----------------------------------------





ForRT 5KΩf1.8

RTCT

---------------=,>

(Deadtime vs CT RT > 5kΩ)

KA3842B/KA3843B/KA3844B/KA3845B

Shutdown of the KA3842B can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage

two di od e d ro ps a bo ve g r ound. E it he r m eth od c a us es t h e ou t pu t of the P WM compara tor t o be hi g h (ref e r to bl o c k di a gr am) .

The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at

pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SOR which

will be reset by cycling Voc below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.

Figure 9. Slope Compensation

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for

converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch

spikes.

TEMPERATURE (°C)

Figure 10 . TEMPERATURE DRIFT (Vref) TEMP ER ATURE ( °C)

Figure 11. TEMPERATURE DRIFT (Ist)

TEMPERATURE (°C)

Figure 12. TEMPERATURE DRIFT ( Ic c)

KA3842B/KA3843B/KA3844B/KA3845B

Mechanical Dimensions

Package

6.40 ±0.20

3.30 ±0.30

0.130 ±0.012

3.40 ±0.20

0.134 ±0.008

#4 #5

0.252 ±0.008

9.20 ±0.20

0.79

2.54

0.100

0.031

()

0.46 ±0.10

0.018 ±0.004

0.060 ±0.004

1.524 ±0.10

0.362 ±0.008

9.60

0.378 MAX

5.08

0.200

0.33

0.013

7.62

0~15°

0.300

MAX

MIN

0.25

+0.10

–0.05

0.010

+0.004

–0.002

8-DIP

KA3842B/KA3843B/KA3844B/KA3845B

Mechanical Dimensions (Continued)

Package

8.56

±0.20

0.337

±0.008

1.27

0.050

5.72

0.225

1.55

±0.10

0.061

±0.004

0.05

0.002

6.00

±0.30

0.236

±0.012

3.95

±0.20

0.156

±0.008

0.60

±0.20

0.024

±0.008

8.70

0.343 MAX

#7 #8

0~8°

#14

0.47

0.019

()

1.80

0.071

MAX0.10

MAX0.004

MAX

MIN

0.10

-0.05

0.20+

0.004

-0.002

0.008

0.10

-0.05

0.406+

0.004

-0.002

0.016

14-SOP

KA3842B/KA3843B/KA3844B/KA3845B

Ordering Information

Product Number Package Operating Temperature

KA3842B

8 DIP

0 ~ + 70°C

KA3843B

KA3844B

KA3845B

KA3842BD

KA3843BD 14 SOPKA3844BD

KA3845BD

KA3842B/KA3843B/KA3844B/KA3845B

7/13/00 0.0m 001

Stock#DSxxxxxxxx

 2000 Fairch il d Semiconduc tor International

LIFE SU PP ORT POL ICY

FAIRCHILD’S PRODUCTS AR E NOT AUTHORIZED FOR USE AS C RITICAL COMPONENTS I N LIFE S UPPORT DEVICE S

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

INTERNATIONAL. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or syst em who se failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effec tiv ene ss.