Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

   
SCLS342L − APRIL 1996 − REVISED JUNE 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DOperating Range of 2 V to 5.5 V
DMax tpd of 6.5 ns at 5 V
DLow Power Consumption, 10-µA Max ICC
D±8-mA Output Drive at 5 V
DSchmitt Trigger Action at All Inputs Makes
the Circuit Tolerant for Slower Input Rise
and Fall Time
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
3
2
4
51
AV
CC
Y
B
GND
DBV PACKAGE
(TOP VIEW) DCK PACKAGE
(TOP VIEW)
3
2
4
51
AV
CC
Y
B
GND
3
2
4
51
AV
CC
Y
B
GND
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
description/ordering information
This device contains a single 2-input NOR gate that performs the Boolean function Y = A SB or Y = A + B in
positive logic.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
SOT (SOT-23) − DBV
Reel of 3000 SN74AHC1G02DBVR
A02_
SOT (SOT-23) − DBV Reel of 250 SN74AHC1G02DBVT A02_
−40°C to 85°C
SOT (SC-70) − DCK
Reel of 3000 SN74AHC1G02DCKR
AB_
−40 C to 85 C
SOT (SC-70) − DCK
Reel of 250 SN74AHC1G02DCKT
AB_
SOT (SOT-553) – DRL Reel of 4000 SN74AHC1G02DRLR AB_
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
‡The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS
OUTPUT
A B
OUTPUT
Y
H X L
XHL
L L H
logic diagram (positive logic)
A
BY
1
24
    !"#   $"%&! '#(
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#-  && $##(
Copyright 2005, Texas Instruments Incorporated

   
SCLS342L − APRIL 1996 − REVISED JUNE 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DBV package 206°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 252°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRL package 142°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VCC = 2 V 1.5
V
IH
High-level input voltage VCC = 3 V 2.1 V
VIH
High-level input voltage
VCC = 5.5 V 3.85
V
VCC = 2 V 0.5
V
IL
Low-level input voltage VCC = 3 V 0.9 V
VIL
Low-level input voltage
VCC = 5.5 V 1.65
V
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 2 V −50 mA
I
OH
High-level output current VCC = 3.3 V ± 0.3 V −4
mA
IOH
High-level output current
VCC = 5 V ±0.5 V −8 mA
VCC = 2 V 50 mA
I
OL
Low-level output current VCC = 3.3 V ±0.3 V 4
mA
IOL
Low-level output current
VCC = 5 V ±0.5 V 8mA
∆t/∆v
Input transition rise or fall rate
VCC = 3.3 V ± 0.3 V 100
ns/V
∆t/∆vInput transition rise or fall rate VCC = 5 V ±0.5 V 20 ns/V
TAOperating free-air temperature −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

   
SCLS342L − APRIL 1996 − REVISED JUNE 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX
UNIT
2 V 1.9 2 1.9
I
OH
= −50 mA3 V 2.9 3 2.9
V
OH
IOH = −50 mA
4.5 V 4.4 4.5 4.4 V
VOH
IOH = −4 mA 3 V 2.58 2.48
V
IOH = −8 mA 4.5 V 3.94 3.8
2 V 0.1 0.1
I
OL
= 50 mA3 V 0.1 0.1
V
OL
IOL = 50 mA
4.5 V 0.1 0.1 V
VOL
IOL = 4 mA 3 V 0.36 0.44
V
IOL = 8 mA 4.5 V 0.36 0.44
IIVI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1mA
ICC VI = VCC or GND, IO = 0 5.5 V 1 10 mA
CiVI = VCC or GND 5 V 4 10 10 pF
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX
UNIT
tPLH
A or B
Y
CL = 15 pF
5.6 7.9 1 9.5
ns
tPHL A or B Y CL = 15 pF 5.6 7.9 1 9.5 ns
tPLH
A or B
Y
CL = 50 pF
8.1 11.4 1 13
ns
tPHL
A or B
Y
C
L
= 50 pF
8.1 11.4 1 13
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX
UNIT
tPLH
A or B
Y
CL = 15 pF
3.6 5.5 1 6.5
ns
tPHL A or B Y CL = 15 pF 3.6 5.5 1 6.5 ns
tPLH
A or B
Y
CL = 50 pF
5.1 7.5 1 8.5
ns
tPHL
A or B
Y
C
L
= 50 pF
5.1 7.5 1 8.5
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 15 pF

   
SCLS342L − APRIL 1996 − REVISED JUNE 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
V
CC
RL = 1 kΩ
GND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74AHC1G02DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DCKT ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DRLR ACTIVE SOT DRL 5 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC1G02DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHC1G02 :
•Enhanced Product: SN74AHC1G02-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AHC1G02DBVR SOT-23 DBV 5 3000 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3
SN74AHC1G02DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G02DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G02DBVT SOT-23 DBV 5 250 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3
SN74AHC1G02DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AHC1G02DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G02DCKR SC70 DCK 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74AHC1G02DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AHC1G02DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G02DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74AHC1G02DRLR SOT DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jun-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC1G02DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G02DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G02DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G02DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G02DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G02DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G02DCKR SC70 DCK 5 3000 205.0 200.0 33.0
SN74AHC1G02DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74AHC1G02DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74AHC1G02DRLR SOT DRL 5 4000 202.0 201.0 28.0
SN74AHC1G02DRLR SOT DRL 5 4000 180.0 180.0 30.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jun-2012
Pack Materials-Page 2
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