SC16C752BIBS,128 - NXP Semiconductors

1. General description

The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with

64-byte FIF Os, aut om a tic ha rd wa re /softwar e flow control, and data rates up to 5 Mbit/s

(3.3 V and 5 V). The SC16 C752B offer s enhanced feat ures. It has a T r ansmission Control

hardware and sof tware flow control. With the FIFO Rdy register, the software gets the

status of TXRDYn/RXRDYn for all four ports in one access. On-chip status registers

provide the user with error indications, operational status, and modem interface control.

System interrupt s may be tailored to meet user requirements. An internal loopback

capability allows on-board diagnostics.

The UART transmits data, sent to it over the peripheral 8-bit bus, on the TXn signal and

receives characters on the RXn signal. Charac ters can be programmed to b e 5 bits, 6 bits,

7 bits, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be

programmed to interrupt at diff erent trigger levels. The UART generates its own desired

baud rate based upon a programmable divisor and its input clock. It can transmit even,

odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing

errors, FIFO overfl ow, and parity errors. The transmitter can detect FIFO underflow. The

UART also co ntains a software interface for modem control operations, and has software

flow control and ha rd wa re flow control capabilities.

The SC16C752B is available in plastic LQFP48 and HVQFN32 packages.

2. Features and benefits

Pin compatible with SC16C2550 with additional enhancements

Up to 5 Mbit/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is 3 Mbit/s)

64-byte tran sm it FIFO

64-byte receive FIFO with error flags

Programmable and selectable transmit and receive FIFO trigger levels for DMA and

interrupt generation

Software/hardware flo w con tr ol

Programmable Xon/Xoff characters

Programmable auto-RTS and auto-CTS

Optional data flow resume by Xon an y cha r act er

DMA signalling capability for both received and transmitted data

Supports 5 V, 3.3 V and 2.5 V operation

SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte

FIFOs

Rev. 6 — 30 November 2010 Product data sheet

Product data sheet Rev. 6 — 30 November 2010 2 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

5 V tolerant on input only pins1

Software selectable baud rate generator

Prescaler prov ide s ad dit ion al div ide -b y- 4 fu nct ion

Industrial temperature range (−40 °C to +85 °C)

Pin and soft ware compatible with SC16C752, TL16C752

Fast data bus access time

Programmable Sleep mode

Programmable serial interface characteristics

5-bit, 6-bit, 7-bit, or 8-bit characte rs

Even, odd, or no parity bit generation and detection

1, 1.5, or 2 stop bit generation

False start bit detection

Complete status reporting capabilities in both normal and Sleep mode

Line break generation and detection

Internal test and loopback capabilities

Fully prioritized interrupt system controls

Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)

3. Ordering information

1. For data bus, D7 to D0, see Table 24 “Limiting values”.

Tabl e 1. Ordering information

Type number Package

Name Description Version

SC16C752BIB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 ×7×1.4 mm SOT313-2

SC16C752BIBS HVQFN32 plastic thermal enhanced very thin qu ad flat package; no leads;

32 terminals; body 5 ×5×0.85 mm SOT617-1

Product data sheet Rev. 6 — 30 November 2010 3 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

4. Block diagram

Fig 1. Block diagram

TXA, TXB

RXA, RXB

SC16C752B

XTAL2XTAL1

D0 to D7

IOR

IOW

RESET

002aaa600

DATA B U S

AND

CONTROL

LOGIC

SELECT

LOGIC

A0 to A2

CSA

CSB

INTERRUPT

CONTROL

LOGIC

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

CLOCK AND

BAUD RATE

GENERATOR

INTERCONNECT BUS LINES

AND

CONTROL SIGNALS

MODEM

CONTROL

LOGIC

DTRA, DTRB

RTSA, RTSB

OPA, OPB

CTSA, CTSB

RIA, RIB

CDA, CDB

DSRA, DSRB

RECEIVE

SHIFT

RECEIVE

FIFO

REGISTERS

FLOW

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

TRANSMIT

SHIFT

TRANSMIT

FIFO

REGISTERS

Product data sheet Rev. 6 — 30 November 2010 4 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

5. Pinning information

5.1 Pinning

Fig 2. Pin configuration for LQFP4 8

Fig 3. Pin configuration for HVQFN32

SC16C752BIB48

D5 RESET

D6 DTRB

D7 DTRA

RXB RTSA

RXA OPA

TXRDYB RXRDYA

TXA INTA

TXB INTB

OPB A0

CSA A1

CSB A2

n.c. n.c.

XTAL1 D4

XTAL2 D3

IOW D2

CDB D1

GND D0

RXRDYB TXRDYA

IOR VCC

DSRB RIA

RIB CDA

RTSB DSRA

CTSB

n.c.

CTSA

n.c.

002aaa601

002aaa95

SC16C752BIBS

Transparent top view

OPB

CSA

TXB A0

TXA INTB

RXA INTA

RXB OPA

D7 RTSA

D6 RESET

CSB

XTAL1

XTAL2

IOW

GND

IOR

RTSB

CTSB

VCC

CTSA

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

Product data sheet Rev. 6 — 30 November 2010 5 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

5.2 Pin description

Table 2. Pin description

Symbol Pin Type Description

LQFP48 HVQFN32

A0 28 19 I Address 0 select bit. Internal registers address selection.

A1 27 18 I Address 1 select bit. Internal registers address selection.

A2 26 17 I Address 2 select bit. Internal registers address selection.

CDA 40 - I Carrier Detect (active LOW). These inputs are associated with individual

UART channels A and B. A logic LOW on these pins indicates that a carrier has

been detected by the modem for that channel. The state of these inputs is

reflected in the Modem St atus Register (MSR).

CDB 16 - i

CSA 10 8 I Chip Select (active LOW). These pins enable data transfers between the user

CPU and the SC16C752B for the channel(s) addressed. Individual UART

sections (A, B) are addressed by providing a logic LOW on the respective CSA

and CSB pins.

CSB 11 9 I

CTSA 38 25 I Clear to Send (active LOW). These inputs are associated with individual UART

channels A and B. A logic 0 (LOW) on the CTSn pins indicate s the modem or

data set is ready to accept transmit data from the SC16C752B. Status can be

tested by reading MSR[4]. These pins only affect the transmit and receive

operations when auto-CTS function is enabled via the Enhanced Feature

CTSB 23 16 I

D0 44 27 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least significant

bit and the first da ta bit in a transmi t or rece i v e seri al da ta stream.

D1 45 28 I/O

D2 46 29 I/O

D3 47 30 I/O

D4 48 31 I/O

D5 1 32 I/O

D6 2 1 I/O

D7 3 2 I/O

DSRA 39 - I Data Set Ready (active LOW). These inputs are associated with individual

UART channels A and B. A logic 0 (LOW) on these pins indicates the modem or

data set is powered-on and is ready for data exchange with the UART. The state

of these inputs is reflected in the Modem Status Register (MSR).

DSRB 20 - I

DTRA 34 - O Data Terminal Ready (active LOW). These outputs are associated with

individual UART channels A and B. A logic 0 (LOW) on these pins indicates that

the SC16C752B is powered-on and ready. These pins can be controlled via the

modem control register. Writing a logic 1 to MCR[0] will set the DTRn output to

logic 0 (LOW), enabli ng the modem. The output of these pins will be a logic 1

after writing a logic 0 to MCR[0], or after a reset.

DTRB 35 - O

GND 17 13 I Signal an d po we r ground

INTA 30 21 O Interrupt A and B (active HIGH). These pins provide individual channel

interrupts INTA and INTB. INTA and INTB are enabled when MCR[3] is set to a

logic 1, interrupt sources are enabled in the Interrupt Enable Register (IER).

Interrupt conditions include: receiver errors, available receiver buffer data,

available transmit buffer space, or when a modem status flag is detected. INTA,

INTB are in the high-impedance state after reset.

INTB 29 20 O

IOR 19 14 I Input/Output Read strobe (active LOW). A HIGH-to-LOW transition on IOR

will load the contents of an internal register defined by address bits A0 to A2

onto the SC16C752B data bus (D0 to D7) for access by external CPU.

Product data sheet Rev. 6 — 30 November 2010 6 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

IOW 15 12 I Input/Output Write strobe (active LOW). A LOW-to-HIGH transition on IOW

will transfer the contents of the data bus (D0 to D7) from the external CPU to an

internal register that is defined by address bits A0 to A2 and CSA and CSB.

n.c. 12, 24,

25, 37 - - not connected

OPA 32 22 O User defined outputs. This function is associated with individual channels A

and B. The state of these pins is defined by the user through the software

settings of MCR[3]. INTA-INTB are set to ac tive mode and OPA-OPB to a logic 0

when MCR[3] is set to a logic 1. INTA-INTB are set to the 3-state mode and

OPA-OPB to a logic 1 when MCR[3] is set to a logic 0. The output of these two

pins is HIGH after reset.

OPB 97 O

RESET 36 24 I Reset. This pin will reset the internal registers and all the outputs. The UART

transmitter output and the receiver input will be disabled during reset time.

RESET is an active HIGH input.

RIA 41 - I Ring Indicator (active LOW). These inputs are associated with individual

UART channels, A and B. A logic 0 on these pins indicates the modem has

received a ringing signal from the telephone line. A LOW-to-HIGH transition on

these input pins generates a modem status interrupt, if enabled. The state of

these inputs is reflected in the Modem Status Register (MSR).

RIB 21 - I

RTSA 33 23 O Request to Send (active LOW). These outputs are associated with individual

UART channels, A and B. A logic 0 on the RTSn pin indicates the transmitter

has data ready and waiting to send. Writing a logic 1 in the modem control

reset these pins are set to a logic 1. These pins only affect the transmit and

receive operations when auto-RTS function is enabled via the Enhanced

Feature Register (EFR[6]) for hardware flow control operation.

RTSB 22 15 O

RXA 5 4 I Receive data input. These inputs are associated with individual serial channel

data to the SC16C752B. During the local Loopback mode, these RXn input pins

are disabled and transmit data is connected to the UART receive input internally.

RXB 4 3 I

RXRDYA 31 - O Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the

trigger level has been reached or the FI FO has at least one character. It goes

HIGH when the receive FIFO is empty.

RXRDYB 18 - O

TXA 7 5 O T ransmit data A, B. These outputs are associated with individual serial transmit

channel data from the SC16C752B. During the local Loopback mode, the TXn

output pin is disabled and transmit data is internally connected to the UART

receive input.

TXB 8 6 O

TXRDYA 43 - O Transmit Ready (active LOW). TXRDYA or TXRDYB go LOW when there are

at least a trigger level number of spaces available or when the FIFO is empty. It

goes HIGH when the FIFO is full or not empty.

TXRDYB 6- O

VCC 42 26 I Power supply input

XTAL1 13 10 I Crystal or external clock inpu t. F unctions as a crystal input or as an external

clock input. A crystal can be connected between XTAL1 and XTAL2 to form an

internal oscillator circuit (see Figure 13). Alternatively, an external clock can be

connected to this pin to provide custom data rates.

XTAL2 14 11 O Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2

is used as a crystal oscillator output or a buffered clock output.

Table 2. Pin description …continued

Symbol Pin Type Description

LQFP48 HVQFN32

Product data sheet Rev. 6 — 30 November 2010 7 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6. Functional description

The SC16C752B UART is pin-compatible with the SC16C2550 UART. It provides more

enhanced features. All additional features are provided through a special Enhanced

Feature Register (EFR).

The UART will perform serial-to-parallel conversion on data characters received from

peripheral de vic es or mo de m s, an d parallel-to -parallel con ver sio n on data charact er s

transmitted by the processor. The complete status of each channel of the SC16C752B

UART can be read at any time during functional operation by the processor.

The SC16C752 B can be placed in an alternate mode ( FIFO mode) relieving the pr ocessor

of excessive software overhead by buffering received/transmitted characters. Both the

receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of

error status per byte for the receiver FIFO) and have selectable or programmable trigger

levels. Primary outputs RXRDYn and TXRDYn allow signalling of DMA transfers.

The SC16C752B has selectable hardware flow control and software flow control.

Hardware flow control significantly reduces software overhead and increases system

efficiency by automatically controlling serial data flow using the RTSn output and CTSn

input signals. Software flow control automatically controls data flow by using

programmable Xon/Xoff characters.

The UAR T includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (216 −1).

6.1 Trigger levels

The SC16C752B provides independent selectable and programmable trigger levels for

both receiver and transmitter DMA and interrupt generation. After reset, both transmitter

and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of

one byte. The selectable trigger levels are available via the FIFO Control Register (FCR).

The programmable trigger levels are available via the Trigger Level Register (TLR).

6.2 Hardware flow control

Hardware flow control is comprised of auto-CTS and auto-RTS. Aut o-CTS and auto-RTS

can be enabled/disabled independ ently by programming EFR[7:6].

With auto-CTS, CTSn must be active before the UART can transmit data.

Auto-RTS only activates the RTSn output when there is enough room in the FIFO to

receive data and de-activates the RTSn output whe n the rec eive FIFO is sufficiently full.

The halt and resume trigger levels in the TCR determine the levels at which RTSn is

activated/deactivated.

If both auto-CTS and auto-RTS are enabled, whe n RTSn is connected to CTSn, data

transmission does not occur unless the receiver FIFO has empty space. Thus, overrun

errors are eliminated during hardware flow control. If not enabled, overrun errors occur if

the transmit data rate exceeds the receive FIFO servicing latency.

Product data sheet Rev. 6 — 30 November 2010 8 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.2.1 Auto-RTS

Auto-RTS data flow control originates in the receiver block (see Figure 1 “Block diagram”

on pa ge 3 ). Figure 5 shows RTSn functional timing. The receiver FIFO trigger levels used

in auto-RTS are stored in the TCR. RTSn is active if the RX FIFO level is below the halt

trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTSn is

de-asserted. The sending device (e.g., another UART) may send an additional byte after

the trigger level is reached (assuming th e sending UART has another byte to send)

because it may not recognize the de-assertion of RTSn until it has begun sending the

additional byte. RTSn is automatically reasserted once the receiver FIFO reaches the

resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending

device to resume transmission.

Fig 4. Auto flow control (auto-RTS and auto-CTS) example

FIFO

FLOW

CONTROL

FIFO

PARALLEL

TO SERIAL

FIFO

UART 1 UART 2

D7 to D0

RXn TXn

RTSn CTSn

TXn RXn

CTSn RTSn

D7 to D0

002aaf905

SERIAL TO

PARALLEL

SERIAL TO

PARALLEL

FLOW

CONTROL

FLOW

CONTROL

FLOW

CONTROL

PARALLEL

TO SERIAL

N = receiver FIFO trigger level.

The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.

Fig 5. RTS functional timing

Start byte N Start byte N + 1 StartStop StopRXn

RTSn

IOR N N+112

002aaf90

Product data sheet Rev. 6 — 30 November 2010 9 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.2.2 Auto-CTS

The transmitter circuitry checks CTSn before sending the next data byte. When CTSn is

active, the transmitter sends the next byte. To stop the transmitter from sending the

following byte, CTSn must be de-asserted before the middle of the last stop bit that is

currently being sent. The auto-CTS function reduces interrupts to the host system. When

flow control is enabled, CTSn level changes do not trigger host interrupts because the

device automatically contr ols its own transm itter. Without auto-CTS, the transm itter sends

any data present in the transmit FIFO and a receive r ov er ru n er ro r ma y re su lt.

6.3 Software flow control

Software flow control is enabled through the enhanced feature register and the modem

control register. Different combinations of software flow control can be enabled by setting

diff erent combinations of EFR[3:0]. Table 3 shows software flow control options.

When CTSn is LOW, the transmitter keeps sending serial data out.

When CTSn goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current

byte, but is does not send the next byte.

When CTSn goes from HIGH to LOW, the transmitter begins sending data again.

Fig 6. CTS functional timing

Start byte 0 to 7 StopTXn

CTSn

002aaa22

Start byte 0 to 7 Stop

Table 3. Software flow control options (EFR[0:3])

EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow controls

0 0 X X no transmit flow control

1 0 X X transmi t Xo n1 , Xo ff1

0 1 X X transmi t Xo n2 , Xo ff2

1 1 X X transmit Xon1, Xon2, Xoff1, Xoff2

X X 0 0 no receive flow control

X X 1 0 receiver compared Xon1, Xoff1

X X 0 1 receiver compares Xon2, Xoff2

1011transmit Xon1, Xoff1

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0111transmit Xon2, Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

1 1 1 1 transmit Xon1, Xon2, Xoff1, Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Product data sheet Rev. 6 — 30 November 2010 10 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

There are two other enhanced features relating to softwar e flow cont rol:

•Xon Any function (MCR[5]): Operation will resume after receiving any character

after recognizing the Xoff character. It is possible that an Xon1 character is

recognized as an Xon Any character, which could cause an Xon2 character to be

written to the receive FIFO.

•Special character (E FR [5 ]) : Incoming data is compared to Xoff2. Detection of the

special charact er sets the Xoff interrupt (IIR[4]) but does not halt transmission. The

Xoff interr upt is cleared by a read of the IIR. The special char acter is transferred to the

receive FIFO.

6.3.1 Receive flow control

When software flow control operation is enabled, the SC16C752B will compare incoming

data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be

received sequentially). When the correct Xoff character are received, transmission is

halted after completing transmission of the current character. Xoff detection also sets

IIR[4] (if enabled via IER[5]) and causes INTA/INTB to go HIGH.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases

Xon1 and Xon2 must be received sequentially). When the correct Xon characters are

received, IIR[4] is cleared, and the Xoff interrupt disappears.

6.3.2 Transmit flow control

Xoff1/Xoff2 character is transmitted when the receive FIFO ha s passed the halt trigger

level programmed in TCR[3:0].

Xon1/Xon2 character is transmitted when the receive FIFO reaches the resume trigger

level programmed in TCR[7:4].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an

ordinary byte from the FIFO. This me ans that even if the word length is set to be 5, 6, or 7

characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xoff2 will be

transmitted. (Note that the transmission of 5 bits, 6 bits, or 7 bits of a character is seldom

done, but this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software flow control and hardware flow control will never be enabled

simultaneously. Figure 7 shows an exam p le of so ftware flow co nt ro l.

Product data sheet Rev. 6 — 30 November 2010 11 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.3.3 Software flow control example

6.3.3.1 Assumptions

UART1 is transmitting a large text file to UART2. Both UARTs are using software flow

control with single character Xoff (0Fh) and Xon (0Dh) tokens. Both have Xoff threshold

(TCR[3:0] = Fh) set to 60, and Xon threshold (TCR[7:4] = 8h) set to 32. Both have the

interrupt rece ive threshold (TLR[7:4] = Dh) set to 52.

UART 1 begins transmission and sends 52 characters, at which point UART2 will

generate an interrupt to its processor to service the receive FIFO, but assume the

interrupt latency is fairly long. UART1 will continue sending characters until a total of 60

characters have been sent. At this time, UART2 will transmit a 0Fh to UART1, informing

UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is

sending the Xof f character. Now UART2 is serviced and the processor reads enoug h data

out of the receive FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1,

informing UART1 to resume transmission.

Fig 7. Software flow control example

TRANSMIT FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

RECEIVE FIFO

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

Xon2 WORD

Xoff1 WORD

Xoff2 WORD

UART2UART1

002aaa22

data

Xoff–Xon–Xoff

compare

programmed

Xon-Xoff

characters

Product data sheet Rev. 6 — 30 November 2010 12 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.4 Reset

Table 4 summarizes the state of register after reset.

[1] Registers DLL, DLM, SPR, XON1, XON2 , XOFF1, XOFF2 are not reset by the top-level reset signal

RESET, i.e., they hold their initialization values during reset.

Table 5 summarizes the state of registers after reset.

Table 4. Register reset functions[1]

Interrupt Enable Register RESET all bits cleared

Interrupt Identification Register RESET bit 0 is set; all other bits cleared

FIFO Control Register RESET all bits cleared

Line Control Register RESET reset to 00011101 (1Dh)

Modem Control Register RESET all bits cleared

Line Status Register RESET bit 5 and bit 6 set; all other bits cleared

Modem Status Register RESET bits [3:0] cleared; bits [7:4] input signals

Enhanced Feature Register RESET all bits cleared

Receiver Holding Register RESET pointer logic cleared

Transmitter Holding Register RESET pointer logic cleared

Transmission Control Register RESET all bits cleared

Trigger Level Register RESET all bits cleared

Table 5. Signal RESET functions

Signal Reset control Reset state

TXn RESET HIGH

RTSn RESET HIGH

DTRn RESET HIGH

RXRDYn RESET HIGH

TXRDYn RESET LOW

Product data sheet Rev. 6 — 30 November 2010 13 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.5 Interrupts

The SC16C752B has interrupt generation and prioritization (six prioritized levels of

interrupts) capa bility. The Interrupt Enable Register (IER) enables each of the six types of

interrupts and the INTA/INTB signal in response to an interrupt generation. The IER can

also disable the interr upt system by clearing bit 0 to bit 3 and bit 5 to bit 7. When an

interrupt is generated, the IIR indicates that an interrupt is pending and provides the type

of interrupt through IIR[5:0]. Table 6 summarizes the interrupt control functions.

It is important to note that for the framing error, parity error, and break conditions, LSR[7]

generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,

and is cleared only whe n there are no more errors r emaining in the FIFO. LSR[4:2] always

represent the error status for the received character at the top of the RX FIFO. Reading

the RX FIFO updates LSR[4:2] to the appropr iate status for the new character at the top of

the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.

For the Xoff interrupt, if an Xof f flow characte r dete ction c ause d th e interr upt, the inte rrupt

is cleared by an Xon flow character detection. If a special character detection caused the

interrupt, the interrupt is cleared by a read of the LSR.

Table 6. Interrupt control functions

IIR[5:0] Priority

level Interrupt type Interrupt source Interrupt reset method

00 0001 None none none none

00 0110 1 receiver line status OE, FE, PE, or BI errors occur in

characters in the RX FIFO FE, PE, BI: all erroneous

characters are read from the

RX FIFO.

OE: read LSR

00 1100 2 RX time-out stale data in RX FIFO read RHR

00 0100 2 RHR interrupt DRDY (data ready)

(FIFO disable)

RX FIFO above trigger level

(FIFO enable)

read RHR

00 0010 3 THR interrupt TFE (THR empty)

(FIFO disable)

TX FIFO passes above trigger level

(FIFO enable)

read IIR or a write to the THR

00 0000 4 modem status MSR[3:0] = logic 0 read MSR

01 0000 5 Xoff interrupt receive Xoff character(s)/special

character receive Xon character(s)/Read of

IIR

10 0000 6 CTS, RTS RTSn pin or CTSn pin change state

from active (LOW) to inactive (HIGH) read IIR

Product data sheet Rev. 6 — 30 November 2010 14 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.5.1 Interrupt mode operation

In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the

receiver and transmitter by an interrupt signal, INTA/INTB. Therefore, it is not necessary

to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be

serviced. Figure 8 shows interrupt mode operation.

6.5.2 Polled mode operation

In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be

checked by polling the Line Status Register (LSR). This mode is an al ternative to the FIFO

interrupt mode of operation where the status of the receiver and transmitter is

automatically known by means of interrupts sent to the CPU. Figure 9 shows FIFO polled

mode operation.

Fig 8. Interrupt mode opera tio n

1111

IIR

IER

THR RHR

PROCESSOR

IOW / IOR

INTn

002aaf90

Fig 9. FI FO polled mode operation

0000

LSR

IER

THR RHR

PROCESSOR

IOW / IOR

002aaa23

Product data sheet Rev. 6 — 30 November 2010 15 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.6 DMA operation

There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by

FCR[3].

In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In

DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the

processor for longer per iods of time.

6.6.1 Single DMA transfers (DMA mode 0/FIFO disable)

Figure 10 shows TXRDYn and RXRDYn in DMA mode 0/FIFO disable.

6.6.1.1 Transmitter

When empty, the TXRDYn signal becomes active. TXRDYn will go inactive after one

character has been loaded into it.

6.6.1.2 Receiver

RXRDYn is active when there is at least one character in the FIFO. It becomes inactive

when the receiver is empty.

Fig 10. TXRDYn and RXRDYn in DMA mode 0/FIFO disable

transmit

wrptr

wrptr FIFO EMPTY

TXRDYn

receive

rdptr

rdptr FIFO EMPTY

RXRDYn

002aaa232

at least one

location filled

at least one

location filled

TXRDYn

Product data sheet Rev. 6 — 30 November 2010 16 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.6.2 Block DMA transfers (DMA mode 1)

Figure 11 shows TXRDYn and RXRDYn in DMA mode 1.

6.6.2.1 Transmitter

TXRDYn is active when there is a trigger level number of spaces available. It becomes

inactive when the FIFO is full.

6.6.2.2 Receiver

RXRDYn becomes active when the trigger level has been reached, or when a time-out

interrupt occurs. It will go inactive when the FIFO is empty o r an error in the receive FIFO

is flagged by LSR[7].

6.7 Sleep mode

Sleep mode is an enhan ced feature of the SC16C752B UAR T. It is enabled when EFR[4],

the enhanced fu nct ion s bit, is set and when IER[4] is set. Sleep mode is entered when:

•The serial data input line, RXn, is idle (see Section 6.8 “Break an d tim e-ou t

conditions”).

•The transmit FIFO and transmit shift register are empty.

•There are no interrupts pending except THR and time-out interrupts.

Remark: Sleep mode will not be entered if there is data in the receive FIFO.

In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are

clocked using these clocks, the power co nsumption is greatly reduced. The UART will

wake up when any change is detected on the RXn line, when there is any change in the

state of the modem input pins, or if data is written to the transmit FIFO.

Remark: Writing to the divisor latches DLL and DLM to set the baud clock must not be

done during Sleep mode. The refore, it is advisable to disable Sleep mode using IER[4]

before writing to DLL or DLM.

Fig 11. TXRDYn and RXRDYn in DMA mode 1

transmit

wrptr

TXRDYn

FIFO full

TXRDYn

receive

rdptr

rdptr FIFO EMPTY

RXRDYn

002aaa234

trigger

level

trigger

level

at least one

location filled

Product data sheet Rev. 6 — 30 November 2010 17 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.8 Break and time-out conditions

An RX idle condition is detected when the receiver line, RXn, has been HIGH for

4 character time. The receiver line is sampled midway through each bit.

When a break condition occurs, the TXn lin e is pulled LOW. A break condition is activated

by setting LCR[6].

6.9 Programmable baud rate generator

The SC16C752B UART contains a programmable baud generator that takes any clock

input and divides it by a divisor in the range between 1 and (216 −1). An additional

divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in

Figure 12. The output frequency of the baud rate generator is 16 × the baud rate. The

formula for the divisor is given in Equation 1:

(1)

Where:

prescaler = 1, when MCR[7] is set to logic 0 after reset (divide-by-1 clock selected);

prescaler = 4, when MCR[7] is set to logic 1 after reset (divide-by-4 clock selected).

Remark: The default value of prescaler after reset is divide-by-1.

Figure 12 shows the internal prescaler and baud rate generator circuitry.

DLL and DLM must be writte n to in or der to p ro gram the ba ud rate. DLL an d DLM are the

least significant and most significant byte of the baud rate divisor. If DLL and DLM are

both zero, the UART is effectively disabled, as no baud clock will be generated.

Remark: The programmab le baud rate generator is provided to select both the transmit

and receive clock rates.

Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency

1.8432 MHz and 3.072 MHz, respectively.

Figure 13 shows the crystal clock circuit reference.

Fig 12. Prescaler and baud rate generator block diagram

divisor

XTAL1 crystal input frequency

prescaler

-----------------------------------------------------------------------------------

⎝⎠

⎛⎞

desired baud rate 16×()

-----------------------------------------------------------------------------------------

BAUD RATE

GENERATOR

LOGIC

MCR[7] = 1

MCR[7] = 0

PRESCALER

LOGIC

(DIVIDE-BY-1)

INTERNAL

OSCILLATOR

LOGIC

002aaa233

XTAL1

XTAL2

input clock

PRESCALER

LOGIC

(DIVIDE-BY-4)

reference

clock

internal

baud rate

clock for

transmitter

and receiver

Product data sheet Rev. 6 — 30 November 2010 18 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Table 7. Baud rates using a 1.8432 MHz crystal

Desired baud rate Divisor used to generate

16×clock Percent error difference

between desired and actual

50 2304

75 1536

110 1047 0.026

134.5 857 0.058

150 768

300 384

600 192

1200 96

1800 64

2000 58 0.69

2400 48

3600 32

4800 24

7200 16

9600 12

19200 6

38400 3

56000 2 2.86

Table 8. Baud rates using a 3.072 MHz crystal

Desired baud rate Divisor used to generate

16×clock Percent error difference

between desired and actual

50 2304

75 2560

110 1745 0.026

134.5 1428 0.034

150 1280

300 640

600 320

1200 160

1800 107 0.312

2000 96

2400 80

3600 53 0.628

4800 40

7200 27 1.23

9600 20

19200 10

38400 5

Product data sheet Rev. 6 — 30 November 2010 19 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7. Register descriptions

Each register is selected using address lines A0, A1, A2, and in some cases, bits from

other registers. The programming combinations for register selection are shown in

Table 9.

[1] MCR[7] can only be modified when EFR[4] is set.

[2] Accessed by a combination of address pins and register bits.

[3] Accessible only when LCR[7] is logic 1.

[4] Accessible only when LCR is set to 10111111 (BFh).

[5] Accessible only when EFR[4] = logic 1 and MCR[6] = logic 1, i.e., EFR[4] and MCR[6] are read/write

enables.

[6] Accessible only when CSA or CSB = logic 0, MCR[2] = logic 1, and loopback is disabled

(MCR[4] = logic 0).

Fig 13. Crystal oscillator connections

002aaa87

47 pF

XTAL1 XTAL2

1.8432 MHz

22 pF

33 pF

XTAL1 XTAL2

1.5 kΩ

1.8432 MHz

22 pF

Table 9. Register map - read/write properties

A2 A1 A0 Read mode Wr ite mode

0 0 0 Receive Holding Reg ister (RHR) Transmit Holding Register (THR)

0 0 1 Interrupt Enable Register (IER) Interrupt Enable Register

0 1 0 Interrupt Identification Register (IIR) FIFO Control Register (FCR)

0 1 1 Line Control Register (LCR) Line Control Register

1 0 0 Modem Control Register (MCR)[1] Modem Control Register[1]

1 0 1 Line Status Register (LSR)

1 1 0 Modem Status Register (MSR)

1 1 1 Scratchpad Register (SPR) Scratchpad Register

0 0 0 Divisor Latch LSB (DLL)[2][3] Divisor Latch LSB[2][3]

0 0 1 Divisor Latch MSB (DLM)[2][3] Divisor Latch MSB[2][3]

0 1 0 Enhanced Feature Registe r (EFR)[2][4] Enhanced Feature Register[2][4]

100Xon1 word

[2][4] Xon1 word[2][4]

101Xon2 word

[2][4] Xon2 word[2][4]

110Xoff1 word

[2][4] Xoff1 word[2][4]

111Xoff2 word

[2][4] Xoff2 word[2][4]

1 1 0 T ransmission Control Register (TCR)[2][5] Transmission Control Register[2][5]

1 1 1 Trigger Level Regi st er (TL R )[2][5] Trigger Level Register [2][5]

1 1 1 FIFO ready register[2][6]

Product data sheet Rev. 6 — 30 November 2010 20 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Table 10 lists and describes the SC16C752B internal registers.

[1] These registers are accessible only when LCR[7] = logic 0.

[2] These bits can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.

[3] The Special register set is accessible only when LCR[7] is set to a logic 1.

[4] Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh.

Table 10. SC16C752B internal register s

A2 A1 A0 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/

Write

General register set[1]

0 0 0 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R

0 0 0 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W

001IER 0/CTS

interrupt

enable[2]

0/RTS

interrupt

enable[2]

0/Xoff[2] 0/X sleep

mode[2] modem

status

interrupt

receive

line status

interrupt

THR

empty

interrupt

Rx data

available

interrupt

R/W

0 1 0 FCR RX trigger

level

(MSB)

RX trigger

level (LSB) 0/TX

trigger

level

(MSB)[2]

0/TX

trigger

level

(LSB)[2]

DMA

mode

select

TX FIFO

reset RX FIFO

reset FIFO

enable W

0 1 0 IIR FCR[0] FCR[0] 0/CTS,

RTS 0/Xoff interrupt

priority

bit 2

interrupt

priority

bit 1

interrupt

priority

bit 0

interrupt

status R

011LCR DLAB break

control bit set parity parity type

select parity

enable number of

stop bits word

length

bit 1

word

length

bit 0

R/W

100MCR 1× or

1×/4

clock[2]

TCR and

TLR

enable[2]

0/Xon

Any[2] 0/enable

loopback IRQ

enable

FIFO

ready

enable

RTS DTR R/W

1 0 1 LSR 0/error in

RX FIFO THR and

TSR empty THR

empty break

interrupt framing

error parity

error overrun

error data in

receiver R

110MSR CD RI DSR CTS ΔCD ΔRI ΔDSR ΔCTS R

1 1 1 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bi t 2 bit 1 bit 0 R/W

1 1 0 TCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 1 1 TLR bi t 7 bit 6 bit 5 bit 4 bit 3 bi t 2 bit 1 bit 0 R/W

111FIFO

Rdy 00 RX FIFO

B status RX FIFO

A status 0 0 TX FIFO

B status TX FIFO

A status R

Special register set[3]

0 0 0 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

0 0 1 DLM bit 15 bit 14 bit 13 bit 12 bit 11 bi t 10 bit 9 bit 8 R/W

Enhanced register set[4]

010EFR auto CTSauto RTS Special

character

detect

Enable

IER[7:4],

FCR[5:4],

MCR[7:5]

software

flow

control

bit 3

software

flow

control

bit 2

software

flow

control

bit 1

software

flow

control

bit 0

R/W

1 0 0 Xon1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 0 1 Xon2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 1 0 Xoff1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

1 1 1 Xoff2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

Product data sheet Rev. 6 — 30 November 2010 21 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Remark: Refer to the notes under Table 9 for more register access information.

7.1 Receiver Holding Register (RHR)

The receiver section consists of the Receiver Holding Register (RHR) and the Receiver

Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data

from the RX terminal. The data is converted to parallel data and moved to the RHR. The

receiver section is contro lled by the L ine Contro l Register. If the FIFO is disabled, loca tion

zero of the FIFO is used to store the characters.

Remark: In this case, characters are overwritten if overflow occurs.

If overflow occurs, characters are lost. The RHR als o stores the error status bits

associated with each character.

7.2 Transmit Holding Register (THR)

The transmitter section consists of the Transmit Holding Register (T HR) and the Transm it

Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and

shifts it into the TSR, where it is converted to serial dat a and moved out on the TXn

terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are

lost if overflow occurs.

Product data sheet Rev. 6 — 30 November 2010 22 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.3 FIFO Control Register (FCR)

This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting

transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11

shows FIFO control register bit settings.

Table 11. FIFO Control Register bits description

Bit Symbol Description

7:6 FCR[7] (MSB),

FCR[6] (LSB) RX trigger. Set s the trigger level for the receive FIFO.

00 - 8 characters

01 - 16 characters

10 - 56 characters

11 - 60 characters

5:4 FCR[5] (MSB),

FCR[4] (LSB) TX trigger. Sets the trigger level for the transmit FIFO.

00 - 8 spaces

01 - 16 spaces

10 - 32 spaces

11 - 56 spaces

FCR[5:4] can only be modified and enabled when EFR[4] is set. This is

because the transmit tri gger level is regarded as an enhanced function.

3 FCR[3] DMA mode select.

logic 0 = set DMA mode ‘0’

logic 1 = set DMA mode ‘1’

2 FCR[2] Reset transmit F IF O.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = Clears the conten ts of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

1 FCR[1] Reset receive FIFO.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = Clears the conten ts of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

0 FCR[0] FIFO enable.

logic 0 = disab le the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO.

Product data sheet Rev. 6 — 30 November 2010 23 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.4 Line Control Register (LCR)

This register controls the data communication format. The wo rd length, number of stop

bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12

shows the Line Control Register bit settings.

Table 12. Line Control Register bits description

Bit Symbol Description

7 LCR[7] Divisor latch enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6 LCR[6] Break control bit. When enabled, the Break control bit causes a break

condition to be transmitted (the TXn output is forced to a logic 0 state). This

condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no break condition (normal default condition)

logic 1 = forces the transmitter output (TXn) to a logic 0 to alert the

communication terminal to a line break condition

5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the

transmit and receive data.

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the

transmit and receive data.

4 LCR[4] Parity type select.

logic 0 = odd parity is generated (if LCR[3] = 1)

logic 1 = even parity is generated (if LCR[3] = 1)

3 LCR[3] Parity enable.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during transmission and the receiver

checks for received parity

2 LCR[2] Number of Stop bits. Specifies the number of stop bits.

0 - 1 stop bit (word length = 5, 6, 7, 8)

1 - 1.5 stop bits (word length = 5)

1 - 2 stop bits (word length = 6, 7, 8)

1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be

transmitted or received.

00 - 5 bits

01 - 6 bits

10 - 7 bits

11 - 8 bits

Product data sheet Rev. 6 — 30 November 2010 24 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.5 Line Status Register (LSR)

Table 13 shows the Line Status Register bit settings.

When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the

top of the receive FIFO (next character to be read). The LSR[4:2] registers do not

physically exist, as the data read from the receive FIFO is output directly onto the output

data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified by

reading the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the receive FIFO, and is cleared only

when there are no mo re errors remaining in the FIFO.

Reading the LSR does not cause an increment of the receive FIFO read pointer. The

receive FIFO read pointer is incremented by reading the RHR.

Table 13. Line Status Register bits description

Bit Symbol Description

7 LSR[7] FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = At least one parity error, framing error, or break indication is in the

receiver FIFO. This bit is cleared when no more errors are present in the

FIFO.

6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator.

logic 0 = transmitter hold and shift registers are not empty

logic 1 = transmitter hold and shift registers are empty

5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator.

logic 0 = Transmit Holding Register is not empty

logic 1 = Transmit Holding Register is empty. The processor can now load

up to 64 bytes of data into the THR if the transmit FIFO is enabled.

4 LSR[4] Break interrupt.

logic 0 = No break condition (normal default condition)

logic 1 = A break condition occurred and associa ted byte is 00, i.e.,

RXn was LOW for one characte r time frame

3 LSR[3] Framing error.

logic 0 = no framing error in data being read fr om receive FIFO (normal

default condition)

logic 1 = framing error occurred in data being read from receive FIFO, i.e.,

received data did not have a valid stop bit.

2 LSR[2] Parity error.

logic 0 = no parity error (normal default conditio n)

logic 1 = parity error in data being read from receive FIFO

1 LSR[1] Overrun error.

logic 0 = no overrun error (normal default condition )

logic 1 = overrun error has occurr ed

0 LSR[0] Data in rec eiv e r.

logic 0 = no data in receive FIFO (normal default conditio n)

logic 1 = at least one chara c ter in the receive FIFO

Product data sheet Rev. 6 — 30 November 2010 25 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.6 Modem Control Register (MCR)

The MCR controls the interface with the mode, data set, or peripheral device that is

emulating the modem. Table 14 shows modem control register bit settings.

[1] MCR[7:5] can only be modified when EFR[4] is set, i.e., EFR[4] is a write enable.

Table 14. Modem Control Register bits description

Bit Symbol Description

7 MCR[7][1] Clock select.

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

6 MCR[6][1] TCR and TLR enable.

logic 0 = no action

logic 1 = enabl e access to the TCR and TLR registers

5 MCR[5][1] Xon An y.

logic 0 = disable Xon Any function

logic 1 = enable Xon Any function

4 MCR[4] Enable loopback.

logic 0 = normal operating mode.

logic 1 = enable local Loopback mode (internal). In this mode the MCR[3:0]

signals are looped back into MSR[7:4] and the TXn output is looped back to

the RXn input internally.

3 MCR[3] IRQ enable OP.

logic 0 = forces INTA, INTB outp uts to the 3-state mode and OP output to

HIGH state

logic 1 = forces the INTA-INTB outputs to the active state and OP output to

LOW state. In Loopback mode, controls MSR[7].

2 MCR[2] FIFO Ready enable.

logic 0 = disable the FIFO Rdy register

logic 1 = enable the FIFO Rdy register . In Loopback mode, controls MSR[6].

1 MCR[1] RTS

logic 0 = force RTSn output to inactive (HIGH)

logic 1 = force RTSn output to active (LOW). In loopback mode, controls

MSR[4]. If auto-RTS is enabled, the RTSn output is controlled by hardware

flow control.

0 MCR[0] DTR

logic 0 = force DTRn output to inactive (HIGH)

logic 1 = force DTRn output to active (LOW). In Loopback mode, controls

MSR[5].

Product data sheet Rev. 6 — 30 November 2010 26 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.7 Modem Status Register (MSR)

This 8-bit register pro vides information about th e current st ate of the control lines from the

mode, data set, or peripheral device to the processor. It also indicates when a control

input from the modem changes state. Table 15 shows Modem Status Register bit settings

per channel.

[1] The primary inputs RIn, CDn, CTSn, DSRn are all active LOW, but their registered equivalents in the MSR

and MCR (in Loopback) registers are active HIGH.

Table 15. Modem Status Register bits description

Bit Symbol Description

7 MSR[7] CD (active HIGH, logic 1)[1]. This bit is the complement of the CDn input

during normal mode. During internal Loopback mode, it is equivalent to

MCR[3].

6 MSR[6] RI (active HIGH, logic 1)[1]. This bit is the complement of the RIn input during

normal mode. During internal Loopb ack mode, it is equi valent to MCR[2].

5 MSR[5] DSR (active HIGH, logic 1)[1]. This bit is the complement of the DSRn input

during normal mode. During Internal Loopback mode, it is equivalent MCR[0].

4 MSR[4] CTS (active HIGH, logic 1)[1]. This bit is the complement of the CTSn input

during normal mode. During internal Loopback mode, it is equivalent to

MCR[1].

3MSR[3]ΔCD. Indicates that CDn input (or MCR[3] in Loopback mode) has changed

state. Cleared on a read.

2MSR[2]ΔRI. Indicates that RIn input (or MCR[2] in Loopback mode) has changed

state from LOW to HIGH. Cleared on a read.

1MSR[1]ΔDSR. Indicates that DSRn input (or MCR[0] in Loopback mode) has changed

state. Cleared on a read.

0MSR[0]ΔCTS. Indicates that CTSn input (or MCR[1] in Loopback mode) has changed

state. Cleared on a read.

Product data sheet Rev. 6 — 30 November 2010 27 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.8 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver

error, RHR interrupt, THR interrupt, Xoff received, or CTSn/RTSn change of state from

LOW to HIGH. The INTA/INTB output signal is activated in response to interrupt

generation. Table 16 shows Interrupt Enable Register bit settings.

[1] IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will not

cause a new interrupt if the THR is below the threshold.

Table 16. Interrupt Enable Register bit s description

Bit Symbol Description

7IER[7]

[1] CTS interrupt enable.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt

6IER[6]

[1] RTS interrupt enable.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enab le the RTS interrupt

5IER[5]

[1] Xoff interrupt.

logic 0 = disable the Xoff interrupt (normal defaul t condition)

logic 1 = enable the Xoff interrupt

4IER[4]

[1] Sleep mode.

logic 0 = disab le Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See Section 6.7 “Sleep mode” for details.

3 IER[3] Mode m Status Interrupt.

logic 0 = disable the Modem Status Register interrupt (normal defaul t

condition)

logic 1 = enab le the Modem Status Register interru pt

2 IER[2] Receive Line Status interrupt.

logic 0 = disab le the receiver line status interrupt (normal default condition)

logic 1 = enab le the receiver line status interrupt

1 IER[1] Transmit Holding Register interrupt.

logic 0 = disable the THR interrupt (normal default condition)

logic 1 = enable the THR interrupt

0 IER[0] Receive Holding Register interrupt.

logic 0 = disab le the RHR interrupt (normal default condition)

logic 1 = enab le the RHR interrupt

Product data sheet Rev. 6 — 30 November 2010 28 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.9 Interrupt Identification Register (IIR)

The IIR is a read-only 8-bi t register which provides the source of the interrupt in a

prioritized manner. Table 17 shows Interrupt Identification Register bit settings.

The interrupt priority list is shown in Table 18.

7.10 Enhanced Feature Register (EFR)

This 8-bit register enables or disables the enhan ced features of the UAR T. Table 19

shows the Enhanced Feature Register bit settings.

Table 17. Interrupt Identification Register bits description

Bit Symbol Description

7:6 IIR[7:6] Mirror the contents of FCR[0]

5 IIR[5] RTSn/CTSn LOW-to-HIGH change of state

4 IIR[4] 1 = Xoff/Special character has been detected

3:1 IIR[3:1] 3-bit encoded interrupt. See Table 18.

0 IIR[0] Interrupt status.

logic 0 = an interrup t is pen ding

logic 1 = no interrup t is pen ding

Table 18. Interrupt priority list

Priority

level IIR[5] IIR[4] IIR[3] IIR[2] IIR[1] IIR[0] Source of the interrupt

1 000110Receiver Line Status error

2 001100Receiver time-out interrupt

2 000100RHR interrupt

3 000010THR interrupt

4 000000Modem interrupt

5 010000Received Xoff signal/ special

character

6 100000CTSn

, RTSn change of state from

active (LOW) to inactive (HIGH)

Table 19. Enhanced Feature Register bits description

Bit Symbol Description

7EFR[7]CTS

flow control enable.

logic 0 = CTS flow control is disabled (normal default condition)

logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH

signal is detected on the CTSn pin.

6 EFR[6] RTS flow control enable.

logic 0 = RTS flow control is disabled (normal default condition)

logic 1 = RTS flow control is enabled. The RTSn pin goes HIGH when the

receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the

receiver FIFO resume transmission trigger level TCR[7:4] is reached.

Product data sheet Rev. 6 — 30 November 2010 29 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.11 Divisor latches (DLL, DLM)

These are two 8-bit registe rs which store the 16-bit divisor for generation of the baud clock

in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores

the least significant part of the divisor.

Note that DLL and DLM can only be written to before Sleep mode is enabled, i.e., before

IER[4] is set.

7.12 Transmission Control Register (TCR)

This 8-bit register is used to store the receive FIFO threshold levels to stop/start

transmission during hardwa re/software flow contro l. Table 20 shows Transmission Control

TCR trigger levels are available from 0 bytes to 60 bytes with a granularity of four.

Remark: TCR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. The

programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in

hardware check to make sure this condition is met. Also, the TCR must be programmed

with this condition before auto-RTS or software flow control is enabled to avoid spurious

operation of the de vic e.

5 EFR[5] S pecial character detect.

logic 0 = spec ial character detect disabled (normal default condition)

logic 1 = spec ial character detect enabled. Received data is compared with

Xoff2 data. If a match occurs, the received data is transferred to FIFO and IIR[4]

is set to a logic 1 to indicate a special character has been detected.

4 EF R[4] Enhan ced functions enable bit.

logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],

MCR[7:5]

logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can

be modified, i.e., this bit is therefore a write enable.

3:0 EFR[3:0] Combinations of software flow control can be selected by programming these bits.

See Table 3 “Software flow control options (EFR[0:3])”.

Table 19. Enhanced Feature Register bits description …continued

Bit Symbol Description

Table 20. Transmission Control Register bits description

Bit Symbol Description

7:4 TCR[7:4] receive FIFO trigger level to resume transmission (0 to 60).

3:0 TCR[3:0] receive FIFO trigger level to halt transmissi on (0 to 60).

Product data sheet Rev. 6 — 30 November 2010 30 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.13 Trigger Level Register (TLR)

This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for

DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a

granularity of 4. Table 21 shows trigger level register bit settings.

Remark: TLR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. If

TLR[3:0] or TL R[7 :4 ] ar e log ic 0, the selectable trigger levels via the FIFO Control

from 4 bytes to 60 bytes are available with a granularity of four. The TLR should be

programme d for N⁄4, where N is the desired trigger level.

When the trigger level setting in TLR is zero, the SC16C752B uses the trigger level setting

defined in FCR. If TLR ha s no n-zero trigger level value, the trigger level defined in FCR is

discarded. This applies to both transmit FIFO and receive FIFO trigger level setting.

When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,

i.e., ‘00’.

7.14 FIFO ready register

The FIFO ready register provid es real-time status of the transmit and receive FIFOs of

both channels.

The FIFO Rdy register is a read-only register that can be accessed when any of the two

UARTs is selected CSA or CSB = logic 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and

loopback is disabled. The address is 111.

Table 21. Trigger Level Register bits description

Bit Symbol Description

7:4 TLR[7:4] receive FIFO trigger levels (4 to 60), number of characters available

3:0 TLR[3:0] transmit FIFO trigger levels (4 to 60), number of spaces available

Table 22. FIFO Ready Register bits description

Bit Symbol Description

7:6 FIFO Rdy[7:6] unused; always 0

5 FIFO Rdy[5] receive FIFO B status. Related to DMA.

4 FIFO Rdy[4] receive FIFO A status. Related to DMA.

3:2 FIFO Rdy[3:2] unused; always 0

1 FIFO Rdy[1] transmit FIFO B status. Related to DMA.

0 FIFO Rdy[0] transmit FIFO A status. Related to DMA.

Product data sheet Rev. 6 — 30 November 2010 31 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

8. Programmer’s guide

The base set of registers that is used during high-speed data transfer have a

straightforw ard access method. The extended function registers require special access

bits to be decoded along with the address lines. The following guide will help with

programming these registers. Note that the descriptions below are for individual register

access. Some streamlining through interleaving can be obtained when programming all

the registers.

Tabl e 23. Register programming gui de

Command Actions

Set baud rate to VALUE1, VALUE2 Read LCR (03h), save in temp

Set LCR (03h) to 80h

Set DLL (00h) to VA LUE1

SET DLM (01h) to VALUE2

Set LCR (03h) to temp

Set Xoff1, Xon1 to VALUE1, VALUE2 Read LCR (03h), save in temp

Set LCR (03h) to BFh

Set Xoff1 (06h) to VALUE1

SET Xon1 (04h) to VALUE2

Set LCR (03h) to temp

Set Xoff2, Xon2 to VALUE1, VALUE2 Read LCR (03h), save in temp

Set LCR (03h) to BFh

Set Xoff2 (07h) to VALUE1

SET Xon2 (05h) to VALUE2

Set LCR (03h) to temp

Set software flow control mode to VALUE Read LCR (03h), save in temp

Set LCR (03h) to BFh

Set EFR (02h) to VALUE

Set LCR (03h) to temp

Set flow control threshold to VALUE Read LCR (03h), save in temp1

Set LCR (03h) to BFh

Read EFR (02h), save in temp2

Set EFR (02h) to 10h + temp2

Set LCR (03h) to 00h

Read MCR (04h), save in temp3

Set MCR (04h) to 40h + temp3

Set TCR (06h) to VALUE

Set MCR (04h) to temp 3

Set LCR (03h) to BFh

Set EFR (02h) to temp2

Set LCR (03h) to temp1

Product data sheet Rev. 6 — 30 November 2010 32 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

[1] × sign here means bit-AND.

Set TX FIFO and RX FIFO thresholds

to VALUE Read LCR (03h), save in temp1

Set LCR (03h) to BFh

Read EFR (02h), save in temp2

Set EFR (02h) to 10h + temp2

Set LCR (03h) to 00h

Read MCR (04h), save in temp3

Set MCR (04h) to 40h + temp3

Set TLR (07h) to VALUE

Set MCR (04h) to temp 3

Set LCR (03h) to BFh

Set EFR (02h) to temp2

Set LCR (03h) to temp1

Read FIFO Rdy register Read MCR (04h), save in temp1

Set temp2 = temp1 × EFh[1]

Set MCR (04h) = 4 0h + temp2

Read FFR (07h), save in temp2

Pass temp2 back to host

Set MCR (04h) to temp 1

Set prescaler value to divide-by-1 Read LCR (0 3h), save in te mp1

Set LCR (03h) to BFh

Read EFR (02h), save in temp2

Set EFR (02h) to 10h + temp2

Set LCR (03h) to 00h

Read MCR (04h), save in temp3

Set MCR (04h) to temp3 × 7Fh[1]

Set LCR (03h) to BFh

Set EFR (02h) to temp2

Set LCR (03h) to temp1

Set prescaler value to divide-by-4 Read LCR (0 3h), save in te mp1

Set LCR (03h) to BFh

Read EFR (02h), save in temp2

Set EFR (02h) to 10h + temp2

Set LCR (03h) to 00h

Read MCR (04h), save in temp3

Set MCR (04h) to temp3 + 80h

Set LCR (03h) to BFh

Set EFR (02h) to temp2

Set LCR (03h) to temp1

Tabl e 23. Register programming gui de …con tinue d

Command Actions

Product data sheet Rev. 6 — 30 November 2010 33 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

9. Limiting values

10. Static characteristics

[1] Meets TTL levels, VIH(min) = 2 V and VIL(max) = 0.8 V on non-hysteresis inputs.

[2] Applies for external output buffers.

[3] These parameters apply for D7 to D0.

[4] These parameters apply for DTRA, DTRB, INTA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB.

Table 24. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage - 7 V

Vnvoltage on any other pin at D7 to D0 pins GND −0.3 VCC +0.3 V

at any input only pin GND −0.3 5.3 V

Tamb ambient temperature operating in free-air −40 +85 °C

Tstg storage temperature −65 +150 °C

Table 25. Static characteristics

VCC = 2.5 V, 3.3 V

10 % or 5 V

10 %.

Symbol Parameter Conditions VCC =2.5V VCC = 3.3V or 5V Unit

Min Typ Max Min Typ Max

VCC supply voltage VCC −10 % VCC VCC +10% V

CC −10 % VCC VCC +10% V

VIinput voltage 0 - VCC 0-V

CC V

VIH HIGH-level input

voltage [1] 1.6 - VCC 2.0 - VCC V

VIL LOW-level input

voltage [1] - - 0.65 - - 0.8 V

VOoutput voltage [2] 0-V

CC 0-V

CC V

VOH HIGH-level

output voltage IOH =−8mA [3] --- 2.0--V

IOH =−4mA [4] --- 2.0--V

IOH =−800 μA[3] 1.85 - - - - - V

IOH =−400 μA[4] 1.85 - - - - - V

VOL LOW-level output

voltage[5] IOL =8mA [3] --- --0.4V

IOL =4mA [4] --- --0.4V

IOL =2mA [3] --0.4 ---V

IOL =1.6mA [4] --0.4 ---V

Ciinput capacitance - - 18 - - 18 p F

Tamb ambient

temperature operating −40 +25 +85 −40 +25 +85 °C

Tjjunction

temperature [6] 025125 025125°C

δclock duty cycle - 50 - - 50 - %

ICC supply current f = 5 MHz [7] --3.5 --4.5mA

ICC(sleep) sleep mode

supply current [8] - - 50 - - 50 μA

Product data sheet Rev. 6 — 30 November 2010 34 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

[5] Except XTAL2, VOL =1V typical.

[6] These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 °C. The customer is

responsible for verifying junction temperature.

[7] Measurement condition, normal operation other than Sleep mode:

VCC = 3.3 V; Tamb =25°C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the

recommended operating conditions with divisor of 1.

[8] Sleep mode current might be higher if there is activity on the UART data bus during Sleep mode.

11. Dynamic characteristics

Table 26 . Dynamic character istics

Tamb =

−

C to +85

C; VCC = 2.5 V, 3.3 V

10 % or 5 V

10 %, unless specified otherwise.

Symbol Parameter Conditions VCC = 2.5 V VCC = 3.3 V or 5 V Unit

Min Max Min Max

td1 IOR delay from chip select 10 - 0 - ns

td2 read cycle delay 25 pF load 20 - 20 - ns

td3 delay from IOR to data 25 pF load - 77 - 26 ns

td4 data disable time 25 pF load - 15 - 15 ns

td5 IOW delay from chip select 10 - 10 - ns

td6 write cycle delay 25 - 25 - ns

td7 delay from IOW to output 25 pF load - 100 - 33 ns

td8 delay to set interrupt from modem input 25 pF load - 100 - 24 ns

td9 delay to reset interrupt from IOR 25 pF load - 100 - 24 ns

td10 delay from stop to set interrupt - 1TRCLK[1] -1T

RCLK[1] s

td11 delay from IOR to reset interrupt 25 pF load - 100 - 29 ns

td12 delay from start to set interrupt - 100 - 100 ns

td13 delay from IOW to transmit start 8 24TRCLK[1] 824T

RCLK[1] s

td14 delay from IOW to reset interrupt - 100 - 70 ns

td15 delay from stop to set RXRDYn -1T

RCLK[1] -1T

RCLK[1] s

td16 delay from IOR to reset RXRDYn -100- 75ns

td17 delay from IOW to set TXRDYn -100- 70ns

td18 delay from start to reset TXRDYn - 16TRCLK[1] -16T

RCLK[1] s

td19 delay between successive assertion of

IOW and IOR -20-20ns

th1 chip select hold time from IOR 0-0-ns

th2 chip select hold time from IOW 0-0-ns

th3 data hold time 15 - 15 - ns

th4 address hold time 0 - 0 - ns

th5 hold time from XT AL1 clock HIGH-to-LOW

transition to IOW or IOR release 20 - 20 - ns

tp1 clock cycle period 10 - 6 - ns

tp2 clock cycle period 10 - 6 - ns

fXTAL1 frequency on pin XTAL1 [2] -48-80MHz

tw(RESET) pulse width on pin RESET [3] 100 - 40 - ns

tsu1 address set-up time 0 - 0 - ns

Product data sheet Rev. 6 — 30 November 2010 35 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

[1] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

[2] Applies to external clock; crystal oscillator max 24 MHz.

[3] Reset pulse must happen when CSA, CSB, IOR, IOW are inactive.

11.1 Timing diagrams

tsu2 data set-up time 16 - 16 - ns

tsu3 set-up time from IOW or IOR assertion to

XTAL1 clock LOW-to-HIGH transition 20 - 20 - ns

tw1 IOR strobe width 77 - 30 - ns

tw2 IOW strobe width 30 - 30 - ns

Table 26 . Dynamic character istics …continued

Tamb =

−

C to +85

C; VCC = 2.5 V, 3.3 V

10 % or 5 V

10 %, unless specified otherwise.

Symbol Parameter Conditions VCC = 2.5 V VCC = 3.3 V or 5 V Unit

Min Max Min Max

Fig 14. General read timing

data

active

valid

address

002aaa23

A0 to A2

CSA, CSB

IOR

D0 to D7

td3 td4

td1 tw1 td2

th4

tsu1

th1

Product data sheet Rev. 6 — 30 November 2010 36 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Fig 15. General write timing

data

active

valid

address

002aaa23

A0 to A2

CSA, CSB

IOW

D0 to D7

tsu2 th3

td5 tw2 td6

th4

tsu1

th2

Fig 16. Modem input/output timing

td7

change of state

td8 td8

td9

002aaa23

td8

change of state

change of state change of state

active

active active active

change of state

RTSA, RTSB

DTRA, DTRB

IOW

CDA, CDB

CTSA, CTSB

DSRA, DSRB

INTA, INTB

IOR

RIA, RIB

Product data sheet Rev. 6 — 30 November 2010 37 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Fig 17. Receive timing

D0 D1 D2 D3 D4 D5 D6 D7

active

16 baud rate clock

002aaa23

td11

data

Start

bit

Stop

bit

parity

bit

Start

bit

td10

RXA, RXB

INTA, INTB

IOR

data bits (0 to 7)

5 data bits

6 data bits

7 data bits

Fig 18. Receive ready timin g in non-FIFO mode

D0 D1 D2 D3 D4 D5 D6 D7

002aab24

data

start

bit

stop

bit

parity

bit

td15

RXA, RXB

RXRDYA

IOR

active data

ready

start

bit data bits (0 to 7)

active

td16

RXRDYB

Product data sheet Rev. 6 — 30 November 2010 38 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Fig 19. Receive ready timing in FIFO mode

D0 D1 D2 D3 D4 D5 D6 D7

002aaa24

first byte that

reaches the

trigger level

stop

bit

parity

bit

td15

RXA, RXB

RXRDYA

IOR

active data

ready

start

bit data bits (0 to 7)

active

td16

RXRDYB

Fig 20. Trans mit timing

D0 D1 D2 D3 D4 D5 D6 D7

active

TX ready

active

16 baud rate clock

002aaa242

td14

Start

bit

td12

TXA, TXB

INTA, INTB

IOW

data bits (0 to 7)

active

td13

5 data bits

6 data bits

7 data bits

parity

bit

Stop

bit

data

Start

bit

Product data sheet Rev. 6 — 30 November 2010 39 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Fig 21. Trans mit ready timing in non-FIFO mode

D0 D1 D2 D3 D4 D5 D6 D7

002aaa24

start

bit

td17

TXRDYA

IOW

data bits (0 to 7)

active

D0 to D7 byte #1 td18

transmitter

not ready

active

transmitter ready

parity

bit

stop

bit

data

start

bit

TXA, TXB

TXRDYB

Fig 22. Trans mit ready timing in FIFO mode

D0 D1 D2 D3 D4 D5 D6 D7

002aaa24

stop

bit

parity

bit

td17

TXA, TXB

IOW

D0 to D7

start

bit data bits (0 to 7)

byte #64

TXRDYA

td18

trigger

lead

active

5 data bits

6 data bits

7 data bits

TXRDYB

Product data sheet Rev. 6 — 30 November 2010 40 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

12. Package outline

Fig 23. Package outline SOT313-2 (LQFP48)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05

1.45

1.35 0.25 0.27

0.17

0.18

0.12

7.1

6.9 0.5 9.15

8.85

0.95

0.55

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

QFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313

-2

Product data sheet Rev. 6 — 30 November 2010 41 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Fig 24. Package outline SOT617-1 (HVQFN32)

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

3.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT617-1 MO-220- - - - - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT617

-1

VQFN32: plastic thermal enhanced very thin quad flat package; no leads;

2 terminals; body 5 x 5 x 0.85 mm

A(1)

max.

detail X

y1C

916

32 25

terminal 1

index area

terminal 1

index area

01-08-08

02-10-18

1/2 e

1/2 e AC

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 6 — 30 November 2010 42 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which p ackages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 6 — 30 November 2010 43 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

13.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 25) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 27 and 28

Moisture sensitivity precautions, as indicated on the packin g, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 25.

Table 27. SnPb eutectic process (from J-STD-0 20C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 28. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 6 — 30 November 2010 44 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Abbreviations

15. Revision history

MSL: Moisture Sensitivity Level

Fig 25. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 29. Abbreviations

Acronym Description

CPU Central Processing Unit

DMA Direct Memory Access

FIFO First In, First Out

TTL Transistor-Transi sto r Lo g ic

UART Universal Asynchronous Receiver/Transmitter

Table 30. Revision history

Document ID Release date Data sheet status Change notice Supersedes

SC16C752B v. 6 20101130 Product data sheet - SC16C752B v.5

Modifications: •Table 2 “Pin descri ption”: signal names CTSB, DTRB, OPB and RXRDYB are corrected by adding

overbar to indicate they are active LOW signals (CTSB, DTRB, OPB and RXRDYB)

•Table 25 “Static characteristics”: Table note [1] corrected from “VIO(min) = 2 V and VIH(max) = 0.8 V”

to “VIH(min) = 2 V and VIL(max) =0.8V”

SC16C752B v. 5 20081002 Product data sheet - SC16C752B v.4

SC16C752B v. 4 20060714 Product data sheet - SC16C752B v.3

SC16C752B v. 3 20041214 Product data - SC16C752B v.2

SC16C752B v. 2 20040527 Product data - SC16C752B v.1

SC16C752B v. 1 20040326 Product data - -

Product data sheet Rev. 6 — 30 November 2010 45 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed be tween

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whethe r or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors product s are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reaso nably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semico nductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the applicatio n or use by custo mer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semicon ductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly object s to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 6 — 30 November 2010 46 of 47

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualifi ed,

the product is not suitable for automo tive use. It is neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automo tive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 30 November 2010

Document identifier: SC16C752B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Functional description . . . . . . . . . . . . . . . . . . . 7

6.1 Trigger levels . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.2 Hardware flow control. . . . . . . . . . . . . . . . . . . . 7

6.2.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.2.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.3 Software flow control . . . . . . . . . . . . . . . . . . . . 9

6.3.1 Receive flow control . . . . . . . . . . . . . . . . . . . . 10

6.3.2 Transmit flow control. . . . . . . . . . . . . . . . . . . . 10

6.3.3 Software flow control example . . . . . . . . . . . . 11

6.3.3.1 Assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.5.1 Interrupt mode operation . . . . . . . . . . . . . . . . 14

6.5.2 Polled mode operation . . . . . . . . . . . . . . . . . . 14

6.6 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 15

6.6.1 Single DMA transfers

(DMA mode 0/FIFO disable). . . . . . . . . . . . . . 15

6.6.1.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.6.1.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.6.2 Block DMA transfers (DMA mode 1). . . . . . . . 16

6.6.2.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.6.2.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.7 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.8 Break and time-out conditions . . . . . . . . . . . . 17

6.9 Programmable baud rate generator . . . . . . . . 17

7 Register descriptions . . . . . . . . . . . . . . . . . . . 19

7.1 Receiver Holding Register (RHR). . . . . . . . . . 21

7.2 Transmit Holding Register (THR) . . . . . . . . . . 21

7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 22

7.4 Line Control Register (LCR) . . . . . . . . . . . . . . 23

7.5 Line Status Register (LSR). . . . . . . . . . . . . . . 24

7.6 Modem Control Register (MCR). . . . . . . . . . . 25

7.7 Modem Status Register (MSR). . . . . . . . . . . . 26

7.8 Interrupt Enable Register (IER) . . . . . . . . . . . 27

7.9 Interrupt Identification Register (IIR). . . . . . . . 28

7.10 Enhanced Feature Register (EF R). . . . . . . . . 28

7.11 Divisor latches (DLL, DLM). . . . . . . . . . . . . . . 29

7.12 Transmission Control Register (TCR). . . . . . . 29

7.13 Trigger Level Register (TLR) . . . . . . . . . . . . . 30

7.14 FIFO ready register . . . . . . . . . . . . . . . . . . . . 30

8 Programmer’s guide . . . . . . . . . . . . . . . . . . . . 31

9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33

10 Static characteristics . . . . . . . . . . . . . . . . . . . 33

11 Dynamic characteristics. . . . . . . . . . . . . . . . . 34

11.1 Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 35

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40

13 Soldering of SMD packages. . . . . . . . . . . . . . 42

13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 42

13.2 Wave and reflow soldering. . . . . . . . . . . . . . . 42

13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 42

13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43

14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44

15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 44

16 Legal information . . . . . . . . . . . . . . . . . . . . . . 45

16.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 45

16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 45

16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46

17 Contact information . . . . . . . . . . . . . . . . . . . . 46

18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47