MC68HC705J1A/D
Rev. 2.0
MC68HC705J1A
MC68HRC705J1A
MC68HSC705J1A
MC68HSR705J1A
HCMOS Microcontroller Units
TECHNICAL DATA
C5H
Motorola, Inc., 1996
MC68HC705J1A — Rev. 2.0
MOTOROLA 3
List of Sections
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Central Processor Unit. . . . . . . . . . . . . . . . . . . . . 31
Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . 53
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . 63
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . 71
Computer Operating Properly Module. . . . . . . 81
External Interrupt Module. . . . . . . . . . . . . . . . . . 85
Multifunction Timer Module . . . . . . . . . . . . . . . . 93
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Appendix A MC68HRC705J1A. . . . . . . . . . . . . 119
Appendix B MC68HSC705J1A . . . . . . . . . . . . . 123
Appendix C MC68HSR705J1A . . . . . . . . . . . . . 129
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Literature Updates. . . . . . . . . . . . . . . . . . . . . . . 141
MC68HC705J1A — Rev. 2.0
4 MOTOROLA
List of Sections List of Modules
List of Modules
All M68HC05 microcontroller units (MCUs) are customer-specified
modular designs. To meet customer requirements, Motorola is
constantly designing new modules and new versions of existing
modules. The following table shows the version levels of the modules in
the MC68HC705J1A MCU.
Module Version
Central Processor Unit HC05CPU
Computer Operating Properly @COP0COPRT2
External Interrupt @KBIELPA4HPD_A
Multifunction Timer TIM15B1RTICLR_A
MC68HC705J1A — Rev. 2.0
MOTOROLA Table of Contents 5
Table of Contents
List of Sections List of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Introduction Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Package Types and Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . .12
Programmable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Pin Descriptions Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . .30
Central Processor
Unit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
CPU Control Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table of Contents
MC68HC705J1A — Rev. 2.0
6 Table of Contents MOTOROLA
Arithmetic/Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Resets and
Interrupts Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Low-Power Modes Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Parallel I/O Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Computer
Operating Properly
Module
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table of Contents
MC68HC705J1A — Rev. 2.0
MOTOROLA Table of Contents 7
External Interrupt
Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Multifunction
Timer Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
5.0 V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .105
3.3 V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .106
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . .111
Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table of Contents
MC68HC705J1A — Rev. 2.0
8 Table of Contents MOTOROLA
Appendix A
MC68HRC705J1A Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Typical Internal Operating Frequency for RC Oscillator Option . . . .120
Package Types and Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . .122
Appendix B
MC68HSC705J1A Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Package Types and Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . .128
Appendix C
MC68HSR705J1A Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
RC Oscillator Connections (External Resistor) . . . . . . . . . . . . . . . . .130
Typical Internal Operating Frequency at 25 °C for High-Speed
RC Oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
RC Oscillator Connections (No External Resistor) . . . . . . . . . . . . . .132
Typical Internal Operating Frequency Versus Temperature
(No External Resistor). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Package Types and Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . .134
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Literature Updates Literature Distribution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Mfax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Motorola SPS World Marketing World Wide Web Server . . . . . . . . .142
CSIC Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . .142
MC68HC705J1A — Rev. 2.0
MOTOROLA Introduction 9
Introduction
Introduction
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . .12
Programmable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
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Introduction
MC68HC705J1A — Rev. 2.0
10 Introduction MOTOROLA
Features
• Peripheral Modules
– 15-Stage Multifunction Timer
– Computer Operating Properly (COP) Watchdog
• 14 Bidirectional Input/Output (I/O) Lines, Including:
– 10 mA Sink Capability on Four I/O Pins
– Mask Option Register (MOR) and Software Programmable
Pulldowns on All I/O Pins
– MOR Selectable Interrupt on Four I/O Pins, a Keyboard Scan
Feature
• MOR Selectable Sensitivity on External Interrupt (Edge- and
Level-Sensitive or Edge-Sensitive Only)
• On-Chip Oscillator with Connections for:
– Crystal
– Ceramic Resonator
– Resistor-Capacitor (RC) Oscillator
– External Clock
• 1240 Bytes of EPROM/OTPROM, Including Eight Bytes for User
Vectors
• 64 Bytes of User RAM
• Memory-Mapped I/O Registers
• Fully Static Operation with No Minimum Clock Speed
• Power-Saving Stop, Halt, Wait, and Data-Retention Modes
• External Interrupt Mask Bit and Acknowledge Bit
• Illegal Address Reset
• Internal Steering Diode and Pullup Resistor from RESET Pin to
VDD
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Introduction
Structure
MC68HC705J1A — Rev. 2.0
MOTOROLA Introduction 11
Structure
Figure 1. Block Diagram
0000000011
WATCHDOG AND
ILLEGAL ADDRESS
DETECT
STATIC RAM (SRAM) – 64 BYTES
ALUCPU CONTROL
68HC05 CPU
ACCUMULATOR
INDEX REGISTER
STK PTR
PROGRAM COUNTER
CONDITION CODE
REGISTER
15-STAGE
MULTIFUNCTION
TIMER SYSTEM
DIVIDE
INTERNAL
OSCILLATOR
OSC1
OSC2
CPU REGISTERS
USER EPROM – 1240 BYTES
MASK OPTION REGISTER (EPROM)
*10-mA sink capability
**External interrupt capability
DATA DIRECTION REGISTER A DATA DIRECTION REGISTER B
PORT A PORT B
PB5
PB4
PB3
PB2
PB1
PB0
PA7*
PA6*
PA5*
PA4*
PA3**
PA2**
PA1**
PA0**
RESET
IRQ/VPP
111HINZC
BY 2
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Introduction
MC68HC705J1A — Rev. 2.0
12 Introduction MOTOROLA
Package Types and Order Numbers
Programmable Options
1. Refer to Appendix A,Appendix B, and Appendix C for ordering information on optional
high-speed and resistor-capacitor oscillator devices.
2. P = plastic dual in-line package (PDIP)
3. C = extended temperature range
4. V = automotive temperature range
5. DW = small outline integrated circuit (SOIC)
6. S = ceramic dual in-line package (Cerdip)
The options in Table 2 are programmable in the mask option register.
Table 1. Order Numbers(1)
Package
Type Case
Outline Pin
Count Operating
Temperature Order Number
PDIP 738-03 20 0 to 70 °C
–40 to +85 °C
–40 to + 105 °C
MC68HC705J1AP(2)
MC68HC705J1AC(3)P
MC68HC705J1AV(4)P
SOIC 751D-04 20 0 to 70 °C
–40 to +85 °C
–40 to + 105 °C
MC68HC705J1ADW(5)
MC68HC705J1ACDW
MC68HC705J1AVDW
Cerdip 732-03 20 0 to 70 °C
–40 to +85 °C
–40 to + 105 °C
MC68HC705J1AS(6)
MC68HC705J1ACS
MC68HC705J1AVS
Table 2. Programmable Options
Feature Option
COP Watchdog Timer Enabled or Disabled
External Interrupt Triggering Edge-Sensitiv e Only or Edge- and Le vel-Sensitive
Port A IRQ Pin Interrupts Enabled or Disabled
Port Pulldown Resistors Enabled or Disabled
STOP Instruction Mode Stop Mode or Halt Mode
Crystal Oscillator Internal Resistor Enab led or Disabled
EPROM Security Enabled or Disabled
Short Oscillator Delay Counter Enabled or Disabled
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MC68HC705J1A — Rev. 2.0
MOTOROLA Pin Descriptions 13
Pin Descriptions
Pin Descriptions
Contents
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .17
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
PB0–PB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
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Pin Descriptions
MC68HC705J1A — Rev. 2.0
14 Pin Descriptions MOTOROLA
Pin Assignments
Figure 1. Pin Assignments
OSC1 1
OSC2 2
PB5 3
PB4 4
PB3 5
PB2 6
PB1 7
PB0 8
RESET
20
IRQ/VPP
19
PA0
18
PA1
17
PA2
16
PA3
15
PA4
14
PA5
13
PA6
12
PA7
11
VSS 10
VDD 9
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Pin Descriptions
Pin Functions
MC68HC705J1A — Rev. 2.0
MOTOROLA Pin Descriptions 15
Pin Functions
VDD and VSS VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Very fast signal transitions occur on the MCU pins, placing high,
short-duration current demands on the power supply. To prevent noise
problems, take special care as Figure 2 shows, by placing the bypass
capacitors as close as possible to the MCU. C2 is an optional bulk
current bypass capacitor for use in applications that require the port pins
to source high current levels.
Figure 2. Bypassing Layout Recommendation
OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the on-chip oscillator.
The oscillator can be driven by any of the following:
1. Crystal (See Figure 3 and Figure 4.)
2. Ceramic resonator (See Figure 5 and Figure 6.)
3. Resistor/capacitor (RC) oscillator (Refer to Appendix A and
Appendix C.)
4. External clock signal as shown in (See Figure 7.)
The frequency, fosc, of the oscillator or external clock source is divided
by two to produce the internal operating frequency, fop.
C1
C2
MCU C1
0.1 µFC2
V+
+
VDD
VSS
VDD
VSS
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Pin Descriptions
MC68HC705J1A — Rev. 2.0
16 Pin Descriptions MOTOROLA
Crystal Oscillator Figure 3 and Figure 4 show a typical crystal oscillator circuit for an
AT-cut, parallel resonant crystal. Follow the crystal supplier’s
recommendations, as the crystal parameters determine the external
component values required to provide reliable startup and maximum
stability. The load capacitance values used in the oscillator circuit design
should include all stray layout capacitances.
To minimize output distortion, mount the crystal and capacitors as close
as possible to the pins. An internal startup resistor of approximately
2MΩ is provided between OSC1 and OSC2 for the crystal oscillator as
a programmable mask option.
NOTE:
Use an AT-cut crystal and not an AT-strip crystal because the MCU can
overdrive an AT-strip crystal.
Figure 3. Crystal Connections with
Oscillator Internal Resistor Mask Option
MCU
C1C2
XTAL
C4
C3
XTAL
C3
27 pF C4
27 pF
OSC1
OSC2
OSC1
OSC2
V
SS
VDD
VSS
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Pin Descriptions
Pin Functions
MC68HC705J1A — Rev. 2.0
MOTOROLA Pin Descriptions 17
Figure 4. Crystal Connections without
Oscillator Internal Resistor Mask Option
Ceramic
Resonator
Oscillator
To reduce cost, use a ceramic resonator instead of the crystal. The
circuits shown inFigure 5 andFigure 6 show ceramic resonator circuits.
Follow the resonator manufacturer’s recommendations, as the resonator
parameters determine the external component values required for
maximum stability and reliable starting. The load capacitance values
used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for
startup stabilization and to minimize output distortion. An internal startup
resistor of approximately 2 MΩ is provided between OSC1 and OSC2 as
a programmable mask option.
MCU
C1C2
R
XTAL
C4
C3
R
10 MΩ
XTAL
C3
27 pF C4
27 pF
OSC1
OSC2
VDD
VSS
OSC1
OSC2
V
SS
5-j_pin_a
Pin Descriptions
MC68HC705J1A — Rev. 2.0
18 Pin Descriptions MOTOROLA
Figure 5. Ceramic Resonator Connections with
Oscillator Internal Resistor Mask Option
Figure 6. Ceramic Resonator Connections without
Oscillator Internal Resistor Mask Option
MCU
C1C2
CERAMIC
C4
C3
CERAMIC
C3
27 pF C4
27 pF
RESONATOR
RESONATOR
OSC1
OSC2
OSC1
OSC2
VDD
VSS
V
SS
MCU
C1C2
R
CERAMIC
C4
C3
R
10 MΩ
CERAMIC
C3
27 pF C4
27 pF
RESONATOR
RESONATOR
VSS
VDD
VSS
OSC1
OSC2
OSC1
OSC2
6-j_pin_a
Pin Descriptions
Pin Functions
MC68HC705J1A — Rev. 2.0
MOTOROLA Pin Descriptions 19
RC Oscillator Refer to Appendix A and Appendix C.
External Clock An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in Figure 7. This configuration is possible regardless of whether
the crystal/ceramic resonator or the RC oscillator is enabled.
Figure 7. External Clock Connections
RESET Applying a logic 0 to the RESET pin forces the MCU to a known startup
state. An internal reset also pulls theRESET pin low. An internal resistor
to VDD pulls the RESET pin high. A steering diode between the RESET
and VDD pins discharges any RESET pin voltage when power is
removed from the MCU. The RESET pin contains an internal Schmitt
trigger to improve its noise immunity as an input. Refer to the Resets
and Interrupts section for more information.
MCU
EXTERNAL
CMOS CLOCK
OSC1
OSC2
7-j_pin_a
Pin Descriptions
MC68HC705J1A — Rev. 2.0
20 Pin Descriptions MOTOROLA
IRQ/VPP The external interrupt/programming voltage pin (IRQ/VPP) drives the
asynchronous IRQ interrupt function of the CPU. Additionally, it is used
to program the user EPROM and mask option register. (See Memory
and External Interrupt Module.)
The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If level-sensitive triggering is selected, the IRQ/VPP input requires an
external resistor to VDD for wired-OR operation. If the IRQ/VPP pin is not
used, it must be tied to the VDD supply.
The IRQ/VPP pin contains an internal Schmitt trigger as part of its input
to improve noise immunity. The voltage on this pin should not exceed
VDD except when the pin is being used for programming the EPROM.
NOTE:
The mask option register can enable the PA0
–
PA3 pins to function as
external interrupt pins.
PA0–PA7 These eight input/output (I/O) lines comprise port A, a general-purpose
bidirectional I/O port. (SeeExternal Interrupt Module for information on
PA0–PA3 external interrupts.)
PB0–PB5 These six I/O lines comprise port B, a general-purpose bidirectional I/O
port.
8-j_pin_a
MC68HC705J1A — Rev. 2.0
MOTOROLA Memory 21
1-e_mem_a
Memory
Memory
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . .25
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . .26
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . .30
Features
• 1232 Bytes of User EPROM, Plus Eight Bytes for User Vectors
• 64 Bytes of User RAM
Memory
MC68HC705J1A — Rev. 2.0
22 Memory MOTOROLA
Memory Map
Port A Data Register (PORTA) $0000
Port B Data Register (PORTB) $0001
Unimplemented $0002
$0003
Data Direction Register A (DDRA) $0004
Data Direction Register B (DDRB) $0005
Unimplemented $0006
$0007
Timer Status and Control Register (TSCR) $0008
Timer Control Register (TCR) $0009
$0000 I/O Registers
32 Bytes
IRQ Status and Control Register (ISCR) $000A
↓Unimplemented $000B
$001F ↓
$0020 Unimplemented
160 Bytes
$000F
↓Pulldown Register Port A (PDRA) $0010
$00BF Pulldown Register Port B (PDRB) $0011
$00C0 RAM
64 Bytes Unimplemented $0012
↓ ↓
$00FF $0017
$0100 Unimplemented
512 Bytes
EPROM Programming Register (EPROG) $0018
↓Unimplemented $0019
$02FF ↓
$0300 EPROM
1232 Bytes
$001E
↓Reserved $001F
$07CF
$07D0 Unimplemented
30 Bytes
COP Register (COPR)(1) $07F0
↓Mask Option Register (MOR) $07F1
$07ED Reserved $07F2
$07EE Test ROM
2 Bytes ↓
$07EF $07F7
$07F0 Registers and EPROM
16 Bytes
Timer Interrupt Vector High $07F8
↓Timer Interrupt Vector Low $07F9
$07FF External Interrupt Vector High $07FA
External Interrupt Vector Low $07FB
Software Interrupt Vector High $07FC
Software Interrupt Vector Low $07FD
Reset Vector High $07FE
Reset Vector Low $07FF
(1)Writing to bit 0 of $07F0 clears the COP watchdog.
Figure 1. Memory Map
2-e_mem_a
Memory
Input/Output Register Summary
MC68HC705J1A — Rev. 2.0
MOTOROLA Memory 23
3-e_mem_a
Input/Output Register Summary
Addr. Register Name Bit 7 654321Bit 0
$0000 Port A Data Register
(PORTA)
Read: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Unaffected by Reset
$0001 Port B Data Register
(PORTB)
Read: 0 0 PB5 PB4 PB3 PB2 PB1 PB0
Write:
Reset: Unaffected by Reset
$0002 Unimplemented
$0003 Unimplemented
$0004 Data Direction Register A
(DDRA)
Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 00000000
$0005 Data Direction Register B
(DDRB)
Read: 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset: 00000000
$0006 Unimplemented
$0007 Unimplemented
$0008 Timer Status and Control
Register (TSCR)
Read: TOF RTIF TOIE RTIE 00
RT1 RT0
Write: TOFR RTIFR
Reset: 00000011
$0009 Timer Counter Register
(TCR)
Read: Bit 7 654321Bit 0
Write:
Reset: 00000000
$000A IRQ Status and Control
Register (ISCR)
Read: IRQE 0 0 0 IRQF 0 0 0
Write: R IRQR
Reset: 10000000
$000B Unimplemented
↓
$000F Unimplemented
$0010 Pulldown Register Port A
(PDRA)
Read:
Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0
Reset: 00000000
= Unimplemented R = Reserved U = Unaffected
Figure 2. I/O Register Summary
Memory
MC68HC705J1A — Rev. 2.0
24 Memory MOTOROLA
RAM
The 64 addresses from $00C0 to $00FF serve as both the user RAM
and the stack RAM. Before processing an interrupt, the CPU uses five
bytes of the stack to save the contents of the CPU registers. During a
subroutine call, the CPU uses two bytes of the stack to store the return
address. The stack pointer decrements when the CPU stores a byte on
the stack and increments when the CPU retrieves a byte from the stack.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
$0011 Pulldown Register Port B
(PDRB)
Read:
Write: PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0
Reset: 00000000
$0012 Unimplemented
↓
$0017 Unimplemented
$0018 EPROM Progr amming
Register (EPROG)
Read: 00000
ELAT MPGM EPGM
Write: RRRR
Reset: 00000000
$0019 Unimplemented
↓
$001E Unimplemented
$001F Reserved RRRRRRRR
$07F0 COP Register (COPR) Read:
Write: COPC
Reset: UUUUUUU0
$07F1 Mask Option Register
(MOR)
Read: SOSCD EPMSEC OSCRES SWAIT PDI PIRQ LEVEL COPEN
Write:
Reset: 00000000
Addr. Register Name Bit 7 654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2. I/O Register Summary
4-e_mem_a
Memory
EPROM/OTPROM
MC68HC705J1A — Rev. 2.0
MOTOROLA Memory 25
EPROM/OTPROM
An MCU with a quartz window has 1240 bytes of erasable,
programmable ROM (EPROM). The quartz window allows EPROM
erasure with ultraviolet light.
NOTE:
Keep the quartz window covered with an opaque material except when
programming the MCU. Ambient light can affect MCU operation.
In an MCU without the quartz window, the EPROM cannot be erased
and serves as 1240 bytes of one-time programmable ROM (OTPROM).
The following addresses are user EPROM/OTPROM locations:
• $0300–$07CF
• $07F8–$07FF, used for user-defined interrupt and reset vectors
The COP register (COPR) is an EPROM/OTPROM location at address
$07F0.
The mask option register (MOR) is an EPROM/OTPROM location at
address $07F1.
EPROM/OTPROM
Programming The two ways to program the EPROM/OTPROM are:
• Manipulating the control bits in the EPROM programming register
to program the EPROM/OTPROM on a byte-by-byte basis
• Programming the EPROM/OTPROM with the M68HC705J
In-Circuit Simulator (M68HC705JICS) available from Motorola
5-e_mem_a
Memory
MC68HC705J1A — Rev. 2.0
26 Memory MOTOROLA
EPROM
Programming
Register
The EPROM programming register (EPROG) contains the control bits
for programming the EPROM/OTPROM.
ELAT — EPROM Bus Latch Bit
This read/write bit latches the address and data buses for
EPROM/OTPROM programming. Clearing the ELAT bit automatically
clears the EPGM bit. EPROM/OTPROM data cannot be read while
the ELAT bit is set. Reset clears the ELAT bit.
1 = Address and data buses configured for EPROM/OTPROM
programming the EPROM
0 = Address and data buses configured for normal operation
MPGM — MOR Programming Bit
This read/write bit applies programming power from the IRQ/VPP pin
to the mask option register. Reset clears MPGM.
1 = Programming voltage applied to MOR
0 = Programming voltage not applied to MOR
EPGM — EPROM Programming Bit
This read/write bit applies the voltage from the IRQ/VPP pin to the
EPROM. To write the EPGM bit, the ELAT bit must be set already.
Reset clears EPGM.
1 = Programming voltage (IRQ/VPP pin) applied to EPROM
0 = Programming voltage (IRQ/VPP pin) not applied to EPROM
NOTE:
Writing logic 1s to both the ELAT and EPGM bits with a single instruction
sets ELAT and clears EPGM. ELAT must be set first by a separate
instruction.
Address: $0018
Bit 7 654321Bit 0
Read: 00000
ELAT MPGM EPGM
Write: RRRR
Reset: 00000000
= Unimplemented R = Reserved
Figure 3. EPROM Programming Register (EPROG)
6-e_mem_a
Memory
Mask Option Register
MC68HC705J1A — Rev. 2.0
MOTOROLA Memory 27
Bits [7:3] — Reserved
Take the following steps to program a byte of EPROM/OTPROM:
1. Apply the programming voltage, VPP, to the IRQ/VPP pin.
2. Set the ELAT bit.
3. Write to any EPROM/OTPROM address.
4. Set the EPGM bit and wait for a time, tEPGM.
5. Clear the ELAT bit.
EPROM Erasing The erased state of an EPROM bit is logic 0. Erase the EPROM by
exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537
angstroms. Position the ultraviolet light source one inch from the
EPROM. Do not use a shortwave filter.
Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that
controls the following options:
• COP watchdog (enable or disable)
• External interrupt pin triggering (edge-sensitive only or edge- and
level-sensitive)
• Port A external interrupts (enable or disable)
• Port pulldown resistors (enable or disable)
• STOP instruction (stop mode or halt mode)
• Crystal oscillator internal resistor (enable or disable)
• EPROM security (enable or disable)
• Short oscillator delay (enable or disable)
7-e_mem_a
Memory
MC68HC705J1A — Rev. 2.0
28 Memory MOTOROLA
Take the following steps to program the mask option register:
1. Apply the programming voltage, VPP, to the IRQ/VPP pin.
2. Write to the MOR.
3. Set the MPGM bit and wait for a time, tMPGM.
4. Clear the MPGM bit.
5. Reset the MCU.
SOSCD — Short Oscillator Delay Bit
The SOSCD bit controls the oscillator stabilization counter. The
normal stabilization delay following reset or exit from stop mode is
4064 tcyc. Setting SOSCD enables a short oscillator stabilization
delay.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
EPMSEC — EPROM Security Bit
The EPMSEC bit controls access to the EPROM/OTPROM.
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
Address: $07F1
Bit 7 654321Bit 0
Read: SOSCD EPMSEC OSCRES SWAIT SWPDI PIRQ LEVEL COPEN
Write:
Reset: 00000000
Figure 4. Mask Option Register (MOR)
8-e_mem_a
Memory
Mask Option Register
MC68HC705J1A — Rev. 2.0
MOTOROLA Memory 29
OSCRES — Oscillator Internal Resistor Bit
The OSCRES bit enables a 2-MΩ internal resistor in the oscillator
circuit.
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
NOTE:
Program the OSCRES bit to logic 0 in devices using RC oscillators.
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the
CPU interprets the STOP instruction as a WAIT instruction, and the
MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 tcyc occurs after
exiting halt mode.
1 = Halt mode enabled
0 = Halt mode not enabled
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown
devices. The SWPDI bit overrides the pulldown inhibit bits in the port
pulldown inhibit registers.
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
PIRQ — Port A External Interrupt Bit
The PIRQ bit enables the PA0–PA3 pins to function as external
interrupt pins.
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
LEVEL —External Interrupt Sensitivity Bit
The LEVEL bit controls external interrupt triggering sensitivity.
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
COPEN — COP Enable Bit
The COPEN bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
9-e_mem_a
Memory
MC68HC705J1A — Rev. 2.0
30 Memory MOTOROLA
EPROM Programming Characteristics
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +105 °C
Table 1. EPROM Programming Characteristics(1)
Characteristic Symbol Min Typ Max Unit
Programming Voltage
IRQ/VPP VPP 16.0 16.5 17.0 V
Programming Current
IRQ/VPP IPP — 3.0 10.0 mA
Programming Time
Per Array Byte
MOR tEPGM
tMPGM 4
4—
——
—ms
ms
10-e_mem_a
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 31
Central Processor Unit
CPU
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Arithmetic/Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .41
Read-Modify- Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . .42
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
1-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
32 CPU MOTOROLA
Features
• 2.1-MHz Bus Frequency
• 8-Bit Accumulator
• 8-Bit Index Register
• 11-Bit Program Counter
• 6-Bit Stack Pointer
• Condition Code Register with Five Status Flags
• 62 Instructions
• 8 Addressing Modes
• Power-Saving Stop, Wait, Halt, and Data-Retention Modes
Introduction
The central processor unit (CPU) consists of a CPU control unit, an
arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit
fetches and decodes instructions. The ALU executes the instructions.
The CPU registers contain data, addresses, and status bits that reflect
the results of CPU operations.
2-hc05cpu
CPU
Introduction
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 33
Figure 1. Programming Model
ACCUMULATOR (A)
INDEX REGISTER (X)
CONDITION CODE REGISTER (CCR)
PROGRAM COUNTER (PC)
STACK POINTER (SP)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
04756 321
0
ARITHMETIC/LOGIC UNIT
CPU CONTROL UNIT
04756 321
04756 32181215 1314 11 10 9
000000011
000
04756 32181215 1314 11 10 9
111HINZC
04756 321
00
3-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
34 CPU MOTOROLA
CPU Control Unit
The CPU control unit fetches and decodes instructions during program
operation. The control unit selects the memory locations to read and
write and coordinates the timing of all CPU operations.
Arithmetic/Logic Unit
The arithmetic/logic unit (ALU) performs the arithmetic, logic, and
manipulation operations decoded from the instruction set by the CPU
control unit. The ALU produces the results called for by the program and
sets or clears status and control bits in the condition code register
(CCR).
CPU Registers
The M68HC05 CPU contains five registers that control and monitor MCU
operation:
• Accumulator
• Index register
• Stack pointer
• Program counter
• Condition code register
CPU registers are not memory mapped.
4-hc05cpu
CPU
CPU Registers
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 35
Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and results of ALU operations.
Index Register In the indexed addressing modes, the CPU uses the byte in the index
register to determine the conditional address of the operand. The index
register also can serve as a temporary storage location or a counter.
Stack Pointer The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset or after the reset stack pointer
instruction (RSP), the stack pointer is preset to $00FF. The address in
the stack pointer decrements after a byte is stacked and increments
before a byte is unstacked.
Bit 7 654321Bit 0
Read:
Write:
Reset: Unaffected by Reset
Figure 2. Accumulator (A)
Bit 7 654321Bit 0
Read:
Write:
Reset: Unaffected by Reset
Figure 3. Index Register (X)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit
0
Read: 0 0 0 0 0 0 0 0 1 1
Write:
Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
= Unimplemented
Figure 4. Stack Pointer (SP)
5-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
36 CPU MOTOROLA
The 10 most significant bits of the stack pointer are permanently fixed at
0000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations;
an interrupt uses five locations.
Program Counter The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched. The five most significant bits
of the program counter are ignored and appear as 00000.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Condition Code
Register The condition code register is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed.
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit
0
Reset: 0 0 0 0 0 Loaded with vector from $07FE and $07FF
Figure 5. Program Counter (PC)
Bit 7 654321Bit 0
Read: 1 1 1 HINZC
Write:
Reset: 1 1 1U1UUU
= Unimplemented U = Unaffected
Figure 6. Condition Code Register (CCR)
6-hc05cpu
CPU
CPU Registers
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 37
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The
half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations.
I — Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic 0, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is logic 1, the interrupt request is latched. Normally, the CPU
processes the latched interrupt request as soon as the interrupt mask
is cleared again.
A return from interrupt instruction (RTI) unstacks the CPU registers,
restoring the interrupt mask to its cleared state. After any reset, the
interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an ALU operation produces a
negative result.
Z — Zero Flag
The CPU sets the zero flag when an ALU operation produces a result
of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
7-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
38 CPU MOTOROLA
Instruction Set
The MCU instruction set has 62 instructions and uses eight addressing
modes.
Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
Inherent Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
Immediate Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
Direct Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
8-hc05cpu
CPU
Instruction Set
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 39
Extended Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
Indexed,
No Offset Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or input/output
(I/O) location.
Indexed,
8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
9-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
40 CPU MOTOROLA
Indexed,
16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
Relative Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset because the assembler determines the proper offset
and verifies that it is within the span of the branch.
10-hc05cpu
CPU
Instruction Set
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 41
Instruction Types The MCU instructions fall into the following five categories:
• Register/memory instructions
• Read-modify-write instructions
• Jump/branch instructions
• Bit manipulation instructions
• Control instructions
Register/Memory
Instructions These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 1. Register/Memory Instructions
Instruction Mnemonic
Add Memory Byte and Carry Bit to Accumulator ADC
Add Memory Byte to Accumulator ADD
AND Memory Byte with Accumulator AND
Bit Test Accumulator BIT
Compare Accumulator CMP
Compare Index Register with Memory Byte CPX
EXCLUSIVE OR Accumulator with Memory Byte EOR
Load Accumulator with Memory Byte LDA
Load Index Register with Memory Byte LDX
Multiply MUL
OR Accumulator with Memory Byte ORA
Subtract Memory Byte and Carry Bit from Accumulator SBC
Store Accumulator in Memory STA
Store Index Register in Memory STX
Subtract Memory Byte from Accumulator SUB
11-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
42 CPU MOTOROLA
Read-Modify-
Write Instructions These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE:
Do not use read-modify-write instructions on registers with write-only
bits.
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
Table 2. Read-Modify-Write Instructions
Instruction Mnemonic
Arithmetic Shift Left (Same as LSL) ASL
Arithmetic Shift Right ASR
Bit Clear BCLR(1)
Bit Set BSET(1)
Clear Register CLR
Complement (One’s Complement) COM
Decrement DEC
Increment INC
Logical Shift Left (Same as ASL) LSL
Logical Shift Right LSR
Negate (Two’s Complement) NEG
Rotate Left through Carry Bit ROL
Rotate Right through Carry Bit ROR
Test for Negative or Zero TST(2)
12-hc05cpu
CPU
Instruction Set
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 43
Jump/Branch
Instructions Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
NOTE:
Do not use BRCLR or BRSET instructions on registers with write-only
bits.
13-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
44 CPU MOTOROLA
Table 3. Jump and Branch Instructions
Instruction Mnemonic
Branch if Carry Bit Clear BCC
Branch if Carry Bit Set BCS
Branch if Equal BEQ
Branch if Half-Carry Bit Clear BHCC
Branch if Half-Carry Bit Set BHCS
Branch if Higher BHI
Branch if Higher or Same BHS
Branch if IRQ Pin High BIH
Branch if IRQ Pin Low BIL
Branch if Lower BLO
Branch if Lower or Same BLS
Branch if Interrupt Mask Clear BMC
Branch if Minus BMI
Branch if Interrupt Mask Set BMS
Branch if Not Equal BNE
Branch if Plus BPL
Branch Always BRA
Branch if Bit Clear BRCLR
Branch Never BRN
Branch if Bit Set BRSET
Branch to Subroutine BSR
Unconditional Jump JMP
Jump to Subroutine JSR
14-hc05cpu
CPU
Instruction Set
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 45
Bit Manipulation
Instructions The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
NOTE:
Do not use bit manipulation instructions on registers with write-only bits.
Control
Instructions These instructions act on CPU registers and control CPU operation
during program execution.
Table 4. Bit Manipulation Instructions
Instruction Mnemonic
Bit Clear BCLR
Branch if Bit Clear BRCLR
Branch if Bit Set BRSET
Bit Set BSET
Table 5. Control Instructions
Instruction Mnemonic
Clear Carry Bit CLC
Clear Interrupt Mask CLI
No Operation NOP
Reset Stack Pointer RSP
Return from Interrupt RTI
Return from Subroutine RTS
Set Carry Bit SEC
Set Interrupt Mask SEI
Stop Oscillator and Enable IRQ Pin STOP
Software Interrupt SWI
Transfer Accumulator to Index Register TAX
Transfer Index Register to Accumulator TXA
Stop CPU Clock and Enable Interrupts WAIT
15-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
46 CPU MOTOROLA
Instruction Set
Summary
Table 6. Instruction Set Summary
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
ADC #
opr
ADC
opr
ADC
opr
ADC
opr
,X
ADC
opr
,X
ADC ,X
Add with Carry A ← (A) + (M) + (C) ↕— ↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ADD #
opr
ADD
opr
ADD
opr
ADD
opr
,X
ADD
opr
,X
ADD ,X
Add without Carry A ← (A) + (M) ↕— ↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
AND #
opr
AND
opr
AND
opr
AND
opr
,X
AND
opr
,X
AND ,X
Logical AND A ← (A) ∧ (M) — — ↕↕—
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ASL
opr
ASLA
ASLX
ASL
opr
,X
ASL ,X
Arithmetic Shift Left (Same as LSL) — — ↕↕↕
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
3
6
5
ASR
opr
ASRA
ASRX
ASR
opr
,X
ASR ,X
Arithmetic Shift Right — — ↕↕↕
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
ff
5
3
3
6
5
BCC
rel
Branch if Carry Bit Clear PC ← (PC) + 2 +
rel
? C = 0 ————— REL 24 rr 3
BCLR
n opr
Clear Bit n Mn ← 0 —————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BCS
rel
Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 +
rel
? C = 1 ————— REL 25 rr 3
BEQ
rel
Branch if Equal PC ← (PC) + 2 +
rel
? Z = 1 ————— REL 27 rr 3
BHCC
rel
Branch if Half-Carry Bit Clear PC ← (PC) + 2 +
rel
? H = 0 ————— REL 28 rr 3
BHCS
rel
Branch if Half-Carry Bit Set PC ← (PC) + 2 +
rel
? H = 1 ————— REL 29 rr 3
Cb0
b7 0
b0
b7 C
16-hc05cpu
CPU
Instruction Set
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 47
BHI
rel
Branch if Higher PC ← (PC) + 2 +
rel
? C ∨ Z = 0 ————— REL 22 rr 3
BHS
rel
Branch if Higher or Same PC ← (PC) + 2 +
rel
? C = 0 ————— REL 24 rr 3
BIH
rel
Branch if IRQ Pin High PC ← (PC) + 2 +
rel
? IRQ = 1 ————— REL 2F rr 3
BIL
rel
Branch if IRQ Pin Low PC ← (PC) + 2 +
rel
? IRQ = 0 ————— REL 2E rr 3
BIT #
opr
BIT
opr
BIT
opr
BIT
opr
,X
BIT
opr
,X
BIT ,X
Bit Test Accumulator with Memory Byte (A) ∧ (M) — — ↕↕—
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
BLO
rel
Branch if Lower (Same as BCS) PC ← (PC) + 2 +
rel
? C = 1 ————— REL 25 rr 3
BLS
rel
Branch if Lower or Same PC ← (PC) + 2 +
rel
? C ∨ Z = 1 ————— REL 23 rr 3
BMC
rel
Branch if Interrupt Mask Clear PC ← (PC) + 2 +
rel
? I = 0 ————— REL 2C rr 3
BMI
rel
Branch if Minus PC ← (PC) + 2 +
rel
? N = 1 ————— REL 2B rr 3
BMS
rel
Branch if Interrupt Mask Set PC ← (PC) + 2 +
rel
? I = 1 ————— REL 2D rr 3
BNE
rel
Branch if Not Equal PC ← (PC) + 2 +
rel
? Z = 0 ————— REL 26 rr 3
BPL
rel
Branch if Plus PC ← (PC) + 2 +
rel
? N = 0 ————— REL 2A rr 3
BRA
rel
Branch Always PC ← (PC) + 2 +
rel
? 1 = 1 ————— REL 20 rr 3
BRCLR
n opr rel
Branch if Bit n Clear PC ← (PC) + 2 +
rel
? Mn = 0 ———— ↕
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN
rel
Branch Never PC ← (PC) + 2 +
rel
? 1 = 0 ————— REL 21 rr 3
BRSET
n opr rel
Branch if Bit n Set PC ← (PC) + 2 +
rel
? Mn = 1 ———— ↕
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET
n opr
Set Bit n Mn ← 1 —————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Table 6. Instruction Set Summary (Continued)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
17-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
48 CPU MOTOROLA
BSR
rel
Branch to Subroutine
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) +
rel
————— REL AD rr 6
CLC Clear Carry Bit C ← 0 ————0 INH 98 2
CLI Clear Interrupt Mask I ← 0 — 0 — — — INH 9A 2
CLR
opr
CLRA
CLRX
CLR
opr
,X
CLR ,X
Clear Byte
M← $00
A← $00
X← $00
M← $00
M← $00
—— 0 1 —
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
ff
5
3
3
6
5
CMP #
opr
CMP
opr
CMP
opr
CMP
opr
,X
CMP
opr
,X
CMP ,X
Compare Accumulator with Memory Byte (A) – (M) — — ↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
COM
opr
COMA
COMX
COM
opr
,X
COM ,X
Complement Byte (One’s Complement)
M← (M) = $FF – (M)
A← (A) = $FF – (A)
X← (X) = $FF – (X)
M← (M) = $FF – (M)
M← (M) = $FF – (M)
—— ↕↕1
DIR
INH
INH
IX1
IX
33
43
53
63
73
dd
ff
5
3
3
6
5
CPX #
opr
CPX
opr
CPX
opr
CPX
opr
,X
CPX
opr
,X
CPX ,X
Compare Index Register with Memory Byte (X) – (M) — — ↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
DEC
opr
DECA
DECX
DEC
opr
,X
DEC ,X
Decrement Byte
M← (M) – 1
A← (A) – 1
X← (X) – 1
M← (M) – 1
M← (M) – 1
—— ↕↕—
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
dd
ff
5
3
3
6
5
EOR #
opr
EOR
opr
EOR
opr
EOR
opr
,X
EOR
opr
,X
EOR ,X
EXCLUSIVE OR Accumulator with Memory Byte A ← (A) ⊕ (M) — — ↕↕—
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
INC
opr
INCA
INCX
INC
opr
,X
INC ,X
Increment Byte
M← (M) + 1
A← (A) + 1
X← (X) + 1
M← (M) + 1
M← (M) + 1
—— ↕↕—
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
ff
5
3
3
6
5
Table 6. Instruction Set Summary (Continued)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
18-hc05cpu
CPU
Instruction Set
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 49
JMP
opr
JMP
opr
JMP
opr
,X
JMP
opr
,X
JMP ,X
Unconditional Jump PC ← Jump Address —————
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
JSR
opr
JSR
opr
JSR
opr
,X
JSR
opr
,X
JSR ,X
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
—————
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
5
6
7
6
5
LDA #
opr
LDA
opr
LDA
opr
LDA
opr
,X
LDA
opr
,X
LDA ,X
Load Accumulator with Memory Byte A ← (M) — — ↕↕—
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LDX #
opr
LDX
opr
LDX
opr
LDX
opr
,X
LDX
opr
,X
LDX ,X
Load Index Register with Memory Byte X ← (M) — — ↕↕—
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LSL
opr
LSLA
LSLX
LSL
opr
,X
LSL ,X
Logical Shift Left (Same as ASL) — — ↕↕↕
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
3
6
5
LSR
opr
LSRA
LSRX
LSR
opr
,X
LSR ,X
Logical Shift Right — — 0 ↕↕
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
ff
5
3
3
6
5
MUL Unsigned Multiply X : A ← (X) × (A) 0 — — — 0 INH 42 11
NEG
opr
NEGA
NEGX
NEG
opr
,X
NEG ,X
Negate Byte (Two’s Complement)
M← –(M) = $00 – (M)
A← –(A) = $00 – (A)
X← –(X) = $00 – (X)
M← –(M) = $00 – (M)
M← –(M) = $00 – (M)
—— ↕↕↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
dd
ff
5
3
3
6
5
NOP No Operation ————— INH 9D 2
ORA #
opr
ORA
opr
ORA
opr
ORA
opr
,X
ORA
opr
,X
ORA ,X
Logical OR Accumulator with Memory A ← (A) ∨ (M) — — ↕↕—
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Table 6. Instruction Set Summary (Continued)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
Cb0
b7 0
b0
b7 C0
19-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
50 CPU MOTOROLA
ROL
opr
ROLA
ROLX
ROL
opr
,X
ROL ,X
Rotate Byte Left through Carry Bit — — ↕↕↕
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
ff
5
3
3
6
5
ROR
opr
RORA
RORX
ROR
opr
,X
ROR ,X
Rotate Byte Right through Carry Bit — — ↕↕↕
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
ff
5
3
3
6
5
RSP Reset Stack Pointer SP ← $00FF ————— INH 9C 2
RTI Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕↕↕↕↕INH 80 9
RTS Return from Subroutine SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL) ————— INH 81 6
SBC #
opr
SBC
opr
SBC
opr
SBC
opr
,X
SBC
opr
,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator A← (A) – (M) – (C) — — ↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
SEC Set Carry Bit C ← 1 ————1 INH 99 2
SEI Set Interrupt Mask I ← 1 — 1 — — — INH 9B 2
STA
opr
STA
opr
STA
opr
,X
STA
opr
,X
STA ,X
Store Accumulator in Memory M ← (A) — — ↕↕—
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
dd
hh ll
ee ff
ff
4
5
6
5
4
STOP Stop Oscillator and Enable IRQ Pin — 0 — — — INH 8E 2
STX
opr
STX
opr
STX
opr
,X
STX
opr
,X
STX ,X
Store Index Register In Memory M ← (X) — — ↕↕—
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
dd
hh ll
ee ff
ff
4
5
6
5
4
SUB #
opr
SUB
opr
SUB
opr
SUB
opr
,X
SUB
opr
,X
SUB ,X
Subtract Memory Byte from Accumulator A ← (A) – (M) — — ↕↕↕
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Table 6. Instruction Set Summary (Continued)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
Cb0
b7
b0
b7 C
20-hc05cpu
CPU
Instruction Set
MC68HC705J1A — Rev. 2.0
MOTOROLA CPU 51
SWI Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
— 1 — — — INH 83 10
TAX Transfer Accumulator to Index Register X ← (A) ————— INH 97 2
TST
opr
TSTA
TSTX
TST
opr
,X
TST ,X
Test Memory Byte for Negative or Zero (M) – $00 — — ↕↕—
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
3
5
4
TXA Transfer Index Register to Accumulator A ← (X) ————— INH 9F 2
WAIT Stop CPU Clock and Enable Interrupts — 0 — — — INH 8F 2
A Accumulator
opr
Operand (one or two bytes)
C Carry/borrow flag PC Program counter
CCR Condition code register PCH Program counter high byte
dd Direct address of operand PCL Program counter low byte
dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode
DIR Direct addressing mode
rel
Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte
EXT Extended addressing mode SP Stack pointer
ff Offset byte in indexed, 8-bit offset addressing X Index register
H Half-carry flag Z Zero flag
hh ll High and low bytes of operand address in extended addressing # Immediate value
I Interrupt mask ∧Logical AND
ii Immediate operand byte ∨Logical OR
IMM Immediate addressing mode ⊕Logical EXCLUSIVE OR
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX1 Indexed, 8-bit offset addressing mode ←Loaded with
IX2 Indexed, 16-bit offset addressing mode ? If
M Memory location : Concatenated with
N Negative flag ↕Set or cleared
n
Any bit — Not affected
Table 6. Instruction Set Summary (Continued)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
21-hc05cpu
CPU
MC68HC705J1A — Rev. 2.0
52 CPU MOTOROLA
Table 7. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX
0123456789ABCDEF
05
BRSET0
3 DIR
5
BSET0
2 DIR
3
BRA
2 REL
5
NEG
2 DIR
3
NEGA
1 INH
3
NEGX
1 INH
6
NEG
2 IX1
5
NEG
1IX
9
RTI
1 INH
2
SUB
2 IMM
3
SUB
2 DIR
4
SUB
3 EXT
5
SUB
3 IX2
4
SUB
2 IX1
3
SUB
1IX
0
15
BRCLR0
3 DIR
5
BCLR0
2 DIR
3
BRN
2 REL
6
RTS
1 INH
2
CMP
2 IMM
3
CMP
2 DIR
4
CMP
3 EXT
5
CMP
3 IX2
4
CMP
2 IX1
3
CMP
1IX
1
25
BRSET1
3 DIR
5
BSET1
2 DIR
3
BHI
2 REL
11
MUL
1 INH
2
SBC
2 IMM
3
SBC
2 DIR
4
SBC
3 EXT
5
SBC
3 IX2
4
SBC
2 IX1
3
SBC
1IX
2
35
BRCLR1
3 DIR
5
BCLR1
2 DIR
3
BLS
2 REL
5
COM
2 DIR
3
COMA
1 INH
3
COMX
1 INH
6
COM
2 IX1
5
COM
1IX
10
SWI
1 INH
2
CPX
2 IMM
3
CPX
2 DIR
4
CPX
3 EXT
5
CPX
3 IX2
4
CPX
2 IX1
3
CPX
1IX
3
45
BRSET2
3 DIR
5
BSET2
2 DIR
3
BCC
2 REL
5
LSR
2 DIR
3
LSRA
1 INH
3
LSRX
1 INH
6
LSR
2 IX1
5
LSR
1IX
2
AND
2 IMM
3
AND
2 DIR
4
AND
3 EXT
5
AND
3 IX2
4
AND
2 IX1
3
AND
1IX
4
55
BRCLR2
3 DIR
5
BCLR2
2 DIR
3
BCS/BLO
2 REL
2
BIT
2 IMM
3
BIT
2 DIR
4
BIT
3 EXT
5
BIT
3 IX2
4
BIT
2 IX1
3
BIT
1IX
5
65
BRSET3
3 DIR
5
BSET3
2 DIR
3
BNE
2 REL
5
ROR
2 DIR
3
RORA
1 INH
3
RORX
1 INH
6
ROR
2 IX1
5
ROR
1IX
2
LDA
2 IMM
3
LDA
2 DIR
4
LDA
3 EXT
5
LDA
3 IX2
4
LDA
2 IX1
3
LDA
1IX
6
75
BRCLR3
3 DIR
5
BCLR3
2 DIR
3
BEQ
2 REL
5
ASR
2 DIR
3
ASRA
1 INH
3
ASRX
1 INH
6
ASR
2 IX1
5
ASR
1IX
2
TAX
1 INH
4
STA
2 DIR
5
STA
3 EXT
6
STA
3 IX2
5
STA
2 IX1
4
STA
1IX
7
85
BRSET4
3 DIR
5
BSET4
2 DIR
3
BHCC
2 REL
5
ASL/LSL
2 DIR
3
ASLA/LSLA
1 INH
3
ASLX/LSLX
1 INH
6
ASL/LSL
2 IX1
5
ASL/LSL
1IX
2
CLC
1 INH
2
EOR
2 IMM
3
EOR
2 DIR
4
EOR
3 EXT
5
EOR
3 IX2
4
EOR
2 IX1
3
EOR
1IX
8
95
BRCLR4
3 DIR
5
BCLR4
2 DIR
3
BHCS
2 REL
5
ROL
2 DIR
3
ROLA
1 INH
3
ROLX
1 INH
6
ROL
2 IX1
5
ROL
1IX
2
SEC
1 INH
2
ADC
2 IMM
3
ADC
2 DIR
4
ADC
3 EXT
5
ADC
3 IX2
4
ADC
2 IX1
3
ADC
1IX
9
A5
BRSET5
3 DIR
5
BSET5
2 DIR
3
BPL
2 REL
5
DEC
2 DIR
3
DECA
1 INH
3
DECX
1 INH
6
DEC
2 IX1
5
DEC
1IX
2
CLI
1 INH
2
ORA
2 IMM
3
ORA
2 DIR
4
ORA
3 EXT
5
ORA
3 IX2
4
ORA
2 IX1
3
ORA
1IX
A
B5
BRCLR5
3 DIR
5
BCLR5
2 DIR
3
BMI
2 REL
2
SEI
1 INH
2
ADD
2 IMM
3
ADD
2 DIR
4
ADD
3 EXT
5
ADD
3 IX2
4
ADD
2 IX1
3
ADD
1IX
B
C5
BRSET6
3 DIR
5
BSET6
2 DIR
3
BMC
2 REL
5
INC
2 DIR
3
INCA
1 INH
3
INCX
1 INH
6
INC
2 IX1
5
INC
1IX
2
RSP
1 INH
2
JMP
2 DIR
3
JMP
3 EXT
4
JMP
3 IX2
3
JMP
2 IX1
2
JMP
1IX
C
D5
BRCLR6
3 DIR
5
BCLR6
2 DIR
3
BMS
2 REL
4
TST
2 DIR
3
TSTA
1 INH
3
TSTX
1 INH
5
TST
2 IX1
4
TST
1IX
2
NOP
1 INH
6
BSR
2 REL
5
JSR
2 DIR
6
JSR
3 EXT
7
JSR
3 IX2
6
JSR
2 IX1
5
JSR
1IX
D
E5
BRSET7
3 DIR
5
BSET7
2 DIR
3
BIL
2 REL
2
STOP
1 INH
2
LDX
2 IMM
3
LDX
2 DIR
4
LDX
3 EXT
5
LDX
3 IX2
4
LDX
2 IX1
3
LDX
1IX
E
F5
BRCLR7
3 DIR
5
BCLR7
2 DIR
3
BIH
2 REL
5
CLR
2 DIR
3
CLRA
1 INH
3
CLRX
1 INH
6
CLR
2 IX1
5
CLR
1IX
2
WAIT
1 INH
2
TXA
1 INH
4
STX
2 DIR
5
STX
3 EXT
6
STX
3 IX2
5
STX
2 IX1
4
STX
1IX
F
INH = Inherent REL = Relative
IMM = Immediate IX = Indexed, No Offset
DIR = Direct IX1 = Indexed, 8-Bit Offset
EXT = Extended IX2 = Indexed, 16-Bit Offset
0MSB of Opcode in Hexadecimal
LSB of Opcode in Hexadecimal 05
BRSET0
3 DIR
Number of Cycles
Opcode Mnemonic
Number of Bytes/Addressing Mode
LSB
MSB LSB
MSB
LSB MSB
22-hc05cpu
MC68HC705J1A — Rev. 2.0
MOTOROLA Resets and Interrupts 53
Resets and Interrupts
Resets and Interrupts
Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Introduction Reset initializes the MCU by returning the program counter to a known
address and by forcing control and status bits to known states.
Interrupts temporarily change the sequence of program execution to
respond to events that occur during processing.
1-ri_a
Resets and Interrupts
MC68HC705J1A — Rev. 2.0
54 Resets and Interrupts MOTOROLA
Resets A reset immediately stops the operation of the instruction being
executed, initializes certain control and status bits, and loads the
program counter with a user-defined reset vector address. The following
sources can generate a reset:
• Power-on reset (POR) circuit
•RESET pin
• Computer operating properly (COP) watchdog
• Illegal address
Figure 1. Reset Sources
Power-On Reset A positive transition on the VDD pin generates a power-on reset.
NOTE:
The power-on reset is strictly for power-up conditions and cannot be
used to detect drops in power supply voltage.
A 4064-tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If any reset source is active
at the end of this delay, the MCU remains in the reset condition until all
reset sources are inactive.
DQ
CK
S
RESET
LATCH
INTERNAL CLOCK
RST TO CPU AND
RESET PIN
VDD
PERIPHERAL
MODULES
ILLEGAL ADDRESS
COP WATCHDOG
POWER-ON RESET
2-ri_a
Resets and Interrupts
Resets
MC68HC705J1A — Rev. 2.0
MOTOROLA Resets and Interrupts 55
Figure 2. Power-On Reset Timing
External Reset A logic 0 applied to the RESET pin for 1 1/2 tcyc generates an external
reset. A Schmitt trigger senses the logic level at the RESET pin.
Figure 3. External Reset Timing
OSCILLATOR STABILIZATION DELAY
VDD
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
NOTES:
INTERNAL
DATA BUS
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
$07FE $07FE $07FE $07FE $07FE $07FE $07FF
NEW PCH NEW PCL
(NOTE 1)
Table 1. External Reset Timing
Characteristic Symbol Min Max Unit
RESET Pulse Width tRL 1.5 — tcyc
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
NOTES:
INTERNAL
DATA BUS
$07FE $07FE $07FE $07FE $07FF NEW PC
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
NEW
PCH
tRL
NEW PC
NEW
PCL DUMMY OP
CODE
RESET
3-ri_a
Resets and Interrupts
MC68HC705J1A — Rev. 2.0
56 Resets and Interrupts MOTOROLA
COP Watchdog
Reset A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the
COP register at location $07F0.
Illegal Address
Reset An opcode fetch from an address not in RAM or EPROM generates a
reset.
Interrupts The following sources can generate interrupts:
• SWI instruction
• External interrupt pins
–IRQ/VPP pin
– PA0–PA3
• Timer
– Real-time interrupt flag (RTIF)
– Timer overflow flag (TOF)
An interrupt temporarily stops the program sequence to process a
particular event. An interrupt does not stop the operation of the
instruction being executed, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a
user-defined interrupt vector address.
Software Interrupt The software interrupt (SWI) instruction causes a nonmaskable
interrupt.
External Interrupt An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. When the CPU completes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
4-ri_a
Resets and Interrupts
Interrupts
MC68HC705J1A — Rev. 2.0
MOTOROLA Resets and Interrupts 57
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/VPP pin can latch another interrupt
request during the interrupt service routine. As soon as the I bit is
cleared during the return from interrupt, the CPU can recognize the new
interrupt request. Figure 4 shows the external interrupt logic.
Figure 4. External Interrupt Logic
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register
enables pins PA0–PA3 to function as external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register
controls interrupt triggering sensitivity of external interrupt pins. The
IRQ/VPP pin can be negative-edge triggered only or negative-edge and
low-level triggered. Port A external interrupt pins can be positive-edge
triggered only or both positive-edge and high-level triggered. The
level-sensitive triggering option allows multiple external interrupt
sources to be wire-ORed to an external interrupt pin.Figure 5 shows the
external interrupt timing.
PIRQ
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
VDD
(MOR LEVEL BIT)
RESET
IRQ VECTOR FETCH
EXTERNAL
INTERRUPT
REQUEST
(MOR)
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
IRQR
IRQE
DQ
CK
IRQ
CLR
LATCH
5-ri_a
Resets and Interrupts
MC68HC705J1A — Rev. 2.0
58 Resets and Interrupts MOTOROLA
Figure 5. External Interrupt Timing
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +105 °C unless otherwise noted.
2. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tcyc.
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +105 °C unless otherwise noted.
2. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tcyc.
Table 2. External Interrupt Timing (VDD = 5.0 Vdc)(1)
Characteristic Symbol Min Max Unit
Interrupt Pulse Width Low (Edge-Triggered) tILIH 125 — ns
Interrupt Pulse Period tILIL Note(2) —t
cyc
Table 3. External Interrupt Timing (VDD = 3.3 Vdc)(1)
Characteristic Symbol Min Max Unit
Interrupt Pulse Width Low (Edge-Triggered) tILIH 250 — ns
Interrupt Pulse Period tILIL Note(2) —t
cyc
IRQ
tILIH
tILIL
tILIH
IRQ PIN
IRQ1
IRQn
.
.
.
(INTERNAL)
6-ri_a
Resets and Interrupts
Interrupts
MC68HC705J1A — Rev. 2.0
MOTOROLA Resets and Interrupts 59
Timer Interrupts The timer can generate the following interrupt requests:
• Real time
• Timer overflow
Setting the I bit in the condition code register disables timer interrupts.
Real-Time Interrupt A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes
set while the real-time interrupt enable bit, RTIE, is also set. RTIF and
RTIE are in the timer status and control register.
Timer Overflow
Interrupt A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. TOF and TOIE are in the timer status and control register.
Interrupt
Processing The CPU takes the following actions to begin servicing an interrupt:
• Stores the CPU registers on the stack in the order shown in
Figure 6
• Sets the I bit in the condition code register to prevent further
interrupts
• Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $07FC and $07FD (software interrupt vector)
– $07FA and $07FB (external interrupt vector)
– $07F8 and $07F9 (timer interrupt vector)
The return from interrupt (RTI) instruction causes the CPU to recover the
CPU registers from the stack as shown in Figure 6.
7-ri_a
Resets and Interrupts
MC68HC705J1A — Rev. 2.0
60 Resets and Interrupts MOTOROLA
Figure 6. Interrupt Stacking Order
CONDITION CODE REGISTER
$00C0 (BOTTOM OF STACK
)
$00C1
$00C2
•
•
•
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
1
2
3
4
5
5
4
3
2
1
UNSTACKING
ORDER
STACKING
ORDER
8-ri_a
Resets and Interrupts
Interrupts
MC68HC705J1A — Rev. 2.0
MOTOROLA Resets and Interrupts 61
1. The COP watchdog is programmable in the mask option register.
Table 4. Reset/Interrupt Vector Addresses
Function Source Local
Mask Global
Mask Priority
(1 = Highest) Vector
Address
Reset
Power-On
RESET Pin
COP Watchdog(1)
Illegal Address
None None 1 $07FE–$07FF
Software
Interrupt
(SWI) User Code None None Same Priority
as Instruction $07FC–$07FD
External
Interrupt
IRQ/VPP Pin
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
IRQE I Bit 2 $07FA–$07FB
Timer
Interrupts RTIF Bit
TOF Bit RTIE Bit
TOIE Bit I Bit 3 $07F8–$07F9
9-ri_a
Resets and Interrupts
MC68HC705J1A — Rev. 2.0
62 Resets and Interrupts MOTOROLA
Figure 7. Interrupt Flowchart
EXTERNAL
INTERRUPT?
I BIT SET?
TIMER
INTERRUPT?
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
RTI
INSTRUCTION?
STACK PC, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
YES
YES
YES
YES
YES UNSTACK CCR, A, X, PC.
EXECUTE INSTRUCTION.
CLEAR IRQ LATCH.
NO
NO
NO
NO
NO
FROM RESET
10-ri_a
MC68HC705J1A — Rev. 2.0
MOTOROLA Low-Power Modes 63
Low-Power Modes
Low-Power Modes
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
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Low-Power Modes
MC68HC705J1A — Rev. 2.0
64 Low-Power Modes MOTOROLA
Introduction
The MCU can enter the following low-power standby modes:
• Stop mode — The STOP instruction puts the MCU in its lowest
power-consumption mode.
• Wait mode — The WAIT instruction puts the MCU in an
intermediate power-consumption mode.
• Halt mode — Halt mode is identical to wait mode, except that an
oscillator stabilization delay of 1 to 4064 internal clock cycles
occurs when the MCU exits halt mode. The stop-to-wait
conversion bit, SWAIT, in the mask option register, enables halt
mode.
Enabling halt mode prevents the computer operating properly
(COP) watchdog from being inadvertently turned off by a STOP
instruction.
• Data-retention mode — In data-retention mode, the MCU retains
RAM contents and CPU register contents at VDD voltages as low
as 2.0 Vdc. The data-retention feature allows the MCU to remain
in a low power-consumption state during which it retains data, but
the CPU cannot execute instructions.
Exiting Stop and Wait Modes
The following events bring the MCU out of stop mode and load the
program counter with the reset vector or with an interrupt vector:
Exiting Stop Mode • External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
• External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
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Low-Power Modes
Effects of Stop and Wait Modes
MC68HC705J1A — Rev. 2.0
MOTOROLA Low-Power Modes 65
Exiting Wait Mode • External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
• External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
• COP watchdog reset — A timeout of the COP watchdog resets the
MCU, starts the CPU clock, and loads the program counter with
the contents of locations $07FE and $07FF. Software can enable
timer interrupts so that the MCU periodically can exit wait mode to
reset the COP watchdog.
• Timer interrupt — Real-time interrupt requests and timer overflow
interrupt requests start the MCU clock and load the program
counter with the contents of locations $07F8 and $07F9.
Effects of Stop and Wait Modes
The STOP and WAIT instructions have the following effects on MCU
modules.
Clock Generation Effects of STOP and WAIT:
STOP The STOP instruction disables the internal oscillator, stopping the CPU
clock and all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral clocks
begin running after the oscillator stabilization delay.
NOTE:
The oscillator stabilization delay holds the MCU in reset for the first 4064
internal clock cycles.
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Low-Power Modes
MC68HC705J1A — Rev. 2.0
66 Low-Power Modes MOTOROLA
WAIT The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral clocks
immediately begin running.
CPU Effects of STOP and WAIT:
STOP The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
WAIT The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts
• Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
COP Watchdog Effects of STOP and WAIT:
STOP The STOP instruction:
• Clears the COP watchdog counter
• Disables the COP watchdog clock
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Low-Power Modes
Effects of Stop and Wait Modes
MC68HC705J1A — Rev. 2.0
MOTOROLA Low-Power Modes 67
NOTE:
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
After exit from stop mode by external interrupt, the COP watchdog
counter immediately begins counting from $0000 and continues
counting throughout the oscillator stabilization delay.
NOTE:
Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
After exit from stop mode by reset:
• The COP watchdog counter immediately begins counting from
$0000.
• The COP watchdog counter is cleared at the end of the oscillator
stabilization delay and begins counting from $0000 again.
WAIT The WAIT instruction has no effect on the COP watchdog.
NOTE:
To prevent a COP timeout during wait mode, exit wait mode periodically
to service the COP.
Timer Effects of STOP and WAIT:
STOP • Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and
control register, disabling timer interrupt requests and removing
any pending timer interrupt requests
• Disables the clock to the timer
After exiting stop mode by external interrupt, the timer immediately
resumes counting from the last value before the STOP instruction and
continues counting throughout the oscillator stabilization delay.
After exiting stop mode by reset and after the oscillator stabilization
delay, the timer resumes operation from its reset state.
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Low-Power Modes
MC68HC705J1A — Rev. 2.0
68 Low-Power Modes MOTOROLA
WAIT The WAIT instruction has no effect on the timer.
EPROM/OTPROM Effects of STOP and WAIT:
STOP The STOP instruction during EPROM programming clears the EPGM bit
in the EPROM programming register, removing the programming
voltage from the EPROM.
WAIT The WAIT instruction has no effect on EPROM/OTPROM operation.
Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU
register contents at VDD voltages as low as 2.0 Vdc. The data-retention
feature allows the MCU to remain in a low power-consumption state
during which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower the VDD voltage. The RESET pin must remain low
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic 1.
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Low-Power Modes
Timing
MC68HC705J1A — Rev. 2.0
MOTOROLA Low-Power Modes 69
Timing
Figure 1. Stop Mode Recovery Timing
tILIH
OSCILLATOR STABILIZATION DELAY
OSC
tRL
RESET
IRQ/VPP
IRQ/VPP
INTERNAL
CLOCK
INTERNAL
ADDRESS
NOTES:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
RESET OR INTERRUPT
VECTOR FETCH
$07FE $07FE $07FE $07FE $07FE $07FF
(NOTE 4)
BUS
(NOTE 3)
(NOTE 2)
(NOTE 1)
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Low-Power Modes
MC68HC705J1A — Rev. 2.0
70 Low-Power Modes MOTOROLA
Figure 2. STOP/HALT/WAIT Flowchart
STOP
SWAIT
BIT SET?
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR.
TURN OFF INTERNAL OSCILLATOR.
EXTERNAL
RESET?
EXTERNAL
INTERRUPT?
NO
NO
NO
TURN ON INTERNAL OSCILLATOR.
RESET STABILIZATION TIMER.
YES
YES
HALT
YES
END OF
STABILIZATION
DELAY? YES
NO
YES
NO
NO
NO
COP
RESET?
TIMER
INTERRUPT?
EXTERNAL
INTERRUPT?
EXTERNAL
RESET?
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
TIMER CLOCK ACTIVE.
YES
YES
YES
YES
NO
NO
NO
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
TIMER CLOCK ACTIVE.
YES
YES
YES
NO NO
TURN ON CPU CLOCK.
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT.
a. SAVE CPU REGISTERS ON STACK.
b. SET I BIT IN CCR.
c. LOAD PC WITH INTERRUPT VECTOR.
EXTERNAL
RESET?
WAIT
EXTERNAL
INTERRUPT?
TIMER
INTERRUPT?
COP
RESET?
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MC68HC705J1A — Rev. 2.0
MOTOROLA Parallel I/O Ports 71
Parallel I/O Ports
Parallel I/O Ports
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Port A LED Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Introduction
Fourteen bidirectional pins form one 8-bit input/output (I/O) port and one
6-bit I/O port. All the bidirectional port pins are programmable as inputs
or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either V
DD
or
V
SS.
Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
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Parallel I/O Ports
MC68HC705J1A — Rev. 2.0
72 Parallel I/O Ports MOTOROLA
Addr. Register Name: Bit 7 654321Bit 0
$0000 Port A Data Register
(PORTA) Read: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Unaffected by Reset
$0001 Port B Data Register
(PORTB) Read: 0 0 PB5 PB4 PB3 PB2 PB1 PB0
Write:
Reset: Unaffected by Reset
$0004 Data Direction Register A
(DDRA) Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 00000000
$0005 Data Direction Register B
(DDRB) Read: 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset: 00000000
$0010 Port A Pulldown Register
(PDRA) Read:
Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0
Reset: 00000000
$0011 Port B Pulldown Register
(PDRB) Read:
Write: PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0
Reset: 000000
= Unimplemented
Figure 1. Parallel I/O Port Register Summary
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Parallel I/O Ports
Port A
MC68HC705J1A — Rev. 2.0
MOTOROLA Parallel I/O Ports 73
Port A
Port A is an 8-bit bidirectional port.
Port A Data
Register The port A data register contains a latch for each port A pin.
PA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
Data Direction
Register A Data direction register A determines whether each port A pin is an input
or an output.
Address: $0000
Bit 7 654321Bit 0
Read: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Unaffected by Reset
Figure 2. Port A Data Register (PORTA)
Address: $0004
Bit 7 654321Bit 0
Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 00000000
Figure 3. Data Direction Register A (DDRA)
3-j_port_a
Parallel I/O Ports
MC68HC705J1A — Rev. 2.0
74 Parallel I/O Ports MOTOROLA
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 4 shows the I/O logic of port A.
Figure 4. Port A I/O Circuitry
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
READ DDRA
WRITE DDRA
RESET
WRITE PORTA
READ PORTA
PAx
INTERNAL DATA BUS
DDRAx
PAx
PDRAx
SWPDI
100-µA
PULLDOWN
(PA0–PA3 TO
IRQ MODULE
)
WRITE PDRA
10 mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
4-j_port_a
Parallel I/O Ports
Port A
MC68HC705J1A — Rev. 2.0
MOTOROLA Parallel I/O Ports 75
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 1 summarizes the operation of
the port A pins.
1. Writing affects data register but does not affect input.
Pulldown
Register A Pulldown register A inhibits the pulldown devices on port A pins
programmed as inputs.
NOTE:
If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port A pins as inputs with enabled pulldown devices.
PDIA[7:0] — Pulldown Inhibit A Bits
PDIA[7:0] disable the port A pulldown devices. Reset clears
PDIA[7:0].
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
Table 1. Port A Pin Operation
Data Direction Bit I/O Pin Mode Accesses to Data Bit
Read Write
0 Input, high-impedance Pin Latch(1)
1 Output Latch Latch
Address: $0010
Bit 7 654321Bit 0
Read:
Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0
Reset: 00000000
= Unimplemented
Figure 5. Pulldown Register A (PDRA)
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Parallel I/O Ports
MC68HC705J1A — Rev. 2.0
76 Parallel I/O Ports MOTOROLA
Port A LED Drive
Capability The outputs for the upper four bits of port A (PA4–PA7) can drive
light-emitting diodes (LEDs). PA4–PA7can sink approximately 10 mA of
current to VSS.
Port A I/O Pin
Interrupts If the PIRQ bit in the mask option register is programmed to logic 1,
PA0–PA3 pins function as external interrupt pins. (See External
Interrupt Module.)
Port B
Port B is a 6-bit bidirectional port.
Port B Data
Register The port B data register contains a latch for each port B pin.
PB[5:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each
port B pin is under the control of the corresponding bit in data direction
register B. Reset has no effect on port B data.
Address: $0001
Bit 7 654321Bit 0
Read: 0 0 PB5 PB4 PB3 PB2 PB1 PB0
Write:
Reset: Unaffected by Reset
= Unimplemented
Figure 6. Port B Data Register (PORTB)
6-j_port_a
Parallel I/O Ports
Port B
MC68HC705J1A — Rev. 2.0
MOTOROLA Parallel I/O Ports 77
Data Direction
Register B Data direction register B determines whether each port B pin is an input
or an output.
DDRB[5:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[5:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 8 shows the I/O logic of port B.
Figure 8. Port B I/O Circuitry
Address: $0005
Bit 7 654321Bit 0
Read: 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset: 00000000
= Unimplemented
Figure 7. Data Direction Register B (DDRB)
READ DDRB
WRITE DDRB
RESET
WRITE PORTB
READ PORTB
PBx
INTERNAL DATA BUS
DDRBx
PBx
PDRBx
SWPDI
100-µA
PULLDOWN
WRITE PDRB
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Parallel I/O Ports
MC68HC705J1A — Rev. 2.0
78 Parallel I/O Ports MOTOROLA
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 2 summarizes the operation of
the port B pins.
1. Writing affects data register, but does not affect input.
Pulldown
Register B Pulldown register B inhibits the pulldown devices on port B pins
programmed as inputs.
NOTE:
If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port B pins as inputs with enabled pulldown devices.
PDIB[7:0] — Pulldown Inhibit B Bits
PDIB[7:0] disable the port B pulldown devices. Reset clears
PDIB[7:0].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Table 2. Port B Pin Operation
Data Direction Bit I/O Pin Mode Accesses to Data Bit
Read Write
0 Input, high-impedance Pin Latch(1)
1 Output Latch Latch
Address: $0011
Bit 7 654321Bit 0
Read:
Write: PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0
Reset: 000000
= Unimplemented
Figure 9. Pulldown Register B (PDRB)
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Parallel I/O Ports
I/O Port Electrical Characteristics
MC68HC705J1A — Rev. 2.0
MOTOROLA Parallel I/O Ports 79
I/O Port Electrical Characteristics
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +105 °C unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C.
Table 3. I/O Port DC Electrical Characteristics (VDD = 5 V)(1)
Characteristic Symbol Min Typ(2) Max Unit
Current Drain Per Pin Excluding PA4–PA7 I — 25 — mA
Output High Voltage
(ILoad = –0.8 mA) PA0–PA7, PB0–PB5 VOH
VDD
–0.8 — — V
Output Low Voltage
(ILoad = 1.6 mA) PA0–PA3, PB0–PB5
(ILoad = 10.0 mA) PA4–PA7 VOL
VOL
—
——
—0.4
0.4 V
Input High Voltage
PA0–PA7, PB0–PB5 VIH
0.7 x
VDD —VDD V
Input Low Voltage
PA0–PA7, PB0–PB5 VIL VSS —0.2 x
VDD V
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB0–PB5 (Without Individual
Pulldown Activated) IIL — 0.2 ±1µA
Input Pulldown Current
PA0–PA7, PB0–PB5 (With Individual Pulldown
Activated) IIL 35 80 200 µA
9-j_port_a
Parallel I/O Ports
MC68HC705J1A — Rev. 2.0
80 Parallel I/O Ports MOTOROLA
1. VDD = 3.3 Vdc ± 10%, VSS= 0 Vdc, TA= –40 °C to +105 °C unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C.
Table 4. I/O Port DC Electrical Characteristics (VDD = 3.3 V)(1)
Characteristic Symbol Min Typ(2) Max Unit
Current Drain Per Pin Excluding PA4–PA7 I — 25 — mA
Output High Voltage
(ILoad = –0.2 mA) PA0–PA7, PB0–PB5 VOH
VDD
–0.3 — — V
Output Low Voltage
(ILoad = 0.4 mA) PA0–PA3, PB0–PB5
(ILoad = 5.0 mA) PA4–PA7 VOL —
——
—0.3
0.3 V
Input High Voltage
PA0–PA7, PB0–PB5 VIH
0.7 x
VDD —VDD V
Input Low Voltage
PA0–PA7, PB0–PB5 VIL VSS —0.2 x
VDD V
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB0–PB5 (Without Individual
Pulldown Activated) IIL — 0.1 ±1µA
Input Pulldown Current
PA0–PA7, PB0–PB5 (With Individual Pulldown
Activated) IIL 12 30 100 µA
10-j_port_a
MC68HC705J1A — Rev. 2.0
MOTOROLA COP 81
Computer Operating Properly Module
COP
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
COP Watchdog Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Clearing the COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Features
• Protection from Runaway Software
• Wait and Halt Mode Operation
Introduction
The computer operating properly (COP) watchdog resets the MCU in
case of software failure. Software that is operating properly periodically
services the COP watchdog and prevents COP reset. The COP
watchdog function is programmable by the COPEN bit in the mask
option register.
1-@cop0coprt2
COP
MC68HC705J1A — Rev. 2.0
82 COP MOTOROLA
Operation
COP Watchdog
Timeout Four counter stages at the end of the timer make up the COP watchdog.
The COP resets the MCU if the timeout period occurs before the COP
watchdog timer is cleared by application software and the IRQ/VPP pin
voltage is between VSS and VDD. Periodically clearing the counter starts
a new timeout period and prevents COP reset. A COP watchdog timeout
indicates that the software is not executing instructions in the correct
sequence.
NOTE:
The internal clock drives the COP watchdog. Therefore, the COP
watchdog cannot generate a reset for errors that cause the internal clock
to stop.
NOTE:
The COP watchdog depends on a power supply voltage at or above a
minimum specification and is not guaranteed to protect against
brownout.
COP Watchdog
Timeout Period The COP watchdog timer function is implemented by dividing the output
of the real-time interrupt circuit (RTI) by eight. The RTI select bits in the
timer status and control register control RTI output, and the selected
output drives the COP watchdog. (See timer status and control register
in Multifunction Timer Module.)
Note that the minimum COP timeout period is seven times the RTI
period. The COP is cleared asynchronously with the value in the RTI
divider; hence, the COP timeout period will vary between 7x and 8x the
RTI period.
Clearing the COP
Watchdog To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $07F0(see Figure 1).
Clearing the COP bit disables the COP watchdog timer regardless of the
IRQ/VPP pin voltage.
2-@cop0coprt2
COP
Interrupts
MC68HC705J1A — Rev. 2.0
MOTOROLA COP 83
If the main program executes within the COP timeout period, the clearing
routine should be executed only once. If the main program takes longer
than the COP timeout period, the clearing routine must be executed
more than once.
NOTE:
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
Interrupts
The COP watchdog does not generate interrupts.
COP Register
The COP register (COPR) is a write-only register that returns the
contents of EPROM location $07F0 when read.
COPC — COP Clear
This write-only bit resets the COP watchdog. Reading address $07F0
returns undefined results.
Address: $07F0
Bit 7 654321Bit 0
Read:
Write: COPC
Reset: 0
= Unimplemented
Figure 1. COP Register
3-@cop0coprt2
COP
MC68HC705J1A — Rev. 2.0
84 COP MOTOROLA
Low-Power Modes
The STOP and WAIT instructions have the following effects on the COP
watchdog.
Stop Mode The STOP instruction clears the COP watchdog counter and disables
the clock to the COP watchdog.
NOTE:
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
Upon exit from stop mode by external reset:
• The counter begins counting from $0000.
• The counter is cleared again after the oscillator stabilization delay
and begins counting from $0000 again.
Upon exit from stop mode by external interrupt:
• The counter begins counting from $0000.
• The counter is not cleared again after the oscillator stabilization
delay and continues counting throughout the oscillator
stabilization delay.
NOTE:
Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
Wait Mode The WAIT instruction has no effect on the COP watchdog.
NOTE:
To prevent a COP timeout during wait mode, exit wait mode periodically
to service the COP.
4-@cop0coprt2
MC68HC705J1A — Rev. 2.0
MOTOROLA IRQ 85
External Interrupt Module
IRQ
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Features
• Dedicated External Interrupt Pin (IRQ/VPP)
• Selectable Interrupt on Four Input/Output (I/O) Pins (PA0–PA3)
• Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity
1-@kbielpa4hpd_a
IRQ
MC68HC705J1A — Rev. 2.0
86 IRQ MOTOROLA
Introduction
The external interrupt (IRQ) module provides asynchronous external
interrupts to the CPU. The following sources can generate external
interrupts:
•IRQ/VPP pin
• PA0–PA3 pins
Operation
The interrupt request/programming voltage pin (IRQ/VPP) and port A
pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the
mask option register (MOR) enables PA0–PA3 as IRQ interrupt sources,
which are combined into a single OR’ing function to be latched by the
IRQ latch. Figure 1 shows the structure of the IRQ module.
After completing its current instruction, the CPU tests the IRQ latch. If
the IRQ latch is set, the CPU then tests the I bit in the condition code
register and the IRQE bit in the IRQ status and control register. If the I
bit is clear and the IRQE bit is set, the CPU then begins the interrupt
sequence. This interrupt is serviced by the interrupt service routine
located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector , so that
another external interrupt request can be latched during the interrupt
service routine. As soon as the I bit is cleared during the return from
interrupt, the CPU can recognize the new interrupt request. Figure 3
shows the sequence of events caused by an interrupt.
2-@kbielpa4hpd_a
IRQ
Operation
MC68HC705J1A — Rev. 2.0
MOTOROLA IRQ 87
Figure 1. IRQ Module Block Diagram
Register Name Bit 7 6 5 4 3 2 1 Bit 0
IRQ Status and Control
Register (ISCR)
Read: IRQE 0 0 0 IRQF 0 0 0
Write: R IRQR
Reset: 1 0 0 0 0 0 0 0
= Unimplemented R = Reserved
Figure 2. IRQ Module I/O Register Summary
Table 1. I/O Register Address Summary
Register: ISCR
Address: $000A
PIRQ
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
VDD
(MOR LEVEL BIT)
RESET
IRQ VECTOR FETCH
EXTERNAL
INTERRUPT
REQUEST
(MOR)
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
IRQR
IRQE
DQ
CK
IRQ
CLR
LATCH
3-@kbielpa4hpd_a
IRQ
MC68HC705J1A — Rev. 2.0
88 IRQ MOTOROLA
Figure 3. Interrupt Flowchart
EXTERNAL
INTERRUPT?
I BIT SET?
TIMER
INTERRUPT?
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
RTI
INSTRUCTION?
STACK PCL, PCH, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
YES
YES
YES
YES
YES UNSTACK CCR, A, X, PCH, PCL.
EXECUTE INSTRUCTION.
CLEAR IRQ LATCH.
NO
NO
NO
NO
NO
FROM RESET
4-@kbielpa4hpd_a
IRQ
Operation
MC68HC705J1A — Rev. 2.0
MOTOROLA IRQ 89
IRQ/VPP Pin An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If edge- and le v el-sensitiv e triggering is selected, a falling edge or a lo w
level on theIRQ/VPP pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. An external interrupt request is latched as long as any
source is holding the IRQ/VPP pin low.
If level-sensitive triggering is selected, the IRQ/VPP input requires an
external resistor to VDD for wired-OR operation. If the IRQ/VPP pin is not
used, it must be tied to the VDD supply.
If edge-sensitive-only triggering is selected, a falling edge on the
IRQ/VPP pin latches an external interrupt request. A subsequent
external interrupt request can be latched only after the voltage level on
the IRQ/VPP pin returns to logic 1 and then falls again to logic 0.
The IRQ/VPP pin contains an internal Schmitt trigger as part of its input
to improve noise immunity. The voltage on this pin can affect the mode
of operation and should not exceed VDD.
5-@kbielpa4hpd_a
IRQ
MC68HC705J1A — Rev. 2.0
90 IRQ MOTOROLA
Optional External
Interrupts The inputs for the lower four bits of port A (PA0–PA3) can be connected
to the IRQ pin input of the CPU if enabled by the PIRQ bit in the mask
option register. This capability allows keyboard scan applications where
the transitions or levels on the I/O pins will behave the same as the
IRQ/VPP pin except for the inverted phase (logic 1, rising edge). The
active state of the IRQ/VPP pin is a logic 0 (falling edge).
The PA0–PA3 pins are selected as a group to function as IRQ interrupts
and are enabled by the IRQE bit in the IRQ status and control register.
The PA0–PA3 pins can be positive-edge triggered only or positive-edge
and high-level triggered.
If edge- and level-sensitive triggering is selected, a rising edge or a high
level on a PA0–PA3 pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. As long as any source is holding a PA0–PA3 pin high,
an external interrupt request is latched, and the CPU continues to
execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3
pin latches an external interrupt request. A subsequent external interrupt
request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE:
The BIH and BIL instructions apply only to the level on the IRQ/V
PP
pin
itself and not to the output of the logic OR function with the PA0
–
PA3
pins. The state of the individual port A pins can be checked by reading
the appropriate port A pins as inputs.
NOTE:
Enabled PA0
–
PA3 pins cause an IRQ interrupt regardless of whether
these pins are configured as inputs or outputs.
NOTE:
The IRQ pin has an internal Schmitt trigger. The optional external
interrupts (PA0
–
PA3) do not have internal Schmitt triggers.
NOTE:
The interrupt mask bit (I) in the condition code register (CCR) disables
all maskable interrupt requests, including external interrupt requests.
6-@kbielpa4hpd_a
IRQ
IRQ Status and Control Register
MC68HC705J1A — Rev. 2.0
MOTOROLA IRQ 91
IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. All unused bits in the ISCR read as logic
0s. The IRQF bit is cleared and the IRQE bit is set by reset.
IRQR — Interrupt Request Reset
This write-only bit clears the external interrupt request flag.
1 = Clears external interrupt and IRQF bit
0 = No effect on external interrupt and IRQF bit
IRQF — External Interrupt Request Flag
The external interrupt request flag is a clearable, read-only bit that is
set when an external interrupt request is pending. Reset clears the
IRQF bit.
1 = External interrupt request pending
0 = No external interrupt request pending
IRQE — External Interrupt Request Enable
This read/write bit enables external interrupts. Reset sets the IRQE
bit.1 = External interrupt requests enabled
0 = External interrupt requests disabled
The STOP and WAIT instructions set the IRQE bit so that an external
interrupt can bring the MCU out of these low-power modes. In addition,
reset sets the I bit which masks all interrupt sources.
Address: $000A
Bit 7 654321Bit 0
Read: IRQE 0 0 0 IRQF 0 0 0
Write: R IRQR
Reset: 10000000
= Unimplemented R = Reserved
Figure 4. IRQ Status and Control Register (ISCR)
7-@kbielpa4hpd_a
IRQ
MC68HC705J1A — Rev. 2.0
92 IRQ MOTOROLA
Timing
Figure 5. External Interrupt Timing
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to + 105 °C unless otherwise noted.
2. tcyc = 1/fop; fop = fosc/2.
3. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tcyc.
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to + 105 °C unless otherwise noted.
2. tcyc = 1/fop; fop = fosc/2.
3. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tcyc.
Table 2. External Interrupt Timing (VDD = 5.0 Vdc)(1)
Characteristic Symbol Min Max Unit
IRQ Interrupt Pulse Width Low
(Edge-Triggered) tILIH 1.5 — tcyc(2)
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered) tILIH 1.5 Note
(3) tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered) tILIL 1.5 — tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge- and Level-Triggered) tILIH 1.5 Note
(3) tcyc
Table 3. External Interrupt Timing (VDD = 3.3 Vdc)(1)
Characteristic Symbol Min Max Unit
IRQ Interrupt Pulse Width Low
(Edge-Triggered) tILIH 1.5 — tcyc(2)
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered) tILIH 1.5 Note
(3) tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered) tILIL 1.5 — tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge- and Level-Triggered) tILIH 1.5 Note
(3) tcyc
IRQ (INTERNAL)
tILIH
tILIL
tILIH
IRQ/VPP PIN
IRQ1
IRQn
.
.
.
8-@kbielpa4hpd_a
MC68HC705J1A — Rev. 2.0
MOTOROLA Timer 93
Multifunction Timer Module
Timer
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . .96
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Features
• Timer Overflow
• Four Selectable Interrupt Rates
• Computer Operating Properly (COP) Watchdog Timer
Introduction
The multifunction timer provides a timing reference with programmable
real-time interrupt capability. Figure 1 shows the timer organization.
1-@tim15b1rticlr_a
Timer
MC68HC705J1A — Rev. 2.0
94 Timer MOTOROLA
Figure 1. Multifunction Timer Block Diagram
CLEAR COP TIMER
TIMER COUNTER REGISTER
BITS [0:7] OF 15-STAGE
OVERFLOW ÷ 4INTERNAL CLOCK
(XTAL ÷2)
TIMER STATUS/CONTROL REGISTER
TOF
RTIF
TOIE
RTIE
TOFR
RTIFR
RT1
RT0
RTI RATE SELECT
÷2÷2÷2÷2÷2÷2÷2
BITS [8:14] OF 15-STAGE RIPPLE COUNTER
÷8S
R
Q
INTERRUPT
REQUEST
COP RESET
INTERNAL DATA BUS
RESET
RIPPLE COUNTER
RESET
RESET
RESET
2-@tim15b1rticlr_a
Timer
Operation
MC68HC705J1A — Rev. 2.0
MOTOROLA Timer 95
Operation
A 15-stage ripple counter, preceded by a prescaler that divides the
internal clock signal by four, provides the timing reference for the timer
functions. The value of the first eight timer stages can be read at any
time by accessing the timer counter register at address $0009. A timer
overflow function at the eighth stage allows a timer interrupt every 1024
internal clock cycles.
The next four stages lead to the real-time interrupt (RTI) circuit. The RT1
and RT0 bits in the timer status and control register at address $0008
allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock
cycles. The last four stages drive the selectable COP system. (For
information on the COP, refer to the Computer Operating Properly
Module.)
Register Name Bit 7 6 5 4 3 2 1 Bit 0
Timer Status and Control Register
(TSCR)
Read: TOF RTIF TOIE RTIE 00
RT1 RT0
Write: TOFR RTIFR
Reset: 0 0 0 0 0 0 1 1
Timer Counter Register (TCR) Read: TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 2. I/O Register Summary
Table 1. I/O Register Address Summary
Register: TSCR TCR
Address: $0008 $0009
3-@tim15b1rticlr_a
Timer
MC68HC705J1A — Rev. 2.0
96 Timer MOTOROLA
Interrupts
The following timer sources can generate interrupts:
• Timer overflow flag (TOF) — The TOF bit is set when the first eight
stages of the counter roll over from $FF to $00. The timer overflow
interrupt enable bit, TOIE, enables TOF interrupt requests.
• Real-time interrupt flag (RTIF) — The RTIF bit is set when the
selected RTI output becomes active. The real-time interrupt
enable bit, RTIE, enables RTIF interrupt requests.
I/O Registers
The following registers control and monitor the timer operation:
• Timer status and control register (TSCR)
• Timer counter register (TCR)
Timer Status and
Control Register The read/write timer status and control register performs the following
functions:
• Flags timer interrupts
• Enables timer interrupts
• Resets timer interrupt flags
• Selects real-time interrupt rates
4-@tim15b1rticlr_a
Timer
I/O Registers
MC68HC705J1A — Rev. 2.0
MOTOROLA Timer 97
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the
counter roll over from $FF to $00. TOF generates a timer overflow
interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to
the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected RTI output
becomes active. RTIF generates a real-time interrupt request if RTIE
is also set. Clear RTIF by writing a logic 1 to the RTIFR bit. Writing
to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables timer overflow interrupts. Reset clears
TOIE.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
Address: $0008
Bit 7 654321Bit 0
Read: TOF RTIF TOIE RTIE 00
RT1 RT0
Write: TOFR RTIFR
Reset: 00000011
= Unimplemented
Figure 3. Timer Status and Control Register (TSCR)
5-@tim15b1rticlr_a
Timer
MC68HC705J1A — Rev. 2.0
98 Timer MOTOROLA
TOFR — Timer Overflow Flag Reset
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always
reads as logic 0. Reset clears TOFR.
RTIFR — Real-Time Interrupt Flag Reset
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as logic 0. Reset clears RTIFR.
RT1 and RT0 — Real-Time Interrupt Select Bits
These read/write bits select one of four real-time interrupt rates, as
shown in Table 2. Because the selected RTI output drives the COP
watchdog, changing the real-time interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0.
NOTE:
Changing RT1 and RT0 when a COP timeout is imminent can cause a
real-time interrupt request to be missed or an additional real-time
interrupt request to be generated. To prevent this occurrence, clear the
COP timer before changing RT1 and RT0.
Table 2. Real-Time Interrupt Rate Selection
RT1:RT0 RTI
Rate
RTI Period
(fOP = 2
MHz)
COP Timeout
Period
(–0/+1 RTI Period)
Minimum COP
Timeout Period
(fOP = 2 MHz)
00 fOP ÷214 8.2 ms 7 x RTI Period 57.3 ms
01 fOP ÷ 215 16.4 ms 7 x RTI Period 114.6 ms
10 fOP ÷216 32.8 ms 7 x RTI Period 229.3 ms
11 fOP ÷217 65.5 ms 7 x RTI Period 458.7 ms
6-@tim15b1rticlr_a
Timer
I/O Registers
MC68HC705J1A — Rev. 2.0
MOTOROLA Timer 99
Timer Counter
Register A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register shown in Figure 4.
Power-on clears the entire counter chain and the internal clock begins
clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in
the mask option register is set), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Address: $0009
Bit 7 654321Bit 0
Read: TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
Write:
Reset: 00000000
= Unimplemented
Figure 4. Timer Counter Register (TCR)
7-@tim15b1rticlr_a
Timer
MC68HC705J1A — Rev. 2.0
100 Timer MOTOROLA
Low-Power Modes
The STOP and WAIT instructions put the MCU in low
power-consumption standby states.
Stop Mode The STOP instruction has the following effects on the timer:
• Clears the timer counter
• Clears interrupt flags (TOF and RTIF) and interrupt enable bits
(TOFE and RTIE) in TSCR, removing any pending timer interrupt
requests and disabling further timer interrupts.
Wait Mode The timer remains active after a WAIT instruction. Any enabled timer
interrupt request can bring the MCU out of wait mode.
8-@tim15b1rticlr_a
MC68HC705J1A — Rev. 2.0
MOTOROLA Specifications 101
Specifications
Contents
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
5.0 V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .105
3.3 V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .106
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . .111
Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
20-Pin PDIP — Case #738-03 . . . . . . . . . . . . . . . . . . . . . . . . . . .117
20-Pin SOIC — Case #751D-04 . . . . . . . . . . . . . . . . . . . . . . . . .117
20-Pin Cerdip — Case #732-03 . . . . . . . . . . . . . . . . . . . . . . . . . .118
1-spec_a
Specifications Maximum Ratings
MC68HC705J1A —Rev. 2.0
102 Specifications MOTOROLA
Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in Table 1. Keep Vin and Vout within the range VSS ≤(Vin
or Vout)≤ VDD. Connect unused inputs to the appropriate voltage level,
either VSS or VDD.
1. Voltages are referenced to VSS.
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to
5.0 V DC Electrical Characteristics
and
3.3 V DC
Electrical Characteristics
for guaranteed operating conditions.
Table 1. Maximum Ratings(1)
Rating Symbol Value Unit
Supply Voltage VDD –0.3 to +7.0 V
Current Drain per Pin
(Excluding VDD, VSS, and
PA4–PA7) I25mA
Input Voltage Vin VSS – 0.3 to VDD + 0.3 V
IRQ/VPP Pin VPP VSS – 0.3 to 2 x VDD +
0.3 V
Storage Temperature Range TSTG –65 to +150 °C
2-spec_a
Specifications
Operating Temperature Range
MC68HC705J1A — Rev. 2.0
MOTOROLA Specifications 103
Operating Temperature Range
Thermal Characteristics
1. P = plastic dual in-line package (PDIP)
2. DW = small outline integrated circuit (SOIC)
3. S = ceramic DIP (Cerdip)
4. C = extended temperature range
5. V = automotive temperature range
1. P = plastic dual in-line package (PDIP)
2. DW = small outline integrated circuit (SOIC)
3. S = ceramic DIP (Cerdip)
Table 2. Operating Temperature Range
Package Type Symbol Value
(TL to TH)Unit
MC68HC705J1AP(1), DW(2), S(3) TA0 to 70 °C
MC68HC705J1AC(4)P, CDW, CS TA–40 to +85 °C
MC68HC705J1AV(5)P, VDW, VS TA–40 to +105 °C
Table 3. Thermal Characteristics
Characteristic Symbol Value Unit
Thermal Resistance
MC68HC705J1AP(1)
MC68HC705J1ADW(2)
MC68HC705J1AS(3) θJA 60 °C/W
3-spec_a
Specifications Power Considerations
MC68HC705J1A —Rev. 2.0
104 Specifications MOTOROLA
Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
(1)
where:
TA= ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD= PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O PINT and can be neglected.
Ignoring PI/O, the relationship between PDand TJ is approximately:
(2)
Solving equations (1) and (2) for K gives:
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD(at equilibrium) for a
known TA. Using this value of K, the values of PDand TJcan be obtained
by solving equations (1) and (2) iteratively for any value of TA.
TJTAPDθ× JA
()+=
P
DK
T
J
273 °C+
----------------------------------=
KP
DT
A273°C+()θ
JA PD
()
2
×+×=
4-spec_a
Specifications
5.0 V DC Electrical Characteristics
MC68HC705J1A — Rev. 2.0
MOTOROLA Specifications 105
5.0 V DC Electrical Characteristics
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +105 °C unless otherwise noted.
2. Typical values at midpoint of voltage range, 25 °C only.
3. Run mode IDD is measured using external square wave clock source (fosc = 4.2 MHz); all inputs 0.2 V from rail; no dc loads;
less than 50 pF on all outputs; CL = 20 pF on OSC2.
4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured
with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V. Wait mode IDD is measured using external square wave
clock source (fosc = 4.2 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs; V IL = 0.2 V;
VIH = VDD – 0.2 V.
6. Only input high current rated to +1 µA on RESET.
7. The Rosc value selected for RC oscillator versions of this device is unspecified. SeeAppendix C for additional information.
Table 4. DC Electrical Characteristics (VDD = 5.0 Vdc)(1)
Characteristic Symbol Min Typ(2) Max Unit
Output Voltage
ILoad = 10.0 µA
ILoad = –10.0 µAVOL
VOH
—
VDD – 0.1 —
—0.1
—V
Output High Voltage
(ILoad = –0.8 mA) PA0–PA7, PB0–PB5 VOH VDD – 0.8 — — V
Output Low Voltage
(ILoad = 1.6 mA) PA0–PA3, PB0–PB5
(ILoad = 10.0 mA) PA4–PA7 VOL ——0.4
0.4 V
Input High Voltage
PA0–PA7, PB0–PB5, IRQ/VPP
, RESET, OSC1 VIH 0.7 × VDD —V
DD V
Input Low Voltage
PA0–PA7, PB0–PB5, IRQ/VPP
, RESET, OSC1 VIL VSS — 0.2 × VDD V
Supply Current
Run Mode(3)
Wait Mode(4)
Stop Mode(5)
25 °C
–40 to 105 °C
IDD
—
—
—
—
3.5
0.45
0.2
2.0
6.0
2.75
10
20
mA
mA
µA
µA
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB0–PB5 (Without Individual Pulldown Activated) IIL — 0.2 ±1µA
Input Pulldown Current
PA0–PA7, PB0–PB5 (With Individual Pulldown Activated) IIL 35 80 200 µA
Input Pullup Current
RESET IIL –15 –35 –85 µA
Input Current(6)
RESET, IRQ/VPP, OSC1 Iin — 0.2 ±1µA
Capacitance
Ports (As Inputs or Outputs)
RESET, IRQ/, OSC1, OSC2 Cout
Cin
—
——
—12
8pF
pF
Crystal/Ceramic Resonator Oscillator Mode Internal Resistor
OSC1 to OSC2(7) Rosc 1.0 2.0 3.0 MΩ
5-spec_a
Specifications 3.3 V DC Electrical Characteristics
MC68HC705J1A —Rev. 2.0
106 Specifications MOTOROLA
3.3 V DC Electrical Characteristics
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +105 °C unless otherwise noted.
2. Typical values at midpoint of voltage range, 25 °C only.
3. Run mode IDD is measured using external square wave clock source (fosc = 2.0 MHz); all inputs 0.2 V from rail; no dc loads;
less than 50 pF on all outputs; CL = 20 pF on OSC2.
4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured
with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V. Wait mode IDD is measured using external square wave
clock source (fosc = 2.0 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs; VIL = 0.2 V;
VIH = VDD – 0.2 V.
6. Only input high current rated to +1 µA on RESET.
7. The Rosc value selected for RC oscillator versions of this device is unspecified. SeeAppendix C for additional information.
Table 5. DC Electrical Characteristics (VDD = 3.3 Vdc)(1)
Characteristic Symbol Min Typ(2) Max Unit
Output Voltage
ILoad = 10.0 µA
ILoad = –10.0 µAVOL
VOH
—
VDD– 0.1 —
—0.1
—V
Output High Voltage
(ILoad = –0.2 mA) PA0–PA7, PB0–PB5 VOH VDD – 0.3 — — V
Output Low Voltage
(ILoad = 0.4 mA) PA0–PA3, PB0–PB5
(ILoad = 5.0 mA) PA4–PA7 VOL ——0.3
0.3 V
Input High Voltage
PA0–PA7, PB0–PB5, IRQ/VPP
, RESET, OSC1 VIH 0.7 × VDD —V
DD V
Input Low Voltage
PA0–PA7, PB0–PB5, IRQ/VPP
, RESET, OSC1 VIL VSS — 0.2 × VDD V
Supply Current
Run Mode(3)
Wait Mode(4)
Stop Mode(5)
25 °C
–40 to 105 °C
IDD
—
—
—
—
1.2
0.25
0.1
1.0
4.0
1.5
5
10
mA
mA
µA
µA
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB0–PB5 (Without Individual Pulldown Activated) IIL — 0.1 ±1µA
Input Pulldown Current
PA0–PA7, PB0–PB5 (With Individual Pulldown Activated) IIL 12 30 100 µA
Input Pullup Current
RESET IIL –10 –25 –45 µA
Input Current(6)
RESET, IRQ/VPP, OSC1 Iin — 0.1 ±1µA
Capacitance
Ports (As Inputs or Outputs)
RESET, IRQ/VPP
, OSC1, OSC2 Cout
Cin
—
——
—12
8pF
pF
Crystal/Ceramic Resonator Oscillator Mode Internal Resistor
OSC1 to OSC2(7) Rosc 1.0 2.0 3.0 MΩ
6-spec_a
Specifications
Driver Characteristics
MC68HC705J1A — Rev. 2.0
MOTOROLA Specifications 107
Driver Characteristics
Figure 1. PA0–PA7, PB0–PB5 Typical High-Side Driver Characteristics
Figure 2. PA0–PA3, PB0–PB5 Typical Low-Side Driver Characteristics
NOTES:
1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH)≤800 mV @ IOH = –0.8 mA.
2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH)≤300 mV @ IOH = –0.2 mA.
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
00−1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA
VDD = 5.0 V
IOH
VDD - VOH
85 °C
25 °C NOMINAL PROCESSING
−40 °C
25 °C NOMINAL PROCESSING
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
00−1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA
VDD = 3.3 V
IOH
VDD - VOH
85 °C
−40 °C
SEE NOTE 1
SEE NOTE 2
105 °C
105 °C
400 mV
350 mV
300 mV
250 mV
200 mV
150 mV
100 mV
50 mV
00 2.0 mA 4.0 mA 6.0 mA 8.0 mA 10.0 mA
VDD = 3.3 V
IOL
VOL
85 °C
–40 °C
25 °C NOMINAL PROCESSING
SEE NOTE 2
NOTES:
1. At VDD = 5.0 V, devices are specified and tested for VOL ≤400 mV @ IOL = 1.6 mA.
2. At VDD = 3.3 V, devices are specified and tested for VOL ≤300 mV @ IOL = 0.4 mA.
105 °C
400 mV
350 mV
300 mV
250 mV
200 mV
150 mV
100 mV
50 mV
00 2.0 mA 4.0 mA 6.0 mA 8.0 mA 10.0 mA
VDD = 5.0 V
IOL
VOL
85 °C
–40 °C
25 °C NOMINAL PROCESSING
SEE NOTE 2
105 °C
7-spec_a
Specifications Driver Characteristics
MC68HC705J1A —Rev. 2.0
108 Specifications MOTOROLA
Figure 3. PA4–PA7 Typical Low-Side Driver Characteristics
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
00 10 mA 20 mA 30 mA 40 mA 50 mA
VDD = 5.0 V
IOL
VOL
85 °C
25 °C NOMINAL PROCESSING
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
00 10 mA 20 mA 30 mA 40 mA 50 mA
IOL
85 °C
−40 °C
25 °C NOMINAL PROCESSING
VOL
SEE NOTE 2
SEE NOTE 1
NOTES:
1. At VDD = 5.0 V, devices are specified and tested for VOL ≤400 mV @ IOL = 10.0 mA.
2. At VDD = 3.3 V, devices are specified and tested for VOL ≤300 mV @ IOL = 5.0 mA.
105°C
105°C
−40 °C
VDD = 3.3 V
8-spec_a
Specifications
Typical Supply Currents
MC68HC705J1A — Rev. 2.0
MOTOROLA Specifications 109
Typical Supply Currents
Figure 4. Typical Operating IDD (25 °C)
6.0 mA
5.0 mA
4.0 mA
3.0 mA
2.0 mA
1.0 mA
00 1.0 MHz 2.0 MHz
3.0 V
4.5 V
3.6 V
5.5 V
SUPPLY CURRENT (IDD)
NOTES:
1. At VDD = 5.0 V, devices are specified and
tested for IDD ≤6.0 mA @ fOP = 2.1 MHz.
2. At VDD = 3.3 V, devices are specified and
tested for IDD ≤4.0 mA @ fOP = 1.0 MHz.
SEE NOTE 1
SEE NOTE 2
INTERNAL OPERATING FREQUENCY (fOP)
9-spec_a
Specifications Typical Supply Currents
MC68HC705J1A —Rev. 2.0
110 Specifications MOTOROLA
Figure 5. Typical Wait Mode IDD (25 °C)
700 µA
600 µA
500 µA
400 µA
300 µA
200 µA
100 µA
00 1.0 MHz 2.0 MHz
3.0 V
4.5 V
3.6 V
5.5 V
SUPPLY CURRENT (IDD)
INTERNAL OPERATING FREQUENCY (fOP)
NOTES:
1. At VDD = 5.0 V, devices are specified and
tested for IDD ≤2.75 mA @ fOP = 2.1 MHz.
2. At VDD = 3.3 V, devices are specified and
tested for IDD ≤1.5 mA @ fOP = 1.0 MHz.
SEE NOTE 1
SEE NOTE 2
10-spec_a
Specifications
EPROM Programming Characteristics
MC68HC705J1A — Rev. 2.0
MOTOROLA Specifications 111
EPROM Programming Characteristics
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +105 °C unless otherwise noted.
Table 6. EPROM Programming Characteristics(1)
Characteristic Symbol Min Typ Max Unit
Programming Voltage
IRQ/VPP VPP 16.0 16.5 17.0 V
Programming Current
IRQ/VPP IPP — 3.0 10.0 mA
Programming Time
Per Array Byte
MOR tEPGM
tMPGM
4
4—
——
—ms
ms
11-spec_a
Specifications Control Timing
MC68HC705J1A —Rev. 2.0
112 Specifications MOTOROLA
Control Timing
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +105 °C unless otherwise noted.
2. The maximum width tILIL or tILIH should not be more than the number of cycles it takes to
execute the interrupt service routine plus 19 tcyc or the interrupt service routine will be
re-entered.
Table 7. Control Timing (VDD = 5.0 Vdc)(1)
Characteristic Symbol Min Max Unit
Oscillator Frequency
Crystal Oscillator Option
External Clock Source fosc —
dc 4.2
4.2 MHz
Internal Operating Frequency (fosc ÷ 2)
Crystal Oscillator
External Clock fOP —
dc 2.1
2.1 MHz
Cycle Time (1 ÷fOP)t
cyc 476 — ns
RESET Pulse Width Low tRL 1.5 — tcyc
IRQ Interrupt Pulse Width Low
(Edge-Triggered) tILIH 1.5 — tcyc
IRQ Interrupt Pulse Width Low (Edge- and
Le vel- Triggered) tILIL 1.5 Note(2) tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered) tIHIL 1.5 — tcyc
PA0–PA3 Interrupt Pulse Width (Edge- and
Level-Triggered) tIHIH 1.5 Note(2) tcyc
OSC1 Pulse Width tOH, tOL 200 — ns
12-spec_a
Specifications
Control Timing
MC68HC705J1A — Rev. 2.0
MOTOROLA Specifications 113
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +105 °C unless otherwise noted.
2. The maximum width tILIL or tILIH should not be more than the number of cycles it takes to
execute the interrupt service routine plus 19 tcyc or the interrupt service routine will be
re-entered.
Table 8. Control Timing (VDD = 3.3 Vdc)(1)
Characteristic Symbol Min Max Unit
Oscillator Frequency
Crystal Oscillator Option
External Clock Source fosc —
dc 2.0
2.0 MHz
Internal Operating Frequency (fosc ÷ 2)
Crystal Oscillator
External Clock fOP —
dc 1.0
1.0 MHz
Cycle Time (1 ÷fOP)t
cyc 1000 — ns
RESET Pulse Width Low tRL 1.5 — tcyc
IRQ Interrupt Pulse Width Low
(Edge-Triggered) tILIH 1.5 — tcyc
IRQ Interrupt Pulse Width Low (Edge- and
Le vel- Triggered) tILIL 1.5 Note(2) tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered) tIHIL 1.5 — tcyc
PA0–PA3 Interrupt Pulse Width (Edge- and
Level-Triggered) tIHIH 1.5 Note(2) tcyc
OSC1 Pulse Width tOH, tOL 400 — ns
13-spec_a
Specifications Control Timing
MC68HC705J1A —Rev. 2.0
114 Specifications MOTOROLA
Figure 6. External Interrupt Timing
Figure 7. Stop Mode Recovery Timing
IRQ (INTERNAL)
tILIH
tILIL
tILIH
IRQ PIN
IRQ1
IRQn
.
.
.
tILIH
4064 tcyc
OSC (NOTE 1)
tRL
RESET
IRQ (NOTE 2)
IRQ (NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
NOTES:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
RESET OR INTERRUPT
VECTOR FETCH
07FE 07FE 07FE 07FE 07FE 07FF
(NOTE 4)
14-spec_a
Specifications
Control Timing
MC68HC705J1A — Rev. 2.0
MOTOROLA Specifications 115
Figure 8. Power-On Reset Timing
Figure 9. External Reset Timing
07FE
4064 tcyc
VDD
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
NOTES:
INTERNAL
DATA BUS
07FE 07FE 07FE 07FE 07FE 07FF
(NOTE 1)
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
NEW
PCH NEW
PCL
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
NOTES:
INTERNAL
DATA BUS
07FE 07FE 07FE 07FE 07FF NEW PC
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
NEW
PCH
tRL
NEW PC
NEW
PCL DUMMY OP
CODE
15-spec_a
Specifications Mechanical Specifications
MC68HC705J1A —Rev. 2.0
116 Specifications MOTOROLA
Mechanical Specifications
The MC68HC705J1A and the RC oscillator and high-speed option
devices described in Appendix A,Appendix B, and Appendix C are
available in the following packages:
• 738-03 — plastic dual in-line package (PDIP)
• 751D-04 — small outline integrated circuit (SOIC)
• 732-03 — ceramic DIP (Cerdip) (windowed)
The following figures show the latest packages at the time of this
publication. To make sure that you have the latest package
specifications, contact one of the following:
• Local Motorola Sales Office
• Motorola Mfax
– Phone 602-244-6609
– EMAIL rmfax0@email.sps.mot.com
• Worldwide Web (wwweb) at http://design-net.com
Follow Mfax or Worldwide Web on-line instructions to retrieve the current
mechanical specifications.
16-spec_a
Specifications
Mechanical Specifications
MC68HC705J1A — Rev. 2.0
MOTOROLA Specifications 117
20-Pin PDIP —
Case #738-03
20-Pin SOIC —
Case #751D-04
°
°
°
°
!
!
$
!
! ! #
! "
-A-
C
K
N
E
GF
D 20 PL
J 20 PL
L
M
-T-
110
1120
!
!
B
°
°
°
°
!
!
%
! !
! "
!"
$" !"
! "
!" #
!"
!! $
! $" ! !
-A-
-B- P 10 PL
110
1120
-T-
D 20 PL
K
C
R X 45°
M
!
G 18 PL
F
J
17-spec_a
Specifications Mechanical Specifications
MC68HC705J1A —Rev. 2.0
118 Specifications MOTOROLA
20-Pin Cerdip —
Case #732-03
NOTES:
1. LEADS WITHIN 0.010 DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
DIM MIN MAX
INCHES
A0.940 0.990
B0.260 0.295
C0.150 0.200
D0.015 0.022
F0.055 0.065
G0.100 BSC
H0.020 0.050
J0.008 0.012
K0.125 0.160
L0.300 BSC
M0 15
N0.010 0.040
__
A
20
110
11
B
FC
SEATING
PLANE
D
HGK
NJM
L
18-spec_a
MC68HC705J1A — Rev. 2.0
MOTOROLA MC68HRC705J1A 119
Appendix A
MC68HRC705J1A
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Typical Internal Operating Frequency for RC Oscillator Option . . . .120
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . .122
Introduction
Appendix A introduces the MC68HRC705J1A, a resistor-capacitor
(RC) oscillator mask option version of the MC68HC705J1A. All of the
information in
MC68HC705J1A Technical Data
Rev. 2.0 applies to the
MC68HRC705J1A with the exceptions given in this appendix.
RC Oscillator Connections
For greater cost reduction, the RC oscillator mask option allows the
configuration shown inFigure 1 to drive the on-chip oscillator. Mount the
RC components as close as possible to the pins for startup stabilization
and to minimize output distortion.
1-j-app_a
MC68HRC705J1A
MC68HC705J1A — Rev. 2.0
120 MC68HRC705J1A MOTOROLA
Figure 1. RC Oscillator Connections
NOTE:
The optional internal resistor isnot recommended for configurations that
use the RC oscillator connections as shown in Figure 1. For such
configurations, the oscillator internal resistor (OSCRES) bit of the mask
option register should be programmed to a logic 0.
Typical Internal Operating Frequency for RC Oscillator Option
Figure 2 shows typical internal operating frequencies at 25°C for the RC
oscillator option.
MCU
VDD
VSS
C1C2
OSC1
OSC2
R
OSC1
OSC2
R
2-j-app_a
MC68HRC705J1A
Typical Internal Operating Frequency for RC Oscillator Option
MC68HC705J1A — Rev. 2.0
MOTOROLA MC68HRC705J1A 121
Figure 2. Typical Internal Operating Frequency for
Various VDD at 25 °C — RC Oscillator Option Only
NOTE:
Tolerance for resistance is
±
50%. When selecting resistor size, consider
the tolerance to ensure that the resulting oscillator frequency does not
exceed the maximum operating frequency.
0.01
0.1
1
10
1 10 100 1000 10000
Resistance (kΩ)
Frequency (MHz)
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
3-j-app_a
MC68HRC705J1A
MC68HC705J1A — Rev. 2.0
122 MC68HRC705J1A MOTOROLA
Package Types and Order Numbers
1. Refer to Introduction (opening section of manual) for standard part ordering information.
2. P = plastic dual in-line package (PDIP)
3. C = extended temperature range
4. V = automotive temperature range
5. DW = small outline integrated circuit (SOIC)
6. S = ceramic dual in-line package (Cerdip)
Table 1. MC68HRC705J1A (RC Oscillator Option) Order Number s (1)
Package
Type Case
Outline Pin
Count Operating
Temperature Order Number
PDIP 738-03 20 0 to 70 °C
–40 to +85 °C
–40 to + 105 °C
MC68HRC705J1AP(2)
MC68HRC705J1AC(3)P
MC68HRC705J1AV(4)P
SOIC 751D-04 20 0 to 70 °C
–40 to +85 °C
–40 to + 105 °C
MC68HRC705J1ADW(5)
MC68HRC705J1ACDW
MC68HRC705J1AVDW
Cerdip 732-03 20 0 to 70 °C
–40 to +85 °C
–40 to + 105 °C
MC68HRC705J1AS(6)
MC68HRC705J1ACS
MC68HRC705J1AVS
4-j-app_a
MC68HC705J1A — Rev. 2.0
MOTOROLA MC68HSC705J1A 123
Appendix B
MC68HSC705J1A
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . .128
MC68HSC705J1A
DC Electrical Characteristics
MC68HC705J1A — Rev. 2.0
MOTOROLA MC68HSC705J1A 125
DC Electrical Characteristics
Table 1. DC Electrical Characteristics (VDD = 5 V)
Characteristic Symbol Min Typ Max Unit
Supply Current (fOP = 4.0 MHz)
Run
Wait IDD — 4.25
0.57 7.0
3.25 mA
Table 2. DC Electrical Characteristics (VDD = 3.3 V)
Characteristic Symbol Min Typ Max Unit
Supply Current (fOP = 2.1 MHz)
Run
Wait IDD — 1.4
0.28 4.25
1.75 mA
MC68HSC705J1A
MC68HC705J1A — Rev. 2.0
126 MC68HSC705J1A MOTOROLA
Typical Supply Currents
Figure 1. Typical High-Speed Operating IDD (25 °C)
6.0 mA
5.0 mA
4.0 mA
3.0 mA
2.0 mA
1.0 mA
00 1.0 MHz 2.0 MHz 3.0 MHz 4.0 MHz
3.0 V
4.5 V
3.6 V
5.5 V
SUPPLY CURRENT (IDD)
INTERNAL OPERATING FREQUENCY (fOP)
NOTES:
1. At VDD = 5.0 V, high-speed devices are specified and tested for
IDD ≤7.0 mA @ fOP = 4.0 MHz.
2. At VDD = 3.3 V, high-speed devices are specified and tested for
IDD ≤4.25 mA @ fOP = 2.1 MHz.
SEE NOTE 1
SEE NOTE 2
7.0 mA
MC68HSC705J1A
Typical Supply Currents
MC68HC705J1A — Rev. 2.0
MOTOROLA MC68HSC705J1A 127
Figure 2. Typical High-Speed Wait Mode IDD (25 °C)
700 µA
600 µA
500 µA
400 µA
300 µA
200 µA
100 µA
00 1.0 MHz 2.0 MHz 3.0 MHz 4.0 MHz
3.0 V
4.5 V
3.6 V
5.5 V
SUPPLY CURRENT (IDD)
INTERNAL OPERATING FREQUENCY (fOP)
NOTES:
1. At VDD = 5.0 V, high-speed devices are specified and tested for
IDD ≤3.25 mA @ fOP = 4.0 MHz.
2. At VDD = 3.3 V, high-speed devices are specified and tested for
IDD ≤1.75 mA @ fOP = 2.1 MHz.
SEE NOTE 1
SEE NOTE 2
MC68HSC705J1A
MC68HC705J1A — Rev. 2.0
128 MC68HSC705J1A MOTOROLA
Package Types and Order Numbers
1. Refer to Introduction (opening section of manual) for standard part ordering information.
2. P = plastic dual in-line package (PDIP)
3. C = extended temperature range
4. DW = small outline integrated circuit (SOIC)
5. S = ceramic dual in-line package (Cerdip)
Table 3. MC68HSC705J1A (High Speed) Order Numbers(1)
Package
Type Case
Outline Pin
Count Operating
Temperature Order Number
PDIP 738-03 20 0 to 70 °C
–40 to +85 °CMC68HSC705J1AP(2)
MC68HSC705J1AC(3)P
SOIC 751D-04 20 0 to 70 °C
–40 to +85 °CMC68HSC705J1ADW(4)
MC68HSC705J1ACDW
Cerdip 732-03 20 0 to 70 °C
–40 to +85 °CMC68HSC705J1AS(5)
MC68HSC705J1ACS
MC68HC705J1A — Rev. 2.0
MOTOROLA MC68HSR705J1A 129
Appendix C
MC68HSR705J1A
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
RC Oscillator Connections (External Resistor) . . . . . . . . . . . . . . . . .130
Typical Internal Operating Frequency at 25 °C for High-Speed
RC Oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
RC Oscillator Connections (No External Resistor) . . . . . . . . . . . . . .132
Typical Operating Frequency Versus Temperature (No External
Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . .134
MC68HSR705J1A
MC68HC705J1A — Rev. 2.0
130 MC68HSR705J1A MOTOROLA
Introduction
Appendix C introduces the MC68HSR705J1A, a high-speed version of
the MC68HRC705J1A. All of the information in
MC68HC705J1A
Technical Data
Rev. 2.0, Appendix A MC68HRC705J1A and
Appendix B MC68HSC705J1A applies to the MC68HSR705J1A with
the exceptions given in this appendix.
RC Oscillator Connections (External Resistor)
Refer to Appendix A MC68HRC705J1A for a description of the RC
oscillator connections with external resistor.
MC68HSR705J1A
Typical Internal Operating Frequency at 25 °C for High-Speed RC Oscillator Option
MC68HC705J1A — Rev. 2.0
MOTOROLA MC68HSR705J1A 131
Typical Internal Operating Frequency at 25 °C for High-Speed
RC Oscillator Option
Figure 1. Typical Internal Operating Frequency
at 25 °C for High-Speed RC Oscillator Option
For lower frequency operation characteristics refer to Appendix A
MC68HRC705J1A.
NOTE:
Tolerance for resistance is
±
50%. When selecting resistor size, consider
the tolerance to ensure that resulting oscillator frequency does not
exceed the maximum operating frequency.
1
10
110 100
Resistance (kΩ)
Frequency (MHz)
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
MC68HSR705J1A
MC68HC705J1A — Rev. 2.0
132 MC68HSR705J1A MOTOROLA
RC Oscillator Connections (No External Resistor)
For maximum cost reduction, the RC oscillator mask connections shown
in Figure 2 allow the on-chip oscillator to be driven with no external
components. This can be accomplished by programming the oscillator
internal resistor (OSCRES) bit in the mask option register to a logic 1.
When programming the OSCRES bit for the MC68HSR705J1A, an
internal resistor is selected which yields typical internal oscillator
frequencies as shown inFigure 3. The internal resistance for this device
is different than the resistance of the selectable internal resistor on the
MC68HC705J1A and the MC68HSC705J1A devices.
NOTE:
This option is not available on the ROM version of this device
(MC68HC05J1A).
Figure 2. RC Oscillator Connections (No External Resistor)
MCU
VDD
VSS
C1C2
OSC1
OSC2
OSC1
OSC2
R
(EXTERNAL CONNECTIONS LEFT OPEN)
MC68HSR705J1A
Typical Internal Operating Frequency Versus Temperature (No External Resistor)
MC68HC705J1A — Rev. 2.0
MOTOROLA MC68HSR705J1A 133
Typical Internal Operating Frequency Versus Temperature
(No External Resistor)
Figure 3. Typical Internal Operating Frequency Versus Temperature (OSCRES Bit = 1)
NOTE:
Due to process variations, operating voltages, and temperature
requirements, the internal resistance and tolerance are unspecified.
Typically for a given voltage and temperature, the frequency should not
vary more than
±
500 kHz. However, this data is not guaranteed. It is the
user’s responsibility to ensure that the resulting internal operating
frequency meets user’s requirements.
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
Frequency (MHz)
Temperature (°C)
3.00
2.50
2.00
1.50
1.00
0.50
0.00–50 0 50 100 150
MC68HSR705J1A
MC68HC705J1A — Rev. 2.0
134 MC68HSR705J1A MOTOROLA
Package Types and Order Numbers
1. Refer to Introduction (opening section of manual) for standard part ordering information.
2. P = plastic dual in-line package (PDIP)
3. C = extended temperature range
4. DW = small outline integrated circuit (SOIC)
5. S = ceramic dual in-line package (Cerdip)
Table 1.MC68HSR705J1A (High-Speed
RC Oscillator Option) Order Numbers(1)
Package
Type Case
Outline Pin
Count Operating
Temperature Order Number
PDIP 738-03 20 0 to 70 °C
–40 to +85 °CMC68HSR705J1AP(2)
MC68HSR705J1AC(3)P
SOIC 751D-04 20 0 to 70 °C
–40 to +85 °CMC68HSR705J1ADW(4)
MC68HSR705J1ACDW
Cerdip 732-03 20 0 to 70 °C
–40 to +85 °CMC68HSR705J1AS(5)
MC68HSR705J1ACS
MC68HC705J1A — Rev. 2.0
MOTOROLA Index 135
Index
A
accumulator register (A) . . . . . . . . . . . . . . .35
addressing modes . . . . . . . . . . . . . . . . . . .38
B
block diagram . . . . . . . . . . . . . . . . . . . . . . .11
brownout . . . . . . . . . . . . . . . . . . . . . . . . . . .82
C
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
case outlines . . . . . . . . . . . . . . . . . .117–118
central processor unit . . . . . . . . . . . . . . .9, 31
condition code register (CCR) . . . . . . . . . .36
COP watchdog . . . . . . . . . . . . . . . . . . . . . .66
COP in stop mode . . . . . . . . . . . . . . . . .84
COP in wait mode . . . . . . . . . . . . . . . . .84
COP register (COPR) . . . . . . . . . . . . . .83
COP reset . . . . . . . . . . . . . . . . . . . . . . .56
features . . . . . . . . . . . . . . . . . . . . . . . . .81
interrupts . . . . . . . . . . . . . . . . . . . . . . . .83
low-power modes . . . . . . . . . . . . . . . . .84
operation . . . . . . . . . . . . . . . . . . . . . . . .82
programmable option . . . . . . . . . . . . . .12
real-time interrupt rate selection table . .98
COPEN bit . . . . . . . . . . . . . . . . . . . . . . . . .29
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
features . . . . . . . . . . . . . . . . . . . . . . . . .32
instruction set . . . . . . . . . . . . . . . . . . . .38
instruction set summary . . . . . . . . . . . .46
instruction types . . . . . . . . . . . . . . . . . .41
opcode map . . . . . . . . . . . . . . . . . . . . .52
programming model . . . . . . . . . . . . . . .33
CPU registers
accumulator register (A) . . . . . . . . . . . .35
index register (X) . . . . . . . . . . . . . . . . .35
program counter register (PC) . . . . . . .36
stack pointer register (SP) . . . . . . . . . .35
D
data direction registers
data direction register A (DDRA) . . . . .73
data direction register B (DDRB) . . . . .77
data-retention mode . . . . . . . . . . . . . . . . . .68
E
ELAT bit . . . . . . . . . . . . . . . . . . . . . . . . . . .26
electrical specifications . . . . . . . . . . . . . .101
control timing . . . . . . . . . . . . . . .112–113
DC electrical characteristics . . . .105–106
driver characteristics . . . . . . . . . . . . . .107
maximum ratings . . . . . . . . . . . . . . . .102
MC68HSC705J1A (high-speed
option) . . . . . . . . . . . . . . .125–126
MC68HSR705J1A (high-speed RC
oscillator option) . . . . . . . . . . . .130
operating temperature range . . . . . . .103
port A . . . . . . . . . . . . . . . . . . . . . . .79–80
port B . . . . . . . . . . . . . . . . . . . . . . .79–80
power considerations . . . . . . . . . . . . .104
thermal characteristics . . . . . . . . . . . .103
thermal resistance . . . . . . . . . . . . . . .103
typical supply currents . . . . . . . . . . . .109
Index
MC68HC705J1A — Rev. 2.0
136 Index MOTOROLA
electrostatic damage . . . . . . . . . . . . . . . . .71
EPGM bit . . . . . . . . . . . . . . . . . . . . . . . . . .26
EPMSEC bit . . . . . . . . . . . . . . . . . . . . . . . .28
EPROM
EPROM security programmable option 12
EPROM/OTPROM . . . . . . . . . . . . . . . . . . .25
erasing . . . . . . . . . . . . . . . . . . . . . . . . .27
programming . . . . . . . . . . . . . . . . . .25, 27
programming characteristics . . . . . . . . .30
programming register (EPROG) . . . . . .26
external interrupt pins . . . . . . . . . . . . . . . . .20
external reset . . . . . . . . . . . . . . . . . . . . . . .55
H
H bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
I
I bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
index register (X) . . . . . . . . . . . . . . . . . . . .35
instruction set . . . . . . . . . . . . . . . . . . . . . . .38
addressing modes . . . . . . . . . . . . . . . . .38
instruction set summary . . . . . . . . . . . .46
instruction types . . . . . . . . . . . . . . . . . .41
opcode map . . . . . . . . . . . . . . . . . . . . .52
instruction types . . . . . . . . . . . . . . . . . . . . .41
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .53
external interrupt . . . . . . . . . . . . . . .56–57
external interrupt logic . . . . . . . . . . . . . .57
external interrupt module . . . . . . . . . . .86
external interrupt timing . . . . . . . . .58, 92
external interrupt vector . . . . . . . . . . . .59
features . . . . . . . . . . . . . . . . . . . . . . . . .85
interrupt flowchart . . . . . . . . . . . . . .62, 88
interrupt processing . . . . . . . . . . . . . . .59
interrupt sources . . . . . . . . . . . . . . . . . .56
interrupt stacking order . . . . . . . . . . . . .60
IRQ module block diagram . . . . . . . . . .87
IRQ status and control register (ISCR) .91
IRQ/VPP pin . . . . . . . . . . . . . . . . . . .86, 89
operation . . . . . . . . . . . . . . . . . . . . . . . .86
optional external interrupts . . . . . . . . . .90
pin sensitivity selection . . . . . . . . . . . . .89
pin triggering option . . . . . . . . . . . . . . .12
port A external interrupts
programmable option . . . . . . . . .12
real-time interrupt rate selection table .98
real-time interrupts . . . . . . . . . . . . . . . .59
reset/interrupt vector addresses . . . . . .61
software interrupt . . . . . . . . . . . . . . . . .56
software interrupt vector . . . . . . . . . . . .59
sources . . . . . . . . . . . . . . . . . . . . . . . . .56
timer interrupt vector . . . . . . . . . . . . . . .59
timer interrupts . . . . . . . . . . . . . . . .59, 96
timer overflow . . . . . . . . . . . . . . . . . . . .59
IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . .56
IRQ/VPP pin . . . . . . . . . . . . . . . . . .20, 82, 89
IRQE bit . . . . . . . . . . . . . . . . . . . . . . . . . . .91
IRQF bit . . . . . . . . . . . . . . . . . . . . . . . . . . .91
IRQR bit . . . . . . . . . . . . . . . . . . . . . . . . . . .91
L
LEVEL bit . . . . . . . . . . . . . . . . . . . . . . . . . .29
literature distribution centers . . . . . . . . . .141
low-power modes . . . . . . . . . . . . . . . . .63–64
COP timeout period . . . . . . . . . . . . . . .67
data-retention mode . . . . . . . . . . . .64, 68
effects on clock generation . . . . . . . . . .65
effects on COP . . . . . . . . . . . . . . . . . . .66
effects on CPU . . . . . . . . . . . . . . . . . . .66
effects on EPROM/OTPROM . . . . . . . .68
effects on timer . . . . . . . . . . . . . . . . . . .67
exiting stop mode . . . . . . . . . . . . . . . . .64
exiting wait mode . . . . . . . . . . . . . . . . .65
flowchart (STOP/HALT/WAIT) . . . . . . .70
halt mode . . . . . . . . . . . . . . . . . . . . . . .64
STOP instruction flowchart . . . . . . . . . .70
stop mode . . . . . . . . . . . . . . . . . . . .64, 66
stop recovery timing . . . . . . . . . . . . . . .69
Index
MC68HC705J1A — Rev. 2.0
MOTOROLA Index 137
timer . . . . . . . . . . . . . . . . . . . . . . . . . .100
timing of stop mode recovery . . . . . . . .69
wait mode . . . . . . . . . . . . . . . . . . . . . . .64
M
mask option register (MOR) . . . . . . . . . . . .27
programming . . . . . . . . . . . . . . . . . . . . .28
MC68HC705J1A
features . . . . . . . . . . . . . . . . . . . . . . . . .10
MC68HRC705J1A (RC oscillator option) .119
operating frequency . . . . . . . . . . . . . .121
order numbers . . . . . . . . . . . . . . . . . . .122
package types . . . . . . . . . . . . . . . . . . .122
RC oscillator connections . . . . . .119–120
MC68HSC705J1A (high-speed
option) . . . . . . . . . . . . . . . . . .123–124
DC electrical characteristics . . . . . . . .125
order numbers . . . . . . . . . . . . . . . . . . .128
package types . . . . . . . . . . . . . . . . . . .128
typical operating current . . . . . . . . . . .126
typical wait mode current . . . . . . . . . .127
MC68HSR705J1A (high-speed RC oscillator
option) . . . . . . . . . . . . . . . . . . . . . .130
operating frequencies
(with OSCRES bit set) . . . . . . .133
operating frequency . . . . . . . . . . . . . .131
order numbers . . . . . . . . . . . . . . . . . . .134
package types . . . . . . . . . . . . . . . . . . .134
RC oscillator . . . . . . . . . . . . . . . . . . . .132
RC oscillator connections . . . . . . . . . .132
mechanical specifications
Cerdip . . . . . . . . . . . . . . . . . . . . . . . . .118
package types . . . . . . . . . . . . . . . . . . .116
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . .117
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . .117
memory . . . . . . . . . . . . . . . . . . . . . . . . . . .21
EPROM/OTPROM . . . . . . . . . . . . . . . .25
EPROM/OTPROM programming . . . . .25
features . . . . . . . . . . . . . . . . . . . . . . . . .21
I/O register summary . . . . . . . . . . . . . .23
mask option register . . . . . . . . . . . . . . .27
memory map . . . . . . . . . . . . . . . . . . . . .22
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . .24
MPGM bit . . . . . . . . . . . . . . . . . . . . . . . . . .26
N
N bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
O
opcode map . . . . . . . . . . . . . . . . . . . . . . . .52
options (mask) . . . . . . . . . . . . . . . . . . . . . .27
options (programmable) . . . . . . . . . . . . . . .12
ordering information
literature distribution centers . . . . . . .141
MC68HRC705J1A (RC oscillator
option) . . . . . . . . . . . . . . . . . . .122
MC68HSC705J1A (high-speed
option) . . . . . . . . . . . . . . . . . . .128
MC68HSR705J1A (high-speed RC
oscillator option) . . . . . . . . . . . .134
Mfax . . . . . . . . . . . . . . . . . . . . . . . . . .142
order numbers . . . . . . .12, 122, 128, 134
Web server . . . . . . . . . . . . . . . . . . . . .142
Web site . . . . . . . . . . . . . . . . . . . . . . .142
OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . .15
OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . .15
oscillator
crystal oscillator internal resistor option 12
delay counter programmable option . . .12
on-chip oscillator stabilization delay . . .54
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
OSCRES bit . . . . . . . . . . . . . . . . . . . . . . . .29
P
PA0–PA3 pins . . . . . . . . . . . . . . . . . . . . . .86
package dimensions
Cerdip . . . . . . . . . . . . . . . . . . . . . . . . .118
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . .117
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . .117
package types . . . . . . . . . . . . . . . . . . . . . .12
Index
MC68HC705J1A — Rev. 2.0
138 Index MOTOROLA
pin assignments . . . . . . . . . . . . . . . . . . . . .14
pin functions . . . . . . . . . . . . . . . . . . . . . . . .15
PIRQ bit . . . . . . . . . . . . . . . . . . . . . . . . . . .29
port A
data direction register (DDRA) . . . . . . .73
data register (PORTA) . . . . . . . . . . . . .73
electrical characteristics . . . . . . . . .79–80
I/O circuitry . . . . . . . . . . . . . . . . . . . . . .74
I/O pin interrupts (PA0–PA3) . . . . . . . .76
LED drive capability . . . . . . . . . . . . . . .76
pin operation . . . . . . . . . . . . . . . . . . . . .75
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
pulldown register (PDRA) . . . . . . . . . . .75
port B
data direction register (DDRB) . . . . . . .77
electrical characteristics . . . . . . . . .79–80
I/O circuitry . . . . . . . . . . . . . . . . . . . . . .77
pin operation . . . . . . . . . . . . . . . . . . . . .78
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
port B data register (PORTB) . . . . . . . .76
pulldown register (PDRB) . . . . . . . . . . .78
power-on reset . . . . . . . . . . . . . . . . . . . . . .54
program counter (PC) . . . . . . . . . . . . . . . . .36
programmable options . . . . . . . . . . . . . . . .12
programming model (CPU) . . . . . . . . . . . .33
pulldown register A (PDRA) . . . . . . . . . . . .75
pulldown register B (PDRB) . . . . . . . . . . . .78
pulldown resistors
programmable option . . . . . . . . . . . . . .12
R
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
stack RAM . . . . . . . . . . . . . . . . . . . . . . .59
registers
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . .34
I/O register summary . . . . . . . . . . . . . .23
parallel I/O port register summary . . . . .72
timer I/O register summary . . . . . . .87, 95
RESET pin . . . . . . . . . . . . . . . . . . . . . .19, 55
resets . . . . . . . . . . . . . . . . . . . . . . . . . .53–54
COP register (COPR) . . . . . . . . . . . . . .56
COP watchdog reset . . . . . . . . . . . . . .56
external reset . . . . . . . . . . . . . . . . . . . .55
external reset timing . . . . . . . . . . . . . . .55
illegal address . . . . . . . . . . . . . . . . . . . .56
power-on reset (POR) . . . . . . . . . . . . .54
power-on reset timing . . . . . . . . . . . . . .55
reset sources . . . . . . . . . . . . . . . . . . . .54
reset/interrupt vector addresses . . . . . .61
resets and interrupts . . . . . . . . . . . . . . . . .53
resistors (pulldown) programmable
option . . . . . . . . . . . . . . . . . . . . . . .12
RT1, RT0 bits . . . . . . . . . . . . . . . . . . . . . . .98
RTIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . .97
RTIF bit . . . . . . . . . . . . . . . . . . . . . . . . . . .97
RTIFR bit . . . . . . . . . . . . . . . . . . . . . . . . . .98
S
Schmitt trigger . . . . . . . . . . . . . . . .20, 89–90
SOSCD bit . . . . . . . . . . . . . . . . . . . . . . . . .28
stack pointer register (SP) . . . . . . . . . . . . .35
STOP instruction . . . . . . . . . . . . . .65, 84, 91
stop mode . . . . . . . . . . . . . . . . . . . . . .66, 84
effect on COP watchdog . . . . . . . . . . . .84
effects on timer . . . . . . . . . . . . . . . . . .100
STOP instruction flowchart . . . . . . . . . .70
stop recovery timing . . . . . . . . . . . . . . .69
stop/halt mode programmable option . . . .12
SWAIT bit . . . . . . . . . . . . . . . . . . . . . . . . . .29
SWPDI bit . . . . . . . . . . . . . . . . . . . . . . . . .29
Index
MC68HC705J1A — Rev. 2.0
MOTOROLA Index 139
T
timer
block diagram . . . . . . . . . . . . . . . . . . . .94
features . . . . . . . . . . . . . . . . . . . . . . . . .93
I/O register summary . . . . . . . . . . .87, 95
I/O registers . . . . . . . . . . . . . . . . . . . . .96
interrupts . . . . . . . . . . . . . . . . . . . . .59, 96
low-power modes . . . . . . . . . . . . . . . .100
operation . . . . . . . . . . . . . . . . . . . . . . . .95
real-time interrupt rate selection . . . . . .98
timer counter register . . . . . . . . . . . . . .99
timer interrupt vector . . . . . . . . . . . . . . .59
timer status and control register
(TSCR) . . . . . . . . . . . . . . . . . . . .97
TOF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
TOFR bit . . . . . . . . . . . . . . . . . . . . . . . . . . .98
TOIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . .97
V
VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
VSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
W
WAIT instruction . . . . . . . . . . . . . . .65, 84, 91
wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .84
effects on timer . . . . . . . . . . . . . . . . . .100
Web server . . . . . . . . . . . . . . . . . . . . . . . .142
Web site . . . . . . . . . . . . . . . . . . . . . . . . . .142
Z
Z bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Index
MC68HC705J1A — Rev. 2.0
140 Index MOTOROLA
MC68HC705J1A — Rev. 2.0
MOTOROLA Literature Updates 141
Literature Updates
This document contains the latest data available at publication time. For
updates, contact one of the centers listed below:
Literature Distribution Centers
Order literature by mail or phone.
USA/Europe Motorola Literature Distribution
P.O. Box 20912
Phoenix, Arizona 85036
Phone 1 800 441-2447 or 602 303-5454
Japan Nippon Motorola Ltd.
Tatsumi-SPD-JLDC
Toshikatsu Otsuki
6F Seibu-Butsuryu Center
3-14-2 Tatsumi Koto-Ku
Tokyo 135, Japan
Phone 03-3521-8315
Hong Kong Motorola Semiconductors H.K. Ltd.
8B Tai Ping Industrial Park
51 Ting Kok Road
Tai Po, N.T., Hong Kong
Phone 852-26629298
Literature Updates
MC68HC705J1A — Rev. 2.0
142 Literature Updates MOTOROLA
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RMFAX0@email.sps.mot.com
TOUCH-TONE 602-244-6609
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Obtain a fax of complete, easy-to-use Mfax instructions by entering your
FAX number and then pressing the 1 key.
Motorola SPS World Marketing World Wide Web Server
Use the Internet to access Motorola’s World Wide Web server. Use the
following URL:
http://Design-net.com
CSIC Microcontroller Division’s Web Site
Directly access the CSIC Microcontroller Division’s web site with the
following URL:
http://Design-net.com/csic/CSIC_home.html
MC68HC705J1A Rev. 2.0
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