LTC7851/LTC7851-1 Quad Output, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing FEATURES DESCRIPTION Operates with Power Blocks, DrMOS or External Gate Drivers and MOSFETs nn Voltage Mode Control with Accurate Current Sharing nn 0.75% 0.6V Voltage Reference nn Quad Differential Output Voltage Sense Amplifiers nn Multiphase Capability nn Phase-Lockable Fixed Frequency 250kHz to 2.25MHz nn Lossless Current Sensing Using Inductor DCR or Precision Current Sensing with Sense Resistor or DrMOS with Integrated Current Sensing nn V CC Range: 3V to 5.5V nn V OUT Range: 0.6V to VCC - 0.5V nn Power Good Output Voltage Monitor nn Output Voltage Tracking Capability with Soft-Start nn Available in 58-Lead 5mm x 9mm QFN Package The LTC(R)7851/LTC7851-1 are quad output multiphase synchronous step-down switching regulator controllers that employ a constant frequency voltage mode architecture. They maintain excellent current balance between channels when paralleled with their internal current sharing loop. Lossless DCR or a low value RSENSE is used for output current sensing. Multiple LTC7851/LTC7851-1 devices can be used for high phase count operation. nn APPLICATIONS A very low offset, high bandwidth error amplifier, combined with remote output voltage sensing, provides excellent transient response and output regulation. The LTC7851/ LTC7851-1 operates with a VCC supply voltage from 3V to 5.5V and is designed for step-down conversion with VIN from 3V to 27V* and produces an output voltage from 0.6V to VCC - 0.5V. The LTC7851-1 is identical to the LTC7851 except it has a lower current sense amplifier gain, making it ideal for DrMOS devices with internal current sense. High Current Distributed Power Systems nn DSP, FPGA and ASIC Supplies nn Datacom, Telecom and Computing Systems nn All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 6144194, 5055767. *See Note 5. TYPICAL APPLICATION Dual-Output Converter: 1V/90A and 1.5V/30A with DrMOS VIN 7V TO 14V VINSNS 0.25H 0.25H DrMOS PWM3 3.57k 0.22F VOUT2 1.5V/30A 1F PINS NOT USED IN THIS CIRCUIT: CLKIN CLKOUT VSNSP2 VSNSP3 VSNSN2 VSNSN3 PGOOD2 PGOOD3 RUN4 IAVG4 TRACK/SS4 3.57k 0.22F ISNS2P ISNS2N FB2,3 100k 0.25H 330F x3 + 100F x2 3.57k 0.22F 3.3nF 332 PGOOD1 PWM1 TRACK/SS1 TRACK/SS2 TRACK/SS3 0.25H DrMOS 3.57k 0.22F ISNS4P ISNS1P ISNS4N ISNS1N VSNSP4 VSNSP1 VSNSN4 VSNSN1 VSNSOUT4 VSNSOUT1,2,3 6.04k 10k 2.2nF VCC 100k PGOOD4 PWM4 RUN1 RUN2 RUN3 DrMOS 15k 10k DrMOS LTC7851 ISNS3P ISNS3N VCC VCC 5V PWM2 100pF 30.9k 42.2k COMP4 FB4 FREQ ILIM4 COMP1,2,3 FB1 IAVG1,2,3 ILIM1,2,3 SGND 100F x6 + 330F x9 VOUT1 1.0V/90A 10k 4.02k 10k 100pF 42.2k 2.2nF 3.3nF 15k 332 100pF 7851 TA01 Rev A Document Feedback For more information www.analog.com 1 LTC7851/LTC7851-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PGOOD1 PWM2 RUN2 PWM1 RUN1 CLKOUT CLKIN TOP VIEW FREQ TRACK/SS1 VCC Voltage ............................................... -0.3V to 6.5V VINSNS Voltage ......................................... -0.3V to 30V RUN1, RUN2, RUN3, RUN4 Voltage .............................-0.3V to (VCC+0.3V) ISNS1P, ISNS1N, ISNS2P, ISNS2N........................ -0.3V to (VCC + 0.1V) ISNS3P, ISNS3N, ISNS4P, ISNS4N........................ -0.3V to (VCC + 0.1V) All Other Pin Voltages....................-0.3V to (VCC + 0.3V) Operating Junction Temperature Range.... -40 to 125C Storage Temperature Range................... -65C to 150C FB1 (Note 1) 58 57 56 55 54 53 52 51 50 49 COMP1 1 48 ILIM1 VSNSP1 2 47 IAVG1 VSNSN1 3 46 ISNS1P VSNSOUT1 4 45 ISNS1N SGND 5 44 ISNS2N VSNSOUT2 6 43 ISNS2P VSNSN2 7 42 IAVG2 VSNSP2 8 41 ILIM2 COMP2 9 40 TRACK/SS2 59 SGND FB2 10 39 VINSNS VCC 11 38 PGOOD2 FB3 12 37 TRACK/SS3 COMP3 13 36 ILIM3 VSNSP3 14 35 IAVG3 VSNSN3 15 34 ISNS3P VSNSOUT3 16 33 ISNS3N VSNSOUT4 17 32 ISNS4N VSNSN4 18 31 ISNS4P 30 IAVG4 VSNSP4 19 ILIM4 PGOOD3 RUN3 PWM3 PWM4 PGOOD4 RUN4 TRACK/SS4 FB4 COMP4 20 21 22 23 24 25 26 27 28 29 UHH PACKAGE 58-LEAD (5mm x 9mm) PLASTIC QFN LEAD PITCH 0.4mm JA = 49C/W, JC = 15.5C/W EXPOSED PAD (PIN 59) IS SGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC7851EUHH#PBF LTC7851EUHH#TRPBF 7851 58-LEAD (5mm x 9mm) Plastic QFN -40C to 125C LTC7851IUHH#PBF LTC7851IUHH#TRPBF 7851 58-LEAD (5mm x 9mm) Plastic QFN -40C to 125C LTC7851EUHH-1#PBF LTC7851EUHH-1#TRPBF 78511 58-LEAD (5mm x 9mm) Plastic QFN -40C to 125C LTC7851IUHH-1#PBF LTC7851IUHH-1#TRPBF 78511 58-LEAD (5mm x 9mm) Plastic QFN -40C to 125C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 Rev A For more information www.analog.com LTC7851/LTC7851-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VCC = 5V, VRUN1,2,3,4 = 5V, VFREQ = VCLKIN = 0V, VFB = 0.6V, fOSC = 600kHz, unless otherwise specified. SYMBOL PARAMETER CONDITIONS VINSNS VIN Sense Range VCC = 5V (Note 5) VCC VCC Voltage Range VOUT VOUT Voltage Range IQ Input Voltage Supply Current Normal Operation Shutdown Mode UVLO Limited by ISNSP/N Common Mode Voltage Range (Note 3) MIN l RUN Input Threshold VRUN Rising VRUN Hysteresis IRUN RUN Input Pull-Up Current VRUN = 2.4V VUVLO Undervoltage Lockout Threshold VCC Rising VCC Hysteresis ISS Soft-Start Pin Output Current VSS = 0V tSS Internal Soft-Start Time VFB Regulated Feedback Voltage MAX V 3 5.5 V l 0.6 VCC - 0.5 V 60 16 1.95 2.25 250 110 100 mA A mA 2.45 V mV 1.5 l 100 1.5 2.5 A 3 3.5 1.5 -20C to 85C -40C to 125C UNITS 27 l VRUN1,2,3,4 = 5V VRUN1,2,3,4 = 0V VCC < VUVLO VRUN TYP 3 l 595.5 594 V mV A ms 600 600 604.5 606 mV mV 0.05 0.2 %/V VFB/VCC Regulated Feedback Voltage Line Dependence 3.0V < VCC < 5.5V ILIMIT ILIM Pin Output Current VILIM = 0.8V 18.5 20 21.5 A VFB(OV) PGOOD/VFB Overvoltage Threshold VFB Falling VFB Rising 650 645 660 670 mV mV VFB(UV) PGOOD/VFB Undervoltage Threshold VFB Falling VFB Rising VPGOOD(ON) PGOOD Pull-Down Resistance IPGOOD(OFF) PGOOD Leakage Current VPGOOD = 5V tPGOOD PGOOD Delay VPGOOD High to Low IFB FB Pin Input Current VFB = 600mV IOUT COMP Pin Output Current Sourcing Sinking AV(OL) Open Loop Voltage Gain SR Slew Rate f0dB COMP Unity-Gain Bandwidth Power Good 530 540 555 550 mV mV 15 60 2 A 30 s Error Amplifier -100 100 nA 1 4 mA mA 75 dB (Note 4) 45 V/s (Note 4) 40 MHz Differential Amplifier VDA VSNSP Accuracy Measured in a Servo Loop with EA in Loop 0C to 85C Measured in a Servo Loop with EA in Loop -40C to 125C l 594 600 606 mV 592 600 608 mV IDIFF+ Input Bias Current VSNSP = 600mV fOdb DA Unity-Gain Bandwidth (Note 4) -100 40 100 MHz nA IOUT(SINK) Maximum Sinking Current VSNSOUT = 600mV 100 A IOUT(SOURCE) Maximum Sourcing Current VSNSOUT = 600mV 500 A Rev A For more information www.analog.com 3 LTC7851/LTC7851-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VCC = 5V, VRUN1,2,3,4 = 5V, VFREQ = VCLKIN = 0V, VFB = 0.6V, fOSC = 600kHz, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Current Sense Amplifier VISENSE(MAX) Maximum Differential Current Sense Voltage (VISNSP - VISNSN) LTC7851 50 mV LTC7851-1 150 mV AV(ISENSE) Voltage Gain LTC7851 VCM(ISENSE) Input Common Mode Range IISENSE SENSE Pin Input Current VCM = 1.5V VIAVG Zero Current IAVG Pin Voltage VISNSP = VISNSN VOS Current Sense Input Referred Offset LTC7851 l -1 1 mV LTC7851-1 l -3 3 mV l l 520 0.85 680 1.15 kHz MHz 20 LTC7851-1 V/V 4 -0.3 V/V VCC - 0.5 100 V nA 500 mV Oscillator and Phase-Locked Loop fOSC Oscillator Frequency VCLKIN = 0V VCLKIN = 5V VFREQ = 0V VFREQ = 5V RFREQ < 24.9k RFREQ = 30.9k RFREQ = 36.5k RFREQ = 48.7k RFREQ = 64.9k RFREQ = 82.5k RFREQ = 88.7k 600 1 180 370 570 970 1.4 1.9 2.1 Maximum Frequency kHz kHz kHz kHz MHz MHz MHz 3 MHz Minimum Frequency MHz 21.5 A IFREQ FREQ Pin Output Current VFREQ = 0.8V 18.5 tCLKIN(HI) CLKIN Pulse Width High VCLKIN = 0V to 5V 100 ns tCLKIN(LO) CLKIN Pulse Width Low VCLKIN = 0V to 5V 100 ns RCLKIN CLKIN Pull Up Resistance 20 k VCLKIN CLKIN Input Threshold VCLKIN Falling VCLKIN Rising 0.8 2 V V VFREQ FREQ Input Threshold VCLKIN = 0V VFREQ Falling VFREQ Rising 1.5 2.5 V V VOL(CLKOUT) CLKOUT Low Output Voltage ILOAD = -500A 0.2 V VOH(CLKOUT) CLKOUT High Output Voltage ILOAD = 500A VCC - 0.2 2 - 1 3 - 1 4 - 1 CLKOUT - 1 20 0.25 V Channel 2 to Channel 1 Phase Relationship 180 Deg Channel 3 to Channel 1 Phase Relationship 90 Deg Channel 4 to Channel 1 Phase Relationship 270 Deg CLKOUT to Channel 1 Phase Relationship 45 Deg PWM Output PWM PWM Output High Voltage ILOAD = 500A l PWM Output Low Voltage ILOAD = -500A l VCC - 0.5 V PWM Output Current in Hi-Z State PWM Maximum Duty Cycle 4 91.5 0.5 V 5 A % Rev A For more information www.analog.com LTC7851/LTC7851-1 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7851/LTC7851-1 are tested under pulsed load conditions such that TJ TA. The LTC7851E/LTC7851E-1 are guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7851I/LTC7851I-1 are guaranteed over the -40C to 125C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD * 49C/W) Note 3: The maximum VOUT range is limited by the current sense pins (ISNSP/ISNSN) common mode voltage range. See the Current Sensing in the Applications Information section. Note 4: Guaranteed by design. Note 5: The Absolute Maximum Voltage Rating for the VINSNS voltage limits the Maximum VIN Voltage. For operation with a VIN range higher than 27V, the VINSNS pin must be connected through a resistor divider from VIN to limit the maximum VINSNS voltage to less than 27V. TYPICAL PERFORMANCE CHARACTERISTICS Load Step Transient Response (Single Phase Using FDMF5820DC DrMOS) Load Step Transient Response (2-Phase Using FDMF58200C DrMOS) ILOAD 25A/DIV ILOAD 20A/DIV 0A TO 15A TO 0A IL1 10A/DIV IL 20A/DIV VOUT AC-COUPLED 50mV/DIV IL2 10A/DIV VIN = 12V VOUT = 1.8V fSW = 400kHz VOUT AC-COUPLED 50mV/DIV 7851 G01 50s/DIV 7851 G02 20s/DIV VIN = 12V VOUT = 1.2V fSW = 400kHz ILOAD = 10A TO 30A TO 10A Load Step Transient Response (4-Phase Using FDMF5820DC DrMOS) Load Step Transient Response (3-Phase Using FDMF5820DC DrMOS) ILOAD 50A/DIV 0A TO 50A TO 0A IL1 20A/DIV IL2 20A/DIV VOUT AC-COUPLED 20mV/DIV IL3 20A/DIV VIN = 12V VOUT = 1.2V fSW = 400kHz VOUT AC-COUPLED 50mV/DIV 40s/DIV VIN = 12V VOUT = 1.2V fSW = 400kHz ILOAD = 0A TO 38A TO 0A 7851 G03 40s/DIV 7851 G04 Rev A For more information www.analog.com 5 LTC7851/LTC7851-1 TYPICAL PERFORMANCE CHARACTERISTICS Line Step Transient Response (2-Phase Using FDMF5820DC DrMOS) EFFICIENCY (%) IL1 10A/DIV IL2 10A/DIV VOUT 50mV/DIV AC-COUPLED VOUT = 1.2V ILOAD = 15A 100 100 90 90 80 80 70 70 EFFICIENCY (%) VIN 10V/DIV 7V TO 14V 60 50 40 30 20 7851 G05 20s/DIV Efficiency vs Load Current (4-Phase Using D12S1R8130A Power Block) Efficiency vs Load Current (2-Phase Using D12S1R8130A Power Block) fSW = 400kHz VIN = 12V VOUT = 1.2V 10 0 0 10 20 30 40 50 LOAD CURRENT (A) 60 70 60 50 40 30 10 0 3681 G06 Feedback Voltage VFB vs Temperature 602 REGULATED VFB VOLTAGE (mV) REGULATED VFB VOLTAGE (mV) 602 601 600 599 598 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 0 20 40 60 80 100 LOAD CURRENT (A) 120 140 3681 G07 Start-Up Response (2-Phase Using FDMF5820DC DrMOS) Regulated VFB vs Supply Voltage RUN 5V/DIV 601 IL1 20A/DIV IL2 20A/DIV 600 VOUT 1V/DIV 599 CSS = 0.1F 5ms/DIV 598 3 3.5 4 4.5 SUPPLY VOLTAGE (V) 5 7851 G08 7851 G10 VIN = 12V VOUT = 1.2V RLOAD = 0.037 fSW = 400kHz 5.5 7851 G09 Start-Up Response (4-Phase Using D12S1R8130A Power Block) Start-Up Response (3-Phase Using FDMF5820DC DrMOS) RUN 5V/DIV IL1 20A/DIV IL2 20A/DIV IL3 20A/DIV ILOAD 50A/DIV VOUT 1V/DIV VOUT 1V/DIV Coincident Tracking (Single Phase Using FDMF5820DC DrMOS) VIN = 12V VOUT = 1.8V RUN 4V/DIV TRACK/SS 500mV/DIV INTERNAL SOFT-START RLOAD = 27m VIN = 12V VOUT = 1.2V 6 fSW = 400kHz VIN = 12V VOUT = 1.2V Airflow 400LFM 20 400s/DIV VOUT 1V/DIV RLOAD = 0.01 fSW = 400kHz INTERNAL SOFT-START 7851 G11 VIN = 12V VOUT = 1.2V RLOAD = 0.017 fSW = 400kHz 500s/DIV 7851 G12 2ms/DIV 7851 G13 Rev A For more information www.analog.com LTC7851/LTC7851-1 TYPICAL PERFORMANCE CHARACTERISTICS Initial 7-Cycle Nonsynchronous Start-Up (Single Phase Using FDMF5820DC DrMOS) Start-Up Response Into a 300mV Prebiased Output (Single Phase Using FDMF5820DC DrMOS) IL 5A/DIV Start-Up Into a Short (2-Phase Using FDMF5820DC DrMOS) TRACK/SS 1V/DIV IL 10A/DIV PWM 5V/DIV IL1 50A/DIV PWM 5V/DIV VOUT 500mV/DIV VIN = 12V VOUT = 1.8V 10s/DIV IL2 50A/DIV VOUT 1V/DIV VIN = 12V VOUT = 1.8V 7851 G14 IL1 20A/DIV IL2 20A/DIV VIN = 12V VOUT = 1.2V 7851 G17 50s/DIV Oscillator Frequency vs RFREQ Frequency < 1MHz 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 Oscillator Frequency vs RFREQ Frequency 1MHz OSCILLATOR FREQUENCY (kHz) VOUT 1V/DIV OSCILLATOR FREQUENCY (kHz) TRACK/SS1 2V/DIV 24 27 30 33 36 39 42 45 48 51 54 RFREQ (k) 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 45 50 3681 G18 LTC7851-1 Overcurrent Threshold vs Temperature 20.8 80 70 60 ILIM = 680mV 50 30 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 7851 G20 65 70 75 RFREQ (k) 80 85 90 3681 G19 20.4 20.4 20.2 20 19.8 19.4 -50 60 FREQ Pin Current vs Temperature 20.2 20 19.8 19.6 19.4 19.6 40 55 20.6 20.6 ILIM = 860mV 90 ILIM Pin Current vs Temperature FREQ PIN CURRENT (A) 100 ILIM PIN CURRENT (A) CURRENT SENSE VOLTAGE (mV) 110 7851 G16 200s/DIV VIN = 12V CTRACK/SS = 2200pF 7851 G15 200s/DIV 128-Cycle Overcurrent Counter (2-Phase Using FDMF5820DC DrMOS) VOUT 50mV/DIV -25 0 25 50 75 TEMPERATURE (C) 100 125 7851 G21 19.2 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 7851 G22 Rev A For more information www.analog.com 7 LTC7851/LTC7851-1 TYPICAL PERFORMANCE CHARACTERISTICS 1MHz Preset Frequency vs Temperature 1000 595 990 590 585 580 575 570 565 -50 -25 0 25 50 75 TEMPERATURE (C) 100 980 970 960 -25 0 25 50 75 TEMPERATURE (C) 100 Shutdown Quiescent Current vs Supply Voltage 60 -50 125 0 25 50 75 TEMPERATURE (C) 100 125 RUN Threshold vs Temperature 2.5 65 2.4 40 30 20 2.3 RUN PIN VOLTAGE (V) SHUTDOWN CURRENT (A) 50 60 55 RISING 2.2 2.1 FALLING 2.0 1.9 1.8 1.7 10 1.6 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 50 -50 6 7851 G26 -25 0 25 50 75 TEMPERATURE (C) 100 1.5 -50 125 2.0 0 2.9 1.2 1.0 -50 TRACK/SS PIN CURRENT (A) 3.0 TRACK/SS PIN CURRENT (A) 0.5 1.4 -0.5 -1.0 -1.5 -2.0 -2.5 -25 0 25 50 75 TEMPERATURE (C) 100 125 7851 G29 100 -3.0 125 TRACK/SS Pull-Up Current vs Temperature 2.2 1.6 0 25 50 75 TEMPERATURE (C) 7851 G28 TRACK/SS Current vs TRACK/SS Voltage 1.8 -25 7851 G27 RUN Pull-Up Current vs Temperature 8 -25 7851 G25 60 SHUTDOWN CURRENT (A) 65 Shutdown Quiescent Current vs Temperature 70 RUN PIN CURRENT (A) 70 7851 G24 7851 G23 0 VIN = VCC = 5V RUN1 = RUN2 = RUN3 = RUN4 = 5V 950 940 -50 125 Quiescent Current vs Temperature 75 QUIESCENT CURRENT (mA) 600 OSCILLATOR FREQUENCY (kHz) OSCILLATOR FREQUENCY (kHz) 600kHz Preset Frequency vs Temperature 2.8 2.7 2.6 2.5 2.4 2.3 0 1 2 3 4 TRACK/SS PIN VOLTAGE (V) 5 7851 G30 2.2 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 7851 G31 Rev A For more information www.analog.com LTC7851/LTC7851-1 PIN FUNCTIONS COMP1 (Pin 1), COMP2 (Pin 9), COMP3 (Pin 13), COMP4 (Pin 20): Error Amplifier Outputs. PWM duty cycle increases with this control voltage. The error amplifiers in the LTC7851/LTC7851-1 are true operational amplifiers with low output impedance. As a result, the outputs of two active error amplifiers cannot be directly connected together! For multiphase operation, connecting the FB pin on an error amplifier to VCC will three-state the output of that amplifier. Multiphase operation can then be achieved by connecting all of the COMP pins together and using one channel as the master and all others as slaves. When the RUN pin is low, the respective COMP pin is actively pulled down to ground. VSNSP1 (Pin 2), VSNSP2 (Pin 8), VSNSP3 (Pin 14), VSNSP4 (Pin 19): Differential Sense Amplifier Noninverting Input. Connect this pin to the midpoint of the feedback resistive divider between the positive and negative output capacitor terminals. VSNSN1 (Pin 3), VSNSN2 (Pin 7), VSNSN3 (Pin 15), VSNSN4 (Pin 18): Differential Sense Amplifier Inverting Input. Connect this pin to sense ground at the output load. If the differential sense amplifier is not used, connect this pin to local ground. Float this pin when the channel is a slave channel. VSNSOUT1 (Pin 4), VSNSOUT2 (Pin 6), VSNSOUT3 (Pin 16), VSNSOUT4 (Pin 17): Differential Amplifier Output. Connect to the corresponding FB pin with a compensation network for remote VOUT sensing. PolyPhase control is also implemented in part by connecting all slave VSNSOUT pins to the master VSNSOUT output. Only the master phase's differential amplifier contributes information to this output. SGND (Pin 5, Exposed Pad Pin 59): Signal Ground. All soft-start, small-signal and compensation components should return to SGND. The exposed pad must be soldered to PCB ground for rated thermal performance. FB1 (Pin 58), FB2 (Pin 10), FB3 (Pin 12), FB4 (Pin 21): Error Amplifier Inverting Input. Connect to the corresponding VSNSOUT pin with a compensation network for remote VOUT sensing. Connecting the FB to VCC disables the differential and error amplifiers of the respective channel, and will three-state the amplifier outputs. VCC (Pin 11): Chip Supply Voltage. Bypass this pin to GND with a capacitor (0.1F to 1F ceramic) in close proximity to the chip. TRACK/SS1 (Pin 57), TRACK/SS2 (Pin 40), TRACK/SS3 (Pin 37), TRACK/SS4 (Pin 22): Combined Soft-Start and Tracking Inputs. For soft-start operation, connecting a capacitor from this pin to ground will control the voltage ramp at the output of the power supply. An internal 2.5A current source will charge the capacitor and thereby control an extra input on the reference side of the error amplifier. For coincident tracking of both outputs at start-up, a resistor divider with values equal to those connected to the secondary VSNSP pin from the secondary output should be used to connect the secondary track input from the primary output. This pin is internally clamped to 2V, and is used to communicate over current events in a masterslave configuration. RUN1 (Pin 53), RUN2 (Pin 51), RUN3 (Pin 27), RUN4 (Pin 23): Run Control Inputs. A voltage above 2.25V on either pin turns on the IC. However, forcing a RUN pin below 2V causes the IC to shut down that particular channel. There are 1.5A pull-up currents for these pins. PWM1 (Pin 52), PWM2 (Pin 50), PWM3 (Pin 26), PWM4 (Pin 24): (Top) Gate Signal Output. This signal goes to the PWM or top gate input of the external gate driver or integrated driver MOSFET. This is a three-state compatible output. In three-state, the voltage of this pin will be determined by the external resistor divider. PGOOD1 (Pin 49), PGOOD2 (Pin 38), PGOOD3 (Pin 28), PGOOD4 (Pin 25): Power Good Indicator Output for Each Channel. Open-drain logic out that is pulled to SGND when either channel output exceeds a 10% regulation window, after the internal 30s power bad mask timer expires. ILIM1 (Pin 48), ILIM2 (Pin 41), ILIM3 (Pin 36), ILIM4 (Pin 29): Current Comparator Sense Voltage Limit Selection Pin. Connect a resistor from this pin to SGND. This pin sources 20A when the channel is a master channel. This pin does not source current when the channel is a slave channel. The resultant voltage sets the threshold for overcurrent protection. For multiphase operation, all ILIM pins are tied together and only master channel's ILIM pin sources 20A. Rev A For more information www.analog.com 9 LTC7851/LTC7851-1 PIN FUNCTIONS IAVG1 (Pin 47), IAVG2 (Pin 42), IAVG3 (Pin 35), IAVG4 (Pin 30): Average Current Monitor Pin. A capacitor tied to ground from the IAVG pin stores a voltage proportional to the instantaneous average current of the master channel. When the average current is zero, the IAVG pin voltage is 500mV. PolyPhase control is also implemented in part by connecting all slave IAVG pins together to the master IAVG output. The total capacitance on the IAVG bus should range from 47pF to 220pF, inclusive, with the typical value being 100pF. Only the master phase contributes information to this average through an internal resistor in current sharing mode. ISNS1P (Pin 46), ISNS2P (Pin 43), ISNS3P (Pin 34), ISNS4P (Pin 31): Current Sense Amplifier(+) Input. The (+) input to the current sense amplifier is normally connected to the midpoint of the inductor's parallel RC sense circuit or to the node between the inductor and sense resistor if using a discrete sense resistor. ISNS1N (Pin 45), ISNS2N (Pin 44), ISNS3N (Pin 33), ISNS4N (Pin 32): Current Sense Amplifier(-) Input. The (-) input to the current amplifier is normally connected to the respective VOUT at the inductor. CLKOUT (Pin 54): Digital Output used for Daisychaining Multiple LTC7851/LTC7851-1 ICs in Multiphase Systems. When all RUN pins are driven low, the CLKOUT pin is actively pulled up to VCC. Signal swing is from VCC to ground. CLKIN (Pin 55): External Clock Synchronization Input. Applying an external clock between 250kHz to 2.25MHz will cause the switching frequency to synchronize to the clock. CLKIN is pulled high to VCC by a 20k internal resistor. The rising edge of the CLKIN input waveform will align with the rising edge of PWM1 in closed-loop operation. If CLKIN is high or floating, a resistor from the FREQ pin to SGND sets the switching frequency. If CLKIN is low, the FREQ pin logic state selects an internal 600kHz or 1MHz preset frequency. FREQ (Pin 56): Frequency Set/Select Pin. This pin sources 20A current. If CLKIN is high or floating, then a resistor between this pin and SGND sets the switching frequency. If CLKIN is low, the logic state of this pin selects an internal 600kHz or 1MHz preset frequency. VINSNS (Pin 39): VIN Sense Pin. Connects to the VIN power supply to provide line feedforward compensation. A change in VIN immediately modulates the input to the PWM comparator and changes the pulse width in an inversely proportional manner, thus bypassing the feedback loop and providing excellent transient line regulation. An external lowpass filter can be added to this pin to prevent noisy signals from affecting the loop gain. 10 Rev A For more information www.analog.com LTC7851/LTC7851-1 BLOCK DIAGRAM 4 2 3 6 8 7 1 57 58 (Only CH1 and CH2 Are Shown) VSNSOUT1 53 11 5 VCC SGND VCC VSNSP1 1.5A 100k 1.5A PGOOD2 VSNSOUT1 VSNSOUT2 VCC VSNSP2 COMP1 38 PGOOD1 PGOOD VCC VSNSOUT2 VSNSN2 49 RUN2 100k DA VSNSN1 51 RUN1 DA BG/BIAS REF TRACK/SS1 + FB1 - + SD/UVLO OC1 OC2 + EA1 OV1 OV2 PWM1 52 NOC1 40 10 9 REF TRACK/SS2 + FB2 - + LOGIC + EA2 VFB1 ILIM1 VFB2 ILIM2 COMP2 MASTER/SLAVE/ INDEPENDENT 45 ISNS1P ISNS1N 44 ISNS2P ISNS2N 50 39 20A + AV(ISENSE) - OC1 VCC NOC1 20A S 43 VINSNS RAMP/SLOPE/ FEEDFORWARD VCC S 46 PWM2 NOC2 + VCC AV(ISENSE) 20A - OC2 PLL/VCO NOC2 IAVG1 47 IAVG2 42 ILIM2 41 ILIM1 48 FREQ 56 CLKOUT CLKIN 54 55 7851BD Rev A For more information www.analog.com 11 LTC7851/LTC7851-1 OPERATION (Refer to Block Diagram) Main Control Architecture The LTC7851/LTC7851-1 are quad-channel/quad-phase, constant frequency, voltage mode controllers for DC/DC step-down applications. They are designed to be used in a synchronous switching architecture with external integrated-driver MOSFETs (DrMOS), power blocks, or external drivers and N-channel MOSFETs using single wire three-state PWM interfaces. The LTC7851-1 is particularly suited for applications using power stages with integrated current sense signals. The controllers allow the use of sense resistors or lossless inductor DCR current sensing to maintain current balance between phases and to provide overcurrent protection. The operating frequency is selectable from 250kHz to 2.25MHz. To multiply the effective switching frequency, multiphase operation can be extended to 2, 3, 4, 8, or higher phases by paralleling additional controllers. In single phase operation, each channel can be used as an independent output, i.e. one single LTC7851/LTC7851-1 can provide four outputs. Unlike a conventional differential amplifier, in which the output is connected directly to the diffamp sensing pins, the output voltage is resistively divided externally to create a feedback voltage for the controller (see Figure 3, and Figure 4). Connect VSNSP of the unity-gain internal differential amplifier, DA, to the center tap of the feedback divider across the output load, and VSNSN to the load ground. The output of the differential amplifier VSNSOUT produces a signal equal to the differential voltage sensed across VSNSP and VSNSN. This scheme overcomes any ground offsets between local ground and remote output ground and common mode voltage variations, resulting in a more accurate output voltage. In the main voltage mode control loop, the error amplifier output (COMP) directly controls the converter duty cycle in order to drive the FB pin to 0.6V in steady state. Dynamic changes in output load current can perturb the output voltage. When the output is below regulation, COMP rises, increasing the duty cycle. If the output rises above regulation, COMP will decrease, decreasing the duty cycle. As the output approaches regulation, COMP will settle to the steady-state value representing the stepdown conversion ratio. 12 In normal operation, the PWM latch is set high at the beginning of the clock cycle (assuming COMP > 0.5V). When the (line feedforward compensated) PWM ramp exceeds the COMP voltage, the comparator trips and resets the PWM latch. If COMP is less than 0.5V at the beginning of the clock cycle, as in the case of an overvoltage at the outputs, the PWM pin remains low throughout the entire cycle. When the PWM pin goes high, it has a minimum on-time of approximately 20ns and a minimum off-time of approximately one-twelfth the switching period. Current Sharing In multiphase operation, the LTC7851/LTC7851-1 also incorporate an auxiliary current sharing loop. Inductor current is sampled each cycle. The master's current sense amplifier output is averaged at the IAVG pin. A small capacitor connected from IAVG to GND (typically 100pF) stores a voltage corresponding to the instantaneous average current of the master. Master phase's and slave phase's IAVG pins must be connected together. Each slave phase integrates the difference between its current and the master's. Within each phase the integrator output is proportionally summed with the system error amplifier voltage (COMP), adjusting that phase's duty cycle to equalize the currents. When multiple ICs are daisy chained, the IAVG pins must be connected together. Figure 1 shows a transient load step with current sharing in a 3-phase system. IL1 (L= 0.47H) 10A/DIV IL2 (L= 0.25H) 10A/DIV IL3 (L= 0.47H) 10A/DIV VOUT 100mV/DIV AC-COUPLED 7851 F01 VIN = 12V VOUT = 1V 50s/DIV ILOAD STEP = 0A TO 30A TO 0A fSW = 500kHz EXTERNAL CLOCK Figure 1. Mismatched Inductor Load Step Transient Response Overcurrent Protection The current sense amplifier outputs also connect to overcurrent (OC) comparators that provide fault protection in the case of an output short. When an OC fault is detected Rev A For more information www.analog.com LTC7851/LTC7851-1 OPERATION (Refer to Block Diagram) for 128 consecutive clock cycles, the controller threestates the PWM output, resets the soft-start capacitor, and waits for 32768 clock cycles before attempting to start up again. The 128 consecutive clock cycle counter has a 7-cycle hysteresis window, after which it will reset. The LTC7851/LTC7851-1 also provide negative OC (NOC) protection by preventing turn-on of the bottom MOSFET during a negative OC fault condition. In this condition, the bottom MOSFET will be turned on for 40ns every eight cycles to allow the driver IC to recharge its topside gate drive capacitor. The negative OC threshold is equal to -3/4 the positive OC threshold. See the Applications Information section for guidelines on setting these thresholds. Excellent Transient Response The LTC7851/LTC7851-1 error amplifiers are true operational amplifiers, meaning that they have high bandwidth, high DC gain, low offset and low output impedance. Their bandwidth, when combined with high switching frequencies and low-value inductors, allows the compensation network to be optimized for very high control loop crossover frequencies and excellent transient response. The 600mV internal reference allows regulated output voltages as low as 600mV without external levelshifting amplifiers. Line Feedforward Compensation The LTC7851/LTC7851-1 achieve outstanding line transient response using a feedforward correction scheme which instantaneously adjusts the duty cycle to compensate for changes in input voltage, significantly reducing output overshoot and undershoot. It has the added advantage of making the DC loop gain independent of input voltage. Figure 2 shows how large transient steps at the input have little effect on the output voltage. VIN 10V/DIV 7V TO 14V IL1 10A/DIV IL2 10A/DIV VOUT 50mV/DIV AC-COUPLED VOUT = 1.2V ILOAD = 15A 20s/DIV 7851 F02 Figure 2. Line Step Transient Response Remote Sense Differential Amplifier The LTC7851/LTC7851-1 include four low offset, unity gain, high bandwidth differential amplifiers for differential output sensing. Output voltage accuracy is significantly improved by removing board interconnection losses from the total error budget. The noninverting input of the differential amplifier is connected to the midpoint of the feedback resistive divider between the positive and negative output capacitor terminals. The VSNSOUT is connected to the FB pin and the amplifier will attempt to regulate this voltage to 0.6V. The amplifier is configured for unity gain, meaning that the differential voltage between VSNSP and VSNSN is translated to VSNSOUT, relative to SGND. Shutdown Control Using the RUN Pins Each channel of the LTC7851/LTC7851-1 can be independently enabled using its own RUN pin. When all RUN pins are driven low, all internal circuitry, including the internal reference and oscillator, are completely shut down. When the RUN pin is low, the respective COMP pin is actively pulled down to ground. In a multiphase operation when the COMP pins are tied together, the COMP pin is held low until all the RUN pins are enabled. This ensures a synchronized start-up of all the channels. A 1.5A pull-up current is provided for each RUN pin internally. The RUN pins remain high impedance up to VCC. Undervoltage Lockout To prevent operation of the power supply below safe input voltage levels, all channels are disabled when VCC is below Rev A For more information www.analog.com 13 LTC7851/LTC7851-1 OPERATION (Refer to Block Diagram) the undervoltage lockout (UVLO) threshold (2.9V falling, 3V rising). If a RUN pin is driven high, the LTC7851/LTC7851-1 will start up the reference to detect when VCC rises above the UVLO threshold, and enable the appropriate channel. Overvoltage Protection If the output voltage rises to more than 10% above the set regulation value, which is reflected as a VSNSOUT voltage of 0.66V or above, the LTC7851/LTC7851-1 will force the PWM output low to turn on the bottom MOSFET and discharge the output. Normal operation resumes once the output is back within the regulation window. However, if the reverse current flowing from VOUT back through the bottom power MOSFET to PGND is greater than 3/4 the positive OC threshold, the NOC comparator trips and shuts off the bottom power MOSFET to protect it from being destroyed. This scenario can happen when the LTC7851/LTC7851-1 try to start into a precharged load higher than the OV threshold. As a result, the bottom switch turns on until the amount of reverse current trips the NOC comparator threshold. Nonsynchronous Start-Up and Prebiased Output The LTC7851/LTC7851-1 will start up with seven cycles of nonsynchronous operation before switching over to a forced continuous mode of operation. The PWM output will be in a three-state condition until start-up. The controller will start the seven nonsynchronous cycles if it is not in an overcurrent or prebiased condition, and if the COMP pin voltage is higher than 500mV, or if the TRACK/SS pin voltage is higher than 900mV. During the seven nonsynchronous cycles the PWM latch is set high at the beginning of the clock cycle, if COMP > 0.5V, causing the PWM output to transition from three-state to VCC. The latch is reset when the PWM ramp exceeds the COMP voltage, causing the PWM output to transition from VCC to threestate followed immediately by a 20ns three-state to ground pulse. The 7-cycle nonsynchronous mode of operation is enabled at initial start-up and also during a restart from a fault condition. In multiphase operation, where all the TRACK/SS pins should be connected together, only an overcurrent event on the master channel will discharge the 14 soft-start capacitor. After 32768 cycles, it will synchronize the restart of all channels in to the nonsynchronous mode of operation. The LTC7851/LTC7851-1 can safely start-up into a prebiased output without discharging the output capacitors. A prebias is detected when the FB pin voltage is higher than the TRACK/SS or the internal soft-start voltage. A prebiased condition will force the COMP pin to be held low, and will three-state the PWM output. The prebiased condition is cleared when the TRACK/SS or the internal soft-start voltage is higher than the FB pin voltage or 900mV, whichever is lower. If the output prebias is higher than the OV threshold then the PWM output will be low, which will pull the output back in to the regulation window. Internal Soft-Start By default, the start-up of each channel's output voltage is normally controlled by an internal soft-start ramp. The internal soft-start ramp represents a noninverting input to the error amplifier. The FB pin is regulated to the lower of the error amplifier's three noninverting inputs (the internal soft-start ramp for that channel, the TRACK/SS pin or the internal 600mV reference). As the ramp voltage rises from 0V to 0.6V over approximately 2ms, the output voltage rises smoothly from its prebiased value to its final set value. Soft-Start and Tracking Using TRACK/SS Pin The user can connect an external capacitor greater than 10nF to the TRACK/SS pin for the relevant channel to increase the soft-start ramp time beyond the internally set default. The TRACK/SS pin represents a noninverting input to the error amplifier and behaves identically to the internal ramp described in the previous section. An internal 2.5A current source charges the capacitor, creating a voltage ramp on the TRACK/SS pin. The TRACK/SS pin is internally clamped to 2V. As the TRACK/SS pin voltage rises from 0V to 0.6V, the output voltage rises smoothly from 0V to its final value in: CSS (F ) * 0.6V seconds 2.5A Rev A For more information www.analog.com LTC7851/LTC7851-1 OPERATION (Refer to Block Diagram) Alternatively, the TRACK/SS pin can be used to force the start-up of VOUT to track the voltage of another supply. Typically this requires connecting the TRACK/SS pin to an external divider from the other supply to ground (see the Applications Information section). It is only possible to track another supply that is slower than the internal soft-start ramp. The TRACK/SS pin also has an internal open-drain NMOS pull-down transistor that turns on to reset the TRACK/SS voltage when the channel is shut down (RUN = 0V or VCC < UVLO threshold) or during an OC fault condition. No external PLL filter is required to synchronize the LTC7851/LTC7851-1 to an external clock. Applying an external clock signal to the CLKIN pin will automatically enable the PLL with internal filter. In multiphase operation, one master error amplifier is used to control all of the PWM comparators. The FB pins for the unused error amplifiers are connected to VCC in order to three-state these amplifier outputs and the COMP pins are connected together. When the FB pin is tied to VCC, the internal 2.5A current source on the TRACK/SS pin is disabled for that channel. The TRACK/SS pins should also be connected together so that the slave phases can detect when soft-start is complete and to synchronize the nonsynchronous mode of operation. The LTC7851/LTC7851-1 feature a CLKOUT pin, which allows multiple LTC7851/LTC7851-1 ICs to be daisy chained together in multiphase applications. The clock output signal on the CLKOUT pin can be used to synchronize additional ICs in a multiphase power supply solution feeding a single high current output, or even several outputs from the same input supply. Frequency Selection and the Phase-Locked Loop (PLL) The selection of the switching frequency is a trade-off between efficiency, transient response and component size. High frequency operation reduces the size of the inductor and output capacitor as well as increasing the maximum practical control loop bandwidth. However, efficiency is generally lower due to increased transition and switching losses. The LTC7851/LTC7851-1's switching frequency can be set in three ways: using an external resistor to linearly program the frequency, synchronizing to an external clock, or simply selecting one of two fixed frequencies (600kHz and 1MHz). Table 1 highlights these modes. Table 1. Frequency Selection CLKIN PIN FREQ PIN FREQUENCY Clocked RFREQ to GND 250kHz to 2.25MHz High or Float RFREQ to GND 250kHz to 2.25MHz Low Low 600kHz Low High 1MHz Constant-frequency operation brings with it a number of benefits: inductor and capacitor values can be chosen for a precise operating frequency and the feedback loop can be similarly tightly specified. Noise generated by the circuit will always be at known frequencies. Using the CLKOUT Pin in Multiphase Applications The phase relationship among each channel, as well as the phase relationship between channel 1 and CLKOUT, are summarized in Table 2. The phases are calculated relative to zero degrees, defined as the rising edge of PWM1. Refer to Application Information for more details on how to create multiphase applications. Table 2. Phase Relationship CH-1 0 CH-2 180 CH-3 90 CH-4 270 CLKOUT 45 Using the LTC7851/LTC7851-1 Error Amplifiers in Multiphase Applications Due to the low output impedance of the error amplifiers, multiphase applications using the LTC7851/LTC7851-1 use one error amplifier as the master with all of the slaves' error amplifiers disabled. The channel 1 error amplifier (phase = 0) may be used as the master with phases 2 through n (up to 12) serving as slaves. To disable the slave error amplifiers, connect the FB pins of the slaves Rev A For more information www.analog.com 15 LTC7851/LTC7851-1 OPERATION (Refer to Block Diagram) to VCC. This three-states the output stages of the amplifiers. All COMP pins should then be connected together to create PWM outputs for all phases. As noted in the section on soft-start, all TRACK/SS pins should also be shorted together. Refer to the Multiphase Operation section in Applications Information for schematics of various multiphase configurations. Theory and Benefits of Multiphase Operation Multiphase operation provides several benefits over traditional single phase power supplies: n Greater output current capability n Improved transient response n Reduction in component size n Increased real world operating efficiency Because multiphase operation parallels power stages, the amount of output current available is n times what it would be with a single comparable output stage, where n is equal to the number of phases. The main advantages of PolyPhase operation are ripple current cancellation in the input and output capacitors, a faster load step response due to a smaller clock delay and reduced thermal stress on the inductors and MOSFETs due to current sharing between phases. These advantages allow for the use of a smaller size or a smaller number of components. Power Good Indicator Pins (PGOOD) Each PGOOD pin is connected to the open drain of an internal pull-down device which pulls the PGOOD pin low when the corresponding VSNSOUT pin voltage is outside the PGOOD regulation window (7.5% entering regulation, 10% leaving regulation). The PGOOD pins 16 are also pulled low when the corresponding RUN pin is low, or during UVLO. When the VSNSOUT pin voltage is within the 10% regulation window, the internal PGOOD MOSFET is turned off and the pin is normally pulled up by an external resistor. When the VSNSOUT pin is exiting a fault condition (such as during normal output voltage start-up, prior to regulation), the PGOOD pin will remain low for an additional 30s. This allows the output voltage to reach steady-state regulation and prevents the enabling of a heavy load from retriggering a UVLO condition. In multiphase application, only the master phase differential and error amplifiers are used to control all phases. The slave phase differential amplifiers are three-stated. The slave phase VSNSOUT pins are connected to the master phase VSNSOUT pin to obtain output voltage information. Only the PGOOD output for the master control error amplifier should be connected to the fault monitor. PWM Pins The PWM pins are three-state compatible outputs, designed to drive MOSFET drivers, DrMOSs, power blocks, etc., which do not represent a heavy capacitive load. An external resistor divider may be used to set the voltage to mid-rail while in the high impedance state. Line Feedforward Gain In a typical LTC7851/LTC7851-1 circuit, the feedback loop consists of the line feedforward circuit, the modulator, the external inductor, the output capacitor and the feedback amplifier with its compensation network. All these components affect loop behavior and need to be accounted for in the loop compensation. The modulator consists of the PWM generator, the external output MOSFET drivers and the external MOSFETs themselves. The modulator gain varies linearly with the input voltage. The line feedforward circuit compensates for this change in gain, and provides a constant gain from the error amplifier output to the inductor input regardless of input voltage. From a feedback loop point of view, the combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from COMP to the inductor input and has a gain roughly equal to 12V/V. Rev A For more information www.analog.com LTC7851/LTC7851-1 APPLICATIONS INFORMATION Output Voltage Programming and Differential Output Sensing More precisely, the VOUT value programmed in the previous equation is with respect to the output's ground reference, and thus, is a differential quantity. The minimum differential output voltage is limited to the internal reference, 0.6V, and the maximum differential output voltage is VCC - 0.5V. The LTC7851/LTC7851-1 integrate differential output sensing with output voltage programming, allowing for a simple and seamless design. As shown in Figure 3, the output voltage is programmed by an external resistor divider from the regulated output point to its ground reference. The resistive divider is tapped by the VSNSP pin, and the ground reference is sensed by VSNSN. An optional feedforward capacitor, CFF, can be used to improve the transient performance. The resulting output voltage is given according to the following equation: The VSNSP pin is high impedance with no input bias current. The VSNSN pin has about 7.5A of current flowing out of the pin. Differential output sensing allows for more accurate output regulation in high power distributed systems having large line losses. Figure 4 illustrates the potential variations in the power and ground lines due to parasitic elements. These variations are exacerbated in multi-application systems with shared ground planes. Without differential output sensing, these variations directly reflect as an error in the regulated output voltage. R VOUT = 0.6 V * 1 + FB2 RFB1 The LTC7851/LTC7851-1's differential output sensing scheme is distinct from conventional schemes. In conventional schemes, the regulated output and its ground reference are directly sensed with a difference amplifier whose output is then divided down with an external resistive divider and fed into the error amplifier input. This conventional scheme is limited by the common mode input range of the difference amplifier and typically limits differential sensing to the lower range of output voltages. VOUT LTC7851/ LTC7851-1 CFF (OPT) RFB2 COUT VSNSP RFB1 VSNSN 7851 F03 The LTC7851/LTC7851-1 allow for seamless differential output sensing by sensing the resistively divided feedback voltage differentially. This allows for differential sensing in the full output range from 0.6V to VCC - 0.5V. The dif- Figure 3. Setting Output Voltage CIN MT LTC7851/ LTC7851-1 VSNSP RFB2 VSNSN RFB1 + - VIN POWER TRACE PARASITICS L VDROP(PWR) MB COUT1 ILOAD COUT2 I LOAD GROUND TRACE PARASITICS VDROP(GND) OTHER CURRENTS FLOWING IN SHARED GROUNDPLANE 7851 F04 Figure 4. Differential Output Sensing Used to Correct Line Loss Variations in a High Power Distributed System with a Shared Ground Plane Rev A For more information www.analog.com 17 LTC7851/LTC7851-1 APPLICATIONS INFORMATION ference amplifier of the LTC7851/LTC7851-1 has a gain bandwidth of 40MHz, high enough not to affect main loop compensation and transient behavior. To avoid noise coupling into VSNSP, the resistor divider should be placed near the VSNSP and VSNSN pins and physically close to the LTC7851/LTC7851-1. The remote output and ground traces should be routed parallel to each other as a differential pair to the remote output. These traces should be terminated as close as physically possible to the remote output point that is to be accurately regulated through remote differential sensing. In addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. Ideally, they should be shielded by a low impedance ground plane to maintain signal integrity. Programming the Operating Frequency The LTC7851/LTC7851-1 can be hard wired to one of two fixed frequencies, linearly programmed to any frequency between 250kHz and 2.25MHz or synchronized to an external clock. Table 1 in the Operation section shows how to connect the CLKIN and FREQ pins to choose the mode of frequency programming. The frequency of operation is given by the following equation: Frequency = (RFREQ - 19.8k) * 33.5Hz/, when Frequency is <1MHz Frequency = (RFREQ - 14.6k) * 28.1Hz/, when Frequency is 1MHz 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 OSCILLATOR FREQUENCY (kHz) OSCILLATOR FREQUENCY (kHz) Figure 5 shows operating frequency vs RFREQ. 24 27 30 33 36 39 42 45 48 51 54 RFREQ (k) 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 45 50 7851 F05a 55 60 65 70 75 RFREQ (k) 80 85 90 7851 F05b Figure 5. Oscillator Frequency vs RFREQ 18 Rev A For more information www.analog.com LTC7851/LTC7851-1 APPLICATIONS INFORMATION Frequency Synchronization The LTC7851/LTC7851-1 incorporate an internal phaselocked loop (PLL) which enables synchronization of the internal oscillator (rising edge of PWM1) to an external clock from 250kHz to 2.25MHz. Since the entire PLL is internal to the LTC7851/LTC7851-1, simply applying a CMOS level clock signal to the CLKIN pin will enable frequency synchronization. A resistor from FREQ to GND is still required to set the free running frequency close to the sync input frequency. For cases where the LTC7851/LTC7851-1's CLKOUT and CLKIN signals are daisy chained, make sure the controllers in the daisy chain are enabled at the same time or the slave is enabled after its master. There is a sequencing requirement for the external clock and the RUN pin. Make sure the external clock is applied before any RUN pin is enabled. If the external clock has to be applied after the RUN pin is enabled, the initial frequency must be set by RFREQ. To enable this resistor-set frequency, keep CLKIN high until the external clock starts switching.(The circuit in Figure 6 can be used to achieve this function.) 1nF EXTERNAL CLOCK The inductor saturation current rating needs to be higher than the peak inductor current during transient conditions. If IOUT is the maximum rated load current, then the maximum transient current, IMAX, would normally be chosen to be some factor (e.g., 60%) greater than IOUT: IMAX = 1.6 * IOUT The minimum saturation current rating should be set to allow margin due to manufacturing and temperature variation in the sense resistor or inductor DCR. A reasonable value would be: ISAT = 2.2 * IOUT The programmed current limit must be low enough to ensure that the inductor never saturates and high enough to allow increased current during transient conditions, to account for inductor ripple current and to allow margin for DCR variation. ILIMIT = 1.6 *IOUT + LTC7851 /LTC7851-1 7851 F06 Figure 6. The Circuit to Keep the CLKIN Pin High Before the External Clock Starts Switching Choosing the Inductor and Setting the Current Limit The inductor value is related to the switching frequency, which is chosen based on the trade-offs discussed in the Operation section. The inductor can be sized using the following equation: V V L = OUT * 1- OUT VIN f * IL IL = 0.3 * IOUT For DCR sensing: CLKIN 100k Choosing a larger value of IL leads to smaller L, but results in greater core loss (and higher output voltage ripple for a given output capacitance and/or ESR). A reasonable starting point for setting the ripple current is 30% of the maximum output current, or: IL 2 For discrete sense resistor: ILIMIT = 1.3 * IOUT + IL 2 where IL = VOUT V L * fSW * 1- OUT VIN provided that ILIMIT < ISAT. Rev A For more information www.analog.com 19 LTC7851/LTC7851-1 APPLICATIONS INFORMATION If the sensed inductor current exceeds current limit for 128 consecutive clock cycles, the IC will three-state the PWM output, reset the soft-start timer and wait 32768 switching cycles before attempting to return the output to regulation. The current limit is programmed using a resistor from the ILIM pin to SGND. The ILIM pin sources 20A to generate a voltage corresponding to the current limit. The current sense circuit has a voltage gain of 20 for the LTC7851 (4 for the LTC7851-1) and a zero current level of 500mV. Therefore, the current limit resistor should be set using the following equation for the LTC7851: RILIM = 20 * I LIMIT-PHASE * R SENSE + 0.5V 20A The equation for the LTC7851-1 is: RILIM = 4 * I LIMIT-PHASE * R SENSE + 0.5V 20A In multiphase applications, all ILIM pins are tied together and only one current limit resistor should be used. The master channel's ILIM pin sources 20A. Slave channels' ILIM pins do not source any current. Inductor Core Selection Once the value of L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core losses found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Also, core losses decrease as inductance increases. Unfortunately, increased inductance requires more turns of wire, larger inductance and larger copper losses. Ferrite designs have very low core loss and are preferred at high switching frequencies. However, these core materials exhibit "hard" saturation, causing an abrupt reduction in the inductance when the peak current capability is exceeded. Do not allow the core to saturate! CIN Selection The input bypass capacitor in the LTC7851/LTC7851-1 circuit is common to all channels. The input bypass capacitor needs to meet these conditions: its ESR must be low 20 enough to keep the supply drop low as the top MOSFETs turn on, its RMS current capability must be adequate to withstand the ripple current at the input, and the capacitance must be large enough to maintain the input voltage until the input supply can make up the difference. Generally, a capacitor (particularly a non-ceramic type) that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. The input capacitor's voltage rating should be at least 1.4 times the maximum input voltage. Power loss due to ESR occurs not only as I2R dissipation in the capacitor itself, but also in overall battery efficiency. For mobile applications, the input capacitors should store adequate charge to keep the peak battery current within the manufacturer's specifications. The input capacitor RMS current requirement is simplified by the multiphase architecture and its impact on the worstcase RMS current drawn through the input network (battery/ fuse/capacitor). It can be shown that the worst-case RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used to determine the maximum RMS current requirement. Increasing the output current drawn from the other out-of-phase controller will actually decrease the input RMS ripple current from this maximum value. The out-of-phase technique typically reduces the input capacitor's RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the top Nchannel MOSFET is approximately a square wave of duty cycle VOUT/ VIN. The maximum RMS capacitor current is given by: IRMS IOUT(MAX ) VOUT ( VIN - VOUT ) VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. The total RMS current is lower when both controllers are operating due to the interleaving of current pulses through the input capacitors. This is why the input capacitance requirement calculated above for the worst-case controller is adequate for the dual controller design. Rev A For more information www.analog.com LTC7851/LTC7851-1 APPLICATIONS INFORMATION Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. Manufacturers such as Sanyo, Panasonic and Cornell Dubilier should be considered for high performance throughhole capacitors. The OS-CON semiconductor electrolyte capacitor available from Sanyo has a good (ESR)(size) product. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to offset the effect of lead inductance. Ceramic, tantalum, OS-CON and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramics have high voltage coefficients of capacitance and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface mount applicability; and electrolytics' higher ESR and dryout possibility require several to be used. Sanyo OSCON SVP, SVPD series; Sanyo POSCAP TQC series or aluminum electrolytic capacitors from Panasonic WA series or Cornell Dubilier SPV series, in parallel with a couple of high performance ceramic capacitors, can be used as an effective means of achieving low ESR and high bulk capacitance. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or transient current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent output capacitor choices include the Sanyo POSCAP TPD, TPE, TPF series, the Kemet T520, T530 and A700 series, NEC/Tokin NeoCapacitors and Panasonic SP series. Other capacitor types include Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. COUT Selection The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple VOUT is approximately bounded by: 1 VOUT IL ESR + 8 * fSW * COUT where IL is the inductor ripple current. IL may be calculated using the equation: IL = VOUT VOUT 1- L * fSW VIN Since IL increases with input voltage, the output ripple voltage is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Current Sensing To maximize efficiency, the LTC7851/LTC7851-1 are designed to sense current through the inductor's DCR, as shown in Figure 7. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which for most inductors applicable to this application, is between 0.3m and 1m for the LTC7851, between 1m and 3m for the LTC7851-1. If the filter RC time constant is chosen to be exactly equal to the L/DCR time constant of the inductor, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR. Check the manufacturer's data sheet for specifications regarding the inductor DCR in order to properly dimension the external filter components. The DCR of the inductor can also be measured using a good RLC meter. Rev A For more information www.analog.com 21 LTC7851/LTC7851-1 APPLICATIONS INFORMATION VIN 12V VINSNS LTC7851/ LTC7851-1 5V VCC VLOGIC BOOST TG VCC LTC4449 IN TS PWM SGND ISNSN ISNSP CF GND SENSE RESISTOR PLUS PARASITIC INDUCTANCE L RS BG ESL VOUT CF * 2RF ESL/RS POLE-ZERO CANCELLATION RF RF 7851 F06a FILTER COMPONENTS PLACED NEAR SENSE PINS (a) Using a Resistor to Sense Current VIN 12V VINSNS LTC7851/ LTC7851-1 5V VCC PWM SGND ISNSN ISNSP VLOGIC BOOST TG VCC LTC4449 TS IN GND BG INDUCTOR L DCR VOUT R1* C1* 7851 F06b R1 * C1 = L *PLACE R1 NEAR INDUCTOR DCR PLACE C1 NEAR ISNSP, ISNSN PINS (b) Using the Inductor to Sense Current Figure 7. Two Different Methods of Sensing Current 22 Rev A For more information www.analog.com LTC7851/LTC7851-1 APPLICATIONS INFORMATION Since the temperature coefficient of the inductor's DCR is 3900ppm/C, first order compensation of the filter time constant is possible by using filter resistors with an equal but opposite (negative) TC, assuming a low TC capacitor is used. That is, as the inductor's DCR rises with increasing temperature, the L/DCR time constant drops. Since we want the filter RC time constant to match the L/DCR time constant, we also want the filter RC time constant to drop with increasing temperature. Typically, the inductance will also have a small negative TC. The ISNSP and ISNSN pins are the inputs to the current comparators. The common mode range of the current comparators is -0.3V to VCC - 0.5V. Continuous linear operation is provided throughout this range, allowing output voltages between 0.6V (the reference input to the error amplifiers) and VCC - 0.5V. The maximum output voltage is lower than VCC to account for output ripple and output overshoot. The maximum differential current sense input (VISNSP - VISNSN) is 50mV for the LTC7851, 150mV for the LTC7851-1. The high impedance inputs to the current comparators allow accurate DCR sensing. However, care must be taken not to float these pins during normal operation. Filter components mutual to the sense lines should be placed close to the LTC7851/LTC7851-1, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 8). Sensing current elsewhere can effectively add parasitic TO SENSE FILTER, NEXT TO THE CONTROLLER COUT INDUCTOR OR RSENSE 7851 F07 Figure 8. Sense Lines Placement with Inductor or Sense Resistor inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If low value (<5m) sense resistors are used, verify that the signal across CF resembles the current through the inductor, and reduce RF to eliminate any large step associated with the turn-on of the primary switch. If DCR sensing is used (Figure 7b), sense resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. The capacitor C1 should be placed close to the IC pins. For the DrMOS with integrated current sensing, the current sense information is provided by the DrMOS itself. The common mode voltage of the ISNSP and ISNSN pins are set by the DrMOS. As a result, the maximum VOUT is not limited by VCC - 0.5V anymore. Multiphase Operation When the LTC7851/LTC7851-1 are used in a single output, multiphase application, the slave error amplifiers must be disabled by connecting their FB pins to VCC. All current limits should be set to the same value using only one resistor to SGND. In a multiphase application, all COMP, RUN, ILIM, IAVG, VSNSOUT and TRACK/SS pins must be connected together. The total capacitance on the IAVG bus should range from 47pF to 220pF, inclusive, with the typical value being 100pF. For output loads that demand high current, multiple LTC7851/LTC7851-1s can be daisy chained to run out of phase to provide more output current without increasing input and output voltage ripple. The CLKIN pin allows the LTC7851/LTC7851-1 to synchronize to the CLKOUT signal of another LTC7851/LTC7851-1. The CLKOUT signal can be connected to the CLKIN pin of the following LTC7851/ LTC7851-1 stage to line up both the frequency and the phase of the entire system. Figure 9 shows the pin connections necessary for 3-, 4-, 8- or 12-phase operation. A total of twelve phases can be daisy chained to run simultaneously out of phase with respect to each other. Rev A For more information www.analog.com 23 LTC7851/LTC7851-1 APPLICATIONS INFORMATION 0, 180, 90, 270 0, 180, 90, 270 CLKIN CLKOUT FB1 COMP1 FB2 LTC7851 COMP2 FB3 /LTC7851-1 COMP3 FB4 COMP4 ILIM1 TRACK/SS1 ILIM2 TRACK/SS2 ILIM3 TRACK/SS3 ILIM4 TRACK/SS4 VSNSOUT1 IAVG1 VSNSOUT2 IAVG2 VSNSOUT3 IAVG3 VSNSOUT4 IAVG4 VCC VCC CLKIN CLKOUT FB1 COMP1 FB2 LTC7851 COMP2 FB3 /LTC7851-1 COMP3 FB4 COMP4 ILIM1 TRACK/SS1 ILIM2 TRACK/SS2 ILIM3 TRACK/SS3 ILIM4 TRACK/SS4 VSNSOUT1 IAVG1 VSNSOUT2 IAVG2 VSNSOUT3 IAVG3 VSNSOUT4 IAVG4 7851 F08b 7851 F08a (a) Triple Phase and Single Phase VCC (b) 4-Phase 0, 180, 90, 270 45, 225, 135, 315 CLKIN CLKOUT FB1 COMP1 FB2 LTC7851 COMP2 FB3 /LTC7851-1 COMP3 FB4 COMP4 ILIM1 TRACK/SS1 ILIM2 TRACK/SS2 ILIM3 TRACK/SS3 ILIM4 TRACK/SS4 VSNSOUT1 IAVG1 VSNSOUT2 IAVG2 VSNSOUT3 IAVG3 VSNSOUT4 IAVG4 CLKIN CLKOUT FB1 COMP1 FB2 LTC7851 COMP2 FB3 /LTC7851-1 COMP3 FB4 COMP4 ILIM1 TRACK/SS1 ILIM2 TRACK/SS2 ILIM3 TRACK/SS3 ILIM4 TRACK/SS4 VSNSOUT1 IAVG1 VSNSOUT2 IAVG2 VSNSOUT3 IAVG3 VSNSOUT4 IAVG4 VCC 7851 F08c (c) 8-Phase VCC V+ OUT4 SET OUT3 MOD OUT2 240 120 0 LTC6902 OUT1 0, 180, 90, 270 VCC 120, 300, 210, 30 CLKIN CLKOUT FB1 COMP1 FB2 LTC7851 COMP2 FB3 /LTC7851-1 COMP3 FB4 COMP4 ILIM1 TRACK/SS1 ILIM2 TRACK/SS2 ILIM3 TRACK/SS3 ILIM4 TRACK/SS4 VSNSOUT1 IAVG1 VSNSOUT2 IAVG2 VSNSOUT3 IAVG3 VSNSOUT4 IAVG4 VCC CLKIN CLKOUT FB1 COMP1 FB2 LTC7851 COMP2 FB3 /LTC7851-1 COMP3 FB4 COMP4 ILIM1 TRACK/SS1 ILIM2 TRACK/SS2 ILIM3 TRACK/SS3 ILIM4 TRACK/SS4 VSNSOUT1 IAVG1 VSNSOUT2 IAVG2 VSNSOUT3 IAVG3 VSNSOUT4 IAVG4 240, 60, 330, 150 VCC CLKIN CLKOUT FB1 COMP1 FB2 LTC7851 COMP2 FB3 /LTC7851-1 COMP3 FB4 COMP4 ILIM1 TRACK/SS1 ILIM2 TRACK/SS2 ILIM3 TRACK/SS3 ILIM4 TRACK/SS4 VSNSOUT1 IAVG1 VSNSOUT2 IAVG2 VSNSOUT3 IAVG3 VSNSOUT4 IAVG4 7851 F09d (d) 12-Phase Figure 9. Multiphase Operation Setup 24 Rev A For more information www.analog.com LTC7851/LTC7851-1 APPLICATIONS INFORMATION A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used. Figure 10 graphically illustrates the principle. sults in peak outputs of 1/4 and 3/4 of input voltage. When the RMS current is calculated, higher effective duty factor results and the peak current levels are divided as long as the current in each stage is balanced. Refer to Application Note 19 for a detailed description of how to calculate RMS current for the single stage switching regulator. Figure 11 and Figure 12 illustrate how the input and output currents are reduced by using an additional phase. For a 2-phase converter, the input current peaks drop in half and the frequency is doubled. The input capacitor requirement is thus reduced theoretically by a factor of four! Just imagine the possibility of capacitor savings with even higher number of phases! The worst-case RMS ripple current for a single stage design peaks at an input voltage of twice the output voltage. The worst case RMS ripple current for a two stage design reSINGLE PHASE SW1 V DUAL PHASE SW1 V SW2 V ICIN IL1 ICOUT IL2 ICIN ICOUT 7851 F09 RIPPLE Figure 10. Single and 2-Phase Current Waveforms 1.0 0.6 0.8 1 PHASE 0.7 DIC(P-P) VO/L RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.9 0.6 0.5 0.4 0.3 0.2 2 PHASE 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.5 0.4 0.3 0.2 2 PHASE 0.1 0 0.9 7851 F10 Figure 11. Normalized Output Ripple Current vs Duty Factor [IRMS 0.3 (DIC(PP))] 1 PHASE 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 7851 F11 Figure 12. Normalized RMS Input Ripple Current vs Duty Factor for 1 and 2 Output Stages Rev A For more information www.analog.com 25 LTC7851/LTC7851-1 APPLICATIONS INFORMATION Output Current Sharing When multiple LTC7851/LTC7851-1's channels or multiple LTC7851/LTC7851-1s are daisy chained to drive a common load, accurate output current sharing is essential to achieve optimal performance and efficiency. Otherwise, if one stage is delivering more current than another, then the temperature between the two stages will be different, and that could translate into higher switch RDS(ON), lower efficiency, and higher RMS ripple. When the COMP and IAVG pins of multiple channels/ICs are tied together, the amount of output current delivered from each LTC7851/ LTC7851-1 channel is actively balanced by the IAVG loop. The SGND pins of the multiple LTC7851/LTC7851-1s must be Kelvined to the same point for optimal current sharing. Quad-Channel Operation The LTC7851/LTC7851-1 can control four independent power supply outputs with no channel-to-channel interaction or jitter. The following recommendations will ensure maximum performance in this mode of operation: n n The output of each channel should be sensed using the differential sense amplifier. The SGND pins and exposed pad and all local small-signal GND should then be a Kelvin connection to the negative terminal of each channel output. This will provide the best possible regulation of each channel without adversely affecting the other channel. Separate current limit resistors on the ILIM pins should be used for each channel in quad-channel operation, even when the values are the same. 26 Table 3 shows the ILIM and EA configuration for Quadchannel operation. The configuration for dual-channel and tri-channel operation are similar. Table 3. Quad-Channel Configuration CH1 CH2 Independent Independent CH3 CH4 Independent Independent EA1 EA2 ILIM1 ILIM2 On On Resistor to SGND Resistor to SGND EA3 EA4 ILIM3 ILIM4 On On Resistor to SGND Resistor to SGND Tracking and Soft-Start (TRACK/SS Pins) The start-up of the supply output is controlled by the voltage on the TRACK/SS pin for that channel. The LTC7851/ LTC7851-1 regulate the FB pin voltage to the lower of the voltage on the TRACK/SS pin and the internal 600mV reference. The TRACK/SS pin can therefore be used to program an external soft-start function or allow the output supply to track another supply during start-up. External soft-start is enabled by connecting a capacitor from the TRACK/SS pin to SGND. An internal 2.5A current source charges the capacitor, creating a linear voltage ramp at the TRACK/SS pin, and causing the output supply to rise smoothly from its prebiased value to its final regulated value. The total soft-start time is approximately: t SS(milliseconds) = CSS (F) * 600mV 2.5A Alternatively, the TRACK/SS pin can be used to track another supply during start-up. Rev A For more information www.analog.com LTC7851/LTC7851-1 APPLICATIONS INFORMATION For example, Figure 13 shows the start-up of VOUT2 controlled by the voltage on the TRACK/SS2 pin. Normally this pin is used to allow the start-up of VOUT2 to track that of VOUT1 as shown qualitatively in Figure 13 and Figure 14. When the voltage on the TRACK/SS2 pin is less than the internal 0.6V reference, the LTC7851/LTC7851-1 regulates the FB2 voltage to the TRACK/SS2 pin voltage instead of 0.6V. VOUT1 R + R TRACKB R2A * TRACKA = R2B + R2A VOUT 2 R TRACKA The LTC7851/LTC7851-1 can only do coincident tracking (VOUT1 = VOUT2 during start-up), as a result: R2A = RTRACKA R2B = RTRACKB R1B RTRACKB LTC7851/ LTC7851-1 VSNSP1 VSNSP2 R2B R2A R1A TRACK/SS2 7851 F12 RTRACKA Figure 13. Output Voltage Tracking Using the TRACK/SS Pin OUTPUT VOLTAGE VOUT1 VOUT2 TIME t SS2 = t SS1 * VOUT 2F VOUT1F where VOUT1F and VOUT2F are the final, regulated values of VOUT1 and VOUT2. VOUT1 should always be greater than VOUT2 when using the TRACK/SS2 pin for tracking. If no tracking function is desired, then the TRACK/SS2 pin may be tied to a capacitor to ground, which sets the ramp time to final regulated output voltage. It is only possible to track another supply that is slower than the internal soft-start ramp. At the completion of tracking, the TRACK/SS pin must be >1V, so as not to affect regulation accuracy and to ensure the part is in CCM mode. Feedback Loop Compensation VOUT2 VOUT1 The ramp time for VOUT2 to rise from 0V to its final value is: The LTC7851/LTC7851-1 are voltage mode controllers with a second dedicated current sharing loop to provide excellent phase-to-phase current sharing in multiphase applications. The current sharing loop is internally compensated. While Type 2 compensation for the voltage control loop may be adequate in some applications (such as with the use of high ESR bulk capacitors), Type 3 compensation, along with ceramic capacitors, is recommended for optimum transient response. Referring to Figure 15, the error amplifiers sense the output voltage at VOUT. The positive input of the error amplifier is connected to an internal 600mV reference, while the negative input is connected to the FB pin. The output is connected to COMP, which is in turn connected to the line feedforward circuit and from there to the PWM generator. To speed up the overshoot recovery time, the maximum potential at the COMP pin is internally clamped. 7851 F13 Figure 14. Coincident Tracking Rev A For more information www.analog.com 27 LTC7851/LTC7851-1 APPLICATIONS INFORMATION Unlike many regulators that use a transconductance (gm) amplifier, the LTC7851/LTC7851-1 are designed to use an inverting summing amplifier topology with the FB pin configured as a virtual ground. This allows the feedback gain to be tightly controlled by external components, which is not possible with a simple gm amplifier. In addition, the voltage feedback amplifier allows flexibility in choosing pole and zero locations. In particular, it allows the use of Type 3 compensation, which provides a phase boost at the LC pole frequency and significantly improves the control loop phase margin. In typical LTC7851/LTC7851-1 circuit, the feedback loop consists of the line feedforward circuit, the modulator, the external inductor, the output capacitor and the feedback amplifier with its compensation network. All these components affect loop behavior and need to be accounted for in the loop compensation. The modulator consists of the PWM generator, the output MOSFET drivers and the external MOSFETs themselves. The modulator gain varies linearly with the input voltage. The line feedforward circuit compensates for this change in gain, and provides a constant gain from the error amplifier output to the inductor input regardless of input voltage. From a feedback loop point of view, the combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from COMP to the inductor input. It has fairly benign AC behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. Figure 15 shows a Type 3 amplifier. The transfer function of this amplifier is given by the following equation: - (1+ sC1R2)[1+ s(R1+ R3)C3] VCOMP = VOUT sR1(C1+ C2) 1+ s(C1//C2)R2 (1+ sC3R3) The RC network across the error amplifier and the feedforward components R3 and C3 introduce two pole-zero pairs to obtain a phase boost at the system unity-gain frequency, fC. In theory, the zeros and poles are placed symmetrically around fC, and the spread between the zeros and the poles is adjusted to give the desired phase boost at fC. However, in practice, if the crossover frequency is much higher than the LC double-pole frequency, this method of frequency compensation normally generates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. R3 - FB VREF C1 + 0 COMP -1 GAIN +1 -1 PHASE (DEG) R2 C3 GAIN (dB) C2 VOUT R1 The external inductor/output capacitor combination makes a more significant contribution to loop behavior. These components cause a second order LC roll-off at the output with 180 phase shift. This roll-off is what filters the PWM waveform, resulting in the desired DC output voltage, but this phase shift causes stability issues in the feedback loop and must be frequency compensated. At higher frequencies, the reactance of the output capacitor will approach its ESR, and the roll-off due to the capacitor will stop, leaving -20dB/decade and 90 of phase shift. FREQ -90 PHASE -180 BOOST -270 -380 7851 F14 Figure 15. Type 3 Amplifier Compensation 28 Rev A For more information www.analog.com LTC7851/LTC7851-1 APPLICATIONS INFORMATION If conditional stability is a concern, move the error amplifier's zero to a lower frequency to avoid excessive phase dip. The following equations can be used to compute the feedback compensation components value: fSW = Switching frequency fLC = 1 2 LCOUT fESR = 1 2 RESR COUT Inductor choose: fC = Crossover frequency = The inductor in typical LTC7851/LTC7851-1 circuits are chosen for a specific ripple current and saturation current. Given an input voltage range and an output voltage, the inductor value and operating frequency directly determine the ripple current. The inductor ripple current in buck mode is: fSW 10 1 2R2C1 f 1 fZ2(RES) = C = 5 2 (R1+ R3) C3 fZ1(ERR) = fLC = IL = 1 2R2(C1// C2) 1 fP2(RES ) = 5fC = 2R3C3 fP1(ERR) = fESR = Required error amplifier gain at frequency fC: 2 2 f f A 40log 1+ C - 20log 1+ C - 20log ( AMOD ) fLC fESR fLC fP2(RES) fP2(RES) - fZ2(RES) + 1+ f 1+ f fZ2(RES) R2 C C 20log * R1 fLC fP2(RES) fC 1+ f + f - f 1+ f ESR ESR LC C where AMOD is the modulator and line feedforward gain and is equal to: A MOD VIN(MAX) * DCMAX VRAMP Compensating a switching power supply feedback loop is a complex task. The applications shown in this data sheet show typical values, optimized for the power components shown. Though similar power components should suffice, substantially changing even one major power component may degrade performance significantly. Stability also may depend on circuit board layout. To verify the calculated component values, all new circuit designs should be prototyped and tested for stability. 12V/ V where DCMAX is the maximum duty cycle and VRAMP is the line feedforward compensated PWM ramp voltage. Once the value of resistor R1, poles and zeros location have been decided, the value of R2, C1, C2, R3 and C3 can be obtained from the previous equations. VOUT VOUT 1- ( f)(L) VIN Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Thus highest efficiency operation is obtained at low frequency with small ripple current. To achieve this, however, requires a large inductor. A reasonable starting point is to choose a ripple current between 20% and 40% of IO(MAX). Note that the largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductor in buck mode should be chosen according to: L VOUT VOUT 1 - f IL(MAX ) VIN(MAX ) Power MOSFET Selection The LTC7851/LTC7851-1 require at least two external N-channel power MOSFETs per channel, one for the top (main) switch and one or more for the bottom (synchronous) switch. The number, type and on-resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and For more information www.analog.com Rev A 29 LTC7851/LTC7851-1 APPLICATIONS INFORMATION much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than one-third of the input voltage. In applications where VIN >> VOUT, the top MOSFETs' onresistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low on-resistance with significantly reduced input capacitance for the main switch application in switching regulators. Selection criteria for the power MOSFETs include the onresistance RDS(ON), input capacitance, breakdown voltage and maximum output current. For maximum efficiency, on-resistance RDS(ON) and input capacitance should be minimized. Low RDS(ON) minimizes conduction losses and low input capacitance minimizes switching and transition losses. MOSFET input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (Figure 16). The curve is generated by forcing a constant-input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is VIN VGS MILLER EFFECT a V b QIN CMILLER = (QB - QA)/VDS + VGS - +V DS - 7851 F15 Figure 16. Gate Charge Characteristic due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain voltage, but can be adjusted for different VDS voltages by 30 multiplying by the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN Synchronous Switch Duty Cycle = VIN - VOUT VIN The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: VOUT 2 IMAX ) (1+ )RDS(ON) + ( VIN I VIN2 MAX (RDR )(CMILLER ) * 2 1 1 + ( f) VCC - VTH(IL) VTH(IL) V -V PSYNC = IN OUT (IMAX )2(1+ )RDS(0N) VIN PMAIN = where is the temperature dependency of RDS(ON), RDR is the effective top driver resistance, VIN is the drain potential and the change in drain potential in the particular application. VTH(IL) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique previously described. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve. Typical values for range from 0.005/C to 0.01/C depending on the particular MOSFET used. Rev A For more information www.analog.com LTC7851/LTC7851-1 APPLICATIONS INFORMATION Multiple MOSFETs can be used in parallel to lower RDS(ON) and meet the current and thermal requirements if desired. Suitable drivers such as the LTC4449 are capable of driving large gate capacitances without significantly slowing transition times. In fact, when driving MOSFETs with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (5 or less) to reduce noise and EMI caused by the fast transitions. MOSFET Driver Selection Gate driver ICs, DrMOSs and power blocks with an interface compatible with the LTC7851/LTC7851-1's three-state PWM outputs can be used. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the system produce losses, three main sources usually account for most of the losses in LTC7851/LTC7851-1 applications: 1) I2R losses, 2) topside MOSFET transition losses, 3) gate drive current. 1. I2R losses occur mainly in the DC resistances of the MOSFET, inductor, PCB routing, and input and output capacitor ESR. Since each MOSFET is only on for part of the cycle, its on-resistance is effectively multiplied by the percentage of the cycle it is on. Therefore in high step-down ratio applications the bottom MOSFET should have a much lower RDS(ON) than the top MOSFET. It is crucial that careful attention is paid to the layout of the power path on the PCB to minimize its resistance. In a 2-phase, 1.2V output, 60A system, 1m of PCB resistance at the output costs 5% in efficiency. 2. Transition losses apply only to the topside MOSFET but in 12V input applications are a very significant source of loss. They can be minimized by choosing a driver with very low drive resistance and choosing a MOSFET with low QG, RG and CRSS. 3. Gate drive current is equal to the sum of the top and bottom MOSFET gate charges multiplied by the frequency of operation. However, many drivers employ a linear regulator to reduce the input voltage to a lower gate drive voltage. This multiplies the gate loss by that step down ratio. In high frequency applications it may be worth using a secondary user supplied rail for gate drive to avoid the linear regulator. Other sources of loss include body or Schottky diode conduction during the driver dependent non-overlap time and inductor core losses. Design Example As a design example, consider a 4-phase application where VIN = 12V, VOUT = 1.2V, ILOAD = 120A and fSWITCH = 400kHz using the LTC7851. Assume that a secondary 5V supply is available for the LTC7851 VCC supply. The inductance value is chosen based on a 25% ripple assumption. Each channel supplies an average 30A to the load resulting in 7.7A peak-peak ripple: V VOUT * 1- OUT VIN IL = f *L A 250nH inductor per phase will create 10.8A peak-to-peak ripple. A 0.25H inductor with a DCR of 0.32m typical is selected from the Wurth 744301025 series. Float CLKIN and connect 30.9k from FREQ to SGND for 400kHz operation. Setting ILIMIT = 54A per phase leaves plenty of headroom for transient conditions while still adequately protecting against inductor saturation. This corresponds to: RILIM = 20 * 54A * 0.32m + 0.5V = 42.28k 20A Choose 42.2k. Rev A For more information www.analog.com 31 LTC7851/LTC7851-1 APPLICATIONS INFORMATION For the DCR sense filter network, we can choose R = 3.57k and C = 220nF to match the L/DCR time constant of the inductor. A loop crossover frequency of 45kHz provides good transient performance while still being well below the switching frequency of the converter. Twelve 330F 9m POSCAPs and eight 100F ceramic capacitors are chosen for the output capacitors to maintain supply regulation during severe transient conditions and to minimize output voltage ripple. The following compensation values (Figure 15) were determined empirically: R1 = 10k R2 = 6.04k R3 = 332 C1 = 2.2nF C2 = 100pF C3 = 3.3nF To set the output voltage equal to 1.2V: RFB1 = 10k, RFB2 = 10k The LTC4449 gate driver and external MOSFETs are chosen for the power stage. DrMOSs from Fairchild, Infineon, Vishay and others can also be used. Printed Circuit Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the converter. 1. The connection between the SGND pin on the LTC7851/ LTC7851-1 and all of the small-signal components surrounding the IC should be isolated from the system power ground. Place all decoupling capacitors, such as the ones on VCC, between ISNSP and ISNSN etc., close to the IC. In multiphase operation SGND should 32 be Kelvin-connected to the main ground node near the bottom terminal of the input capacitor. In dual-channel operation, SGND should be Kelvin-connected to the bottom terminal of the output capacitor for channel 2, and channel 1 should be remotely sensed using the remote sense differential amplifier. 2. Place the small-signal components away from high frequency switching nodes on the board. The LTC7851/ LTC7851-1 contains remote sensing of output voltage and inductor current and logic-level PWM outputs enabling the IC to be isolated from the power stage. 3. The PCB traces for remote voltage and current sense should avoid any high frequency switching nodes in the circuit and should ideally be shielded by ground planes. Each pair (VSNSP and VSNSN, ISNSP and ISNSN) should be routed parallel to one another with minimum spacing between them. If DCR sensing is used, place the top resistor (Figure 7b, R1) close to the switching node. 4. The input capacitor should be kept as close as possible to the power MOSFETs. The loop from the input capacitor's positive terminal, through the MOSFETs and back to the input capacitor's negative terminal should also be as small as possible. 5. If using discrete drivers and MOSFETs, check the stress on the MOSFETs by independently measuring the drainto-source voltages directly across the device terminals. Beware of inductive ringing that could exceed the maximum voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, choose a higher voltage rated MOSFET. 6. When cascading multiple LTC7851/LTC7851-1 ICs, minimize the capacitive load on the CLKOUT pin to minimize phase error. Kelvin all the LTC7851/LTC7851-1 IC grounds to the same point, typically SGND of the IC containing the master. Rev A For more information www.analog.com LTC7851/LTC7851-1 TYPICAL APPLICATIONS Dual-Output Converter: Triple Phase + Single Phase with Power Block Using the LTC7851-1, fSW = 400kHz VCC 30.9k 332 3.3nF VOUT1 4.99k 10k 2.2nF 10k 1 VCC 3.3V VOUT2 1 1F 20k 3.3nF 332 10k 100pF RUN1 FREQ CLKOUT CLKIN PGOOD1 RUN1 RUN2 FB1 ISNS1N 100pF 10k 100k COUT1,3,5,7: MURATA GRM31CR60J107M (100F, 6.3V, X5R, 1206) COUT2,4,6,8: PANASONIC EEFSX0E331ER (330F, 2.5V, 9m) D12S1R8130A: DELTA 4-PHASE POWER BLOCK 10k 2.2nF COMP1 COMP2 COMP3 ISNS1P PWM1 ISNS2N VSNSOUT1 VSNSOUT2 VSNSOUT3 VSNSN1 VSNSP1 SGND VSNSN2 VSNSP2 FB2 VCC FB3 ISNS2P PWM2 IAVG1 IAVG2 IAVG3 IAVG4 VINSNS ILIM1 ILIM2 ILIM3 TRACK/SS1 TRACK/SS2 TRACK/SS3 TRACK/SS4 ISNS3N LTC7851-1 VSNSN3 VSNSP3 VSNSN4 VSNSP4 VSNSOUT4 COMP4 ISNS3P PWM3 ISNS4N 7.15k FB4 RUN4 PGOOD4 RUN3 100k VCC ILIM4 ISNS4P PWM4 PGOOD2 PGOOD3 39.2k RUN1 100pF 4.99k 100pF 4.99k -CS1 VO1 COUT1 100F x 3 6.3V +CS1 PWM1 -CS2 COUT2 330F x 3 2.5V GND +CS2 PWM2 COUT3 100F x 3 6.3V 100pF VIN 39.2k + + COUT4 330F x 3 2.5V VO2 VIN 7V TO 14V 22F x4 VIN GND 100pF 4.99k 100pF 4.99k VCC 3.3V D12S1R8130A -CS3 +CS3 PWM3 -CS4 7V 4.7F VBIAS 7V VO3 COUT5 100F x 3 6.3V VOUT1 1.2V/95A + COUT6 330F x 3 2.5V GND COUT7 100F x 3 6.3V +CS4 PWM4 + COUT8 330F x 3 2.5V VO4 7851 TA02 VOUT2 1.8V/30A 121 100 0.01F x 4 (1 PER -CSn PIN) Rev A For more information www.analog.com 33 LTC7851/LTC7851-1 TYPICAL APPLICATIONS Quad-Output Converter: 4 Single Phase Outputs with DrMOS Using the LTC7851, fSW = 400kHz VIN 7V TO 14V COUT1,3,5,7: MURATA GRM31CR60J107M (100F, 6.3V, X5R, 1206) COUT2,4,6,8: PANASONIC EEFSX0E331ER (330F, 2.5V, 9m) L1-4: WURTH 744301025 (0.25H, DCR = 0.325m 7%) VCC 100k 30.9k 100pF 10k 332 20k VOUT1 7.15k FREQ CLKOUT CLKIN PGOOD1 ILIM1 IAVG1 PWM1 ISNS1P ISNS1N VSNSOUT1 VSNSP1 TRACK/SS1 RUN1 VSNSN1 TRACK/SS2 SGND RUN2 FB2 FB1 COMP1 2.2nF 3.3nF 10k 100pF COMP2 10k 332 VSNSOUT2 VSNSP2 10k 1F VCC FB3 100pF VINSNS LTC7851 VOUT3 332 4.99k 3.3nF 10k ILIM3 IAVG3 PWM3 ISNS3P ISNS3N VSNSN3 COMP4 VOUT4 332 4.02k 3.3nF 10k 15k 2.2nF VSNSOUT4 VSNSP4 VSNSN4 PGOOD4 PGOOD3 ILIM4 IAVG4 PWM4 ISNS4P ISNS4N 10k VCC 5V 1 10k 10k 2.2F 16V 22F x 2 VIN 43.2k VIN TRACK/SS3 RUN3 TRACK/SS4 RUN4 FB4 10k 22F x 2 43.2k PGOOD2 VSNSOUT3 VSNSP3 10k 100pF 10k VIN 100k 2.2nF 1 2.2F 16V VIN COMP3 10k VCC 5V 43.2k VSNSN2 1 VCC 5V ILIM2 IAVG2 PWM2 ISNS2P ISNS2N 2.2nF 3.3nF 15k VOUT2 6.04k 22F x 2 43.2k VCC VCC 5V 1 10k 10k 2.2F 16V 22F x 2 VCC 5V 1 10k 10k 2.2F 16V VIN BOOT FDMF5820DC PWM PHASE PVCC SW EN/FAULT# GL VCC TMON ZCD# AGND PGND VIN BOOT FDMF5820DC PWM PHASE PVCC SW EN/FAULT# GL VCC TMON ZCD# AGND PGND VIN BOOT FDMF5820DC PWM PHASE PVCC SW EN/FAULT# GL VCC TMON ZCD# AGND PGND VIN BOOT FDMF5820DC PWM PHASE PVCC SW EN/FAULT# GL VCC TMON ZCD# AGND PGND 0.22F L1 0.25H 3.57k 24.9k 0.1F 0.22F 0.22F 0.1F 0.22F 0.22F 0.1F 0.22F 0.22F + COUT5 100F x 2 6.3V + L4 0.25H 3.57k 24.9k COUT3 100F x 2 6.3V L3 0.25H 3.57k 24.9k + L2 0.25H 3.57k 24.9k COUT1 100F x 2 6.3V 0.1F 0.22F COUT7 100F x 2 6.3V + VOUT1 1.8V/30A COUT2 330F x 3 2.5V VOUT2 1.5V/30A COUT4 330F x 3 2.5V VOUT3 1.2V/30A COUT6 330F x 3 2.5V VOUT4 1.0V/30A COUT8 330F x 3 2.5V 7851 TA03 100k 100k VCC 34 Rev A For more information www.analog.com LTC7851/LTC7851-1 TYPICAL APPLICATIONS 4-Phase 1.2V/140A Converter with Discrete Gate Drivers and MOSFETs Using the LTC7851, fSW = 250kHz COUT1,3,5,7: MURATA GRM31CR60J107M (100F, 6.3V, X5R, 1206) COUT2,4,6,8: PANASONIC EEFSX0E331ER (330F, 2.5V, 9m) L1-4: COILCRAFT XAL1010-451ME (0.45H, DCR = 0.625m TYP., 0.72m MAX) VCC 5V 26.1k 100pF 332 10k 6.04k 2.2nF VCC 100k VOUT ISNS1N VCC 5V ILIM1 ILIM2 ILIM3 ILIM4 1F BG 22F x2 BSC050NE2LS x 2 BSC010NE2LS x 2 L1 0.45H 2.8k 0.22F VIN 4.7F 42.2k VCC BOOST VLOGIC TG LTC4449 TS IN ISNS2N VINSNS IAVG1 IAVG2 IAVG3 IAVG4 LTC7851 VCC VIN 5V4.7F 100pF PWM3 VSNSN2 GND BG 22F x2 BSC050NE2LS x 2 BSC010NE2LS x 2 2.8k 0.22F TRACK/SS1 TRACK/SS2 TRACK/SS3 TRACK/SS4 PGOOD2 PGOOD3 PGOOD4 VSNSN3 VIN VCC BOOST VLOGIC TG LTC4449 TS IN VSNSP3 VSNSN4 VSNSP4 PWM4 VCC 5V GND D4 BG 22F x2 BSC050NE2LS x 2 BSC010NE2LS x 2 VCC BOOST VLOGIC TG LTC4449 TS IN RUN4 RUN3 VCC RUN RUN VOUT 1.2V/140A L3 0.45H 2.8k 0.22F GND BG 22F x2 BSC050NE2LS x 2 + COUT5 100F x 2 6.3V COUT6 330F x 3 2.5V BSC010NE2LS x 2 L4 0.45H 2.8k 0.22F ISNS4P FB4 COUT3 100F x 2 6.3V COUT4 330F x 3 2.5V 0.22F VIN 4.7F + 0.22F D3 ISNS3N COUT2 330F x 3 2.5V L2 0.45H ISNS3P VSNSP2 + COUT1 100F x 2 6.3V 0.22F ISNS2P VSNSN1 FB2 VCC FB3 D2 PWM2 VSNSP1 1 GND VIN 7V TO 14V ISNS1P COMP1 COMP2 COMP3 COMP4 SGND VCC 5V 0.22F VCC BOOST TG VLOGIC LTC4449 TS IN FREQ CLKOUT CLKIN PGOOD1 RUN1 RUN2 PWM1 FB1 VSNSOUT1 VSNSOUT2 VSNSOUT3 VSNSOUT4 10k 4.7F RUN 3.3nF 10k D1 ISNS4N + COUT7 100F x 2 6.3V COUT8 330F x 3 2.5V 7851 TA04 Rev A For more information www.analog.com 35 LTC7851/LTC7851-1 PACKAGE DESCRIPTION UHH Package 58-Lead Plastic QFN (5mm x 9mm) (Reference LTC DWG # 05-08-1672 Rev O) Exposed Pad Variation AA 0.70 0.05 4.80 0.05 5.50 0.05 (2 SIDES) 4.10 0.05 (2 SIDES) 2.32 0.05 3.60 REF (2 SIDES) PACKAGE OUTLINE 0.20 0.05 0.40 BSC 7.20 REF (2 SIDES) 8.10 0.05 (2 SIDES) 9.50 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.75 0.05 5.00 0.10 (2 SIDES) PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 3.60 REF 57 0.00 - 0.05 58 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 9.00 0.10 (2 SIDES) 7.20 REF 4.80 0.10 2.32 0.10 1.60 REF 0.40 0.10 0.200 REF 0.200 REF 0.00 - 0.05 0.75 0.05 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 36 (UHH) QFN 0315 REV O 0.20 0.05 0.40 BSC BOTTOM VIEW--EXPOSED PAD R = 0.10 TYP 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev A For more information www.analog.com LTC7851/LTC7851-1 REVISION HISTORY REV DATE DESCRIPTION A 5/18 Revised fOSC Specs Changed Oscillator Frequency vs RFREQ Curve Modified Programming the Operating Frequency section PAGE NUMBER 4 7 18 Rev A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications moreby information www.analog.com subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. 37 LTC7851/LTC7851-1 TYPICAL APPLICATION Dual-Output Converter: 1.0V/60A and 1.2V/60A with DrMOS VIN 7V TO 14V 22F 22F VINSNS L3 0.25H DrMOS 3.57k 0.22F VCC 5V VOUT2 1.2V/60A 330F x6 + 1F 22F 100F x4 3.3nF 10k 332 PWM3 FREQ PWM2 ISNS3P ISNS3N VCC ISNS2P ISNS2N FB2,3 DrMOS 3.57k 0.22F 30.9k 100k L4 0.25H DrMOS 3.57k 0.22F 4.99k 10k 2.2nF 100pF 100pF LTC7851 VCC 100k PGOOD4 PGOOD1 PWM4 PWM1 RUN1 TRACK/SS1 RUN2 TRACK/SS2 RUN3 TRACK/SS3 RUN4 TRACK/SS4 ISNS4P ISNS1P ISNS4N ISNS1N VSNSP4 VSNSP1 VSNSN4 VSNSN1 VSNSOUT3,4 VSNSOUT1,2 10k PINS NOT USED IN THIS CIRCUIT: CLKIN CLKOUT VSNSP2 VSNSP3 VSNSN2 VSNSN3 PGOOD2 PGOOD3 L2 0.25H 42.2k COMP3,4 FB4 IAVG3,4 ILIM3,4 SGND COMP1,2 FB1 IAVG1,2 ILIM1,2 22F L1 0.25H DrMOS 0.22F VOUT1 1.0V/60A 330F x6 + 100F x4 3.57k 10k 4.02k 3.3nF 10k 100pF 42.2k 2.2nF 15k 332 100pF 7851 TA05 L1-4: WURTH ELEKTRONIK 744301025 (0.25H, DCR = 0.325m 7%) DrMOS: FAIRCHILD FDMF5820DC RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4630/ LTM4630A Dual 18A or Single 36A Step-Down DC/DC Module Regulator 4.5V VIN 15V, 0.6V VOUT 1.8V, 16mm x 16mm x 4.4mm BGA and LGA Packages LTM4677 Dual 18A or Single 36A Module Regulator with Digital Power System Management 4.5V VIN 16V, 0.5V VOUT 1.8V, I2C/PMBus Interface, 16mm x 16mm x 5mm BGA Package LTC3861 Dual, Multiphase, Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing Operates with Power Blocks, DrMOS or External MOSFETs, 3V VIN 24V LTC3774 Dual, Multiphase, Current Mode Synchronous Step-Down DC/DC Controller for Sub-Milliohm DCR Sensing Operates with DrMOS, Power Blocks or External Drivers/MOSFETs, 4.5V VIN 38V, 0.6V VOUT 3.5V LTC3875 Dual, 2-Phase, Synchronous Controller with Sub-Milliohm DCR Sensing and Temperature Compensation 4.5V VIN 38V, 0.6V VOUT 3.5V/5V Excellent Current Sharing When Paralleled LTC3884 Dual Output Multiphase Step-Down Controller with SubMilliohm DCR Sensing Current Mode Control and Digital Power System Management 4.5V VIN 38V, 0.5V VOUT (0.5%) 5.5V, 70ms Start-Up, I2C/PMBus Interface, Programmable Analog Loop Compensation, Input Current Sense LTC3882/ LTC3882-1 Dual Output Multiphase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management 3V VIN 38V, 0.5V VOUT0,1 5.25V, 0.5% VOUT Accuracy, I2C/PMBus Interface, Uses DrMOS or Power Blocks LTC2977 8-Channel, PMBus Power System Manager Featuring Accurate Output Voltage Measurement 0.25% TUE 16-Bit ADC, Voltage/Temperature Monitoring and Supervision LTC3887/ LTC3887-1 Dual Output, Multiphase Step-Down DC/DC Controller with with Digital Power System Management, 70ms Start-Up 4.5V VIN 24V, 0.5V VOUT0,1 (0.5%) 5.5V, 70ms Start-Up, I2C/PMBus Interface, LTC3887-1 Version Uses DrMOS or Power Blocks LTC4449 High Speed Synchronous N-Channel MOSFET Driver VIN Up to 38V, 4V VCC 6.5V, Adaptive Shoot-Through Protection, 2mm x 3mm DFN-8 LTC3886 60V Dual Output Step-Down DC/DC Controller with Digital Power System Management 4.5V VIN 60V, 0.5V VOUT0,1 (0.5%) 13.8V, 0.5% VOUT Accuracy, I2C/PMBus Interface, Input Current Sense, 70ms Start-Up 38 Rev A D16996-0-5/18(A) For more information www.analog.com www.analog.com (c) ANALOG DEVICES, INC. 2016-2018