ANALOG , LC?MOS DEVICES Complete, 12-Bit, 100 kHz, Sampling ADCs AD7870/AD7870A/AD7875/AD7876 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete Monolithic 12-Bit ADC with: 2 ws Track/Hold Amplifier aGNo REFOUT Ve Yoo 8 ys A/D Converter On-Chip Reference Laser-Trimmed Clock ote Parallel, Byte and Serial Digital Interface 72 dB SNR at 10 kHz Input Frequency (AD7870, AD7870A, AD7875) comp 57 ns Data Access Time av 12-BIT Low Power 60 mW typ REFERENCE DAG Variety of Input Ranges: +3 V for AD7870/AD7870A cuK cloce 0 to +5 V for AD7875 : +10 V for AD7876 COUNTER 12AVCLK TRACK/HOLD CONTROL CONVST toic PARALLEL GENERAL DESCRIPTION a sumsen | Mvaeeiorare, The AD7870/AD7870A/AD7875/AD7876 is a fast, complete, _ 12-bit A/D converter. It consists of a track/hold amplifier, 8 ps successive-approximation ADC, 3 V buried Zener reference and int versatile interface logic. The ADC features a self-contained internal clock which is laser trimmed to guarantee accurate con- trol of conversion time. No external clock timing components are required; the on-chip clock may be overridden by an exter- nal clock if required. PRODUCT HIGHLIGHTS 1. Complete 12-Bit ADC on a Chip. The AD7870/AD7870A/AD7875/AD7876 provides all the functions necessary for analog-to-digital conversion and com- The parts offer a choice of three data output formats: a single, bines a 12-bit ADC with internal clock, track/hold amplifier parallel, 12-bit word; two 8-bit bytes, or serial data. Fast bus and reference on a single chip. access times and standard control inputs ensure easy interfacing to modern microprocessors and digital signal processors. 2, Dynamic Specifications for DSP Users. The AD7870/AD7870A and AD7875 are fully specified and All parts operate from +5 V power supplies. The AD7870 and tested for ac parameters, including signal-to-noise ratio, har- AD7876 accept input signal ranges of +3 V and +10 V, respec- monic distortion and intermodulation distortion. tively, while the AD7875 accepts a unipolar 0 to +5 V input range. The parts can convert full power signals up to 50 kHz. 3. Fast Microprocessor Interface. Data access times of 57 ns make the parts compatible with The AD7870/AD7870A/AD7875/AD7876 feature de accuracy modern 8- and 16-bit microprocessors and digital signal pro- specifications such as linearity, full-scale and offset error. In cessors. Key digital timing parameters are tested and guaran- addition, the AD7870/AD7870A and AD7875 are fully specified teed over the full operating temperature range. for dynamic performance parameters including distortion and signal-to-noise ratio. The parts are fabricated in Analog Devices Linear Compatible CMOS (LC?MOS) process, a mixed technology process that combines precision bipolar circuits with low-power CMOS logic. The parts are available in a 24-pin, 0.3 inch-wide, plastic or her- metic dual-in-line package (DIP). The AD7870/AD7870A and AD7875 are available in a 28-pin plastic leaded chip carrier (PLCC), while the AD7876 is available and in a 24-pin small outline (SOIC) package. This is an abridged data sheet. To obtain the most recent version or complete data sheet, call our fax retrieval system at 1-800-446-6212. REV.B ANALOG-TO-DIGITAL CONVERTERS 2-317AD7870/AD7870A/AD7875/AD7876 SPECIFICATIONS w,, -+5 + sx, v. =5 V + 5%, AGND = DGND = 0 V, fx, = 2.5 MHz external, unless otherwise stated. All Specifications Tra t0 Trax unless otherwise noted.) AD7870/AD7870A Parameter J, A' | K,B' | 1, c'| st T Units Test Conditions/Comments DYNAMIC PERFORMANCE Signal to Noise Ratio? (SNR) @ +25C 70 70 72 69 69 dB min Vin = 10 kHz Sine Wave, fsamprn = 100 kHz Twin tO Trax 70 70 71 69 69 dB min Typically 71.5 dB for 0 < Vy < 50 kHz Total Harmonic Distortion (THD) -80 | -80 | -80 | -78 | -78 | dB max Vey= 10 KHz Sine Wave,fs,upce = 100kHz Typically ~86 dB for 0 < Vy, < 50-kHz Peak Harmonic or Spurious Noise ~80 | -80 | -80 | -78 | 78 | dB max Voy = 10 kHz, fsampre = 100 kHz Typically 86 dB for 0 < Viy < 50 kHz Intermodulation Distortion (IMD) Second Order Terms ~80 | ~-80 | -80 | -78 | -78 | dB max fa = 9 kHz, fo = 9.5 kHz, foampre = 50 KHz Third Order Terms ~80 | -80 | -80 | -78 | -78 | dB max fa = 9 kHz, fo = 9.5 kHz, fsampie = 50kHz Track/Hold Acquisition Time 2 2 2 2 2 ps max DC ACCURACY Resolution 12 12 12 12 12 Bits Minimum Resolution for which No Missing Codes are Guaranteed 12 12 12 12 12 Bits Integral Nonlinearity #2 | 1/2 | 1/4 | +1/2 | +1/2 | LSB typ Integra! Nonlinearity +1 +12 +1 LSB max Differential Nonlinearity th +1 +1 LSB max Bipolar Zero Error +5 +5 +5 +5 +5 LSB max Positive Full-Scale Error* +5 +5 +5 +5 +5 LSB max Negative Full-Scale Error* +5 +5 +5 +5 +5 LSB max ANALOG INPUT Input Voltage Range +3 +3 +3 +3 +3 Volts Input Current +500 | +500 | +500 | +500 | +500 | A max REFERENCE OUTPUT REF OUT @ +25C 2.99 | 2.99 | 2.99 | 2.99 | 2.99 | V min 3.01 3.01 3.01 3.01 3.01 V max REF OUT Tempco +60 | +60 | +35 | +60 | +35 | ppm/C max Reference Load Sensitivity(AREF OUT/AD | +1 +1 +1 +1 +1 mV max Reference Load Current Change (0-500 A) Reference Load Shouitd Not Be Changed During Conversion. LOGIC INPUTS Input High Voltage, Viuy 2.4 2.4 2.4 2.4 2.4 V min Vpp = 5V + 5% Input Low Voltage, Vinx 0.8 0.8 0.8 0.8 0.8 V max Vpp = 5V + 5% Input Current, Ing +10 | +10 | +10 | +10 | +10 | pA max Vin = 0 V to Vpp Input Current (12/8/CLK Input Only) +10 | +10 +10 | +10 | +10 | pA max Vin = Vsg to Von Input Capacitance, Cy 10 10 10 10 10 pF max LOGIC OUTPUTS Output High Voltage, Vou 4.0 4.0 4.0 4.0 4.0 V min Tsournce = 40 vA Output Low Voltage, Vor 0.4 0.4 0.4 0.4 0.4 V max Tgwe = 1.6 mA DB11-DB0O Floating-State Leakage Current +10 | +10 +10 | +10 | +10 | pA max Floating-State Output Capacitance* 15 15 15 15 15 pF max CONVERSION TIME External Clock (fonx = 2.5 MHz) 8 8 8 8 8 ws max Internal Clock 719 n9 7119 719 79 wS min/s max POWER REQUIREMENTS Vop +5 +5 +5 +5 +5 V nom +5% for Specified Performance Vss. -5 -5 -5 5 -5 V nom +5% for Specified Performance Ipp 13 13 13 13 13 mA max Typically 8 mA Isg 6 6 6 6 6 mA max Typically 4 mA Power Dissipation 95 95 95 95 95 mW max Typically 60 mW NOTES Temperature ranges are as follows: J, K, L Versions; 0 to +70C: A, B, C Versions; J Version. 2Vin (pk-pk) = +3 V. 3SNR calculation includes distortion and noise components. Measured with respect to internal reference and includes bipolar offset error. 5Sample tested @ +25C to ensure compliance. Specifications subject to change without notice. 2-318 ANALOG-TO-DIGITAL CONVERTERS 25C to +85C: $, T Versions; -55C to +125C. AD7870A has only REV. BAD7870/AD7870A/AD7875/AD7876 AD7875/AD7876 Parameter K,B | L, Cc? T Units Test Conditions/Comments DC ACCURACY Resolution 12 12 12 Bits Minimum Resolution for Which No Missing Codes Are Guaranteed 12 12 12 Bits Integral Nonlinearity @ +25C +1 +1/2 +1 LSB max Tin 10 Tyg, (AD7875 Only) +1 +1 +1 LSB max Tin 80 Trax (AD7876 Only) +1 +12 +1 LSB max Differential Nonlinearity +1 +1 1, +1.5 | LSB max Unipolar Offset Error (AD7875 Only) +5 +5 +5 LSB max Bipolar Zero Error (AD7876 Only) +6 +2 +6 LSB max Full-Scale Error at +25C? +8 +8 +8 LSB max Typical full-scale error is +1 LSB Full-Scale TC? +60 +35 +60 ppm/C max Typical TC is +20 ppm/C Track/Hold Acquisition Time 2 2 2 ps max DYNAMIC PERFORMANCE? (AD7875 ONLY) Signal-to-Noise Ratio* (SNR) @ +25C 70 72 69 dB min Vin = 10 kHz Sine Wave, fgsampie = 100 kHz Tran 10 Tinax 70 val 69 dB min Typically 71.5 dB for 0 < Vj < 50 kHz Total Harmonic Distortion (THD) -80 80 78 dB max Vin = 10 kHz Sine Wave, fsampre = 100 kHz Typically 86 dB for 0 < V,y < 50 kHz Peak Harmonic or Spurious Noise 80 ~-80 -78 dB max Vin = 10 kHz, fgsamerE = 100 kHz Typically 86 dB for 0 < Vix < 50 kHz Intermodulation Distortion (IMD) Second Order Terms 80 80 -78 dB max fa = 9 kHz, fb = 9.5 kHz, fsampre = 50 kHz Third Order Terms 80 80 78 dB max fa = 9 kHz, fo = 9.5 kHz, foanpte = 50 kHz ANALOG INPUT AD7875 Input Voltage Range Oto +5 | Oto +5 | Oto +5 Volts AD7875 Input Current 500 500 500 yA max AD7876 Input Voltage Range +10 +10 +10 Valts AD7876 Input Current +600 +600 +600 pA max REFERENCE OUTPUT REF OUT @ +25C 2.99 2.99 2.99 V min 3.01 3.01 3.01 V max REF OUT Tempco +60 #35 +60 ppm/C max Typical Tempco is +20 ppm/C Reference Load Sensitivity (AREF OUT/AD 1 -1 -1 mV max Reference Load Current Change (0-500 A) Reference Load Should Not Be Changed During Conversion. LOGIC INPUTS Input High Voltage, Vinu 2.4 2.4 2.4 V min Vpn = 5 V + 5% Input Low Voltage, Vist 0.8 0.8 0.8 V max Vpp = 5V + 5% Input Current, I, +10 +10 +10 A max Vin = 90 V to Vop Input Current (12/8/CLK Input Only) +10 +10 +10 pA max Vin = Vgs to Vpp Input Capacitance, C), 10 10 10 pF max LOGIC OUTPUTS Output High Voltage, Voy 4.0 4.0 4.0 V min Isource = 40 pA Output Low Voltage, Vo, 0.4 0.4 0.4 V max Isinx = 1.6 mA DB11-DBo0 Floating-State Leakage Current 10 10 10 pA max Floating-State Output Capacitance* 15 15 15 pF max CONVERSION TIME External Clock (fo). = 2.5 MHz) 8 8 8 ws max Internal Clock 79 7/9 79 ys min/ps max POWER REQUIREMENTS As per AD7870/AD7870A | NOTES Temperature ranges are as follows: AD7875: K, L Versions, 0 to +70C; B, C Versions, 40C to +85C; T Version, 55C to +125C. AD7876: B, C Ver- sions, 40C to +85C; T Version, 55C to +125C. 7Includes internal reference error and is calculated after unipolar offset error (AD7875) or bipolar zero error (AD7876) has been adjusted out. Full-scale error refers to both positive and negative full-scale error for the AD7876. *Dynamic performance parameters are not tested on the AD7876 but these are typically the same as for the AD7875. SNR calculation includes distortion and noise components. Sample tested @ +25C to ensure compliance. Specifications subject to change without notice. REV. B ANALOG-TO-DIGITAL CONVERTERS 2-319AD7870/AD7870A/AD7875/AD7876 TIMING CHARACTERISTICS': 2 ,, = +5 + 5%, Vo = 5 + 5%, AGND = DGND = 0 V, See Figures 9, 10,11 and 12, Limit at T,nins Tmax Limit at Trains Tmax Parameter J, K, L, A, B, C Versions) (S, T Versions) Units Conditions/Comments t 50 50 ns min CONVST Pulse Width io 0 0 ns min CS to RD Setup Time (Mode 1) 3 60 75 ns min RD Pulse Width ty 0 0 ns min CS to RD Hold Time (Mode 1) ls 70 70 ns max RD to INT Delay t 57 70 ns max Data Access Time after RD t,* 5 5 ns min Bus Relinquish Time after RD 50 50 ns max tg 0 0 ns min HBEN to RD Setup Time tg 0 0 ns min HBEN to RD Hold Time tho 100 100 ns min SSTRB to SCLK Falling Edge Setup Time ty 370 370 ns min SCLK Cycle Time t2 135 150 ns max SCLK to Valid Data Delay. C, =35 pF tis 20 20 ns min SCLK Rising Edge to SSTRB 100 100 ns max us 10 10 ns min Bus Relinquish Time after SCLK 100 100 ns max us 60 60 ns min CS to RD Setup Time (Mode 2) lie 120 120 ns max CS to BUSY Propagation Delay ti 200 200 ns min Data Setup Time Prior to BUSY tig 0 0 ns min CS to RD Hold Time (Mode 2) the 0 0 ns min HBEN to CS Setup Time toy 0 0 ns min HBEN to CS Hold Time NOTES Timing specifications in bold print are 100% production tested. All other times are sample tested at + 25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2Serial timing is measured with a 4.7 kQ pull-up resistor on SDATA and SSTRB and a 2 k{ pull-up on SCLK. The capacitance on all three outputs is 35 pF. *t, is measured with the load circuits of Figure } and defined as the time required for an output to cross 0.8 V or 2.4 V. +t, is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2. *SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40. *SDATA will drive higher capacitive loads but this will add to 1,, since it increases the external RC time constant (4.7 kMIIC,) and hence the time to reach 2.4 V. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* Vpp toAGND ...........0..00002. -0.3Vt0+7V +8v Vsg tO AGND .. 0. 0.-000.02.02......05. +0.3V10-7V AGND toDGND .............. 0.3 V to Vpp +0.3 V S6kn Vin t9 AGND .......0...-00. 000006. -1SVto +15 V DBN ? DEN REF OUTtoAGND ................... 0V to Vip | I Digital Inputs to DGND ......... -0.3 V to Vpp +0.3 V 56k. ~~ SOpF 50pF Digital Outputs to DGND ........ -0.3 V to Vpp +0.3V Operating Temperature Range DGND DGND Commercial (J, K, L Versions - AD7870) ..... 0 to +70C : . Commercial (K, L Versions - AD7875) ....... 0 to +70C a. High-Z to Von b. High-Z to Voy Industrial (A, B, C Versions - AD7870) .. . 25C to +85C Figure 1. Load Circuits for Access Time Industrial (B, C Versions AD7875/AD7876) Lene eee eee eee, -40C to +85C +8V Extended (S, T Versions)............ SSC to +125C Storage Temperature Range ........... 65C to + 150C aKa Lead Temperature (Soldering, 10 sec) ........... +300C DBN DBN Power Dissipation (Any Package) to +75C ....... 450 mW Derates above +75C by ...........2.00006 10 mW/C 3kn 10pF 10pF *Stresses above thase listed under Absolute Maximum Ratings may cause a J permanent damage to the device. This is a stress rating only and functional DGND operation of the device at these or any other conditions above those listed in DGND the operational sections of this specification is not implied. Exposure 8. Voy to High-Z b. Vo, to High-Z ieee clabinm rating conditions for extended periods may affect Figure 2. Load Circuits for Ou tput Float Delay CAUTION however, permanent damage may occur on unconnected devices subject to high energy electro- ( static fields. Unused devices must be stored in conductive foam or shunts. The protective foam ae aah es 7 should be discharged to the destination socket before devices are inserted. eee Cia aT et ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; Tevet en 2-320 ANALOG-TO-DIGITAL CONVERTERS REV. BAD7870/AD7870A/AD7875/AD7876 AD7870 ORDERING GUIDE Integral Temperature Vin Voltage | SNR Nonlinearity | Package Model? ? Range Range (V) (dBs) | (LSB) Option? AD7870AJN | 0 to +70C +3 70 min | +1/2 typ N-24 AD7870JN 0 to +70C +3 70 min | +1/2 typ N-24 AD7870KN | 0 to +70C +3 70 min | +1 max N-24 AD7870LN 0 to +70C +3 72 min | +1/2 max N-24 AD7870JP 0 to +70C +3 70 min | +1/2 typ P-28A AD7870KP | 0 to +70C +3 70 min | +1 max P-28A AD7870LP 0 to +70C +3 72 min | +1/2 max P-28A AD7870AQ 25C to + 85C +3 70 min | +1/2 typ Q-24 AD7870BQ 25C to +85C +3 70 min | +1 max Q-24 AD7870CQ 25C to +85C +3 72 min | +1/2 max Q-24 AD7870SQ* | ~-55C to +125C +3 69 min | +1/2 typ Q-24 AD7870TQ* | 55C to +125C +3 69 min | +1 max Q-24 NOTES 'To order MIL-STD-883, Class B, processed parts, add /883B to part number. Contact local sales office for military data sheet. Contact local sales office for LCCC (Leadless Ceramic Chip Carrier) availability. 3N = Narrow Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip. For outline information see Package Information section. Available to /883B processing only. AD7875 ORDERING GUIDE Integral Temperature Vin Voltage | SNR Nonlinearity | Package Model! Range Range (V) (dBs) | (LSB) Option? AD7875KN | 0 to +70C Oto +5 70 min | +1 max N-24 AD7875LN | 0 to +70C Oto +5 72 min | +1/2 max N-24 AD7875KR | 0 to +70C Oto +5 70 min | +1 max R-24 AD7875KP | 0 to +70C Oto +5 70 min | +1 max P-28A AD7875LP 0 to +70C Oto +5 72 min | +1/2 max P-28A AD7875BQ 40C to +85C Oto +5 70 min | +1 max Q-24 AD7875CQ 40C to +85C Oto +5 72 min | +1/2 max Q-24 AD7875TQ? | 55C to +125C | 0 to +5 69 min | +1 max Q-24 NOTES 'To order MIL-STD-883, Class B, processed parts, add /883B to part number. Contact local sales office for military data sheet. *N = Narrow Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; R = Small Outline IC (SOIC). For outline information see Package Information section. 3 Available to /883B processing only. AD7876 ORDERING GUIDE Integral Temperature Vin Voltage | Nonlinearity | Package Model! Range Range (V) (LSB) Option AD7876BN 40C to +85C +10 +1 max N-24 AD7876CN 40C to +85C +10. +1/2 max N-24 AD7876BR 40C to +85C +10 +1 max R-24 AD7876CR 40C to +85C +10 + 1/2 max R-24 AD7876BQ 40C to +85C +10 +1 max Q-24 AD7876CQ_ | 40C to +85C +10 1/2 max Q-24 AD7876TQ? | SS*C to +125C | +10 +1 max Q-24 NOTES 'To order MIL-STD-883, Class B, processed parts, add /883B to part number. Contact local sales office for military data sheet. ?N = Narrow Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC). For outline information see Package Information section. Available to /883B processing only. REV. B ANALOG-TO-DIGITAL CONVERTERS 2-321AD7870/AD7870A/AD7875/AD7876 PIN FUNCTION DESCRIPTION DIP Pin Pin No. Mnemonic Function RD Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs. 2 BUSY/INT _ Busy/Interrupt, Active low logic output indicating converter status. See timing diagrams. 3 CLK Clock input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying this pin to V5 enables the internal laser-trimmed clock oscillator. 4 DBII/HBEN Data Bit 11 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 12/8/CLK input (see below). When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is low, DB7/LOW to DBO/DB8 become DB7 to DBO. With HBEN high, DB7/LOW to DB0/DB8 are used for the upper byte of data (see Table I). 5 DB10/SSTRB Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output. SSTRB is an active low open-drain output that provides a strobe or framing pulse for serial data. An external 4.7 kO pull-up resis- tor is required on SSTRB. 6 DB9/SCLK __ Data Bit 9/Serial Clock. When 12-bit parailel data is selected, this pin provides the DB9 output. SCLK is the gated serial clock output derived from the internal or external ADC clock. If the 12/8/CLK input is at 5 V, then SCLK runs continuously. If 12/8/CLK is at 0 V, then SCLK is gated off after serial transmission is complete. SCLK is an open-drain output and requires an external 2 kO: pull-up resistor. 7 DB8/SDATA Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA is an open- drain serial data output which is used with SCLK and SSTRB for serial data transfer. Serial data is valid on the fall- ing edge of SCLK while SSTRB is low. An external 4.7 kQ pull-up resistor is required on SDATA. 8-11 DB7/LOW- _ Three-state data outputs which are controlled by CS and RD. Their function depends on the 12/8/CLK and HBEN DB4/LOW inputs. With 12/8/CLK high, they are always DB7-DB4. With 12/8/CLK low or 5 V, their function is controlled by HBEN (see Table I). 12 DGND Digital Ground. Ground reference for digital circuitry. 13-16 DB3/DBl1l- Three-state data outputs which are controlled by CS and RD. Their function depends on the 12/8/CLK and HBEN DB0/DB8 inputs. With/12/8/CLK high, they are always DB3-DBO. With 12/8/CLK low or 5 V, their function is controlled by HBEN (see Table I). 17 Vpp Positive Supply, +5 V +5%. 18 AGND Analog Ground. Ground reference for track/hold, reference and DAC. 19 REF OUT Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is 500 yA. 20 Vin Analog Input. The analog input range is +3 V for the AD7870, +10 V for the AD7876 and 0 to +5 V for the AD7875. 21 Vss Negative Supply, 5 V +5%. 22 12/8/CLK Three Function Input. Defines the data format and serial clock format. With this pin at +5 V, the output data for- mat is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK is not continuous. With this pin at ~5 V, byte or serial data is again available but SCLK is now continuous. 23 CONVST Convert Start. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. This input is asynchronous to the CLK input. 24 cs Chip Select. Active low logic_input. The device is selected when this input is active. With CONVST tied low, a new conversion is initiated when CS goes low. HBEN | DB7/LOW | DB6/LOW | DB5/LOW | DB4/LOW | DB3/DB11 DB2/DB10 | DBI/DB9 | DB0O/DB8 HIGH | LOW LOW LOW Low DB11 (MSB) | DB10 DB9 DBS LOW DB7 DB6 DB5 DB4 DB3 DB2 DBL DBO (LSB) Table |. Output Data for Byte Interfacing PIN CONFIGURATIONS! DIP and SOIC? a ws BUSY int conveT cx [3 | 128/CLK parrneen [4 | Ves DB1HBEN ppiossire {5 | VIN 0810557RE ossscik [6 | REF OUT DBSISCLK DeE/SDATA tNot to Seale] AGND nc (Not to Scetel DBB/SDATA car.ow [a] Yoo psrow f pasiow [5] oBa0B8 paenow DBSLOW p81089 peaitow [17] OB2/DB10 PIN CONFIGURATIONS ARE THE SAME FOR Lz] 3] jdm oano [12] DB3:DBIt THE AD7870, AD7875 AND AD7876. *THE ADTE70 AND AD7875 ARE AVAILABLE IN ze = 2 38 iP AND PLCC; THE AD7870A IS AVAILABLE IV 8 84e PLASTIC DIP; THE ADIT AND AD7876 ARE & & S @ AVAILABLE IN SOIC AND Di a8 @ 8 Ne = NO cONNECT 2-322 ANALOG-TO-DIGITAL CONVERTERS REV. B