HTSC424.xxx - 0402 High Temperature Silicon Capacitor Rev 3.1 Key features Key applications n High stability up to 200C: n All applications up to 200C, such as military, aerospace and automotive industries w Voltage <0.1 %/V n High reliability applications w Negligible capacitance loss through aging n Replacement of X7R and C0G dielectrics n Decoupling / Filtering / Charge pump (i.e.: motor management, temperature sensors) n Downsizing w Temperature <1% (-55 C to +200 C) n Unique high capacitance in EIA/0402 package size, up to 47 nF n High reliability (FIT <0.017 parts / billion hours) n Low leakage current down to 100 pA n Low ESL and Low ESR n Suitable for lead free reflow-soldering *Please refer to our assembly Application Note for further recommendations Thanks to the unique IPDiA Silicon capacitor The IPDiA technology offers industry leading technology, most of the problems encountered in performances relative to Failure rate with a demanding applications can be solved. FIT<0.017. High Temperature Silicon Capacitors are This technology also offers high reliability, up to dedicated to applications where reliability up to 10 200C is the main parameter. technologies, such as Tantalum or MLCC, and This technology features a capacitor integration capability (up to 250nF/mm ) which times better than alternative capacitor eliminates cracking phenomena. offers This Silicon based technology is RoHS compliant capacitance value similar to X7R dielectric, but and compatible with lead free reflow soldering with better electrical performances than C0G/NP0 process. dielectrics, up to 200C. HTSC provides the highest capacitor stability over the full -55C/+200C temperature range in the market with a Temperature coefficient Lower than 1%. HTSC424.xxx Electrical specification Capacitance value 10 15 22 Contact Contact Contact IPDIA Sales IPDIA Sales IPDIA Sales 100 pF: 150 pF: 220 pF: 10 pF 935.132.424.310 935.132.424.315 935.132.424.322 1 nF: 1.5 nF: 2.2 nF: 0.1 nF 935.132.424.410 935.132.424.415 935.132.424.422 10 nF: 15 nF: 22 nF: 935.132.424.510 935.132.424.515 935.132.424.522 100 nF: 10 nF 935.132.424.610 1 nF 47 Parameters Capacitance range Capacitance tolerances Operating temperature range Storage temperatures Temperature coefficient Breakdown voltage (BV) Capacitance variation versus RVDC Equivalent Serial Inductor (ESL) Equivalent Serial Resistor (ESR) 68 Contact Contact IPDIA Sales IPDIA Sales 330 pF: 470 pF: 935.132.424.333 935.132.424.347 3.3 nF: 4.7 nF: 935.132.424.433 935.132.424.447 47 nF: 33 nF: 935.132.424.547 935.132.424.533 935.132.724.547 Contact IPDIA Sales 680 pF: 935.132.424.368 6.8 nF: 935.132.424.468 Contact IPDIA Sales Value 100 pF to 100 nF(***) 15 %(***) -55 C to 200 C (**) - 70 C to 215 C <1 %, from -55 C to +200 C 11 VDC, 30VDC 0.1 % /V (from 0 V to RVDC) Max 100 pH (***) Max 400mW 50GW min @ 3V,25C 20GW min @ 3V,200C Negligible, < 0.001 % / 1000 h FIT<0.017 parts / billion hours, (*) Max 400 m Insulation resistance (*) Thinner thickness (as low as 100 m thick) available, see Low Profile Silicon Capacitor product: LPSC Ageing Reliability Capacitor height (**) Extended temperature range (up to +250 C) available, see Xtreme Temperature Silicon Capacitor product: XTSC (***) Other values on request. DC Voltage stability MLCC capacitors vs. PICS ESL (nH) @25C 0402 C0G(NPO) vs. PICS 1,1 10 PICS 1 0 -10 C0G 0,9 C0G 0,8 -20 0,7 -30 ESL(nH) Capacitance change (%) Unit 1 pF 33 X7R -40 -50 0,6 0,5 0,4 -60 0,3 -70 -80 0,2 Y5V PICS 0,1 -90 0 -100 0 1 2 3 4 5 6 0 7 50 100 150 Fig.1 Capacitance change versus temperature variation compared with alternative dielectrics 200 250 300 350 400 450 500 550 600 650 700 750 Fig.3 ESL versus capacitance value compared with alternative dielectrics Fig.2 Capacitance change versus voltage variation compared with alternative dielectrics Part Number 935.132. i.e.: 47 nF/0402 case (HTSC type) a 935.132.424.547 B.2 S. Breakdown Voltage 4 = 11V 7 = 30V U Size 4 = 0402 xx Unit 0 = 10 f 1 = 0.1 p 2=1p 3 = 10 p 4 = 0.1 n Value 10 15 22 33 47 68 5=1n 6 = 10 n 7 = 0.1 8=1 9 = 10 Termination and Outline Termination Lead-free nickel/solder coating compatible with automatic soldering technologies: reflow and manual. Package outline Typical dimensions, all dimensions in mm. L Typ. 0402 W Comp. size L 1.200.05 W 0.700.05 Land pattern IPD component Solder Resist (0402 PCB footprint) Packaging Tape and reel, tray, waffle pack or wafer delivery. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 800 Capacitance (pF) Bias voltage (V) For more information, please visit: http://www.ipdia.com To contact us, email to: sales@ipdia.com Date of release: 28th February 2014 Document identifier: CL431 111 615 132 850 900 950 1000 IPD Capacitor Assembly Set Up Rev 1.0 Application Note Outline Silicon Capacitor for surface mounting device (SMD) assembly is a Wafer Level Chip Scale Packaging with the following features: x x x x Package dedicated to solve tombstoning effect of small SMD package; Package compatible with SMD assembly; Package without underfilling step; Interconnect available with various optional finishing for specific assembly. Assembly consideration x x x Standard pick & place equipment dedicated to WLCSP down to 400m pitch. Solder paste type 3 in most cases of EIA size. Reflow has to be done with standard lead-free profile (for SAC alloys) or according to JEDEC recommendations J-STD 020D-01. Lead Leadfree Tp: 235 C Tp: 260 C TL: 183 C TL: 217 C Ts min: 100 C Ts min: 150 C Ts max: 150 C Ts max: 200 C tL: 60-150 s tL: 60-150 s Process recommendation After soldering, no solder paste should touch the side of the capacitor die as that might results in leakage currents due to remaining flux. In order to use IPDiA standard capacitors within the JEDEC format and recommendation, the solder flux must be cleaned after reflow soldering step. Notes: for a proper flux cleaning process, "rosin" flux type (R) or "water soluble" flux type (WS) is recommended for the solder printing material. "No clean" flux (NC) solder paste is not recommended. In case the flux is not cleaned after the reflow soldering, the standard JEDEC would probably not be appropriate and the solder volume must be controlled: - using smallest aperture design for the stencil, and using finer solder paste type 4 or 5 for a proper printing process. - Mirroring pads would be the best recommendation Application Note Pad recommendation The capacitor is compatible with generic requirements for flip chip design (IPC7094). Standard IPDiA 3D package can be compliant with established EIA size (0201, 0402, 0603, ...). Die size and land pattern dimensions is set up according to following range : EIA size 0201 0402 0603 0805 1206 1812 Dimension max(X1 x X2) mm 0.86x0.66 1.26x0.76 1.86x1.16 2.26x1.46 3.46x1.86 4.76x3.66 Typical . die thickness X3 (mm) 0.1 or 0.4 Typical pad size* (mm) 0.15x0.40 0.30x0.50 0.40x0.90 0.50x1.20 0.60x1.60 0.90x3.40 Typical pad separation (X4 mm) 0.3 0.4 0.8 1 2 2.7 X3 X2 X1 Top side silicon Typ.UBM thickness 3 to 5 m X4 After soldering, no solder paste should touch the side of the capacitor die as that might result in leakage currents due to remaining flux. Rev 1.0 2 of 3 Application Note Manual Handling Considerations These capacitors are designed to be mounted with a standard SMT line, using solder printing step, pick and place machine and a final reflow soldering step. In case of manual handling and mounting conditions, please follow below recommendations: x x x x Minimize mechanical pressure on the capacitors (use of a vacuum nozzle is recommended). Use of organic tip instead of metal tip for the nozzle. Minimize temperature shocks (Substrate pre-heating is recommended). No wire bonding on 0402 47nF, 0402 100nF, 1206 1F and 1812 3,3F Process steps: x On substrate, form the solder meniscus on each land pattern targeting 100 m height after reflow (screen printing, dispensing solder paste or by wire soldering). x Pick the capacitor from the tape & reel or the Gel Pack keeping backside visible using a vacuum nozzle and organic tip. x Temporary place the capacitor on land pattern assuming the solder paste (Flux) will stick and maintain the capacitor. x Reflow the assembly module with a dedicated thermal profile (see reflow recommendation profile). Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. For more information, please visit: http://www.ipdia.com To contact us, email to: sales@ipdia.com Date of release: 20th April 2012 Document identifier: Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IPDiA: 935132424410-T3N 935132424510-T3N 935132424533-T3N 935132424547-T3N 935132424610-T3N 935132424310-T1N 935132424310-T3N 935132424347-T1N 935132424347-T3N 935132424522-T3N 935132424547-T1N 935132424610-T1N 935132724547-T3N 935132424522-T1N 935132724547-T1N