935132724547-T1N - IPDiA - Datasheet.Live

HTSC424.xxx - 0402 High

Temperature

Silicon Capacitor

Rev 3.1

Thanks to the unique IPDiA Silicon capacitor

technology, most of the problems encountered in

demanding

applications can be solved.

igh Temperature Silicon C

apacitors are

dedicated to applications where

reliability

up to

200°C

is the main parameter.

This technology features a capacitor integration

capability (up to 250nF/mm

) which offers

capacitance value

similar to X7R dielectric, but

with better

electrical performances than C0G/NP0

dielectrics, up

to 200°C.

HTSC provides the highest capacitor stability

over the full

55°C/+200°C temperature range in

the market with a

Temperature coefficient

Lower than ±1%.

The IPDiA technology offers industry leading

performances relative to

Failure rate

with a

FIT<0.

017.

This technology also offers

high reliability,

up to

10 times better than alternative capacitor

technologies, such as Tantalum or MLCC, and

elimina

tes cracking phenomena.

Thi

s Silicon based technology is Ro

HS compliant

and compatible with lead free reflow soldering

process.

Key features

n High stability up to 200°C:

w Temperature <±1% (-55 °C to +200 °C)

w Voltage <0.1 %/V

Negligible capacitance loss through aging

n Unique high capacitance

in EIA/0402 package

size, up to 47 nF

High reliability (FIT <0.017 parts / billion hours)

n Low leakage current down to 100 pA

n Low ESL and Low ESR

n Suitable for lead free reflow-soldering

*Please refer

to our assembly Application Note for further recommendations

Key applications

n All applications up to 200°C, such as

military, aerospace and automotive

industries

n High reliability applications

n Replacement of X7R and C0G dielectrics

n Decoupling / Filtering / Charge pump

(i.e.: motor management, temperature

sensors)

n Downsizing

Reproduction in whole or in part is prohibited without the

prior written consent of the copyright owner. The information

presented in this document does not form part of any

quotation or contract, is believed to be accurate and reliable

and may be changed without notice. No liability will be

accepted by the publisher for any consequence of its use.

Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

For more information, please visit: http://www.ipdia.com

To contact us, email to: sales@ipdia.com

Date of release: 28th February 2014

Document identifier: CL431 111 615 132

HTSC424.xxx

Electrical specification

(*) Thinner thickness (as low as 100 µm thick) available, see Low Profile Silicon Capacitor product: LPSC

(**) Extended temperature range (up to +250 °C) available, see Xtreme Temperature Silicon Capacitor product: XTSC

(***) Other values on request.

Part Number

935.132. B.2 S. U xx

i.e.: 47 nF/0402 case (HTSC type)

à 935.132.424.547

Termination and Outline

(0402 PCB footprint)

Packaging

Parameters

Value

Capacitance range

100 pF to 100 nF(***)

Capacitance tolerances

±15 %(***)

Operating temperature range

-55 °C to 200 °C (**)

Storage temperatures

- 70 °C to 215 °C

Temperature coefficient

<±1 %, from -55 °C to +200 °C

Breakdown voltage (BV)

11 VDC, 30VDC

Capacitance variation versus

RVDC

0.1 % /V (from 0 V to RVDC)

Equivalent Serial Inductor (ESL)

Max 100 pH

Equivalent Serial Resistor (ESR)

Max 400mW(***)

Insulation resistance

50G

min @ 3V,25°C

20G

min @ 3V,200°C

Ageing

Negligible, < 0.001 % / 1000 h

Reliability

FIT<0.017 parts / billion hours,

Capacitor height

Max 400 µm (*)

Capacitance value

Unit

1 pF

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10 pF

100 pF:

935.132.424.310

150 pF:

935.132.424.315

220 pF:

935.132.424.322

330 pF:

935.132.424.333

470 pF:

935.132.424.347

680 pF:

935.132.424.368

0.1 nF

1 nF:

935.132.424.410

1.5 nF:

935.132.424.415

2.2 nF:

935.132.424.422

3.3 nF:

935.132.424.433

4.7 nF:

935.132.424.447

6.8 nF:

935.132.424.468

1 nF

10 nF:

935.132.424.510

15 nF:

935.132.424.515

22 nF:

935.132.424.522

33 nF:

935.132.424.533

47 nF:

935.13

.424.547

935.132.724.547

Contact

IPDIA Sales

10 nF

100 nF:

935.132.424.610

Typ.

0402

Comp.

size

1.20

0.05

0.70

0.05

Termination

Lead

free nickel/solder coating compatible

with automatic soldering

technologies:

reflow and manual.

Typical dimensions, all dimensions in mm.

Package outline

Land

pattern

IPD

component

Solder

Resist

Tape and reel, tray, waffle pack or wafer delivery.

Fig.1 Capacitance change versus temperature

variation compar

ed with alternative dielectrics

DC Voltage stability

MLCC capacitors vs. PICS

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0 1 2 3 4 5 6 7

Bias voltage (V)

Capacitance change (%)

Y5V

X7R

PICS

C0G

Fig.2 Capacitance change versus voltage

variation compared with alternative

dielectrics

ESL (nH) @25°C

0402 C0G(NPO) vs. PICS

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1,1

0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000

Capacitance (pF)

ESL(nH)

PICS

C0G

Fig.3 ESL versus capacitance value

compared with alternative dielectrics

Size

4 = 0402

Breakdown

Voltage

4 = 11V

7 = 30V

5 = 1 n

6 = 10 n

7 = 0.1 µ

8 = 1 µ

9 = 10 µ

Unit

0 = 10 f

1 = 0.1

2 = 1 p

3 = 10 p

4 = 0.1 n

Value

IPD Capacitor Assembly Set Up

Rev 1.0

Outline

Silicon Capacitor for surface mounting device (SMD) assembly is a Wafer Level Chip Scale Packaging

with the following features:

xPackage dedicated to solve tombstoning effect of small SMD package;

xPackage compatible with SMD assembly;

xPackage without underfilling step;

xInterconnect available with various optional finishing for specific assembly.

Assembly consideration

xStandard pick & place equipment dedicated to WLCSP down to 400µm pitch.

xSolder paste type 3 in most cases of EIA size.

xReflow has to be done with standard lead-free profile (for SAC alloys) or

according to JEDEC recommendations J-STD 020D-01.

Lead

Tp: 235 °C

TL: 183 °C

Ts min: 100 °C

Ts max: 150 °C

tL: 60-150 s

Leadfree

Tp: 260 °C

TL: 217 °C

Ts min: 150 °C

Ts max: 200 °C

tL: 60-150 s

Process recommendation

After soldering, no solder paste should touch the side of the capacitor die as that might results in

leakage currents due to remaining flux.

In order to use IPDiA standard capacitors within the JEDEC format and recommendation, the solder

flux must be cleaned after reflow soldering step.

Notes: for a proper flux cleaning process, “rosin” flux type (R) or “water soluble” flux type (WS) is

recommended for the solder printing material. “No clean” flux (NC) solder paste is not recommended.

In case the flux is not cleaned after the reflow soldering, the standard JEDEC would probably not be

appropriate and the solder volume must be controlled:

- using smallest aperture design for the stencil, and using finer solder paste type 4 or 5 for a

proper printing process.

- Mirroring pads would be the best recommendation

Application Note

Rev 1.0 2 of 3

Application Note

Top side

silicon

Typ.UBM thickness

3 to 5 µm

Pad recommendation

The capacitor is compatible with generic requirements for flip chip design (IPC7094).

Standard IPDiA 3D package can be compliant with established EIA size (0201, 0402, 0603, …).

Die size and land pattern dimensions is set up according to following range :

EIA size 0201 0402 0603 0805 1206 1812

Dimension max(X1 x X2) mm 0.86x0.66 1.26x0.76 1.86x1.16 2.26x1.46 3.46x1.86 4.76x3.66

Typical . die thickness X3 (mm) 0.1 or 0.4

Typical pad size* (mm) 0.15x0.40 0.30x0.50 0.40x0.90 0.50x1.20 0.60x1.60 0.90x3.40

Typical pad separation (X4

mm)

0.3 0.4 0.8 1 2 2.7

After soldering, no solder paste should touch the side of the capacitor die as that might result in

leakage currents due to remaining flux.

Application Note

Manual Handling Considerations

These capacitors are designed to be mounted with a standard SMT line, using solder printing step,

pick and place machine and a final reflow soldering step. In case of manual handling and mounting

conditions, please follow below recommendations:

xMinimize mechanical pressure on the capacitors (use of a vacuum nozzle is

recommended).

xUse of organic tip instead of metal tip for the nozzle.

xMinimize temperature shocks (Substrate pre-heating is recommended).

xNo wire bonding on 0402 47nF, 0402 100nF, 1206 1ȝF and 1812 3,3µF

Process steps:

xOn substrate, form the solder meniscus on each land pattern targeting 100 µm

height after reflow (screen printing, dispensing solder paste or by wire soldering).

xPick the capacitor from the tape & reel or the Gel Pack keeping backside visible

using a vacuum nozzle and organic tip.

xTemporary place the capacitor on land pattern assuming the solder paste (Flux)

will stick and maintain the capacitor.

xReflow the assembly module with a dedicated thermal profile (see reflow

recommendation profile).

Reproduction in whole or in part is prohibited without the

prior written consent of the copyright owner. The information

presented in this document does not form part of any

quotation or contract, is believed to be accurate and reliable

and may be changed without notice. No liability will be

accepted by the publisher for any consequence of its use.

Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

For more information, please visit: http://www.ipdia.com

To contact us, email to: sales@ipdia.com

Date of release: 20th April 2012

Document identifier:

Mouser Electronics

Authorized Distributor

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