HM5164800 Series
HM5165800 Series
64 M FP DRAM (8-Mword × 8-bit)
8 k Refresh/4 k Refresh
ADE-203-811B (Z)
Rev. 1.0
Feb. 27, 1998
Description
The Hitachi HM5164800 Series, HM5165800 Series are 64M-bit dynamic RAMs organized as 8,388,608-
word × 8-bit. They have realized high performance and low power by employing CMOS process
technology. The HM5164800 Series, HM5165800 Series offer Fast Page Mode as a high speed access
mode. They have the package variations of standard 32-pin plastic SOJ and standard 32-pin plastic TSOPII.
Features
• Single 3.3 V supply: 3.3 V ± 0.3 V
• Access time: 50 ns/60 ns (max)
• Power dissipation
Active: 414 mW/378 mW (max) (HM5164800 Series)
: 486 mW/414 mW (max) (HM5165800 Series)
Standby: 1.8 mW (max) (CMOS interface)
: 0.54 mW (max) (L-version)
• Fast page mode capability
• Refresh cycles
5$6
-only refresh
8192 cycles /64 ms (HM5164800)
/128 ms (HM5164800L) (L-version)
4096 cycles /64 ms (HM5165800)
/128 ms (HM5165800L) (L-version)
CBR/Hidden refresh
4096 cycles /64 ms (HM5164800, HM5165800)
/128 ms (HM5164800L, HM5165800L) (L-version)
HM5164800 Series, HM5165800 Series
2
• 4 variations of refresh
5$6
-only refresh
&$6
-before-
5$6
refresh
Hidden refresh
Self refresh (L-version)
• Battery backup operation (L-version)
Ordering Information
Type No. Access time Package
HM5164800J-5
HM5164800J-6 50 ns
60 ns 400-mil 32-pin plastic SOJ
(CP-32DC)
HM5164800LJ-5
HM5164800LJ-6 50 ns
60 ns
HM5165800J-5
HM5165800J-6 50 ns
60 ns
HM5165800LJ-5
HM5165800LJ-6 50 ns
60 ns
HM5164800TT-5
HM5164800TT-6 50 ns
60 ns 400-mil 32-pin plastic TSOP II
(TTP-32DC)
HM5164800LTT-5
HM5164800LTT-6 50 ns
60 ns
HM5165800TT-5
HM5165800TT-6 50 ns
60 ns
HM5165800LTT-5
HM5165800LTT-6 50 ns
60 ns
HM5164800 Series, HM5165800 Series
3
Pin Arrangement (HM5164800 Series)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(Top view)(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
I/O0
I/O1
I/O2
I/O3
NC
VCC
WE
RAS
A0
A1
A2
A3
A4
A5
VCC
VCC
I/O0
I/O1
I/O2
I/O3
NC
VCC
WE
RAS
A0
A1
A2
A3
A4
A5
VCC
V
I/O7
I/O6
I/O5
I/O4
V
CAS
OE
A12
A11
A10
A9
A8
A7
A6
V
SS
SS
SS
V
I/O7
I/O6
I/O5
I/O4
V
CAS
OE
A12
A11
A10
A9
A8
A7
A6
V
SS
SS
SS
32-pin TSOP32-pin SOJ
Pin Description
Pin name Function
A0 to A12 Address input
• Row/Refresh address A0 to A12
• Column address A0 to A9
I/O0 to I/O7 Data input/output
5$6
Row address strobe
&$6
Column address strobe
:(
Write enable
2(
Output enable
VCC Power supply
VSS Ground
NC No connection
HM5164800 Series, HM5165800 Series
4
Pin Arrangement (HM5165800 Series)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin TSOP32-pin SOJ
(Top view)(Top view)
V
I/O7
I/O6
I/O5
I/O4
V
CAS
OE
NC
A11
A10
A9
A8
A7
A6
V
SS
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
I/O0
I/O1
I/O2
I/O3
NC
V
CC
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
V
CC
I/O0
I/O1
I/O2
I/O3
NC
V
CC
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
SS
V
I/O7
I/O6
I/O5
I/O4
V
CAS
OE
NC
A11
A10
A9
A8
A7
A6
V
SS
SS
SS
Pin Description
Pin name Function
A0 to A11 Address input
• Row/Refresh address A0 to A11
• Column address A0 to A10
I/O0 to I/O7 Data input/output
5$6
Row address strobe
&$6
Column address strobe
:(
Write enable
2(
Output enable
VCC Power supply
VSS Ground
NC No connection
HM5164800 Series, HM5165800 Series
5
Block Diagram (HM5164800 Series)
•
•
•
•
•
•
A0
A1
to
A9
Timing and control
Column
address
buffers
Row
address
buffers
I/O buffers I/O0
to
I/O7
RAS CAS WE OE
Column decoder
Row decoder
8M array
8M array
8M array
8M array
8M array
8M array
8M array
8M array
A10
to
A12
HM5164800 Series, HM5165800 Series
6
Block Diagram (HM5165800 Series)
•
•
•
•
•
•
A0
A1
to
A10
Timing and control
Column
address
buffers
Row
address
buffers
I/O buffers I/O0
to
I/O7
RAS CAS WE OE
Column decoder
Row decoder
A11
8M array
8M array
8M array
8M array
8M array
8M array
8M array
8M array
HM5164800 Series, HM5165800 Series
7
Operation Table
5$6
5$6 &$6
&$6 :(
:( 2(
2(
I/O 0 to I/O 7 Operation
H×××High-Z Standby
L L H L Dout Read cycle
LL L*
2×Din Early write cycle
LL L*
2H Din Delayed write cycle
L L H to L L to H Dout/Din Read-modify-write cycle
LH××High-Z
5$6
-only refresh cycle
H to L L H ×High-Z
&$6
-before-
5$6
refresh cycle or
Self refresh cycle (L-version)
L L H H High-Z Read cycle (Output disabled)
Notes: 1. H: VIH (inactive), L: VIL (active), ×: VIH or VIL
2. tWCS ≥ 0 ns: Early write cycle
tWCS < 0 ns: Delayed write cycle
Absolute Maximum Ratings
Parameter Symbol Value Unit
Terminal voltage on any pin relative to VSS VT–0.5 to VCC + 0.5 (² 4.6 V (max)) V
Power supply voltage relative to VSS VCC –0.5 to +4.6 V
Short circuit output current Iout 50 mA
Power dissipation PT1.0 W
Storage temperature Tstg –55 to +125 °C
DC Operating Conditions
Parameter Symbol Min Typ Max Unit Notes
Supply voltage VCC 3.0 3.3 3.6 V 1, 2
VSS 000 V2
Input high voltage VIH 2.0 — VCC + 0.3 V 1
Input low voltage VIL –0.3 — 0.8 V 1
Ambient temperature range Ta 0 — 70 _C
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS
pins must be on the same level.
HM5164800 Series, HM5165800 Series
8
DC Characteristics (HM5164800 Series)
HM5164800
-5 -6
Parameter Symbol Min Max Min Max Unit Test conditions
Operating current*1, *2ICC1 — 115 — 105 mA tRC = min
Standby current ICC2 — 2 — 2 mA TTL interface
5$6
,
&$6
= VIH
Dout = High-Z
— 0.5 — 0.5 mA CMOS interface
5$6
,
&$6
≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version) ICC2 — 150 — 150 µA CMOS interface
5$6
,
&$6
≥ VCC – 0.2 V
Dout = High-Z
5$6
-only refresh current*2ICC3 — 115 — 105 mA tRC = min
Standby current*1ICC5 —5 —5 mA
5$6
= VIH,
&$6
= VIL
Dout = enable
&$6
-before-
5$6
refresh
current ICC6 — 115 — 105 mA tRC = min
Fast page mode current*1, *3ICC7 —90—80mA
5$6
= VIL ,
&$6
cycle,
tPC = tPC min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10 — 500 — 500 µA CMOS interface
Dout = High-Z
CBR refresh: tRC = 31.3 µs
tRAS ≤ 0.3 µs
Self refresh mode current
(L-version) ICC11 — 400 — 400 µA CMOS interface
5$6
, ≤0.2 V
Dout = High-Z
Input leakage current ILI –5 5 –5 5 µA 0 V ≤ Vin ≤ VCC + 0.3 V
Output leakage current ILO –5 5 –5 5 µA 0 V ≤ Vout ≤ VCC
Dout = disable
Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –2 mA
Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while
5$6
= VIL.
3. Measured with one sequential address change per fast page mode cycle, tPC.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
HM5164800 Series, HM5165800 Series
9
DC Characteristics (HM5165800 Series)
HM5165800
-5 -6
Parameter Symbol Min Max Min Max Unit Test conditions
Operating current*1, *2ICC1 — 135 — 115 mA tRC = min
Standby current ICC2 — 2 — 2 mA TTL interface
5$6
,
&$6
= VIH
Dout = High-Z
— 0.5 — 0.5 mA CMOS interface
5$6
,
&$6
≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version) ICC2 — 150 — 150 µA CMOS interface
5$6
,
&$6
≥ VCC – 0.2 V
Dout = High-Z
5$6
-only refresh current*2ICC3 — 135 — 115 mA tRC = min
Standby current*1ICC5 —5 —5 mA
5$6
= VIH,
&$6
= VIL
Dout = enable
&$6
-before-
5$6
refresh
current ICC6 — 135 — 115 mA tRC = min
Fast page mode current*1, *3ICC7 —90—80mA
5$6
= VIL ,
&$6
cycle,
tPC = tPC min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10 — 500 — 500 µA CMOS interface
Dout = High-Z
CBR refresh: tRC = 31.3 µs
tRAS ≤ 0.3 µs
Self refresh mode current
(L-version) ICC11 — 400 — 400 µA CMOS interface
5$6
,
&$6
≤ 0.2 V
Dout = High-Z
Input leakage current ILI –5 5 –5 5 µA 0 V ≤ Vin ≤ VCC + 0.3 V
Output leakage current ILO –5 5 –5 5 µA 0 V ≤ Vout ≤ VCC
Dout = disable
Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –2 mA
Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while
5$6
= VIL.
3. Measured with one sequential address change per fast page mode cycle, tPC.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
HM5164800 Series, HM5165800 Series
10
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter Symbol Typ Max Unit Notes
Input capacitance (Address) CI1 —5 pF1
Input capacitance (Clocks) CI2 —7 pF1
Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2.
5$6
,
&$6
= VIH to disable Dout.
HM5164800 Series, HM5165800 Series
11
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *19
Test Conditions
• Input rise and fall time: 5 ns
• Input timing reference levels: 0.8 V, 2.0 V
• Output timing reference levels: 0.8 V, 2.0 V
• Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5164800/HM5165800
-5 -6
Parameter Symbol Min Max Min Max Unit Notes
Random read or write cycle time tRC 90 — 110 — ns
5$6
precharge time tRP 30 — 40 — ns
&$6
precharge time tCP 8—10—ns
5$6
pulse width tRAS 50 10000 60 10000 ns
&$6
pulse width tCAS 13 10000 15 10000 ns
Row address setup time tASR 0—0—ns
Row address hold time tRAH 8—10—ns
Column address setup time tASC 0—0—ns
Column address hold time tCAH 8—10—ns
5$6
to
&$6
delay time tRCD 18 37 20 45 ns 3
5$6
to column address delay time tRAD 13 25 15 30 ns 4
5$6
hold time tRSH 13 — 15 — ns
&$6
hold time tCSH 50 — 60 — ns
&$6
to
5$6
precharge time tCRP 5—5—ns
2(
to Din delay time tOED 13 — 15 — ns 5
2(
delay time from Din tDZO 0—0—ns6
&$6
delay time from Din tDZC 0—0—ns6
Transition time (rise and fall) tT350350ns7
HM5164800 Series, HM5165800 Series
12
Read Cycle
HM5164800/HM5165800
-5 -6
Parameter Symbol Min Max Min Max Unit Notes
Access time from
5$6
tRAC — 50 — 60 ns 8, 9
Access time from
&$6
tCAC — 13 — 15 ns 9, 10, 17
Access time from address tAA — 25 — 30 ns 9, 11, 17
Access time from
2(
tOEA —13—15ns9
Read command setup time tRCS 0—0—ns
Read command hold time to
&$6
tRCH 0—0—ns12
Read command hold time to
5$6
tRRH 0—0—ns12
Column address to
5$6
lead time tRAL 25 — 30 — ns
Column address to
&$6
lead time tCAL 25 — 30 — ns
&$6
to output in low-Z tCLZ 0—0—ns
Output data hold time tOH 3—3—ns
Output data hold time from
2(
tOHO 3—3—ns
Output buffer turn-off time tOFF — 13 — 15 ns 13
Output buffer turn-off to
2(
tOEZ — 13 — 15 ns 13
&$6
to Din delay time tCDD 13 — 15 — ns 5
Write Cycle
HM5164800/HM5165800
-5 -6
Parameter Symbol Min Max Min Max Unit Notes
Write command setup time tWCS 0—0—ns14
Write command hold time tWCH 8—10—ns
Write command pulse width tWP 8—10—ns
Write command to
5$6
lead time tRWL 13 — 15 — ns
Write command to
&$6
lead time tCWL 13 — 15 — ns
Data-in setup time tDS 0—0—ns15
Data-in hold time tDH 8—10—ns15
HM5164800 Series, HM5165800 Series
13
Read-Modify-Write Cycle
HM5164800/HM5165800
-5 -6
Parameter Symbol Min Max Min Max Unit Notes
Read-modify-write cycle time tRWC 131 — 155 — ns
5$6
to
:(
delay time tRWD 73 — 85 — ns 14
&$6
to
:(
delay time tCWD 36 — 40 — ns 14
Column address to
:(
delay time tAWD 48 — 55 — ns 14
2(
hold time from
:(
tOEH 13 — 15 — ns
Refresh Cycle
HM5164800/HM5165800
-5 -6
Parameter Symbol Min Max Min Max Unit Notes
&$6
setup time (CBR refresh cycle) tCSR 5—5—ns
&$6
hold time (CBR refresh cycle) tCHR 8—10—ns
:(
setup time (CBR refresh cycle) tWRP 0—0—ns
:(
hold time (CBR refresh cycle) tWRH 8—10—ns
5$6
precharge to
&$6
hold time tRPC 5—5—ns
Fast Page Mode Cycle
HM5164800/HM5165800
-5 -6
Parameter Symbol Min Max Min Max Unit Notes
Fast page mode cycle time tPC 35 — 40 — ns
Fast page mode
5$6
pulse width tRASP — 100000 — 100000 ns 16
Access time from
&$6
precharge t CPA — 30 — 35 ns 9, 17
5$6
hold time from
&$6
precharge tCPRH 30 — 35 — ns
HM5164800 Series, HM5165800 Series
14
Fast Page Mode Read-Modify-Write Cycle
HM5164800/HM5165800
-5 -6
Parameter Symbol Min Max Min Max Unit Notes
Fast page mode read-modify-write cycle
time tPRWC 76 — 85 — ns
:(
delay time from
&$6
precharge tCPW 53 — 60 — ns 14
Refresh (HM5164800 Series)
Parameter Symbol Max Unit Note
Refresh period tREF 64 ms 8192 cycles
Refresh period (L-version) tREF 128 ms 8192 cycles
Refresh (HM5165800 Series)
Parameter Symbol Max Unit Note
Refresh period tREF 64 ms 4096 cycles
Refresh period (L-version) tREF 128 ms 4096 cycles
Self Refresh Mode (L-version)
HM5164800L/HM5165800L
-5 -6
Parameter Symbol Min Max Min Max Unit Notes
5$6
pulse width (Self refresh) tRASS 100 — 100 — µs 23
5$6
precharge time (Self refresh) tRPS 90 — 110 — ns 23
&$6
hold time (Self refresh) tCHS –50 — –50 — ns
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
5$6
-only refresh or
&$6
-before-
5$6
refresh).
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, t RAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
HM5164800 Series, HM5165800 Series
15
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10.Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ³ tRAD + t AA (max).
11.Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ² tRAD + tAA (max).
12.Either tRCH or tRRH must be satisfied for a read cycles.
13.tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14.tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD
(min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW
(min), the cycle is a read-modify-write and the data output will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access
time) is indeterminate.
15.tDS, tDH are referred to
&$6
leading edge in early write cycles and to
:(
leading edge in delayed
write or read-modify-write cycles.
16.tRASP defines
5$6
pulse width in fast page mode cycles.
17.Access time is determined by the longest among tAA, tCAC and tCPA.
18.In delayed write or read-modify-write cycles,
2(
must disable output buffer prior to applying data
to the device.
19.When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
20.Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms period on the condition a and b below.
a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6µs after exiting from self refresh mode.
21.In case of entering from
5$6
-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 20.
22.For L-version, it is available to apply each 128 ms and 31.2 µs instead of 64 ms and 15.6 µs at
note 20.
23 At tRASS > 100 µs, self refresh mode is activated, and not activated at tRASS < 10 µs. It is undefined
within the range of 10 µs ≤ tRASS ≤ 100 µs. For tRASS ≥ 10 µs, it is necessary to satisfy tRPS.
24.XXX: H or L (H: VIH (min) ² VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
HM5164800 Series, HM5165800 Series
16
Timing Waveforms*24
Read Cycle
RAS
CAS
Address
WE
Dout
OE
Din
tCSH
tRC
tRAS tRP
tCRP
tRCD tRSH
tCAS
tT
tRAD tRAL
tCAL
tCAH
tASR
Row Column
tRAH
tRCS tRCH
tRRH
tCDD
High-Z
Dout
tDZO tOED
tRAC
tOEA
tAA
tCAC
tCLZ tOH
tOFF
tOHO
tOEZ
tDZC
tASC
HM5164800 Series, HM5165800 Series
17
Early Write Cycle
RAS
Address
WE
Din
Dout
t
RC
*
t
RAS
t
RP
t
CRP
t
CSH
t
RCD
t
RSH
t
CAS
t
T
t
ASR
t
RAH
t
ASC
t
CAH
ColumnRow
t
WCS
t
WCH
t
DS
t
DH
Din
t
WCS WCS
(min)
High-Z*
t
CAS
HM5164800 Series, HM5165800 Series
18
Delayed Write Cycle*18
Address
CAS
RAS
WE
Din
OE
Dout
t
RC
t
RAS
t
RP
t
CSH
t
RCD
t
RSH
t
CAS
t
CRP
t
T
ColumnRow
t
ASR
t
RAH
t
ASC
t
CAH
t
RCS
t
CWL
t
RWL
t
WP
t
DZC
t
DS
t
DH
t
DZO
t
OED
t
OEH
t
CLZ
t
OEZ
High-Z
Invalid Dout
Din
High-Z
HM5164800 Series, HM5165800 Series
19
Read-Modify-Write Cycle*18
Address
RAS
Din
Dout
OE
WE
t
RWC
t
RAS
t
RP
t
CRP
t
CAS
t
RCD
t
T
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
ColumnRow
t
RCS
t
CWD
t
CWL
t
AWD
t
RWD
t
RWL
t
WP
t
DZC
t
DH
t
DS
Din
High-Z
t
DZO
t
OED
t
OEH
t
OEA
t
CAC
t
AA
t
RAC
t
OHO
t
OEZ
t
CLZ
Dout High-Z
CAS
HM5164800 Series, HM5165800 Series
20
5$6
5$6
-Only Refresh Cycle
RAS
CAS
Address
Dout High-Z
Row
t
RC
t
RP
t
RAS
t
T
t
CRP
t
RPC
t
CRP
t
ASR
t
RAH
t
OFF
HM5164800 Series, HM5165800 Series
21
&$6
&$6
-Before-
5$6
5$6
Refresh Cycle
RAS
CAS
WE
Address
Dout High-Z
t
OFF
t
WRP
t
WRH
t
WRP
t
WRH
t
CP
t
RPC
t
CSR
t
CHR
t
CP
t
RPC
t
CSR
t
CHR
t
CRP
t
RP
t
RAS
t
RC
t
RC
t
RP
t
RAS
t
RP
t
T
HM5164800 Series, HM5165800 Series
22
Hidden Refresh Cycle
Din
OE
Dout
WE
Address
CAS
RAS
t
RC
t
RC
t
RC
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
T
t
RCD
t
RSH
t
CHR
t
CRP
t
RAD
t
RAL
t
CAH
t
ASC
t
RAH
t
ASR
t
RCS
t
CDD
t
DZC
DZO
t
OED
t
OEZ
t
OHO
t
OFF
t
OH
t
CAC
t
AA
t
RAC
t
CLZ
t
Dout
OEA
t
High-Z
t
RRH
t
RCH
ColumnRow
HM5164800 Series, HM5165800 Series
23
Fast Page Mode Read Cycle
WE
Din
OE
Dout
Address
RAS
t
RASP
t
CPRH
t
RP
t
T
t
CSH
t
RCD
t
CAS
t
CP
t
CAS
t
PC
t
RSH
t
CP
t
CAS
t
CRP
t
RAL
t
CAL
t
CAHASC
tt
ASC
tt
CAL
t
CAL
t
ASC
t
t
RAD
t
ASR
t
RAH
tt
RCH
t
RCH
tt t
RRH
t
RCH
t
CDD
High-Z
t
DZC
t
CDD
t
DZC
t
CDD
t
DZC
High-ZHigh-Z
t
DZO
t
OED
t
OED
t
DZO
tt
OED
t
OH
t
AA
t
OH
t
AA
t
OH
t
CPA
t
CPA
t
RAC
t
AA
t
OEA
t
OEA
t
OEA
t
OHO
t
OHO
t
OHO
t
CAC
t
CLZ
t
OEZ
t
OFF
t
CAC
t
CLZ
t
OEZ
t
OFF
t
CAC
t
CLZ
t
OEZ
t
OFF
Dout NDout 2Dout 1
Row Column 1 Column 2 Column N
CAH CAH
RCS RCS
RCS
DZO
CAS
HM5164800 Series, HM5165800 Series
24
Fast Page Mode Early Write Cycle
*t
WCS WCS
(min)
RAS
Address
WE
Din
Dout
t
RASP
t
RP
t
T
t
CSH
t
PC
t
RSH
t
CRP
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RCD
t
ASR
t
RAH
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
WCH
t
WCS
t
WCH
t
WCS
t
WCH
t
WCS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
Din 1 Din 2 Din N
High-Z*
t
Row Column 1 Column 2 Column N
CAS
HM5164800 Series, HM5165800 Series
25
Fast Page Mode Delayed Write Cycle*18
WE
Din
OE
Dout
Address
RAS
t
RASP
t
RP
t
CRP
t
RSH
t
CAS
t
PC
t
CAS
t
CAS
t
CSH
t
RCD
t
T
t
CP
t
CP
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAD
t
ASR
t
RAH
t
RCS
t
RCS
t
RCS
t
RWL
t
CWL
t
CWL
t
CWL
t
WP
t
WP
t
WP
t
DZC
t
DS
t
DZC
t
DS
t
DS
t
DZC
t
DH
t
DH
t
DH
t
DZO
t
OED
t
DZO
t
OED
t
DZO
t
OED
t
OEH
t
OEH
t
OEH
t
OEZ
t
CLZ
t
CLZ
t
OEZ
t
CLZ
t
OEZ
Invalid Dout Invalid Dout Invalid Dout
Din
1Din
2Din
N
Column NColumn 2Column 1Row
High-Z
CAS
HM5164800 Series, HM5165800 Series
26
Fast Page Mode Read-Modify-Write Cycle*18
WE
Din
OE
Dout
Address
RAS
t
RASP
t
CRP
t
CP
t
PRWC
t
T
t
RCD
t
CAS
t
CP
t
CAS
t
CAS
t
RAD
t
ASR
t
ASC
t
ASC
t
ASC
t
RAH
t
CAH
t
CAH
t
CAH
t
CWL
t
CPW
t
CWL
t
CPW
t
CWL
t
RWD
t
AWD
t
AWD
t
AWD
t
CWD
t
RCS
t
CWD
t
RCS
t
CWD
t
RCS
t
WP
t
WP
t
WP
t
DS
t
DZC
t
DS
t
DZC
t
DS
t
DZC
t
DH
t
DH
t
DH
t
DZO
t
DZO
t
DZO
t
OEH
t
OEH
t
OEH
t
AA
t
RAC
t
OEZ
t
CLZ
Dout NDout 2Dout 1
Din
1Din
2Din
N
Column NColumn 2Column 1
t
RP
Row
t
RWL
t
OHO
t
OEA
t
CAC
t
OEZ
t
CLZ
t
OHO
t
OEA
t
CAC
t
CPA
t
OEZ
t
CLZ
t
OHO
t
OEA
t
CAC
t
CPA
High-Z
t
OED
t
OED
t
OED
AA
t
AA
t
t
RSH
CAS
HM5164800 Series, HM5165800 Series
27
Self Refresh Cycle (L-version)*20, 21, 22, 23
RAS
Dout
t
RP
t
RASS
t
RPS
t
RPC
t
T
t
CP
t
CSR
t
CHS
t
CRP
t
OFF
High-Z
CAS
WRP
t
WRH
t
WE
HM5164800 Series, HM5165800 Series
28
Package Dimensions
HM5164800J/LJ Series
HM5165800J/LJ Series (CP-32DC)
20.95
21.38 Max
32 17
116
0.74
10.16 ± 0.13
11.18 ± 0.13
3.50 ± 0.26
0.43 ± 0.10 9.40 ± 0.25
2.55 ± 0.46
1.165 Max
0.10
1.27
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
CP-32DC
—
Conforms
1.2 g
0.41 ± 0.08
0.90 ± 0.26
Unit: mm
Dimension including the plating thickness
Base material dimension
HM5164800 Series, HM5165800 Series
29
HM5164800TT/LTT Series
HM5165800TT/LTT Series (TTP-32DC)
1.27
0.21
M
0.42 ± 0.08
0.10
10.16
20.95
21.35 Max 17
16
32
1
1.20 Max
0° – 5°
0.13 ± 0.05
0.145 ± 0.05
11.76 ± 0.20
1.15 Max
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
TTP-32DC
Conforms
—
0.51 g
0.40 ± 0.06
0.125 ± 0.04
Unit: mm
0.50 ± 0.10
0.68
0.80
Dimension including the plating thickness
Base material dimension
HM5164800 Series, HM5165800 Series
30
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: 415-589-8300
Fax: 415-583-4207
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 0628-585000
Fax: 0628-778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
HM5164800 Series, HM5165800 Series
31
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Jul. 23, 1997 Initial issue J. Miyake M. Saeki
0.1 Nov. 1997 Change of Subtitle J. Miyake Y. Takahashi
1.0 Feb. 27, 1998 Deletion of Preliminary
