HM5164800 Series, HM5165800 Series
15
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10.Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ³ tRAD + t AA (max).
11.Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ² tRAD + tAA (max).
12.Either tRCH or tRRH must be satisfied for a read cycles.
13.tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14.tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD
(min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW
(min), the cycle is a read-modify-write and the data output will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access
time) is indeterminate.
15.tDS, tDH are referred to
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leading edge in early write cycles and to
:(
leading edge in delayed
write or read-modify-write cycles.
16.tRASP defines
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pulse width in fast page mode cycles.
17.Access time is determined by the longest among tAA, tCAC and tCPA.
18.In delayed write or read-modify-write cycles,
2(
must disable output buffer prior to applying data
to the device.
19.When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
20.Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms period on the condition a and b below.
a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6µs after exiting from self refresh mode.
21.In case of entering from
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-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 20.
22.For L-version, it is available to apply each 128 ms and 31.2 µs instead of 64 ms and 15.6 µs at
note 20.
23 At tRASS > 100 µs, self refresh mode is activated, and not activated at tRASS < 10 µs. It is undefined
within the range of 10 µs ≤ tRASS ≤ 100 µs. For tRASS ≥ 10 µs, it is necessary to satisfy tRPS.
24.XXX: H or L (H: VIH (min) ² VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.