HM5164800 Series HM5165800 Series 64 M FP DRAM (8-Mword x 8-bit) 8 k Refresh/4 k Refresh ADE-203-811B (Z) Rev. 1.0 Feb. 27, 1998 Description The Hitachi HM5164800 Series, HM5165800 Series are 64M-bit dynamic RAMs organized as 8,388,608word x 8-bit. They have realized high performance and low power by employing CMOS process technology. The HM5164800 Series, HM5165800 Series offer Fast Page Mode as a high speed access mode. They have the package variations of standard 32-pin plastic SOJ and standard 32-pin plastic TSOPII. Features * Single 3.3 V supply: 3.3 V 0.3 V * Access time: 50 ns/60 ns (max) * Power dissipation Active: 414 mW/378 mW (max) (HM5164800 Series) : 486 mW/414 mW (max) (HM5165800 Series) Standby : 1.8 mW (max) (CMOS interface) : 0.54 mW (max) (L-version) * Fast page mode capability * Refresh cycles 5$6-only refresh 8192 cycles /64 ms (HM5164800) /128 ms (HM5164800L) (L-version) 4096 cycles /64 ms (HM5165800) /128 ms (HM5165800L) (L-version) CBR/Hidden refresh 4096 cycles /64 ms (HM5164800, HM5165800) /128 ms (HM5164800L, HM5165800L) (L-version) HM5164800 Series, HM5165800 Series * 4 variations of refresh 5$6-only refresh &$6-before-5$6 refresh Hidden refresh Self refresh (L-version) * Battery backup operation (L-version) Ordering Information Type No. Access time Package HM5164800J-5 HM5164800J-6 50 ns 60 ns 400-mil 32-pin plastic SOJ (CP-32DC) HM5164800LJ-5 HM5164800LJ-6 50 ns 60 ns HM5165800J-5 HM5165800J-6 50 ns 60 ns HM5165800LJ-5 HM5165800LJ-6 50 ns 60 ns HM5164800TT-5 HM5164800TT-6 50 ns 60 ns HM5164800LTT-5 HM5164800LTT-6 50 ns 60 ns HM5165800TT-5 HM5165800TT-6 50 ns 60 ns HM5165800LTT-5 HM5165800LTT-6 50 ns 60 ns 2 400-mil 32-pin plastic TSOP II (TTP-32DC) HM5164800 Series, HM5165800 Series Pin Arrangement (HM5164800 Series) 32-pin SOJ 32-pin TSOP VCC 1 32 V SS VCC 1 32 V SS I/O0 2 31 I/O7 I/O0 2 31 I/O7 I/O1 3 30 I/O6 I/O1 3 30 I/O6 I/O2 4 29 I/O5 I/O2 4 29 I/O5 I/O3 5 28 I/O4 I/O3 5 28 I/O4 NC 6 27 V SS NC 6 27 V SS VCC 7 26 CAS VCC 7 26 CAS WE 8 25 OE WE 8 25 OE RAS 9 24 A12 RAS 9 24 A12 A0 10 23 A11 A0 10 23 A11 A1 11 22 A10 A1 11 22 A10 A2 12 21 A9 A2 12 21 A9 A3 13 20 A8 A3 13 20 A8 A4 14 19 A7 A4 14 19 A7 A5 15 18 A6 A5 15 18 A6 VCC 16 17 V SS VCC 16 17 V SS (Top view) (Top view) Pin Description Pin name Function A0 to A12 Address input I/O0 to I/O7 5$6 &$6 :( 2( * Row/Refresh address A0 to A12 * Column address A0 to A9 Data input/output Row address strobe Column address strobe Write enable Output enable VCC Power supply VSS Ground NC No connection 3 HM5164800 Series, HM5165800 Series Pin Arrangement (HM5165800 Series) 32-pin SOJ 32-pin TSOP VCC 1 32 VSS VCC 1 32 VSS I/O0 2 31 I/O7 I/O0 2 31 I/O7 I/O1 3 30 I/O6 I/O1 3 30 I/O6 I/O2 4 29 I/O5 I/O2 4 29 I/O5 I/O3 5 28 I/O4 I/O3 5 28 I/O4 NC 6 27 VSS NC 6 27 VSS VCC 7 26 CAS VCC 7 26 CAS WE 8 25 OE WE 8 25 OE RAS 9 24 NC RAS 9 24 NC A0 10 23 A11 A0 10 23 A11 A1 11 22 A10 A1 11 22 A10 A2 12 21 A9 A2 12 21 A9 A3 13 20 A8 A3 13 20 A8 A4 14 19 A7 A4 14 19 A7 A5 15 18 A6 A5 15 18 A6 VCC 16 17 V SS VCC 16 17 V SS (Top view) (Top view) Pin Description Pin name Function A0 to A11 Address input I/O0 to I/O7 5$6 &$6 :( 2( * Row/Refresh address A0 to A11 * Column address Data input/output Row address strobe Column address strobe Write enable Output enable VCC Power supply VSS Ground NC No connection 4 A0 to A10 HM5164800 Series, HM5165800 Series Block Diagram (HM5164800 Series) RAS CAS WE OE Timing and control Column decoder A0 Column A1 to * * * 8M array address 8M array buffers A9 * * * Row address buffers A10 to A12 Row decoder 8M array 8M array 8M array I/O buffers I/O0 to I/O7 8M array 8M array 8M array 5 HM5164800 Series, HM5165800 Series Block Diagram (HM5165800 Series) RAS CAS WE OE Timing and control Column decoder A0 Column A1 to * * * 8M array address 8M array buffers A10 * * * Row address buffers Row decoder 8M array 8M array 8M array 8M array 8M array 8M array A11 6 I/O buffers I/O0 to I/O7 HM5164800 Series, HM5165800 Series Operation Table 5$6 &$6 :( 2( I/O 0 to I/O 7 Operation H x x x High-Z Standby L L H L L L Dout Read cycle L* 2 x Din Early write cycle 2 H Din Delayed write cycle Read-modify-write cycle L L L* L L H to L L to H Dout/Din L H x x High-Z H to L L H x High-Z 5$6-only refresh cycle &$6-before-5$6 refresh cycle or Self refresh cycle (L-version) L L H H High-Z Read cycle (Output disabled) Notes: 1. H: VIH (inactive), L: VIL (active), x: VIH or VIL 2. tWCS 0 ns: Early write cycle tWCS < 0 ns: Delayed write cycle Absolute Maximum Ratings Parameter Symbol Value Unit Terminal voltage on any pin relative to VSS VT -0.5 to VCC + 0.5 ( 4.6 V (max)) V Power supply voltage relative to VSS VCC -0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Storage temperature Tstg -55 to +125 C DC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC 3.0 3.3 3.6 V 1, 2 VSS 0 0 0 V 2 Input high voltage VIH 2.0 -- VCC + 0.3 V 1 Input low voltage VIL -0.3 -- 0.8 V 1 Ambient temperature range Ta 0 -- 70 _C Notes: 1. All voltage referred to VSS. 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 7 HM5164800 Series, HM5165800 Series DC Characteristics (HM5164800 Series) HM5164800 -5 Parameter 1, Operating current* * 2 Standby current Standby current (L-version) -6 Symbol Min Max Min Max Unit Test conditions ICC1 -- 115 -- 105 mA tRC = min ICC2 -- 2 -- 2 mA TTL interface 5$6, &$6 = VIH Dout = High-Z -- 0.5 -- 0.5 mA CMOS interface 5$6, &$6 VCC - 0.2 V Dout = High-Z -- 150 -- 150 A ICC2 CMOS interface 5$6, &$6 V CC - 0.2 V Dout = High-Z 5$6-only refresh current* 2 1 Standby current* ICC3 -- 115 -- 105 mA tRC = min ICC5 -- 5 -- 5 mA 5$6 = V , &$6 = V IH IL Dout = enable &$6-before-5$6 refresh current ICC6 -- 115 -- 105 mA tRC = min ICC7 -- 90 -- 80 mA 5$6 = VIL , &$6 cycle, tPC = tPC min Battery backup current* (Standby with CBR refresh) (L-version) ICC10 -- 500 -- 500 A Self refresh mode current (L-version) ICC11 -- 400 -- 400 A Input leakage current ILI -5 5 -5 5 A 0 V Vin VCC + 0.3 V Output leakage current ILO -5 5 -5 5 A 0 V Vout VCC Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = -2 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 2 mA 1, Fast page mode current* * 4 3 CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s tRAS 0.3 s CMOS interface 5$6, 0.2 V Dout = High-Z Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while 5$6 = VIL. 3. Measured with one sequential address change per fast page mode cycle, tPC. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V. 8 HM5164800 Series, HM5165800 Series DC Characteristics (HM5165800 Series) HM5165800 -5 Parameter 1, Operating current* * 2 Standby current Standby current (L-version) -6 Symbol Min Max Min Max Unit Test conditions ICC1 -- 135 -- 115 mA tRC = min ICC2 -- 2 -- 2 mA TTL interface 5$6, &$6 = VIH Dout = High-Z -- 0.5 -- 0.5 mA CMOS interface 5$6, &$6 VCC - 0.2 V Dout = High-Z -- 150 -- 150 A ICC2 CMOS interface 5$6, &$6 V CC - 0.2 V Dout = High-Z 5$6-only refresh current* 2 1 Standby current* ICC3 -- 135 -- 115 mA tRC = min ICC5 -- 5 -- 5 mA 5$6 = V , &$6 = V IH IL Dout = enable &$6-before-5$6 refresh current ICC6 -- 135 -- 115 mA tRC = min ICC7 -- 90 -- 80 mA 5$6 = VIL , &$6 cycle, tPC = tPC min Battery backup current* (Standby with CBR refresh) (L-version) ICC10 -- 500 -- 500 A Self refresh mode current (L-version) ICC11 -- 400 -- 400 A Input leakage current ILI -5 5 -5 5 A 0 V Vin VCC + 0.3 V Output leakage current ILO -5 5 -5 5 A 0 V Vout VCC Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = -2 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 2 mA 1, Fast page mode current* * 4 3 CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s tRAS 0.3 s CMOS interface 5$6, &$6 0.2 V Dout = High-Z Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while 5$6 = VIL. 3. Measured with one sequential address change per fast page mode cycle, tPC. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V. 9 HM5164800 Series, HM5165800 Series Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 -- 5 pF 1 Input capacitance (Clocks) CI2 -- 7 pF 1 Output capacitance (Data-in, Data-out) CI/O -- 7 pF 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. 5$6, &$6 = VIH to disable Dout. 10 HM5164800 Series, HM5165800 Series AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2, *19 Test Conditions * * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5164800/HM5165800 -5 -6 Parameter Symbol Min Max Min Max Unit Random read or write cycle time tRC 90 -- 110 -- ns tRP 30 -- 40 -- ns tCP 8 -- 10 -- ns tRAS 50 10000 60 10000 ns tCAS 13 10000 15 10000 ns Row address setup time tASR 0 -- 0 -- ns Row address hold time tRAH 8 -- 10 -- ns Column address setup time tASC 0 -- 0 -- ns Column address hold time tCAH 8 -- 10 -- ns tRCD 18 37 20 45 ns 3 tRAD 13 25 15 30 ns 4 tRSH 13 -- 15 -- ns tCSH 50 -- 60 -- ns tCRP 5 -- 5 -- ns tOED 13 -- 15 -- ns 5 tDZO 0 -- 0 -- ns 6 tDZC 0 -- 0 -- ns 6 tT 3 50 3 50 ns 7 5$6 precharge time &$6 precharge time 5$6 pulse width &$6 pulse width 5$6 to &$6 delay time 5$6 to column address delay time 5$6 hold time &$6 hold time &$6 to 5$6 precharge time 2( to Din delay time 2( delay time from Din &$6 delay time from Din Transition time (rise and fall) Notes 11 HM5164800 Series, HM5165800 Series Read Cycle HM5164800/HM5165800 -5 -6 Parameter Symbol Min Max Min Max Unit Notes Access time from 5$6 tRAC -- 50 -- 60 ns 8, 9 Access time from &$6 tCAC -- 13 -- 15 ns 9, 10, 17 Access time from address tAA -- 25 -- 30 ns 9, 11, 17 Access time from 2( tOEA -- 13 -- 15 ns 9 Read command setup time tRCS 0 -- 0 -- ns Read command hold time to &$6 tRCH 0 -- 0 -- ns 12 Read command hold time to 5$6 tRRH 0 -- 0 -- ns 12 Column address to 5$6 lead time tRAL 25 -- 30 -- ns Column address to &$6 lead time tCAL 25 -- 30 -- ns &$6 to output in low-Z tCLZ 0 -- 0 -- ns Output data hold time tOH 3 -- 3 -- ns Output data hold time from 2( tOHO 3 -- 3 -- ns Output buffer turn-off time tOFF -- 13 -- 15 ns 13 Output buffer turn-off to 2( tOEZ -- 13 -- 15 ns 13 &$6 to Din delay time tCDD 13 -- 15 -- ns 5 Write Cycle HM5164800/HM5165800 -5 Parameter -6 Symbol Min Max Min Max Unit Notes Write command setup time tWCS 0 -- 0 -- ns 14 Write command hold time tWCH 8 -- 10 -- ns Write command pulse width tWP 8 -- 10 -- ns Write command to 5$6 lead time tRWL 13 -- 15 -- ns Write command to &$6 lead time tCWL 13 -- 15 -- ns Data-in setup time tDS 0 -- 0 -- ns 15 Data-in hold time tDH 8 -- 10 -- ns 15 12 HM5164800 Series, HM5165800 Series Read-Modify-Write Cycle HM5164800/HM5165800 -5 -6 Parameter Symbol Min Max Min Max Unit Read-modify-write cycle time tRWC 131 -- 155 -- ns tRWD 73 -- 85 -- ns 14 tCWD 36 -- 40 -- ns 14 tAWD 48 -- 55 -- ns 14 tOEH 13 -- 15 -- ns 5$6 to :( delay time &$6 to :( delay time Column address to :( delay time 2( hold time from :( Notes Refresh Cycle HM5164800/HM5165800 -5 Parameter &$6 setup time (CBR refresh cycle) &$6 hold time (CBR refresh cycle) :( setup time (CBR refresh cycle) :( hold time (CBR refresh cycle) 5$6 precharge to &$6 hold time -6 Symbol Min Max Min Max Unit tCSR 5 -- 5 -- ns tCHR 8 -- 10 -- ns tWRP 0 -- 0 -- ns tWRH 8 -- 10 -- ns tRPC 5 -- 5 -- ns Notes Fast Page Mode Cycle HM5164800/HM5165800 -5 -6 Parameter Symbol Min Max Min Max Unit Notes Fast page mode cycle time tPC 35 -- 40 -- ns Fast page mode 5$6 pulse width tRASP -- 100000 -- 100000 ns 16 Access time from &$6 precharge tCPA -- 30 -- 35 ns 9, 17 5$6 hold time from &$6 precharge tCPRH 30 -- 35 -- ns 13 HM5164800 Series, HM5165800 Series Fast Page Mode Read-Modify-Write Cycle HM5164800/HM5165800 -5 Parameter Symbol Fast page mode read-modify-write cycle tPRWC time :( delay time from &$6 precharge tCPW -6 Min Max Min Max Unit 76 -- 85 -- ns 53 -- 60 -- ns Notes 14 Refresh (HM5164800 Series) Parameter Symbol Max Unit Note Refresh period tREF 64 ms 8192 cycles Refresh period (L-version) tREF 128 ms 8192 cycles Parameter Symbol Max Unit Note Refresh period tREF 64 ms 4096 cycles Refresh period (L-version) tREF 128 ms 4096 cycles Refresh (HM5165800 Series) Self Refresh Mode (L-version) HM5164800L/HM5165800L -5 Parameter 5$6 pulse width (Self refresh) 5$6 precharge time (Self refresh) &$6 hold time (Self refresh) -6 Symbol Min Max Min Max Unit Notes tRASS 100 -- 100 -- s 23 tRPS 90 -- 110 -- ns 23 tCHS -50 -- -50 -- ns Notes: 1. AC measurements assume tT = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing 5$6-only refresh or &$6-before-5$6 refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 14 HM5164800 Series, HM5165800 Series 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. tDS, tDH are referred to &$6 leading edge in early write cycles and to :( leading edge in delayed write or read-modify-write cycles. 16. tRASP defines 5$6 pulse width in fast page mode cycles. 17. Access time is determined by the longest among tAA, tCAC and tCPA. 18. In delayed write or read-modify-write cycles, 2( must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 20. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. Enter self refresh mode within 15.6 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6s after exiting from self refresh mode. 21. In case of entering from 5$6-only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 20. 22. For L-version, it is available to apply each 128 ms and 31.2 s instead of 64 ms and 15.6 s at note 20. 23 At tRASS > 100 s, self refresh mode is activated, and not activated at t RASS < 10 s. It is undefined within the range of 10 s tRASS 100 s. For tRASS 10 s, it is necessary to satisfy tRPS. 24. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 15 HM5164800 Series, HM5165800 Series Timing Waveforms*24 Read Cycle tRC tRAS tRP RAS tCRP tCSH tRCD tRSH tCAS tT CAS tRAD tASR Address tRAH tRAL tCAL tASC Row tCAH Column tRRH tRCS tRCH WE tDZC tCDD High-Z Din tDZO tOEA tOED OE tOEZ tOHO tCAC tAA tRAC tCLZ Dout 16 tOFF tOH Dout HM5164800 Series, HM5165800 Series Early Write Cycle tRC tRP tRAS RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din Dout tDH Din High-Z* * t WCS t WCS (min) 17 HM5164800 Series, HM5165800 Series 18 Delayed Write Cycle* tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH tASC Row tCAH Column tCWL tRWL tWP tRCS WE tDS tDZC Din High-Z Din tOED tDZO tDH tOEH OE tOEZ tCLZ High-Z Dout Invalid Dout 18 HM5164800 Series, HM5165800 Series Read-Modify-Write Cycle* 18 tRWC tRAS tRP RAS tT tRCD tCAS tCRP CAS tRAD tASR Address tASC tRAH Row tCAH Column tCWL tCWD tRCS tRWL tWP tAWD tRWD WE tDZC tDS High-Z Din Din tDH tOED tDZO tOEH tOEA OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ 19 HM5164800 Series, HM5165800 Series 5$6-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP t RPC CAS t ASR Address t RAH Row t OFF Dout 20 High-Z t CRP HM5164800 Series, HM5165800 Series &$6-Before-5$6 Refresh Cycle t RC t RP t RAS t RC t RP t RAS t RP RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR CAS t WRP t WRH t WRP t WRH WE Address t OFF High-Z Dout 21 HM5164800 Series, HM5165800 Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD CAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t RRH t RCH t RCS WE t DZC t CDD High-Z Din t DZO t OED t OEA OE t CAC t OEZ t OHO t AA t RAC t OFF t OH t CLZ Dout 22 Dout HM5164800 Series, HM5165800 Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD t PC t CAS t CP t RSH t CAS t CP t CRP t CAS CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH t CAL t ASC t CAH t ASC t CAH Column 1 Column 2 Column N t CAL t RCS tRCS tRCH t RCS t RRH t RCH tRCH WE t DZC Din t DZO t DZC t DZC t CDD t CDD High-Z High-Z t OED t DZO t OED t CDD High-Z t DZO t OED OE t RAC t AA t OH t OEA t OHO t OH t OEA t OFF t CAC t OEZ t CLZ t CAC t CLZ Dout t CPA t AA Dout 1 t CPA t AA t OHO t OFF t OEZ Dout 2 t OH t OHO t OEA t CAC t CLZ t OFF t OEZ Dout N 23 HM5164800 Series, HM5165800 Series Fast Page Mode Early Write Cycle t RP t RASP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH Address Row t ASC t CAH t ASC t CAH t ASC t CAH Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din Dout t DH Din 1 t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS 24 t WCS (min) HM5164800 Series, HM5165800 Series 18 Fast Page Mode Delayed Write Cycle* t RASP t RP RAS tT t CP t CSH t RCD t CRP t CP t PC t CAS t RSH t CAS t CAS CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t RCS WE t WP t WP t WP t DZC t DS t DZC t DS t DZC t DS t DH t DH Din 1 Din Din 2 t DZO Din N t DZO t DZO t DH t OED t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t OEZ t CLZ t OEZ t OEZ High-Z Dout Invalid Dout Invalid Dout Invalid Dout 25 HM5164800 Series, HM5165800 Series Fast Page Mode Read-Modify-Write Cycle* 18 t RASP t RP RAS tT t PRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t ASR t RAD t ASC t RAH Address t ASC t CAH t CAH Column 1 Row t ASC t CAH Column 2 t RWD t CWL t AWD t CPW t CWL t AWD t RCS t CWD Column N t CPW t AWD t RCS t CWD t CWL t RWL t CWD WE t RCS t WP t WP t DZC t DS t WP t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t OED t DH Din 2 t OED t DZO t OED t DZO t OEH t OEH t OEH Din N OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t OEA t CAC t AA t CPA t RAC t OEZ t CLZ t OHO t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 26 Dout 2 Dout N HM5164800 Series, HM5165800 Series Self Refresh Cycle (L-version)* 20, 21, 22, 23 t RASS t RP t RPS RAS tT t RPC t CP t CRP t CSR t CHS CAS t WRP t WRH WE t OFF Dout High-Z 27 HM5164800 Series, HM5165800 Series Package Dimensions HM5164800J/LJ Series HM5165800J/LJ Series (CP-32DC) Unit: mm 3.50 0.26 1.165 Max 0.43 0.10 0.41 0.08 1.27 0.10 Dimension including the plating thickness Base material dimension 28 2.55 0.46 16 0.74 0.90 0.26 1 11.18 0.13 17 10.16 0.13 32 20.95 21.38 Max 9.40 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-32DC -- Conforms 1.2 g HM5164800 Series, HM5165800 Series HM5164800TT/LTT Series HM5165800TT/LTT Series (TTP-32DC) Unit: mm 20.95 21.35 Max 17 10.16 32 1.27 0.21 M 0.80 11.76 0.20 0.10 Dimension including the plating thickness Base material dimension 0.145 0.05 0.125 0.04 1.20 Max 1.15 Max 0 - 5 0.50 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) 0.68 0.42 0.08 0.40 0.06 16 0.13 0.05 1 TTP-32DC Conforms -- 0.51 g 29 HM5164800 Series, HM5165800 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 30 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 HM5164800 Series, HM5165800 Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Jul. 23, 1997 Initial issue J. Miyake M. Saeki 0.1 Nov. 1997 Change of Subtitle J. Miyake Y. Takahashi 1.0 Feb. 27, 1998 Deletion of Preliminary 31