© 2005 Fairchild Semiconductor Corporation DS500271 www.fairchildsemi.com
April 2000
Revised January 2005
NC7WZ38 TinyLogi c
UHS Dual 2-Input NAND Gate (Open Drain Output)
NC7WZ38
TinyLogic UHS Dual 2-Input NAND Gate
(Open Drain Output)
General Description
The NC7WZ38 is a dual 2-Input NAND Gate with open
drain output stage from Fairchild’s Ultra High Speed Series
of TinyLogic. The device is fabricated with advanced
CMOS technology to achieve ultra high speed with high
output drive while maintaining low static power d issipation
over a very broad VCC operating range. The device is
specified to operate over the 1.65V to 5.5V VCC range. The
inputs and output are high impedance when VCC is 0V.
Inputs tol era te vo ltage s up to 7V inde pe nde nt o f VCC oper-
ating voltage. The open drain output stage will tolerate volt-
ages up to 7V independent of VCC when in the high
impeda nce stat e.
Features
Space saving US8 surface mount package
MicroPak Pb-Free leadless package
Open Drain output stage for OR tied applications
Ultra High Speed; tPD 2.2 ns Typ into 50 pF at 5V VCC
High Output Sink Drive; 24 mA at 3V VCC
Broad VCC Operating Range; 1.65V to 5.5V
Matches the performance of LCX when operated at
3.3V VCC
Power down high impedance inputs/output
Overvoltage Tolerant inputs facilitate 5V to 3V
translation
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Pb-F ree packag e per JEDE C J-ST D -020B.
TinyLogic is a regist ered trad em ark of Fairc hild Semicond uc t or Corporation.
MicroPak is a trad em ark of Fairchild Sem icond uc t or Corporation.
Product Package Description Supplied AsOrder Package Code
Numbe r Number Top Mark
NC7WZ38K8X MAB08A WZ38 8-Lead US8, JEDEC MO-187, V ariation CA 3.1mm Wide 3k Units on Tape and Reel
NC7WZ38L8X MAC08A U5 Pb-Free 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and Reel
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NC7WZ38
Logic Symbol
IEEE/IEC
Pin Descriptions
Function Table
Y = AB
H = HIGH Logic Level
L = LO W Lo gic Lev el
*H = HIGH Im pedanc e output stat e (Open Drain)
Connection Diagrams
(Top View)
Pin One Orientation Diagram
AAA represen t s P roduct Code Top Ma rk - s ee orderin g c ode
Note: Orientation of Top Mark determines Pin One location. Read the top
produc t co de mark lef t to right, Pin On e is th e lower lef t pi n (see dia gram).
Pad Assignm ents for Micr oPak
(Top Thru View)
Pin Names Description
An, BnInputs
YnOutput
Inputs Output
AB Y
LL*H
LH*H
HL*H
HH L
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NC7WZ38
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions (Note 2)
Note 1: Abs olut e maxi mum ratin gs ar e DC value s beyond whi ch t he devi ce
may b e dam aged or h ave its usef ul li fe i mpa ired . Th e data she et sp ecif ica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (VCC)0.5V to +7V
DC Input Voltage (VIN)0.5V to +7V
DC Output Voltage (VOUT)0.5V to +7V
DC Input Diode Current (IIK)
@VIN < 0.5V 50 mA
DC Output Diode Current (IOK)
@VOUT < 0.5V 50 mA
DC Output Current (IOUT)+50 mA
DC VCC/GND Current (ICC/IGND)±100 mA
Storage Temperature (TSTG)65°C to +150°C
Junction Temperature under Bias (TJ) 150°C
Junction Lead Temperature (TL);
(Soldering, 10 seconds) 260°C
Power Dissipation (PD) @ +85°C 250 mW
Supply Voltage Operating (VCC) 1.65V to 5.5V
Supply Voltage Data Retention (VCC) 1.5V to 5.5V
Input Voltage (VIN) 0V to 5.5V
Output Voltage (VOUT)0V to V
CC
Operating Temperature (TA)40°C to +85°C
Input Rise and Fall Time (tr, tf)
VCC = 1.8V ± 0.15V, 2.5V ± 0.2V 0 ns/V to 20 ns/V
VCC = 3.3V ± 0.3V 0 ns/V to 10 ns/V
VCC = 5.0V ± 0.5V 0 ns/V to 5 ns/V
Thermal Resistance (θJA)250°C/W
Symbol Parameter VCC TA = +25°CT
A = 40°C to +85°CUnits Conditions
(V) MinTypMaxMinMax
VIH HIGH Level 1.65 to 1.95 0.75 VCC 0.75 VCC V
Input Voltage 2.3 to 5.5 0.7 VCC 0.7 VCC
VIL LOW Level 1.65 to 1.95 0.25 VCC 0.25 VCC V
Input Voltage 2.3 to 5.5 0.3 VCC 0.3 VCC
ILKG HIGH Level 5.5 ±5±10 µAVIN = VIL
Output Leakage VOUT = VCC or GND
VOL LOW Level 1.65 0.0 0.1 0.1
VV
IN = VIH IOL = 100 µA
Output Voltage 2.3 0.0 0.1 0.1
3.0 0.0 0.1 0.1
4.5 0.0 0.1 0.1
1.65 0.08 0.24 0.24
V
IOL = 4 mA
2.3 0.10 0.3 0.3 IOL = 8 mA
3.0 0.15 0.4 0.4 IOL = 16 mA
3.0 0.22 0.55 0.55 IOL = 24 mA
4.5 0.22 0.55 0.55 IOL = 32 mA
IIN Input Leakage Current 5.5 ±0.1 ±1µAV
IN = 5.5V, GND
IOFF Power Off Leakage Current 0.0 1 10 µAV
IN or VOUT = 5.5V
ICC Quiescent Supply Current 1.65 to 5.5 1 10 µAV
IN = 5.5V, GND
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NC7WZ38
AC Electrical Characteristi cs
Note 3: CPD is defined as the value of th e internal equivalent c apacita nc e which is deriv ed from dy namic operat ing current con su m pt ion (ICCD) at no output
loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to I CCD dynamic operating current by the expression:
ICCD = (CPD) (VCC) (f IN) + (ICC static).
AC Loading and Waveforms
CL includes load and stray capacitance
Input PRR = 1.0 MHz; tw = 50 0 ns
FIGURE 1. AC Test Circuit
Input = AC Waveform; tr = tf = 1.8 ns
PRR = 10 MHz; Duty Cycle = 50%
FIGURE 2. ICCD Test Circuit
FIGURE 3. AC Waveforms
Symbol Parameter VCC TA = +25°CT
A = 40°C to +85°CUnits Conditions Figure
(V) Min Typ Max Min Max Number
tPZL Propagation Delay 1.8 ± 0.15 2.0 5.2 9.2 2.0 9.6
ns
CL = 50 pF
2.5 ± 0.2 1.5 3.5 5.7 1.5 6.1 RU = 500Figures
1, 3
3.3 ± 0.3 1.0 2.8 4.1 1.0 4.5 RD = 500
5.0 ± 0.5 0.5 2.2 3.4 0.5 3.6 VI = 2 × VCC
tPLZ Propagation Delay 1.8 ± 0.15 2.0 4.6 9.2 2.0 9.6
ns
CL = 50 pF
2.5 ± 0.2 1.5 3.2 5.7 1.5 6.1 RU = 500Figures
1, 3
3.3 ± 0.3 1.0 2.4 4.1 1.0 4.5 RD = 500
5.0 ± 0.5 0.5 1.6 3.4 0.5 3.6 VI = 2 × VCC
CIN Input Capacitance 0 2.5 pF
COUT Output Capacitance 0 4.2 pF
CPD Power Dissipation 3.3 7 pF (Note 3) Figure 2
Capacitance 5.0 9
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NC7WZ38
Tape and Reel Specificati o n
TAPE FORMAT for US8
TAPE DIMENSIONS inches (millimeters)
TAPE FORMAT for MicroPak
TAPE DIMENSIONS inches (millimeters)
Packa ge Tape Number Cavit y Cove r Tap e
Designator Section Cavities Status Status
Leader (Start End) 125 (typ) Empty Sealed
K8X Carrier 3000 Filled Sealed
Trailer (Hub End) 75 (typ) Empty Sealed
Packa ge Tape Number Cavit y Cove r Tap e
Designator Section Cavities Status Status
Leader (Start End) 125 (typ) Empty Sealed
L8X Carrier 3000 Filled Sealed
Trailer (Hub End) 75 (typ) Empty Sealed
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NC7WZ38
Tape and Reel Specification (Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size ABCDN W1 W2 W3
8 mm 7.0 0.059 0.512 0.795 2.165 0.331 + 0.059/0.000 0.567 W1 + 0.078/0.039
(177.8) (1.50) (13.00) (20.20) ( 55.00) (8.40 + 1.5 0/0.00) (14.40) (W1 + 2.00/1.00)
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NC7WZ38
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
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NC7WZ38 TinyLogic
UHS Dual 2-Input NAND Gate (Open Drain Output)
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syste ms are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent i n any compon ent of a lif e supp ort
device or system whose failure to perform can be rea-
sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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