DLP2010NIRFQJ - Texas Instruments

DLPC150

Display Controller DLP2010 DMD

DLP2010NIR DMD

DLPA2000

DLPA2005

(PMIC and LED

Driver)

VOFFSET

VBIAS

VRESET

D_P(0)

D_N(0)

D_P(1)

D_N(1)

D_P(2)

D_N(2)

D_P(3)

D_N(3)

DCLK_P

DCLK_N

DMD_DEN_ARSTZ

LS_WDATA

LS_CLK

LS_RDATA

120-MHz

SDR

Interface

600-MHz

SubLVDS

DDR

Interface

VDDI

VDD

VSS

System Signal Routing Omitted For Clarity

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

DLP2010NIR

DLPS059A –MARCH 2015–REVISED OCTOBER 2015

DLP2010NIR (0.2 WVGA Near-Infrared DMD)

1 Features 2 Applications

1• 0.2-Inch (5.29-mm) Diagonal Micromirror Array • Spectrometers (Chemical Analysis):

– 854 × 480 Array of Aluminum Micrometer- – Portable Process Analyzers

Sized Mirrors, in an Orthogonal Layout – Portable Equipment

– 5.4-µm Micromirror Pitch • Compressive Sensing (Single Pixel NIR Cameras)

– ±17° Micromirror Tilt (Relative to Flat Surface) • 3D Biometrics

– Side Illumination for Optimal Efficiency and • Machine Vision

Optical Engine Size • Infrared Scene Projection

• Highly Efficient Steering of NIR light • Microscopes

– Window Transmission Efficiency 96% Nominal • Laser Marking

(700 to 2000 nm, Single Pass Through Two • Optical Choppers

Window Surfaces) • Optical Networking

– Window Transmission Efficiency 90% Nominal

(2000 to 2500 nm, Single Pass Through Two 3 Description

Window Surfaces) The DLP2010NIR digital micromirror device (DMD)

– Polarization Independent Aluminum acts as a spatial light modulator (SLM) to steer near-

Micromirrors infrared (NIR) light and create patterns with speed,

precision, and efficiency. Featuring high resolution in

• Dedicated DLPC150 Controller for Reliable a compact form factor, the DLP2010NIR DMD is

Operation often combined with a grating single element detector

– Binary Pattern Rates up to 2880 Hz to replace expensive InGaAs linear array-based

– Pattern Sequence Mode for Control over Each detector designs, leading to high performance, cost-

Micromirror in Array effective portable NIR Spectroscopy solutions. The

DLP2010NIR DMD enables wavelength control and

• Dedicated Power Management Integrated Circuit programmable spectrum and is well suited for low

(PMIC) DLPA2000 or DLPA2005 for Reliable power mobile applications such as skin analysis,

Operation material identification and chemical sensing.

• 15.9-mm × 5.3-mm × 4-mm Body Size for

Portable Instruments Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DLP2010NIR CLGA (40) 15.90 × 5.30 × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

DLP®0.2" WVGA Chipset

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DLP2010NIR

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Table of Contents

7.3 Feature Description................................................. 20

1 Features.................................................................. 17.4 Device Functional Modes........................................ 20

2 Applications ........................................................... 17.5 Window Characteristics and Optics........................ 20

3 Description............................................................. 17.6 Micromirror Array Temperature Calculation............ 21

4 Revision History..................................................... 27.7 Micromirror Landed-On/Landed-Off Duty Cycle .... 22

5 Pin Configuration and Functions......................... 38 Application and Implementation ........................ 24

6 Specifications......................................................... 68.1 Application Information............................................ 24

6.1 Absolute Maximum Ratings ..................................... 68.2 Typical Application.................................................. 24

6.2 Storage Conditions.................................................... 69 Power Supply Recommendations...................... 27

6.3 ESD Ratings.............................................................. 79.1 Power Supply Power-Up Procedure ...................... 27

6.4 Recommended Operating Conditions....................... 79.2 Power Supply Power-Down Procedure .................. 27

6.5 Thermal Information.................................................. 99.3 Power Supply Sequencing Requirements .............. 28

6.6 Electrical Characteristics........................................... 910 Layout................................................................... 30

6.7 Timing Requirements.............................................. 10 10.1 Layout Guidelines ................................................. 30

6.8 Switching Characteristics ....................................... 15 10.2 Layout Example .................................................... 30

6.9 System Mounting Interface Loads .......................... 15 11 Device and Documentation Support................. 32

6.10 Physical Characteristics of the Micromirror Array. 16 11.1 Device Support...................................................... 32

6.11 Micromirror Array Optical Characteristics ............. 17 11.2 Related Links ........................................................ 32

6.12 Window Characteristics......................................... 18 11.3 Community Resources.......................................... 33

6.13 Chipset Component Usage Specification ............. 18 11.4 Trademarks........................................................... 33

6.14 Typical Characteristics.......................................... 18 11.5 Electrostatic Discharge Caution............................ 33

7 Detailed Description............................................ 19 11.6 Glossary................................................................ 33

7.1 Overview................................................................. 19 12 Mechanical, Packaging, and Orderable

7.2 Functional Block Diagram....................................... 19 Information ........................................................... 33

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2015) to Revision A Page

• Lowered minimum delay time .............................................................................................................................................. 29

• Added Community Resources ............................................................................................................................................. 33

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

5 Pin Configuration and Functions

FQJ Package

40-Pin CLGA

Bottom View

Pin Functions – Connector Pins(1)

PIN PACKAGE NET TRACE

TYPE SIGNAL DATA RATE DESCRIPTION LENGTH(2) (mm)

NAME NO.

DATA INPUTS, SUBLVDS INTERFACE

D_N(0) G4 I SubLVDS Double Input Data Pair 0, Negative 7.03

D_P(0) G3 I SubLVDS Double Input Data Pair 0, Positive 7.03

D_N(1) G8 I SubLVDS Double Input Data Pair 1, Negative 7.03

D_P(1) G7 I SubLVDS Double Input Data Pair 1, Positive 7.03

D_N(2) H5 I SubLVDS Double Input Data Pair 2, Negative 7.02

D_P(2) H6 I SubLVDS Double Input Data Pair 2, Positive 7.02

(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard

No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.

(2) Net trace lengths inside the package:

Relative dielectric constant for the FQJ ceramic package is 9.8.

Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns.

Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.

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Pin Functions – Connector Pins(1) (continued)

PIN PACKAGE NET TRACE

TYPE SIGNAL DATA RATE DESCRIPTION LENGTH(2) (mm)

NAME NO.

D_N(3) H1 I SubLVDS Double Input Data Pair 3, Negative 7.00

D_P(3) H2 I SubLVDS Double Input Data Pair 3, Positive 7.00

DCLK_N H9 I SubLVDS Double Clock, Negative 7.03

DCLK_P H10 I SubLVDS Double Clock, Positive 7.03

CONTROL INPUTS, LPSDR INTERFACE

Active low asynchronous DMD reset

signal. A low signal places the DMD in

DMD_DEN_ARSTZ G12 I LPSDR(1) 5.72

reset. A high signal releases the DMD

from reset and places it in active mode.

LS_CLK G19 I LPSDR Single Clock for low-speed interface 3.54

LS_WDATA G18 I LPSDR Single Write data for low-speed interface 3.54

LS_RDATA G11 O LPSDR Single Read data for low-speed interface 8.11

POWER

Supply voltage for Micromirror positive

VBIAS(3) H17 Power bias level

Supply voltage for High Voltage CMOS

(HVCMOS) core logic.

Includes: supply voltage for stepped high

VOFFSET(3) H13 Power level at micromirror address electrodes

and supply voltage for offset level at

micromirrors.

Supply voltage for Micromirror negative

VRESET(3) H18 Power reset level

VDD(3) G20 Power

VDD H14 Power Supply voltage for low voltage CMOS

(LVCMOS) core logic. Includes supply

VDD H15 Power voltage for LPSDR inputs and supply

VDD H16 Power voltage for normal high level at micromirror

address electrodes.

VDD H19 Power

VDD H20 Power

VDDI(3) G1 Power

VDDI G2 Power Supply voltage for SubLVDS receivers

VDDI G5 Power

VDDI G6 Power

VSS(3) G9 Power

VSS G10 Power

VSS G13 Power

VSS G14 Power

VSS G15 Power

VSS G16 Power

VSS G17 Power Ground. Common return for all power.

VSS H3 Power

VSS H4 Power

VSS H7 Power

VSS H8 Power

VSS H11 Power

VSS H12 Power

(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

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Pin Functions – Connector Pins(1) (continued)

PIN PACKAGE NET TRACE

TYPE SIGNAL DATA RATE DESCRIPTION LENGTH(2) (mm)

NAME NO.

RESERVED

A2,

A3,

A4,

A5,

A7,

A8,

A9,

A10, Reserved pins. For proper device

No Connect A11, operation, leave these pins unconnected.

A12,

A13,

A14,

A15,

A16,

A17,

A18,

A19

B2,

B3, Reserved pins. For proper device

No Connect B17, operation, leave these pins unconnected.

B18

C2,

C3, Reserved pins. For proper device

No Connect C17, operation, leave these pins unconnected.

C18

D2,

D3, Reserved pins. For proper device

No Connect D17, operation, leave these pins unconnected.

D18

E2,

E3, Reserved pins. For proper device

No Connect E17, operation, leave these pins unconnected.

E18

F1,

F2,

F3,

F4,

F5,

F6,

F7,

F8,

F9, Resereved pins. For proper device

No Connect F10, operation, leave these pins unconnected.

F11,

F12,

F13,

F14,

F15,

F16,

F17,

F18,

F19

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6 Specifications

6.1 Absolute Maximum Ratings

(see (1))MIN MAX UNIT

Supply voltage for LVCMOS core logic and LPSDR

VDD –0.5 2.3 V

low speed interface(2)

VDDI Supply voltage for SubLVDS receivers(2) –0.5 2.3 V

Supply voltage for HVCMOS and micromirror

VOFFSET –0.5 10.6 V

electrode(2) (3)

Supply voltage for micromirror electrode bias

VBIAS –0.5 19 V

Supply voltage circuits(2)

Supply voltage for micromirror electrode reset

VRESET –15 0.3 V

circuits(2)

| VDDI–VDD | Supply voltage delta (absolute value)(4) 0.3 V

| VBIAS–VOFFSET | Supply voltage delta (absolute value)(5) 11 V

| VBIAS–VRESET | Supply voltage delta (absolute value)(6) 34 V

Input voltage for other –0.5 VDD + 0.5 V

inputs LPSDR(2)

Input voltage Input voltage for other –0.5 VDDI + 0.5 V

inputs SubLVDS(2) (7)

| VID | SubLVDS input differential voltage (absolute value)(7) 810 mV

Input pins IID SubLVDS input differential current 8.1 mA

ƒclock Clock frequency for low speed interface LS_CLK 130 MHz

Clock

frequency ƒclock Clock frequency for high speed interface DCLK 620 MHz

Temperature – operational(8) –10 90 °C

TARRAY and TWINDOW

Environmental Temperature – non-operational(8) –40 90 °C

TDP Dew Point (operating and non-operating) 81 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure above or below Recommended Operating Conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:

VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.

(3) VOFFSET supply transients must fall within specified voltages.

(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current

draw.

(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.

(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8) The highest temperature of the active array (as calculated by the Micromirror Array Temperature Calculation), or of any point along the

Window Edge as defined in Figure 19. The locations of thermal test points TP2 and TP3 in Figure 19 are intended to measure the

highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,

that test point should be used.

6.2 Storage Conditions

applicable before the DMD is installed in the final product. MIN MAX UNIT

Tstg DMD storage temperature –40 85

Storage Dew Point - long-term (1) 24 °C

TDP Storage Dew Point - short-term (2) 28

(1) Long-term is defined as the usable life of the device.

(2) Dew points beyond the specified long-term dew point are for short-term conditions only, where Short-term is defined as less than 60

cumulative days over the usable life of the device (operating, non-operating, or storage).

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6.3 ESD Ratings VALUE UNIT

Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

V(ESD) ±1000 V

discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN NOM MAX UNIT

SUPPLY VOLTAGE RANGE(3)

VDD Supply voltage for LVCMOS core logic 1.65 1.8 1.95 V

Supply voltage for LPSDR low-speed interface

VDDI Supply voltage for SubLVDS receivers 1.65 1.8 1.95 V

VOFFSET Supply voltage for HVCMOS and micromirror 9.5 10 10.5 V

electrode(4)

VBIAS Supply voltage for mirror electrode 17.5 18 18.5 V

VRESET Supply voltage for micromirror electrode –14.5 –14 –13.5 V

|VDDI–VDD| Supply voltage delta (absolute value)(5) 0.3 V

|VBIAS–VOFFSET| Supply voltage delta (absolute value)(6) 10.5 V

|VBIAS–VRESET| Supply voltage delta (absolute value)(7) 33 V

OUTPUT TERMINALS

IOH High-level output current at Voh = 0.8 × VDD –30 mA

IOL Low-level output current at Vol = 0.2 × VDD 30 mA

CLOCK FREQUENCY

ƒclock Clock frequency for low speed interface LS_CLK(8) 108 120 MHz

ƒclock Clock frequency for high speed interface DCLK(9) 300 600 MHz

Duty cycle distortion DCLK 44% 56%

SUBLVDS INTERFACE(9)

| VID | SubLVDS input differential voltage (absolute value) 150 250 350 mV

Figure 8,Figure 9

VCM Common mode voltage Figure 8,Figure 9 700 900 1100 mV

VSUBLVDS SubLVDS voltage Figure 8,Figure 9 575 1225 mV

ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω

ZIN Internal differential termination resistance Figure 10 80 100 120 Ω

100-Ωdifferential PCB trace 6.35 152.4 mm

LPSDR INTERFACE(10)

ZLINE Line differential impedance (PWB/trace) 61.2 68 74.8 Ω

(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(2) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by

the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the

Recommended Operating Conditions limits.

(3) All voltage values are with respect to the ground pins (VSS).

(4) VOFFSET supply transients must fall within specified max voltages.

(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(7) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit.

(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(9) Refer to the SubLVDS timing requirements in Timing Requirements.

(10) Refer to the LPSDR timing requirements in Timing Requirements.

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Micromirror Landed Duty Cycle

Operational (°C)

0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55

D001

50/50

100/0 95/5 90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45

Max Recommended Array Temperature –

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Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN NOM MAX UNIT

ENVIRONMENTAL

TARRAY Array temperature – operational, long-term (11) (12) (13) 0 40 to 70(11)

°C

Array temperature – operational, short-term (14) (12) –10 75

(13)

TWINDOW Window temperature – operational(15) 90 °C

|TDELTA | Absolute Temperature difference between any point 30 °C

on the window edge and the ceramic test point TP1(16)

ILLUV&VIS Illumination, wavelength < 700 nm 0.68 mW/cm2

ILLNIR Illumination, wavelength 700 - 2500 nm 2000 mW/cm2

ILLIR Illumination, wavelength > 2500 nm 10 mW/cm2

(11) Per Figure 1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD

experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty

cycle.

(12) Long-term is defined as the usable life of the device.

(13) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1) shown in Figure 19 and the package thermal resistance using Micromirror Array Temperature Calculation.

(14) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is

defined as cumulative time over the usable life of the device and is less than 500 hours for temperatures between long-term maximum

and 75°C, less than 500 hours for temperatures between 0°C and -10°C.

(15) Window temperature is the highest temperature on the window edge shown in Figure 19. The locations of thermal test points TP2 and

TP3 in Figure 19 are intended to measure the highest window edge temperature. If a particular application causes another point on the

window edge to be at a higher temperature, a test point should be added to that location.

(16) Temperature delta is the highest difference from the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 19.

The window test points TP2 and TP3 shown in Figure 19 are intended to result in the worst case delta temperature. If a particular

application causes another point on the window edge to result in a larger delta temperature, that point should be used.

SPACE

Figure 1. Max Recommended Array Temperature – Derating Curve

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6.5 Thermal Information DLP2010NIR

FQJ (CLGA)

THERMAL METRIC(1) UNIT

40 PINS

MIN TYP MAX

Thermal resistance Active area to test point TP1(1) 7.9 °C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Recommended Operating Conditions . The total heat load on the

DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the

window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling

outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT

CURRENT

VDD = 1.95 V 34.7

IDD Supply current: VDD(3) (4) mA

VDD = 1.8 V 27.5

VDDI = 1.95 V 9.4

IDDI Supply current: VDDI(3) (4) mA

VDD = 1.8 V 6.6

VOFFSET = 10.5 V 1.7

IOFFSET Supply current: VOFFSET(5) (6) mA

VOFFSET = 10 V 0.9

VBIAS = 18.5 V 0.4

IBIAS Supply current: VBIAS(5) (6) mA

VBIAS = 18 V 0.2

VRESET = –14.5 V 2

IRESET Supply current: VRESET(6) mA

VRESET = –14 V 1.2

POWER(7)

VDD = 1.95 V 67.7

PDD Supply power dissipation: VDD(3) (4) mW

VDD = 1.8 V 49.5

VDDI = 1.95 V 18.3

PDDI Supply power dissipation: VDDI(3) (4) mW

VDD = 1.8 V 11.9

VOFFSET = 10.5 V 17.9

Supply power dissipation:

POFFSET mW

VOFFSET(5) (6) VOFFSET = 10 V 9

VBIAS = 18.5 V 7.4

PBIAS Supply power dissipation: VBIAS(5) (6) mW

VBIAS = 18 V 3.6

VRESET = –14.5 V 29

PRESET Supply power dissipation: VRESET(6) mW

VRESET = –14 V 16.8

PTOTAL Supply power dissipation: Total 90.8 140.3 mW

LPSDR INPUT(8)

VIH(DC) DC input high voltage(9) 0.7 × VDD VDD + 0.3 V

VIL(DC) DC input low voltage(9) –0.3 0.3 × VDD V

VIH(AC) AC input high voltage(9) 0.8 × VDD VDD + 0.3 V

VIL(AC) AC input low voltage(9) –0.3 0.2 × VDD V

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

(2) All voltage values are with respect to the ground pins (VSS).

(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(4) Supply power dissipation based on non–compressed commands and data.

(5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(6) Supply power dissipation based on 3 global resets in 200 µs.

(7) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard

No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

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Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT

∆VTHysteresis ( VT+ – VT– )Figure 10 0.1 × VDD 0.4 × VDD V

IIL Low–level input current VDD = 1.95 V; VI= 0 V –100 nA

IIH High–level input current VDD = 1.95 V; VI= 1.95 V 100 nA

LPSDR OUTPUT(10)

VOH DC output high voltage IOH = –2 mA 0.8 × VDD V

VOL DC output low voltage IOL = 2 mA 0.2 × VDD V

CAPACITANCE

Input capacitance LPSDR ƒ = 1 MHz 10 pF

CIN Input capacitance SubLVDS ƒ = 1 MHz 20 pF

COUT Output capacitance ƒ = 1 MHz 10 pF

CRESET Reset group capacitance ƒ = 1 MHz; (480 × 108) micromirrors 95 113 pF

(10) LPSDR specification is for pin LS_RDATA.

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN NOM MAX UNIT

LPSDR

tRRise slew rate(1) (30% to 80%) × VDD, Figure 3 1 3 V/ns

tVFall slew rate(1) (70% to 20%) × VDD, Figure 3 1 3 V/ns

tRRise slew rate(2) (20% to 80%) × VDD, Figure 3 0.25 V/ns

tFFall slew rate(2) (80% to 20%) × VDD, Figure 3 0.25 V/ns

tCCycle time LS_CLK, Figure 2 7.7 8.3 ns

tW(H) Pulse duration LS_CLK 3.1 ns

50% to 50% reference points,Figure 2

high

tW(L) Pulse duration LS_CLK 3.1 ns

50% to 50% reference points, Figure 2

low

tSU Setup time LS_WDATA valid before LS_CLK ↑,Figure 2 1.5 ns

tHHold time LS_WDATA valid after LS_CLK ↑,Figure 2 1.5 ns

tWINDOW Window time(1) (3) Setup time + Hold time, Figure 2 3 ns

tDERATING Window time derating(1) For each 0.25 V/ns reduction in slew rate below 0.35 ns

(3) 1 V/ns, Figure 5

SubLVDS

tRRise slew rate 20% to 80% reference points, Figure 4 0.7 1 V/ns

tFFall slew rate 80% to 20% reference points, Figure 4 0.7 1 V/ns

tCCycle time LS_CLK, Figure 6 1.61 1.67 ns

tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6 0.71 ns

tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6 0.71 ns

D(0:3) valid before

tSU Setup time DCLK ↑or DCLK ↓,Figure 6

D(0:3) valid after

tHHold time DCLK ↑or DCLK ↓,Figure 6

tWINDOW Window time Setup time + Hold time, Figure 6,Figure 7 0.3 ns

tLVDS- Power-up receiver(4) 2000 ns

ENABLE+REFGEN

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 3.

(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 3.

(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

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1.0 * VID

VDCLK_P , VDCLK_N

VD_P(0:3) , VD_N(0:3)

0.0 * VID

VCM

0.2 * VID

0.8 * VID

0.0 * VDD

0.2 * VDD

0.3 * VDD

0.7 * VDD

0.8 * VDD

1.0 * VDD

VIH(AC)

VIH(DC)

VIL(DC)

VIL(AC)

LS_CLK, LS_WDATA

0.0 * VDD

0.2 * VDD

0.8 * VDD

1.0 * VDD

DMD_DEN_ARSTZ

LS_WDATA

LS_CLK

tw(H) tw(L)

50%50%50%

50% 50%

tsu

twindow

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Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in

JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.

Figure 2. LPSDR Switching Parameters

Figure 3. LPSDR Input Rise and Fall Slew Rate

Figure 4. SubLVDS Input Rise and Fall Slew Rate

Product Folder Links: DLP2010NIR

50%

50%50%

DCLK_N

DCLK_P

D_N(0:3)

D_P(0:3)

50%50%

tw(L) tw(H)

tsu

twindow

LS_WDATA

LS_CLK

tSU tH

tWINDOW

VIH MIN

VIL MAX

Midpoint

VIH MIN

VIL MAX

Midpoint

tSU tH

tWINDOW

VIH MIN

VIL MAX

Midpoint

VIH MIN

VIL MAX

Midpoint

LS_WDATA

LS_CLK

tDERATING

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

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Figure 5. Window Time Derating Concept

Figure 6. SubLVDS Switching Parameters

Product Folder Links: DLP2010NIR

VCM VID

VSubLVDS max = VCM max + | 1/2 * VID max|

0.575V

1.225V

VSubLVDS min = VCM min – | 1/2 * VID max |

DCLK_P , D_P(0:3)

DCLK_N , D_N(0:3)

SubLVDS

Receiver

VIN

VIP

VID

VCM

(VIP + VIN

) / 2

DCLK_ N

DCLK_ P

High Speed Training Scan Window

¼ tc

D_N(0:3)

D_P(0:3)

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Note: Refer to High-Speed Interface for details.

Figure 7. High-Speed Training Scan Window

Figure 8. SubLVDS Voltage Parameters

Figure 9. SubLVDS Waveform Parameters

Product Folder Links: DLP2010NIR

Tester Channel

Output Under Test

Data Sheet Timing Reference Point

Device Pin

Stop Start

LS_CLK

LS_WDATA

LS_RDATA

Acknowledge

tPD

VIH

Δ VT

VT+

VT- VIL

LS_WDATA

LS_CLK

Not to Scale

DCLK_P , D_P(0:3)

DCLK_N , D_N(0:3)

ESD

ESD Internal

Termination SubLVDS

Receiver

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

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Figure 10. SubLVDS Equivalent Input Circuit

Figure 11. LPSDR Input Hysteresis

Figure 12. LPSDR Read Out

See Timing for more information.

Figure 13. Test Load Circuit for Output Propagation Measurement

Product Folder Links: DLP2010NIR

µuZ[

(3 places)

µuZ[

(1 place)

DMD Mounting Area

(4 o}}]µuZ[vZ[

Connector Area

DLP2010NIR

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

6.8 Switching Characteristics(1)

Over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CL= 5 pF 11.1 ns

Output propagation, Clock to Q, rising

tPD edge of LS_CLK input to LS_RDATA CL= 10 pF 11.3 ns

output. Figure 12 CL= 85 pF 15 ns

Slew rate, LS_RDATA 0.5 V/ns

Output duty cycle distortion, LS_RDATA 40% 60%

(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

6.9 System Mounting Interface Loads

PARAMETER MIN NOM MAX UNIT

Maximum system mounting interface load to be applied to the: 45 N

• Connector area (see Figure 14)100 N

• DMD mounting area uniformly distributed over 4 areas (see Figure 14)

Figure 14. System Interface Loads

Product Folder Links: DLP2010NIR

Illumination

Mirror 2

Mirror 1

Mirror 0

Mirror 1

Mirror 2

Mirror 479

Mirror 478

Mirror 477

Mirror 851

Mirror 852

Mirror 853

DMD Active Mirror Array

Width

Height

Not To Scale

Mirror 476

Mirror 3

Mirror 850

854 Mirrors * 480 Mirrors

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

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6.10 Physical Characteristics of the Micromirror Array

VALUE UNIT

Number of active columns See Figure 15 854 micromirrors

Number of active rows See Figure 15 480 micromirrors

εMicromirror (pixel) pitch See Figure 16 5.4 µm

Micromirror pitch × number of active columns; see

Micromirror active array width 4.6116 mm

Figure 15

Micromirror active array height Micromirror pitch × number of active rows; see Figure 15 2.592 mm

Micromirror active border Pond of micromirror (POM)(1) 20 micromirrors/side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.

These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical

bias to tilt toward OFF.

Figure 15. Micromirror Array Physical Characteristics

Figure 16. Mirror (Pixel) Pitch

Product Folder Links: DLP2010NIR

Incident

Illumination

Light Path

(0,0)

(853,479)

(0,479)

(853,0)

Tilted Axis of

Pixel Rotation

Off-State

Landed Edge

On-State

Landed Edge

Off-State

Light Path

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6.11 Micromirror Array Optical Characteristics

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Micromirror tilt angle DMD landed state(1) 17 °

Micromirror tilt angle tolerance(1) (2) (3) (4) –1 1 °

(5)

Landed ON state 180

Micromirror tilt direction(6) (7) °

Landed OFF state 270

Micromirror crossover time Typical Performance 1.5 4 μs

Micromirror switching time Typical Performance 6

Adjacent micromirrors 0

Number of out-of-specification micromirrors

micromirrors(8) Non-adjacent micromirrors 10

(1) Measured relative to the plane formed by the overall micromirror array.

(2) Additional variation exists between the micromirror array and the package datums.

(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.

(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different

devices.

(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some

system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field

reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in

colorimetry variations, system efficiency variations or system contrast variations.

(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of

the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State

direction. A binary value of 0 results in a micromirror landing in the OFF State direction.

(7) Micromirror tilt direction is measured as in a typical polar coordinate system: measuring counter-clockwise from a 0° reference which is

aligned with the +X Cartesian axis.

(8) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the

specified Micromirror Switching Time.

Figure 17. Landed Pixel Orientation and Tilt

Product Folder Links: DLP2010NIR

Wavelength (nm)

Transmittance (%)

700 900 1100 1300 1500 1700 1900 2100 2300 2500

100

D001

Nominal

Minimum

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

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6.12 Window Characteristics

PARAMETER(1) MIN NOM MAX UNIT

Window material designation Corning Eagle XG

Window refractive index at wavelength 546.1 nm 1.5119

Window aperture(2) See (2)

Illumination overfill(3) See (3)

Window transmittance, single-pass Minimum within the wavelength range 92 96 %

through both surfaces and glass 700 to 2000 nm. at 0° angle of

incidence.

Window transmittance, single-pass Minimum within the wavelength range 85 90 %

through both surfaces and glass 2000 to 2500 nm. at 0° angle of

incidence.

(1) See Window Characteristics and Optics for more information.

(2) See the package mechanical characteristics for details regarding the size and location of the window aperture.

(3) The active area of the DLP2010NIR device is surrounded by an aperture on the inside of the DMD window surface that masks

structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light

illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the

DMD. The illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the

average flux level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of

overfill light on the outside of the active array may cause system performance degradation.

6.13 Chipset Component Usage Specification

The DLP2010NIR is a component of one or more DLP chipsets. Reliable function and operation of the

DLP2010NIR requires that it be used in conjunction with the other components of the applicable DLP chipset,

including those components that contain or implement TI DMD control technology. TI DMD control technology is

the TI technology and devices for operating or controlling a DLP DMD.

NOTE

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical

system operating conditions exceeding limits described previously.

6.14 Typical Characteristics

Figure 18. DLP2010NIR DMD Window Transmittance

Product Folder Links: DLP2010NIR

VBIAS

VRESET

VSS

VOFFSET

VDDI

D_P(0:3)

DCLK_P

DCLK_N

LS_WDATA

LS_CLK

LS_RDATA

DMD_DEN_ARSTZ

High Speed Interface

Column Write

Bit Lines

Word Lines

(0,0)

(479, 853)

SRAM

Control

Row

Voltage

Generators

Misc

VDD

VBIAS

VSS

VOFFSET

VDD

VRESET

D_N(0:3)

Column ReadControl Control

Low Speed Interface

Voltages

DLP2010NIR

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

7 Detailed Description

7.1 Overview

The DLP2010NIR is a 0.2 inch diagonal spatial light modulator designed for near-infrared applications. Pixel

array size is 854 columns by 480 rows in a square grid pixel arrangement. The electrical interface is Sub Low

Voltage Differential Signaling (SubLVDS) data.

DLP2010NIR is one device in a chipset, which includes the DLP2010NIR DMD, the DLPC150 controller and the

DLPA200X (DLPA2000 or DLPA2005) PMIC. To ensure reliable operation, the DLP2010NIR DMD must always

be used with a DLPC150 controller and a DLPA200X PMIC.

7.2 Functional Block Diagram

Details omitted for clarity.

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7.3 Feature Description

7.3.1 Power Interface

The power management IC, DLPA200X, contains 3 regulated DC supplies for the DMD reset circuitry: VBIAS,

VRESET and VOFFSET, as well as the 2 regulated DC supplies for the DLPC150 controller.

7.3.2 Low-Speed Interface

The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is the

low–speed clock, and LS_WDATA is the low speed data input.

7.3.3 High-Speed Interface

The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed

DDR transfer and compression techniques to save power and time. The high-speed interface is composed of

differential SubLVDS receivers for inputs, with a dedicated clock.

7.3.4 Timing

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. Figure 13 shows an equivalent test load circuit for the

output under test. Timing reference loads are not intended as a precise representation of any particular system

environment or depiction of the actual load presented by a production test. System designers should use IBIS or

other simulation tools to correlate the timing reference load to a system environment. The load capacitance value

stated is only for characterization and measurement of AC timing signals. This load capacitance value does not

indicate the maximum load the device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC150 controller. See the DLPC150 controller data sheet or

contact a TI applications engineer.

7.5 Window Characteristics and Optics

NOTE

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical

system operating conditions exceeding limits described previously.

7.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections:

7.5.1.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The mirror tilt angle defines DMD capability to separate the ON optical path from any other light

path, including undesirable flat–state specular reflections from the DMD window, DMD border structures, or other

system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt

angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination

numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur and affect

system performance.

Product Folder Links: DLP2010NIR

Illumination

Direction

Off-state

Light

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

Window Characteristics and Optics (continued)

7.5.1.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable

artifacts in the display’s border and/or active area, which may require additional system apertures to control,

especially if the numerical aperture of the system exceeds the pixel tilt angle.

7.5.1.3 Illumination Overfill

The active area of the device is surrounded by an aperture on the inside DMD window surface that masks

structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating

conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window

aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system

should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately

10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill

light may have to be further reduced below the suggested 10% level in order to be acceptable.

7.6 Micromirror Array Temperature Calculation

Figure 19. DMD Thermal Test Points

Micromirror array temperature can be computed analytically from measurement points on the outside of the

package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load.

The relationship between micromirror array temperature and the reference ceramic temperature is provided by

the following equations:

TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC) (1)

QARRAY = QELECTRICAL + QILLUMINATION (2)

QILLUMINATION = (AILLUMINATION × PNIR X DMD absorption factor)

where

• TARRAY = Computed DMD array temperature (°C)

• TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 19

• RARRAY–TO–CERAMIC = DMD package thermal resistance from array to outside ceramic (°C/W) specified in

Thermal Information

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Micromirror Array Temperature Calculation (continued)

• QARRAY = Total DMD power; electrical, specified in Electrical Characteristics , plus absorbed (calculated) (W)

• QELECTRICAL = Nominal DMD electrical power dissipation (W), specified in Electrical Characteristics

• AILLUMINATION = Illumination area (assumes 83.7% on the active array and 16.3% overfill)

• PNIR = Illumination Power Density (W/cm2) (3)

Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating

frequencies. Refer to the specifications in Electrical Characteristics. Absorbed power from the illumination source

is variable and depends on the operating state of the mirrors and the intensity of the light source. The DMD

absorption constant of 0.42 assumes nominal operation with an illumination distribution of 83.7% on the DMD

active array, and 16.3% on the DMD array border and window aperture.

A sample calculation is detailed below:

TCERAMIC = 35 °C, assumed system measurement; see Recommended Operating Conditions for specification

limits

PNIR= 2 W/cm2

QELECTRICAL = 0.0908 W; See the table notes in Recommended Operating Conditions for details.

AILLUMINATION = 0.143 cm2

QARRAY = QELECTRICAL + (QILLUMINATION X DMD absoprtion factor) = 0.0908 W + (2 W/cm2X 0.143 cm2X 0.42)

= 0.211 W

TARRAY = 35 °C + (0.211 W × 7.9°C/W) = 36.67 °C

7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle

The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a

percentage) that an individual micromirror is landed in the On state versus the amount of time the same

micromirror is landed in the Off state.

As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On state 100% of the

time (and in the Off state 0% of the time), whereas 0/100 would indicate that the pixel is in the Off state 100% of

the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.

Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other

state (OFF or ON) is considered negligible and is thus ignored.

Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)

always add to 100.

7.7.2 Landed Duty Cycle and Useful Life of the DMD

Knowing the long-term average landed duty cycle (of the end product or application) is important because

subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed

duty cycle for a prolonged period of time can reduce the DMD’s usable life.

Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed

duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed

duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly

asymmetrical.

7.7.3 Landed Duty Cycle and Operational DMD Temperature

Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this

interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s

usable life. This is quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:

• All points along this curve represent the same usable life.

• All points above this curve represent lower usable life (and the further away from the curve, the lower the

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

Micromirror Landed-On/Landed-Off Duty Cycle (continued)

usable life).

• All points below this curve represent higher usable life (and the further away from the curve, the higher the

usable life).

In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at

for a give long-term average Landed Duty Cycle.

7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application

During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being

displayed by that pixel.

For example, in binary pattern display with value '1' or when displaying pure-white on a given pixel for a given

time period, that pixel will experience a 100/0 Landed Duty Cycle during that time period. Likewise, a binary

pattern display with value '0' or when displaying pure-black, the pixel will experience a 0/100 Landed Duty Cycle.

Table 1. Binary Pattern Mode

Example: Binary Value and

Landed Duty Cycle

BINARY LANDED DUTY

VALUE CYCLE

0 0/100

1 100/0

During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:

Landed Duty Cycle = ∑{Pattern[i]_Binary_Value} / {Total_Patterns}

where

• Pattern[i]_Binary_Value represent a pixel's pattern and its corresponding binary value over all patterns in the

pattern sequence: Total_Patterns. (4)

For example, assume a pattern sequence with three patterns using pixel x. In this sequence the first pattern has

pixel x on, the second pattern has pixel x off, and the third pattern has pixel x off. Thus, the Landed Duty Cycle is

33%.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two

directions, with the primary direction being into a projection or collection optic. Each application is derived

primarily from the optical architecture of the system and the format of the data coming into the DLPC150

controller. The new high tilt pixel in the side illuminated DMD increases device efficiency and enables a compact

optical system. The DLP2010NIR DMD can be combined with a grating and single element detector to replace

expensive InGaAs linear array detector designs, leading to high performance, cost-effective portable NIR

Spectroscopy solutions. Applications of interest include machine vision systems, spectrometers, medical

systems, skin analysis, material identification, chemical sensing, infrared projection, and compressive sensing.

DMD power-up and power-down sequencing is strictly controlled by the DLPA2000 or DLPA2005. Refer to

Power Supply Recommendations for power-up and power-down specifications. DLP2010NIR DMD reliability is

only specified when used with DLPC150 controller and DLPA2000 or DLPA2005 PMIC/LED Driver.

8.2 Typical Application

A typical embedded system application using the DLPC150 controller and DLP2010NIR is shown in Figure 20. In

this configuration, the DLPC150 controller supports a 24-bit parallel RGB input, typical of LCD interfaces, from an

external source or processor. The DLPC150 controller processes the digital input image and converts the data

into the format needed by the DLP2010NIR. The DLP2010NIR steers light by setting specific micromirrors to the

on position, directing light to the detector, while unwanted micromirrors are set to "off" position, directing light

away from the detector. The microprocessor sends binary images to the DMD to steer specific wavelengths of

light into the detector. The microprocessor uses an analog-to-digital converter to sample the signal received by

the detector into a digital value. By sequentially selecting different wavelengths of light and capturing the values

at the detector, the microprocessor can then plot a spectral response to the light.

Product Folder Links: DLP2010NIR

Power

Management

1.1 V

WVGA

DDR DMD

DLP2010NIR

(WVGA

DMD)

DLP® Chip Set

1.8S V

2.3 to 5.5 V

DLPA2000

DLPA2005

PARKZ

1.1 V

1.8S V

VCORE

VIO

Projection

Optics

BIAS, RST, OFS

Thermistor

VCC_INTF

DLPC150

VCC_FLSH

SPI_1

1.8 V

Other

Supplies 1.1-V

Reg

FLASH,

SDRAM

Keypad

Microprocessor

ADC

Charger

DC_IN

VDD

On/Off

FLASH

PROJ_ON

LS_IN

SPI_0

LED_SEL(2)

RESETZ

CMP_PWM

CMP_OUT

INTZ

Sub-LVDS DATA

LPSDR CTRL

PROJ_ON

SYSPWR

1.8 V

PROJ_ON

HOST_IRQ

Parallel RGB I/F (28)

I2C

BAT

–

VIN

TRIG_IN

TRIG_OUT (2)

ADC + Ampliﬁer

Card

Bluetooth

USB

Illumination

Optics

Detector

Current

Sense

VLED

RED

NIR

Detector

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DLPS059A –MARCH 2015–REVISED OCTOBER 2015

Typical Application (continued)

Figure 20. Typical Application Diagram

8.2.1 Design Requirements

All applications using DLP 0.2-inch WVGA chipset require the DLPC150 controller, DLPA2000 or DLPA2005

PMIC, and DLP2010NIR DMD components for operation. The system also requires an external SPI flash

memory device loaded with the DLPC150 Configuration and Support Firmware. The chipset has several system

interfaces and requires some support circuitry. The following interfaces and support circuitry are required for the

DLP2010NIR:

• DMD Interfaces:

– DLPC150 to DLP2010NIR SubLVDS Digital Data

– DLPC150 to DLP2010NIR LPSDR Control Interface

• DMD Power:

– DLPA2000 or DLPA2005 to DLP2010NIR VBIAS Supply

– DLPA2000 or DLPA2005 to DLP2010NIR VOFFSET Supply

– DLPA2000 or DLPA2005 to DLP2010NIR VRESET Supply

– DLPA2000 or DLPA2005 to DLP2010NIR VDDI Supply

– DLPA2000 or DLPA2005 to DLP2010NIR VDD Supply

The illumination light that is applied to the DMD is typically from an infrared LED or lamp.

8.2.2 Detailed Design Procedure

For connecting together the DLPC150, the DLPA2005, and the DLP2010NIR DMD, see the TI DLP NIRscan

Nano EVM reference design schematic.

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Typical Application (continued)

8.2.3 Application Curve

In a reflective spectroscopy application, a broadband light source illuminates a sample and the reflected light

spectrum is dispersed onto the DLP2010NIR. A microprocessor in conjunction with the DLPC150 controls

individual DLP2010NIR micromirrors to reflect specific wavelengths of light to a single point detector. The

microprocessor uses an analog-to-digital converter to sample the signal received by the detector into a digital

value. By sequentially selecting different wavelengths of light and capturing the values at the detector, the

microprocessor can then plot a spectral response to the light. This systems allows the measurement of the

collected light and derive the wavelengths absorbed by the sample. This process leads to the absorption

spectrum shown in Figure 21.

SPACE

Figure 21. Sample DLP2010NIR Based Spectrometer Output

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and

VRESET. DMD power-up and power-down sequencing is strictly controlled by the DLPA2000 or DLPA2005

device.

CAUTION

For reliable operation of the DMD, the following power supply sequencing

requirements must be followed. Failure to adhere to the prescribed power-up and

power-down procedures may affect device reliability.

VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated

during power-up and power-down operations. Failure to meet any of the below

requirements will result in a significant reduction in the DMD’s reliability and lifetime.

Refer to Figure 23. VSS must also be connected.

9.1 Power Supply Power-Up Procedure

• During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET

voltages are applied to the DMD.

• During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the

specified limit shown in Recommended Operating Conditions. Refer to Table 2 and the Layout Example for

power-up delay requirements.

• During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled

at operating voltage.

• During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow

the requirements listed previously and in Figure 22.

9.2 Power Supply Power-Down Procedure

• Power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be

supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.

• During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement

that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended

Operating Conditions (Refer to Note 2 for Figure 22).

• During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in

Recommended Operating Conditions.

• During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and

VBIAS.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements listed previously and in Figure 22.

Product Folder Links: DLP2010NIR

VOFFSET

VBIAS

VRESET

VOFFSET

VBIAS

VDD / VDDI

Mirror Park

Sequence

Power Off

VBIAS < 4 V

VOFFSET < 4 V

VRESET < 0.5 V

VDD

VRESET > - 4 V

VSS

DMD_DEN_ARSTZ

Note 4

VSS

VDD

VDD / VDDI VSS

VSS

LS_WDATA

DCLK_P, DCLK_N VSS

VID

VSS

VDD / VDDI

VBIAS

VOFFSET

VRESET

VDD

VID

Note 2

Note 3

ûV < Specification Limit

Note 2

LS_CLK

D_P(0:3), D_N(0:3)

< 6 V

VDD < VBIAS < 6 V

INITIALIZATION

DLP Display Controller and

PMIC control start of DMD

operation

DLP Display Controller and PMIC

disable VBIAS, VOFFSET and

VRESET

Note 1

ûV < Specification Limit

VDD < VOFFSET

DLP2010NIR

DLPS059A –MARCH 2015–REVISED OCTOBER 2015

www.ti.com

9.3 Power Supply Sequencing Requirements

(1) Refer to Table 2 and Figure 23 for critical power-up sequence delay requirements.

(2) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in

Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET

prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. Refer to Table 2 and

Figure 23 for power-up delay requirements

(3) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in

Recommended Operating Conditions.

(4) When system power is interrupted, the ASIC driver initiates hardware power-down that disables VBIAS, VRESET and

VOFFSET after the Micromirror Park Sequence. Software power-down disables VBIAS, VRESET, and VOFFSET

after the Micromirror Park Sequence through software control.

(5) Drawing is not to scale and details are omitted for clarity.

Figure 22. Power Supply Sequencing Requirements (Power Up and Power Down)

Product Folder Links: DLP2010NIR

VOFFSET

VBIAS

VSS

VDD VOFFSET≤< 6 V

VDD VBIAS≤< 6 V

VSS

tDELAY

20 V

16 V

12 V

8 V

4 V

0 V

12 V

8 V

4 V

0 V

DLP2010NIR

www.ti.com

DLPS059A –MARCH 2015–REVISED OCTOBER 2015

Power Supply Sequencing Requirements (continued)

Table 2. Power-Up Sequence Delay Requirement

PARAMETER MIN UNIT

tDELAY Delay requirement from VOFFSET power up to VBIAS power up 2 ms

VOFFSET Supply voltage level during power–up sequence delay (see Figure 23) 6 V

VBIAS Supply voltage level during power–up sequence delay (see Figure 23) 6 V

A. Refer to Table 2 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.

Figure 23. Power-Up Sequence Delay Requirement

Product Folder Links: DLP2010NIR

DLP2010NIR

DLPS059A –MARCH 2015–REVISED OCTOBER 2015

www.ti.com

10 Layout

10.1 Layout Guidelines

There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board

connector to a flex cable. Flex cable provides the interface of data and Ctrl signals between the DLPC343x

controller and the DLP2010 DMD. For detailed layout guidelines refer to the layout design files. Some layout

guideline for the flex cable interface with DMD are:

• Match lengths for the LS_WDATA and LS_CLK signals.

• Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 24.

• Minimum of 100-nF decoupling capacitor close to VBIAS. Capacitor C4 in Figure 25.

• Minimum of 100-nF decoupling capacitor close to VRST. Capacitor C6 in Figure 25.

• Minimum of 220-nF decoupling capacitor close to VOFS. Capacitor C7 in Figure 25.

• Optional minimum 200- to 220-nF decoupling capacitor to meet the ripple requirements of the DMD. C5 in

Figure 25.

• Minimum of 100-nF decoupling capacitor close to Vcci. Capacitor C1 in Figure 25.

• Minimum of 100-nF decoupling capacitor close to both groups of Vcc pins, for a total of 200 nF for Vcc.

Capacitor C2/C3 in Figure 25.

10.2 Layout Example

Figure 24. High-Speed (HS) Bus Connections

Product Folder Links: DLP2010NIR

DLP2010NIR

www.ti.com

DLPS059A –MARCH 2015–REVISED OCTOBER 2015

Layout Example (continued)

Figure 25. Power Supply Connections

Product Folder Links: DLP2010NIR

GHJJJJK VVVVH

DLP2010NIRFQJ

Package Type

Device Descriptor

NIR DMD

DLP2010NIR

DLPS059A –MARCH 2015–REVISED OCTOBER 2015

www.ti.com

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Figure 26. Part Number Description

11.1.2 Device Markings

Device Marking will include the human–readable character string GHJJJJK VVVV on the electrical connector.

GHJJJJK is the lot trace code. VVVV is a 4 character encoded device part number

Figure 27. DMD Marking

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 3. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

DLPC150 Click here Click here Click here Click here Click here

DLPA2000 Click here Click here Click here Click here Click here

DLPA2005 Click here Click here Click here Click here Click here

Product Folder Links: DLP2010NIR

DLP2010NIR

www.ti.com

DLPS059A –MARCH 2015–REVISED OCTOBER 2015

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

DLP is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: DLP2010NIR

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DLP2010NIRFQJ ACTIVE CLGA FQJ 40 1 RoHS & Green Call TI Level-1-NC-NC

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

SECTION A-A

NOTCH OFFSETS

DWG NO. SH

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INV11-2006a

2512515 1

TITLE

SIZE DWG NO REV

SCALE SHEET OF

DATE

ENGINEER

QA/CE

APPROVED

DRAWN

INSTRUMENTS

Dallas Texas

APPLICATION

NEXT ASSY USED ON

THIRD ANGLE

PROJECTION

TEXAS

UNLESS OTHERWISE SPECIFIED

DIMENSIONS AR E IN MILLIMETERS

TOLERANCES:

ANGLES 1

2 PLACE DECIMALS 0.25

1 PLACE DECIMALS 0.50

DIMENSIONAL LIMITS APPLY BEFORE PROCESSES

INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME

Y14.5M-1994

REMOVE ALL BURRS AND SHARP EDGES

PARENTHETICAL INFORMATION FOR REFERENCE ONLY

ICD, MECHANICAL, DMD,

.2 WVGA SERIES 244

2512515 1 3

9/14/2012

20:1

P. KONRAD

F. ARMSTRONG

M. SOUCEK

9/26/2012

9/18/2012

9/14/2012

0314DA

B. HASKETT

NOTES UNL E SS O T HERWISE SPECIFIED: REVISIONS

UN-PUBLISHED, AL L RIGHTS RESERVED.

B. HASKETT

M. DORAK 9/18/2012

H H

REV DESCRIPTION DATE BY

A ECO 2127544: INITIAL RELEASE 9/14/2012 BMH

B ECO 2129552: E NL A R GE APERTURE ON RIGHT SIDE;

MOVE ACTIVE ARRA Y Y-LOCATION DIM, SH. 3 12/10/2012 BMH

C ECO 21312 5 2: E NL A R GE APERTURE ALONG BOTTOM EDG E 2/20/2013 BMH

D ECO 2135244: CORR E C T WI NDOW THK TOL, ZONE B6 8/5/2013 BMH

E ECO 2138016: INCREASE WINDOW THK NOMINAL 11/21/2013 BMH

2.65 -0.1

0.2

1.1760.05

0.780.063

1.0030.077 0.70.05 D

(1.783) A3 SURFACES INDICATED

IN VIEW B (SHEET 2)

DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY.

ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION

TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES.

BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.

DMD MARKING TO APPEAR IN CONNECTOR RECESS.

NOTCH DIMENSIONS ARE DEFINED BY UPP ERM O ST L A YE RS O F CERA MIC,

AS SHOWN IN SECTION A-A.

ENCAPSULA NT TO BE CONTAINED WITHI N DI MENSIONS SHOWN IN VIE W C

(SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW.

ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW.

DATUM B IS DEFINED BY A DIA. 2.5 PIN, WITH A FLAT ON THE SIDE FACING

TOWARD THE CENTER OF THE ACTIVE ARRAY, AS SHOWN IN VIEW B (SHEET 2).

WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED

FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1,

TO SUPPORT MECHANICAL LOADS.

(ILLUMINATION

DIRECTION)

ACTIVE ARRAY

0.038A

0.02D

(PANASONIC AXT640124DD1, 40-CONTACT, 0.4 mm

PITCH BOARD-TO-BOARD CONNECTOR HEADER)

MATES WITH PANASONIC AXT540124DD1 OR EQUIVALENT

CONNECTOR SOCKET

(SHEET 3)

(2.5)

2X ENCAPSULANT

(0.88)

(2.5)

90°1°

5.3 -0.1

0.3

15.9 -0.1

0.3

0.8 -0.1

0.2

+14.10.08 (1)

1.4 -0.1

0.2

2.50.0752X

0.4R0.14X

4X (R0.2)

1.40.1

50.05

1.25 5

0.4 MIN

TYP.

(1.4)

0 MIN TYP.

(OFF-STATE

DIRECTION)

VIEW B

DATUMS A, B, C, AND E

(FROM SHEET 1)

VIEW C

ENCAPSULANT MAXIMUM X/Y DIMENSIONS

(FROM SHEET 1)

VIEW D

ENCAPSULANT MAXIMUM HEIGHT

DWG NO. SH

8765431

INV11-2006a

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SIZE DWG NO REV

SCALE SHEET OF

DATE

INSTRUMENTS

Dalla s Texas

TEXAS DRAWN 2512515 2 3

B. HASKETT 9/14/2012

1.1762X

(0.8)2X

14.12X (1)2X

1.454X

(1.2)4X

2.5

A3 A2

1.25

(1.1)

1.25

(2.5) C

5.5

1.176 14.1

2.75

0 MIN2X 7

VIEW E

WINDOW AND ACTIVE ARRAY

(FROM SHEET 1)

VIEW H-H

TEST PADS AND CONNECTOR

(FROM SHEET 1)

DETAIL F

APERTURE LEFT EDGE

SCALE 60 : 1

DETAIL G

APERTURE RIGHT EDGE

(POND OF MIRRORS OMITTED FOR CLARITY)

SCALE 60 : 1

DWG NO. SH

8765431

INV11-2006a

2512515 3

SIZE DWG NO REV

SCALE SHEET OF

DATE

INSTRUMENTS

Dalla s Texas

TEXAS DRAWN 2512515 3 3

B. HASKETT 9/14/2012

(4.6116)

ACTIVE ARRAY

(2.592)

ACTIVE ARRAY

6.4540.075

1.1020.075

0.940.05

3.920.05

(4.86)

WINDOW

0.1340.0635

3.0160.0635 (3.15)

APERTURE

4.8390.06350.4240.0635

6.5050.052.9610.05

(9.466)

WINDOW

(2.5)

(0.15) TYP.

(0.068) TYP.





(2.5)

3.326

0.932X 0.4ABC

0.4ABC

0.2ABC

0.1A

H20

1.25

1.25 C

(ILLUMINATION

DIRECTION)

H1G1

G20

4.465 X 0.892 =

2.23

BACK INDEX MARK

53X TEST PADS

50X 0.6±0.1 X 0.54±0.1

3X Ø0.54±0.1

(5.263)

APERTURE

(42°) T YP.

(42°) TY P.

(1.86)2X

(9.8)

(42°) T YP.

(0.075) TYP.



(0.068) TYP. 14.418 X 0.8 = 1.026

(0.108)4X

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DLP2010NIRFQJ