Features e 55, 70 ns access time CMOS for optimum speed/power Wide voltage range: 2.7V3.6V Low active power (70 ns, LL version) 108 mW (max.) @ Low standby power (70 ns, LL version) 18 pW (max.) Easy memory expansion with CE and OE features e TTL-compatible inputs and outputs e Automatic power-down when deselected PRELIMINARY CY62256V Functional Description The CY62256V is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 98% when de- selected. The CY62256V isin the standard 450-mil-wide (300-mil body width) SOIC, TSOP and reverse TSOP packages. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/ 32K x 8 Static RAM output pins (1/O9 through I/O) is written into the memory location addressed by the address present on the address pins (Ag through Ay4). Reading the device is ac- complished by selecting the device and en- abling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the con- tents of the location addressed by the in- formation on address pins is present on the eight data input/output pins. The input/output pins remain in a high-im- pedance state unless the chip is selected, outputs are enabled, and write enable WE) is HIGH. A die coat is used to en- sure alpha immunity. Logic Block Diagram INPUT BUFFER 512x512 ARRAY cc wi a 9 o wi a = o x man COLUMN Ri = 2 =< wr a oo or Pin Configurations Oo VO, VOo VO3 VO, SENSE AMPS Os, Og VOz CG2256V-1 SOIC Top View 451 28D Voo Ae W2 271) WE Ard3 260A, Ag 04 2510 Ag Ag 5 247 Ag Aw Ws 23 A; Ai 7 220 OE Ai 08 21 HN Ag ars OS oH ce 14 10 I) t/ O,qi1 180 Vor vO, 12 170 VOs VO. 413 1600 W/O, GND Gia = 15 Wg ce22seve2 Cypress Semiconductor Corporation 3901 North First Street @ San Jose CA 95134 @ 408-943-2600 March 1996 Revised May 1996PRELIMINARY CY62256V Pin Configurations (continued eur ( ) TSOP Top View OE | 22 21 Aid] 2a 20 a Ao 24 19L] 1/07 A3 O 25 18L] Og A, @ 26 171] W/Os5 ed oie Vi 28 18 As ; 140] GND AsO 2 1a] Oe Arg 3 12] 1/0, AsO 4 1100 1/09 Ag O 5 10] Aa Ai 6 90) Ai3 Awd 7 8H Are cez2sev-a TSOP Reversed Top View Aud 7 80 Ais Ao 6 90 Aig Ao 5 10D Aya AsO a4 10) WOo x q 3 12 A vor 2 1390 VO. As, mo): 140 GND Voc Ch 28 160 Og we q 27 16H 04 A, 2 7B Os Ag Q 2 180 Vg Ao 24 if Oz AiG 2 20 CE oe 4_ 219) Ag Cez25ev-4 Selection Guide CY62256V55 CY62256V70 Maximum Access Time (ns) 55 70 Maximum Operating Current (mA} 50 50 L 50 50 LL 30 30 Maximum Standby Current (uA) 500 500 L 50 50 LL 5 Shaded area contains advanced information. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, DC Input Voltage) ................. -O0.5V to Voc + 0.5V not tested.) Output Current into Outputs (LOW) ............... 20mA Storage Temperature .... 0. cece cere eae -65C to +150C Static Discharge Voltage ...........0 000000 cee eee >2001V Ambient Temperature with (per MIL-STD-883, Method 3015) Power Applied ........ 0... e cece eee ence ees OCto +70C = Latch-Up Current 0.0.0.0... 0. ccc cece e een eens >200 mA Supply Voltage to Ground Potential ing Ran (Pin 28 to Pin 14) .......ccccccceeeeeeeees -osvto +46v Operating Range DC Voltage Applied to Outputs Range Ambient Temperature Voc In High Z State Wis ee cee ceseees 0.5 to Veco + 0.5V Commercial 0Cto +70C 2TV to 3.6V Notes: 1. Vy. (min.) = 2.0V for pulse durations of less than 20 ns.PRELIMINARY CY62256V Electrical Characteristics Over the Operating Range CY62256V55 | CY62256V70 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Unit Vou Output HIGH Voltage Vcc = Min. Iog = 1.0mA 24 2.4 Vv VoL Output LOW Voltage Vcc = Min, Ip, = 2.1 mA 0.4 0.4 Vv Vin Input HIGH Voltage 2.2 Veco 2.2 Voc Vv +037 +03V VIL Input LOW Voltage -0,5 0.8 -0.5 0.8 Vv Ibx Input Load Current GND < V) < Vcc -1 +1 -1 +1 pA loz Output Leakage Current GND < Vo < Vcc, Output 5 +5 -5 +5 pA Disabled los Output Short Circuit Vcc = Max., Vour = GND 200 -200 | mA Currentl?1 Icc Vcc Operating Supply Vcc = Max. 50 50 mA Current Iout = 0 mA, f = fax = Ltrc L 50 50 LL 30 30 spi Automatic CE Max. Vcc, CE > Vip 5 5 mA Power-Down Current Vin 2 Vin or L 3 TTL Inputs Vin < Vis f = fax LL 1 1 Isp2 Automatic CE Max. Vcc, 500 300 pA Power-Down Current CE > Vcc 0.3V L 50 50 CMOS Inputs Vin = Vcc 03V or Vn < 0.3V,f=90 LL 5 5 Shaded area contains advanced information. Capacitance!) Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 6 pF CoutT Output Capacitance Vee = 3.0V 8 pF Note: 2. Notmore than one output should be shorted at onetime. Durationof 3. Tested initially and after any design or process changes that may affect the short circuit should not exceed 30 seconds. these parameters. AC Test Loads and Waveforms 1.1 kQ SV 0"wr ALL INPUT PULSES out F 30V 50 pF Re GND | L' 55 ke <5ns INCLUDING = = ~ JIG AND ~ ~ SCOPE CR2256V'5 CR2256V.6 Equivalent to: THEVENIN EQUIVALENT 6432 OUTPUT 9nan 1.75PRELIMINARY CY62256V Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions|*] Min. Max. Unit VpR Vcc for Data Retention 2.0 Vv IccpR Data Retention Current Vcc = Vopr = 3.09, 200 uA CE > Voc - 034, L Vin = Vec 0.3V or 20 pA LL Vn <03V 5 uA tcprl) Chip Deselect to Data 0 ns Retention Time tpl] Operation Recovery Time tre ns Data Retention Waveform DATA RETENTION MODE Veo 3.0V Vor = 2V 3.0V j~ cpr tk CALMLLLLLLJ ROY C62256V-7 Switching Characteristics Over the Operating Rangel>) CY62256V 55 CY62256V70 Parameter Description Min. Max. Min. Max. Unit READ CYCLE tre Read Cycle Time SS 70 ns tad Address to Data Valid 55 70 ns toHA Data Hold from Address Change 3 3 nis tacE CE LOW to Data Valid 55 70 ns took OE LOW to Data Valid 25 35 ns tLZ0E OE LOW to Low ZI] 3 3 ns tHZz0R OE HIGH to High Z/6 7] 20 25 ns tLZCE CE LOW to Low ZS] 3 3 ns tHZCE CE HIGH to High Z@.71 20 25 ns teu CE LOW to Power-Up 0 0 ns tpp CE HIGH to Power-Down 55 70 ns Shaded area contains advanced information. Notes: 4, No input may exceed Voc +0.3V. 7. tyzor. tyzcr. and tyzwe are specified with C, = 5 pF as in part (b) 5. Test conditions assume signal transition time of 5 nsor less timing ref- of AC Test Loads. Transition is measured +500 mV from steady-state erence levels of 1.5V, inputpulse levels of 0 to 3.0V., and output loading voltage. of the specified Ig /loy and 100-pF load capacitance. 6. At any given temperature and voltage condition, tyzce is less than tizce. tyzok is Jess than thzog. and tyzweisless than thzwe for any given device.PRELIMINARY CY62256V Switching Characteristics Over the Operating Rangell CY62256V 55 CY62256V70 Parameter Description Min. Max. Min. Max. Unit WRITE CYCLE? tw Write Cycle Time 53 70 ns tscEe CE LOW to Write End 45 60 ns taw Address Set-Up to Write End 45 60) ns tHa Address Hold from Write End 0 ns tsa Address Set-Up to Write Start 0 ns tpwe WE Pulse Width 40 50 ns tsp Data Set-Up to Write End 25 30 ns typ Data Hold from Write End 0 0 ns tHzwE WE LOW to High ZI- 7] 20 25 ns tLZWE WE HIGH to Low Z/ 3 3 ns Shaded area contains advanced information. Switching Waveforms Read Cycle No, 110. 11] trc | ADDRESS * a tas | DATA OUT PREVIOUS DATA VALID KxKx DATA VALID C82256V.8 Read Cycle No. 2/11. 12] te \ at tre *- fT \ /) nat tace > DE To \ tHZz0& at t zoe | IHZCE HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT K DATA VALID tizce = t bx tpp >, re tpy supPiy 0% som Ice 5 CURRENT XL ISB Gea2sev-9 Notes: 8 The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LO'W to initiate a write and either signal can terminate a write by going HIGH. The data input set- up and holdtiming should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tyzwe and tsp. 10. Device is continuously selected. OE, CE = Vj,. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW.PRELIMINARY CY62256V Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[&: 13. 14] ADDRESS 4 EMA V ] = a . taw mrs tha 7 tsa * * tpwe * e V ROSS 7 cE Y v < tsp eas tip DATA W/O NOTE 15. DATAin VALID tHz0E 062256v-10 Write Cycle No. 2 (CE Controlled)l3: 13, 14) a two > appRess * cE N tt tsce ool tsa > KU at tow it ty - FE UMQOQAAQL LLL ___ tsp _____- typ DATA VO DATA) VALID O62256V-11 Write Cycle No. 3 (WE Controlled, OF LOW)I> 14] nit twe ADDRESS x x = WSS LA Ze, tt taw e tH tsa WE N 7 a tsp ae] typ NSN iv orrauo KKK Oath VAD XXX t ee ti 7we HOWE G62256V-12 Notes: 13. Data J/O is high impedance if OE = Vi. 13. During this period, the I/Os are in outputstate and inputsignalsshould 14, IfCE goes HIGH simultaneously with WE HIGH. the output remains not be applied. in a high-impedance state.PRELIMINARY CY62256V Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT ys. SUPPLY VOLTAGE 1.40 a 1.20 5 leo 3 1.00 ot nN 0.80 a = 0.60 o D 0.40 0.20 0,00 2.70 3.00 3.30 3.60 3.90 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.40 3 1.30 @ 1.20% N \ az 1.10 nd = Ts = 25C Oo 1.00 =z ell 0.90 0.80 2.70 3.00 3.30 3.60 3.90 SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 2 25 A 20 BJ z S15 oc 2 10 SJ 0.5 7 0. 00 10 20 30 40 50 SUPPLY VOLTAGE (V) NORMALIZED loc, | se NORMALIZED tas o x & 8 _ o Ss = DELTA t 2.00 | 21.50 NORMALIZED SUPPLY CURRENT ys. AMBIENT TEMPERATURE loc = 0 0UlUmt ooo 9 = 8$8 8886 Voc = 3.3 Vin = 3.3V Isp 0.00 55.00 40.00 135.00 AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME s. AMBIENT TEMPERATURE 8 Bs | pa ral Voc = 3.3V a =a au o 0.80 55,00 40,00 135.00 AMBIENT TEMPERATURE (C} TYPICAL ACCESS TIME CHANGE s. OUTPUT LOADING 2.50 1.00 f H Voc = 3.0V Ta = 25C 0.50 0,00 0.00 33.00 66.00 CAPACITANCE (pF) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE = 50.00 a = = 40,00 \ cS oO w Voc = 3.3V 2 30.00 Ts = 25C 2 2 20.00 > a ee B 10.00 2.00 2.25 250 275 3.00 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE z E 10.00 & 2 8,00 aa Ss 2 6.00 rd a 400 | x B 2.00 = oO 0.00 0.00 0.06 0.12 0.18 0.24 OUTPUT VOLTAGE (V) NORMALIZED Icc vs. CYCLE TIME 1.30 | 2 1.20 - Voo = 3.3V LO = Ts = 25C VA Hato YIN= O08 a a g Lf Z 1.00 Oo 1 = 0.90 a 0.80 29.00 47.00 65.00 83.00 CYCLE FREQUENCY (MHz}PRELIMINARY CY62256V CE | WE | OE | Inputs/Outputs Mode Power H | X | X | HighZ Deselect/Power-Down Standby (Isp) L | H |] L |] Data Out Read Active (Icc} LJ] L | X | Dataln Write Active (Icc} L | H] AH ] HighZ Deselect, Output Disabled | Active (Icc} Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 55 CY62256V 55SNC $22 28-Lead 450-Mil (300-Mil Body Width} SOIC Commercial CY62256VL55SNC $22 28-Lead 450-Mil (300-Mil Body Width) SOIC CY62256VLLS5SNC $22 28-Lead 450-Mil (300-Mil Body Width) SOIC CY62256V SSRZC RZ28 | 28-Lead Reverse Thin Small Outline Package CY62256VLS5RZC RZ28 | 28-Lead Reverse Thin Small Outline Package CY62256VLLS55RZC | RZ28 | 28-Lead Reverse Thin Small Outline Package CY62256V -55ZC Z28 28-Lead Thin Small Outline Package CY62256VL55ZC Z28 28-Lead Thin Small Outline Package CY62256VLLS55ZC 228 28-Lead Thin Small Outline Package 70 CY62256V -70SNC $22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial CY62256VL-70SNC $22 28-Lead 450-Mil 300-Mil Body Width) SOIC CY62256VLL-70SNC $22 28-Lead 450-Mil (300-Mil Body Width} SOIC CY62256V 70RZC RZ28 | 28-Lead Reverse Thin Small Outline Package CY62256VL70RZC RZ28 | 28-Lead Reverse Thin Small Outline Package CY62256VLL-7ORZC | RZ28 | 28-Lead Reverse Thin Small Outline Package CY62256V 70ZC 228 28-Lead Thin Small Outline Package CY62256VL70ZC Z28 28-Lead Thin Small Outline Package CY62256VLL70ZC Z28 28-Lead Thin Small Outline Package Shaded area contains advanced information. Document #: 38-00519PRELIMINARY CY62256V Package Diagrams 28-Lead 450-Mil (300-Mil Body Width) SOIC 822 RXX _ XXX HYUNDAI DIMENSIONS XXX) _ CXKX) ANAM DIMENSIONS 0720 (0.7103 PIN 1 ID 0.460 (0.463) 0.480 (477) 0291 0.295 DIMENSIONS IN INCHES MIN. 0.300 0.304 MAX, | LEAT COPLANARITY 0.004 MAX. SEATING PLANE O/7F8 (./ee3 0.050 TYP, 0.080 0.080) 0.002 0,004> 0.014 <0.0102 0.030 TYP3 28-Lead Reverse Thin Small Outline Package RZ28 NOTE: OPIENTATION LD May BE LOCATED EITHEP DIMEN IOM IM MM SIMCH> _ A> SHOWN IM OPTION 1 OF OPTION 2 MA, = TM. a el 136 536) ul The Sen! " Leo 047s lla "4nca Lng 6 yaar _ oe IL7 80: Men gs OOS oo USS 022) E& foBLL OPTION &, S 1 WEE NOTE! SS Ee | 75 SN) = m1 A = PIN oe & my ae a i er oll : Ole Oo OPTION 1 " TEE MOTE: Ler) or fms [ Testes Le 0400 L US] ofS i ai AL po so 1? 0.027% Go le:PRELIMINARY we Paes CY62256V wey ak Preps Package Diagrams (continued) 28-Lead Thin Small Outline Package Z28 MOTE: ORIENTATION LD MAY BE LOCATED EITHER A] THOWM IM OPTION 1 OP OPTION 2 DIMEN TOM IM MM INCH: MA Led ' 047) OPTION 1. | | LS Cae: Goes SEE WOTE * IL? teu * SS 022: = a ( J = Bre OPTION 2 .. ~ et iSEE NOTE. = =e FF = - PIr 1 Ee | OE ey? lio Se 12 wns t 9) Se. aan f ore We, / wo f wo 7 00271 Z Toile s LE ATING FLAME O20 wong. O05 800 Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied ina Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or otherrights. Cypress Semicon- ductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.