June 2007 Rev 15 1/52
1
M25P80
8 Mbit, low voltage, serial Flash memory
with 75 MHz SPI bus interface
Features
SPI bus compatible serial interface
75 MHz Clock rate (maximum)
2.7 V to 3.6 V single supply voltage
8 Mbit of Flash memory
Page Program (up to 25 6 by te s) in 0. 64 ms
(typical)
Sector Erase (512 Kbit) in 0.6 s (typical)
Bulk Erase (8 Mbit) in 8 s (typical)
Hardware Write protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
Deep Power-down mode 1 µA (typical)
Electronic signatures
JEDEC Standard two-byte signature
(2014h)
Unique ID code (UID) +16 bytes of CFI
data
RES instruction one-byte signature (13h)
for backward compatibility
More than 100 000 Program/Erase cycles per
sector
More than 20 years’ data r etention
Packages
ECOPACK® (RoHS compliant)
SO8W (MW)
208 mils width
VFQFPN8 (MP)
6 × 5 mm (MLP8)
SO8N (MN)
150 mils width
www.st.com
Contents M25P80
2/52
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . 12
4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13
4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M25P80 Contents
3/52
6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 27
6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 33
7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of tables M25P80
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List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Read Identification (RDID) data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. Data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. AC characteristics (75 MHz operation, Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. AC characteristics (25 MHz operation, Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. VFQFPN8 (MLP8) 8- lea d Very th in Fin e Pitch Qu ad Fla t Pack ag e No lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 19. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
M25P80 List of figures
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List of figures
Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. VFQFPN and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus Master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21
Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 23
Figure 11. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. Release from Deep Power-down (RES) instruction sequence. . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 22. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1. . . . . . . . . . . . . . . . . 44
Figure 24. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 26. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 27. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . 47
Figure 28. SO8N – 8 lead Plastic Small Outline, 15 0 mils body wid th, pac ka ge out line . . . . . . . . . . . 48
Description M25P80
6/52
1 Description
The M25P80 is an 8 Mbit (1 Mbit × 8) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-co mpa tible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The memory is organized as 16 sec to rs, each contain i n g 25 6 pa g es. Each page is 256
bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or
1,048,576 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, ST offers the M25P80 in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST tr ademark. ECOPACK specificat ions are available at: www.st.com.
Figure 1. Logic diagram
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data input Input
Q Serial Data output Output
S Chip Select Input
W Write Protect Input
HOLD Hold Input
VCC Supply voltage
VSS Ground
AI04964
S
VCC
M25P80
HOLD
VSS
W
Q
C
D
M25P80 Description
7/52
Figure 2. VFQFPN and SO8 connections
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
1
AI04965B
2
3
4
8
7
6
5DVSS C
HOLDQ
SV
CC
W
M25P80
Signal description M25P80
8/52
2 Signal description
2.1 Serial Data output (Q)
This output signal is used to tr ansf er data serially out of the de vice . Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Value s are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the de vice is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progr ess,
the device will be in the Standby mode (this is not the Deep Po wer-down mode). Driving
Chip Select (S) Low enables the device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S) is requir ed prior to the start of any
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any se rial communications with the de vice without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impe da nc e, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
2.6 Write Protect (W)
The main purpose of this input signa l is to free ze the size of the area of memory that is
protected against pro g ram or er ase instructions (as specified by the values in t he BP2, BP1
and BP0 bits of the Status Re gister).
M25P80 Signal description
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2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
SPI modes M25P80
10/52
3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two follo wing modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between t he t w o mod es, as shown in Figure 4, is the clock polarity when the
bus mast er is in Standby mod e and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus Master an d memory devi ces on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3 shows a n examp le of three de vices connected t o an MCU , on an SPI bus . Only one
device is selected at a time, so only one device drives the Serial Data Output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M25P80 is not selected if the Bus Master leaves the S line in the high impedance
state . As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for e xample, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Lo w ( thus ensuring that S a nd
C do not become High at the same time , and so, that the tSHCH requirement is met). The
typical v alue of R is 100 k, assuming that the tim e co nst an t R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impe dance.
AI12836b
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
RR R
VCC
VCC VCC VCC
VSS
VSS VSS VSS
R
M25P80 SPI modes
11/52
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
s.
Figure 4. SPI modes suppor ted
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
Operating features M25P80
12/52
4 Operating features
4.1 Page Programming
To prog ram one data b yte, two in structions are required: Write Enable (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration t PP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), pro vided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Progr am (PP) sequences with each containing only a few bytes (see Page Program (PP),
and Table 15: AC characteristics (75 MHz operation, Grade 6)).
4.2 Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been er ased to all 1s (FFh). This can be
achie v ed either a se ctor at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3 Polling During a Write, Program or Erase Cycle
A further improvement in the t ime to Write Status Regi ster (WRSR) , Prog r am (PP) or Era se
(SE or BE) can be achieved b y no t waiting for the worst case delay (tW, tPP
, tSE, or tBE). The
Write In Progress (WIP) bit is pro vided in the Status Register so t hat the application progr am
can monitor its v alue , polling it to establish when the previous Write cycle, Prog r am cycle or
Erase cycle is complete.
M25P80 Operating features
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4.4 Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is enabled, and in the Active Power mode.
When Chip Select (S) is High, the device is disabled, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep
Power-down mode (DP) instruction) is executed. The device consumption drops further to
ICC2. The device remains in this mode until another specific instruction (the Release from
Deep Power-down mode an d Read Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the d evice is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
4.5 Status Register
The Status Regist er conta ins a n umber o f stat us and cont rol bit s that can be rea d or set (a s
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see Section 6.4: Read Status Register (RDSR).
4.6 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P80 boasts the following data protection mechanisms:
Power-On Reset and an internal timer (tPUW) can provide protection against
inadvertent changes while the power supply is outside the operating specification.
Progr am, Er ase and Write Status Regist er instructions are chec ked that the y consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data m ust be preceded by a Write Enab le (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is re turned to its re set state
by the following events:
–Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase ( SE) instruction co mpletion
Bulk Erase (BE) instruction completion
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be config ur ed as
read-only. This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRW D) bit to be protected. This is the Hardware Protected
Mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers
e xtra softw are protection from inadv ertent Write , Program and Erase instructions, as all
instructions are ignored except one particular instruction (the Release from Deep
Power-down instruction).
Operating features M25P80
14/52
4.7 Hold condition
The Hold (HOLD) signal is used to pause any se rial communications with the de vice without
resetting the clocking seque nce. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is current ly in progress.
To enter the Hold condition, the device must be selected, with Chip Se lect (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 5).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 5).
During the Hold condition, the Serial Data Output (Q) is high impe da nc e, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driv en Lo w, f or the whole dur ation
of the Hold conditi on. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Table 2. Protected area sizes
Status Register
content Memory conten t
BP2
bit BP1
bit BP0
bit Protected area Unprotected area
0 0 0 none All sectors(1) (sixteen sectors: 0 to 15)
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
0.
0 0 1 Upper sixteenth (Sector 15) Lower fifteen-sixteenths (fifteen sectors:
0 to 14)
0 1 0 Upper eighth (two sectors: 14 and 15) Lower seven-eighths (fourteen sectors:
0 to 13)
0 1 1 Upper quarter (four sectors: 12 to 15) Lower three-quarters (twelve sectors: 0
to 11)
1 0 0 Upper half (eight sectors: 8 to 15) Lower half (eight sectors: 0 to 7)
1 0 1 All sectors (sixteen sectors: 0 to 15) none
1 1 0 All sectors (sixteen sectors: 0 to 15) none
1 1 1 All sectors (sixteen sectors: 0 to 15) none
M25P80 Operating features
15/52
Figure 5. Hold condition activation
AI02029D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
Memory organization M25P80
16/52
5 Memory organization
The memory is organized as:
1,048,576 bytes (8 bits each)
16 sectors (512 Kbits, 65536 bytes each)
4096 pages (256 bytes each).
Each page can be individually pro grammed (bits are prog rammed from 1 to 0). The de vice is
Sector or Bulk Er asable (bits are erased from 0 to 1) but not Page Erasable.
Table 3. Memory organization
Sector Address range
15 F0000h FFFFFh
14 E0000h EFFFFh
13 D0000h DFFFFh
12 C0000h CFFFFh
11 B0000h BFFFFh
10 A0000h AFFFFh
9 90000h 9FFFFh
8 80000h 8FFFFh
7 70000h 7FFFFh
6 60000h 6FFFFh
5 50000h 5FFFFh
4 40000h 4FFFFh
3 30000h 3FFFFh
2 20000h 2FFFFh
1 10000h 1FFFFh
0 00000h 0FFFFh
M25P80 Memory organization
17/52
Figure 6. Block diagram
AI04987
HOLD
S
W Control Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
Size of the
read-only
memory area
C
D
Q
Status
Register
00000h
FFFFFh
000FFh
Instructions M25P80
18/52
6 Instructions
All instruct ion s, addresses and dat a are shifted in and out of the device, most significan t bit
first.
Serial Data Input (D) is sampled on the first rising edge of Serial Cloc k (C) after Chip Select
(S) is drive n L ow. Then, t he on e- byte i nstruction code must be shifte d in to t he device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence st arts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-
down, an d Read Electronic Signature (RES) instruction, the shifted-in instruction sequence
is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the
data-out se quence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when
the number of clock pulses after Chip Select (S) being driven Low is an ex act multiple of
eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
M25P80 Instructions
19/52
6.1 Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entere d b y driving Chip Select (S) Lo w, sending the
instruction code, an d then driving Chip Select (S) High.
Table 4. Instruction set
Instruction Description One-byte
instruction code Address
bytes Dummy
bytes Data
bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disab le 0000 0100 04h 0 0 0
RDID(1)
1. The RDID instruction is available only for parts made with Technology T9HX (0.11µm), identified with
Process letter '4'. (Details of how to find the Technology Process in the part marking are given in AN1995,
see also Section 12: Part numbering.)
Read Identification 1001 1111 9Fh 0 0 1 to 20
RDSR Read Status Register 0000 0101 05h 0 0 1 to
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to
FAST_READ Read Data Bytes at Higher
Speed 0000 1011 0Bh 3 1 1 to
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RES
Release from Deep Power-
down, and Read Electronic
Signature 1010 1011 ABh 0 3 1 to
Release from Deep Power-
down 0 0 0
Instructions M25P80
20/52
Figure 7. Write Enable (WREN) instruction sequence
6.2 Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.
The Write Disab le (WRDI) instruction is entered b y driving Chip Select (S) Low, sending the
instruction code, an d then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 8. Write Disable (WRDI) instruction sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M25P80 Instructions
21/52
6.3 Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:
Manufacturer identification (one byte)
De vice identification (two bytes)
A Unique ID code (UID) followed by 16 bytes of CFI data
The manufacturer identification is assigned by JEDEC, and has the value 20h for
STMicroelectronics. The device identification is assigned by the device manufacturer, and
indicates the memory type in the first byte (20h), and the memory capacity of the de vice in
the second byte (14h). The UID is set to 10h and indicate s that 16 bytes, related to the CFI
content, are following.
Any Read Id entification (RDID) instruction while an Erase or Pr ogram cycle is in progress , is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 8-bit Unique ID code followed by 16 bytes of CFI content will be shifted out on
Serial Data Output (Q). Each bit is shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standb y Pow er mode, the de vice w aits to be selected, so that it can receiv e , decode and
execute instructions.
Figure 9. Read Identification (RDID) instruction sequence and da ta-out sequence
Table 5. Read Identification (RDID) d ata-out sequence
Manufacturer
identification
Device identification UID CFI content
Memory type Memory capacity
20h 20h 14h 10h 16 bytes
C
D
S
213456789101112 13 14 15
Instruction
0
AI06809c
Q
Manufacturer Identification
High Impedance
MSB
Device Identification
MSB
15 14 13 3 2 1 0
16 17 18 28 29 30 31
MSB
UID + CFI Data
Instructions M25P80
22/52
6.4 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. Th e
Status Register may be read at any time, even while a Program, Er ase or Write Status
Register cycle is in progress . When one of these cycles is in progress , it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as show n in Figure 10.
The status and control bits of the Status Register are as follows:
6.4.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the inte rnal Write Enable Latch is set, when set to 0 t he internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3 BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits ar e written with
the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes
protected against P age Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Er ase (BE) instruction is executed if , and only if, both Block Protect
(BP2, BP1, BP0) bits are 0.
6.4.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with th e Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Prot ect ( W ) is driv en Lo w). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) be come read-only bits an d
the Write Status Register (WRSR) instruction is no longer accepted for e xecution.
Table 6. Status Register f ormat
b7 b0
SRWD 0 0 BP2 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect bits
Write Enable Latc h bi t
Write In Progress bit
M25P80 Instructions
23/52
Figure 10. Read Status Register (RDSR) instruction sequence and data-out
sequence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
Instructions M25P80
24/52
6.5 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must pre viously
have been executed. After the Write Enable (WREN) instruction has been decoded an d
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driv en Hig h after the eighth bit of the d ata b yte has bee n latched in.
If not, the Write Status Register ( WRSR) instruction is not e x e cuted. As soon as Chip Sele ct
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enab le Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allo ws the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 2. The Write Status Register (WRSR) ins truction also allows
the user to set or reset th e Status Register Write Disable (SR WD) bit in accordance with the
Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware Protected Mode
(HPM) is entered.
Figure 11. Write Status Register (WRSR) instruction seque nce
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M25P80 Instructions
25/52
The protection features of the device are summarized in Table 7.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provid ed that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
If Write Protect (W) is driven High, it is possible to write to the St atus Register p rov ided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Lat ch (WEL) bi t has previously been set by a Write Enab le (WREN)
instruction. (Attempts to write to the Status Register are reject ed, and ar e not accepte d
for execution). As a consequence, all the data bytes in the memory area t hat are
software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protect ed again st da ta mo dification.
Regardless of the order of the two events , the Hardware Protected Mode (HPM) can be
entered:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Table 7. Protection modes
W
signal SRWD
bit Mode Write Pr otection of the
Status Register
Memory content
Protected area(1)
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2.
Unprotected area(1)
10
Software
Protected
(SPM)
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the SR WD ,
BP2, BP1 and BP0 bits
can be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the SR WD ,
BP2, BP1 and BP0 bits
cannot be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
Instructions M25P80
26/52
6.6 Read Data Bytes (READ)
The de vice is first selected by driving Chip Select (S) Low. Th e instruction code f or the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated b y driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase , Prog ra m or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence
1. Address bits A23 to A20 are Don’t Care.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
Data Out 2
M25P80 Instructions
27/52
6.7 Read Data Bytes at Higher Speed (FAST_READ)
The de vice is first selected by driving Chip Select (S) Low. Th e instruction code f or the Read
Data Bytes at Higher Speed (FAST_READ) instruction is f ollo w ed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents , at that address, is shift ed out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Byte s at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driv en High at an y time during data output. An y
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Da ta Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence
1. Address bits A23 to A20 are Don’t Care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
Instructions M25P80
28/52
6.8 Page Program (PP)
The Page Program (PP) instruction allows b ytes to be programmed in the mem ory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed . After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address b ytes and at least one data byte on Serial Data input ( D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entir e duration of the sequence .
The instruction sequence is shown in Figure 14.
If more tha n 256 bytes are se nt t o the device, previously latched data are discard ed an d the
last 256 dat a bytes ar e guaranteed to be progr ammed corr ectly within the same pag e. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Progr am (PP) sequences with each containing only a few bytes (see Table 15: A C
characteristics (75 MHz operation, Grade 6)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Prog ram cycle is in progre ss, th e Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.
M25P80 Instructions
29/52
Figure 14. Page Program (PP) instruction sequence
1. Address bits A23 to A20 are Don’t Care.
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
Instructions M25P80
30/52
6.9 Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Lo w, followed by the
instruction code, an d three address bytes on Serial Data In put (D). Any address inside the
Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select ( S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (S E) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle , and is 0 when it is completed. At some unspe cified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.
Figure 15. Sector Erase (SE) instruction sequence
1. Address bits A23 to A20 are Don’t Care.
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M25P80 Instructions
31/52
6.10 Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose dur ation is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progre ss (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Era se (BE) instruction is e x ecuted only if all Bloc k Protect (BP2, BP1, BP0) bits are
0. The Bulk Erase (BE) instruction is ignored if one, o r more, sectors are protected.
Figure 16. Bulk Erase (BE) instruction sequence
C
D
AI03752D
S
21 345670
Instruction
Instructions M25P80
32/52
6.11 Deep Power- down (DP)
Executing the Deep Po wer-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
softwar e protecti on mechanism, wh ile the device is not in activ e use , since in this m ode , the
device ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby mo de
(if there is no internal cycle currently in progress). But this mode is not the Deep Power-
down mode. The Deep Power-down mode can only be entered by executing the Deep
Power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified
in Table 14).
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. This releases the device from this mode. The Release from Deep Power-down
and Read Electronic Signatur e (RES) in struction also allows the Electronic Signature of the
de vice to be output on Serial Data Output (Q).
The Deep Power-down mode automatically stops at Power-down, and the device always
Powers-up in the Standby mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of tDP bef ore t he supply curr ent is redu ced
to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Deep Power-down (DP) instruction sequence
C
D
AI03753D
S
21 345670t
DP
Deep Power-down Mode
Stand-by Mode
Instruction
M25P80 Instructions
33/52
6.12 Release from Deep Power-down and Read Electronic
Signature (RES)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. Executing this instruction takes the device out of the Deep Power-down mode.
The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic
Signature, whose value for the M25P80 is 13h.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic
Signature that is read by the Read Identifier (RDID) inst ruction. The ol d-style Electronic
Signature is supported for reasons of backward compatibility, only, and should not be used
for new designs. New designs should, instead, mak e use of the JEDEC 16-bit Electronic
Signature, and the Read Iden tifier (RDID) instruction.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release
from Deep Power-do wn and Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep
Power-down mode has not been entered.
Any Relea se from Deep P o wer-do wn and Read Ele ctronic Signature (R ES) instruction while
an Erase , Progr am or Write Status Register cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge
of Serial Clock ( C). The n, the 8-bit Electronic Sig natu re , sto red in t he memory, is shifted out
on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock
(C).
The instruction sequence is shown in Figure 18.
The Release from Deep Power-down and Read Electronic Signature (RES) instruction is
terminated by driving Chip Select (S) High after the Electronic Signature has been read at
least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is
driven Low, cause the Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Stan dby
Power mode is immediate. If the device was previously in the Deep Pow er-down mode,
though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S)
must remain High for at least tRES2(max), as specified in Table 15. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Driving Chip Select (S) High after the 8-bit instruction b yte has be en receiv ed b y the device,
but before the whole of the 8-bit Electronic Signature has been transmitted for the first time
(as shown in Figure 19), still insures that the device is put into Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Stan dby
Power mode is immediate. If the device was previously in the Deep Pow er-down mode,
though, the transition to the Standby Power mode is delayed by tRES1, and Chip Select (S)
must remain High for at least tRES1(max), as specified in Table 15. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Instructions M25P80
34/52
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) i n struction
sequence and data -out sequence
1. The value of the 8-bit Electronic Signature, for the M25P80, is 13h.
Figure 19. Release from Deep Power-do wn (RES) instruction sequence
C
D
AI04047C
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
765432 0
1
High Impedance Electronic Signature Out
Instruction 3 Dummy Bytes
0
MSB
Stand-by Mode
Deep Power-down Mode
MSB
tRES2
C
D
AI04078B
S
21 345670tRES1
Stand-by Mode
Deep Power-down Mode
QHigh Impedance
Instruction
M25P80 Power-up and Power-down
35/52
7 Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
VCC(min) at Power-up, and then for a further delay of tVSL
VSS at Powe r-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during Powe r-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the POR thre shold value , VWI – all operations are disabled, and the device does not
respond to any instruction.
Moreover, the de vice ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the
correct opera tion of t he device is not guaranteed if, by this time, V CC is still belo w VCC(min).
No Write Status Register, Program or Erase instructions should be sent until the later of:
tPUW after VCC passed the VWI threshold
tVSL after VCC passed the VCC(min) level
These values are specified in Table 8.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
The device is in the Standby mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
Normal precautions must be tak en f or supply rail decoupling, to stabilize the VCC f eed. Each
device in a system should ha ve the VCC rail decoupled by a suitable capacitor close to the
package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold va lue, VWI, all operations are disabled and the device does not respond to
any inst ruction. (The designer nee ds to be a w are th at if a Pow er-do wn occu rs while a Write,
Program or Erase cycle is in progress, some data corruption can result.)
Power-up and Power-down M25P80
36/52
Figure 20. Power-up timing
Table 8. Power-up timing and VWI threshold
Symbol Parameter Min. Max. Unit
tVSL(1)
1. These parameters are characterized only.
VCC(min) to S low 10 µs
tPUW(1) Time delay to Write instruction 1 10 ms
VWI(1) Write Inhibit voltage 1 2 V
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
device
Chip selection Not Allowed
Program, Erase and Write commands are Rejected by the device
tVSL
tPUW
time
Read Access allowed Device fully
accessible
VCC(max)
M25P80 Initial delivery st at e
37/52
8 Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Reg ister bits are 0).
9 Maximum rating
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exp osur e to abso lute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant qu ality documents.
Table 9. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering see (1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
°C
VIO Input and output voltage (with respect to ground) –0.6 VCC + 0.6 V
VCC Supply voltage –0.6 4.0 V
VESD Electrostatic discharge voltage (Human Body model) (2)
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
–2000 2000 V
DC and AC parameters M25P80
38/52
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurem ent conditions when relying on the quoted parameters.
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 21. AC measurement I/O waveform
Table 10. Operating conditions
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.7 3.6 V
TAAmbient operating temperature grade 3 –40 125 °C
grade 6 –40 85 °C
Table 11. Data retention and endurance
Parameter Condition Min. Max. Unit
Erase/Program cycles Device grade 6 100 000 cycles per sector
Device grade 3 10 000
Data Retention at 55 °C 20 years
Table 12. AC measurement conditions
Symbol Parameter Min. Max. Unit
CLLoad capacitance 30 pF
Input rise and fall times 5 ns
Input pulse voltages 0.2VCC to 0.8VCC V
Input timing reference voltages 0.3VCC to 0.7VCC V
Output timing reference voltages VCC / 2 V
Table 13. Capacitance(1)
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 20 MHz.
Symbol Parameter Test condition Min. Max. Unit
COUT Output capacitance (Q) VOUT = 0 V 8 pF
CIN Input capacitance (other pins) VIN = 0 V 6 pF
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
0.5VCC
M25P80 DC and AC parameters
39/52
Table 14. DC characteristics
Symbol Parameter Test condition (in ad dition
to those in Table 10)Min. Max. Unit
ILI Input leakage current ± 2 µA
ILO Output leakage current ± 2 µA
ICC1 Standby current Grade 6 S = VCC, VIN = VSS or VCC 50 µA
Grade 3 100
ICC2 Deep Power-dow n current Grade 6 S = VCC, VIN = VSS or VCC 10 µA
Grade 3 100
ICC3 Operating current (READ)
C = 0.1VCC / 0.9.VCC at
75 MHz, Q = open 12 mA
C = 0.1VCC / 0.9.VCC at
20 MHz, Q = open 4mA
ICC4 Operating current (PP) S = VCC 15 mA
ICC5 Operating current (WRSR) S = VCC 15 mA
ICC6 Operating current (SE) S = VCC 15 mA
ICC7 Operating current (BE) S = VCC 15 mA
VIL Input low voltage –0.5 0.3VCC V
VIH Input high voltage 0.7VCC VCC + 0.4 V
VOL Output low voltage IOL = 1.6 mA 0.4 V
VOH Output high voltage IOH = –100 µA VCC – 0.2 V
DC and AC parameters M25P80
40/52
Table 15. AC characteristics (75 MHz operation, Grade 6)
75 MHz av ailable only for products made in T9HX technology, identified with Process digit “4”(1)
Test conditions specified in Table 10 and Table 12
Symbol Alt. Parameter Min. Typ.(2) Max. Unit
fCfC
Clock frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI,
RDID, RDSR, WRSR D.C. 75 MHz
fRClock frequency for READ instructions D.C. 33 MHz
tCH(3) tCLH Clock High time 11 ns
tCL(3) tCLL Clock Low time 11 ns
tCLCH(4) Clock Rise time(5) (peak to peak) 0.1 V/ns
tCHCL(4) Clock Fall time(4) (peak to peak) 0.1 V/ns
tSLCH tCSS S active setup time (relative to C) 5 ns
tCHSL S not active hold time (relative to C) 5 ns
tDVCH tDSU Data In setup time 2 ns
tCHDX tDH Data In hold time 5 ns
tCHSH S active hold time (relative to C) 5 ns
tSHCH S not active setup time (relative to C) 5 ns
tSHSL tCSH S deselect time 100 ns
tSHQZ(4) tDIS Output disable time 9 ns
tCLQV tVClock Low to Output Valid 9 ns
tCLQX tHO Output hold time 0 ns
tHLCH HOLD setup time (relative to C) 5 ns
tCHHH HOLD hold time (relative to C) 5 ns
tHHCH HOLD setup time (relative to C) 5 ns
tCHHL HOLD hold time (relative to C) 5 ns
tHHQX(4) tLZ HOLD to Output Low-Z 9 ns
tHLQZ(4) tHZ HOLD to Output High-Z 9 ns
tWHSL(6) Write Protect setup time 20 ns
tSHWL(6) Write Protect hold time 100 ns
tDP(4) S High to Deep Power-down mode 3 µs
tRES1(4) S High to Standb y mode without Electronic Signature
Read 3µs
tRES2(4) S High to Standby mode with Electronic Signature
Read 1.8 µs
tWWrite Status Register cycle time 1.3 15 ms
M25P80 DC and AC parameters
41/52
tPP (7)
Page Program cycle time (256 byte) 0.64
5ms
Page Program cycle time (n bytes, where n = 1 to 4) 0.01
Page Program cycle time (n bytes, where n = 5 to
256) int(n/8) × 0.02(8)
tSE Sector erase cycle time 0.6 3 s
tBE Bulk erase cycle time 8 20 s
1. Details of how to find the Technology Process in the marking are given in AN1995, see also Section 12: Part numbering.
2. Typical values given for TA = 25°C.
3. tCH + tCL must be greater than or equal to 1/ fC
4. Value guaranteed by characterization, not 100% tested in production.
5. Expressed as a slew-rate.
6. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
7. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one
sequence including all the bytes versus several sequences of only a few bytes. (1 n 256)
8. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Table 15. AC characteristics (75 MHz operation, Grade 6) (continued)
75 MHz av ailable only for products made in T9HX technology, identified with Process digit “4”(1)
Test conditions specified in Table 10 and Table 12
Symbol Alt. Parameter Min. Typ.(2) Max. Unit
DC and AC parameters M25P80
42/52
Table 16. AC characteristics (25 MHz operation, Grade 3)(1)
Test conditions specified in Table 10 and Table 12
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, RDSR, WRSR D.C. 25 MHz
fRClock frequency for READ instructions D.C. 20 MHz
tCH(2) tCLH Clock high time 18 ns
tCL(2) tCLL Clock low time 18 ns
tCLCH(3) Clock rise time(4) (peak to peak) 0.1 V/ns
tCHCL(3) Clock fall time(4) (peak to peak) 0.1 V/ns
tSLCH tCSS S active setup time (relative to C) 10 ns
tCHSL S not active hold time (relative to C) 10 ns
tDVCH tDSU Data in setup time 5 ns
tCHDX tDH Data in hold time 5 ns
tCHSH S active hold time (relative to C) 10 ns
tSHCH S not active setup time (relative to C) 10 ns
tSHSL tCSH S deselec t t im e 100 ns
tSHQZ(3) tDIS Output di sable time 15 ns
tCLQV tVClock low to output valid 15 ns
tCLQX tHO Output hold time 0 ns
tHLCH HOLD setup time (relative to C) 10 ns
tCHHH HOLD hold time (relative to C) 10 ns
tHHCH HOLD setup time (relative to C) 10 ns
tCHHL HOLD hold time (relative to C) 10 ns
tHHQX(3) tLZ HOLD to Output low-Z 15 n s
tHLQZ(3) tHZ HOLD to Output high-Z 20 ns
tWHSL(5) Write Protect setup time 20 ns
tSHWL(5) Write Protect hold time 100 ns
tDP(3) S High to Deep Power-down mode 3 µs
tRES1(3) S High to Standby mode without Electronic
Signature Read s
tRES2(3) S High to Standby mode with Electronic
Signature Read 1.8 µs
tW(6) Write Status Register cycle time 1.5 15 ms
tPP(6) Page Program cycle time (256 bytes) 0.8 5ms
Page Program cycle time (n bytes) int(n/8) × 0.025(7)
M25P80 DC and AC parameters
43/52
Figure 22. Serial input timing
tSE(6) Sector Erase cycle time 0.8 3 s
tBE(6) Bulk Erase cycle time 10 20 s
1. Preliminary data.
2. tCH + tCL must be greater than or equal to 1/ fC
3. Value guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
6. Typical values given for TA = 85 °C.
7. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Table 16. AC characteristics (25 MHz operation, Grade 3)(1) (continue d)
Test conditions specified in Table 10 and Table 12
Symbol Alt. Parameter Min. Typ. Max. Unit
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
DC and AC parameters M25P80
44/52
Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1
Figure 24. Hold timing
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI07439
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
M25P80 DC and AC parameters
45/52
Figure 25. Output t iming
C
Q
AI01449e
S
LSB OUT
D
ADDR.
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
Package mechanical M25P80
46/52
11 Package mechanical
Figure 26. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package outline
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 17. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.85 0.80 1.00 0.0335 0.0315 0.0394
A1 0.00 0.05 0.0000 0.0020
A2 0.65 0.0256
A3 0.20 0.0079
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 6.00 0.2362
D1 5.75 0.2264
D2 3.40 3.20 3.60 0.1339 0.1260 0.1417
E 5.00 0.1969
E1 4.75 0.1870
E2 4.00 3.80 4.30 0.1575 0.1496 0.1693
e1.27– 0.0500
R1 0.10 0.00 0.0039 0.0000
L 0.60 0.50 0.75 0.0236 0.0197 0.0295
Θ12° 12°
aaa 0.15 0.0059
bbb 0.10 0.0039
ddd 0.05 0.0020
D
E
70-ME
A2
AA3
A1
E1
D1
eE2
D2
L
b
θ
R1
ddd
bbb
C
CAB
aaa CA
A
B
aaa CB
M
0.10 CA
0.10 CB
2x
M25P80 Package mechanical
47/52
Figure 27. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package
outline
1. Drawing is not to scale.
2. The ‘1’ that appears in the top view of the package shows the position of pin 1.
Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width,
package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A2.500.098
A1 0.00 0.25 0.000 0.010
A2 1.51 2.00 0.059 0.079
b 0.40 0.35 0.51 0.016 0.014 0.020
c 0.20 0.10 0.35 0.008 0.004 0.014
CP 0.10 0.004
D6.050.238
E 5.02 6.22 0.198 0.245
E1 7.62 8.89 0.300 0.350
e1.27– 0.050
k 10° 10°
L 0.50 0.80 0.020 0.031
N8 8
6L_ME
E
N
CP
be
A2
D
c
LA1 k
E1
A
1
Package mechanical M25P80
48/52
Figure 28. SO8N – 8 lead Plastic Small Outline, 150 mils bod y width, pa c kage outline
1. Package is not to scale.
Table 19. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e1.27– 0.050
h 0.25 0.50 0.010 0.020
k0°8°0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
be
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
M25P80 Part numbering
49/52
12 Part numbering
Note: F or a list of a vailable options (spee d, pac kage , etc. ), f o r further information on an y aspect of
this device or when ordering parts operating at 75 MHz (0.11 µm, process digit “4”), please
contact your nearest ST Sales Office.
The category of second Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standar d JESD97. The maximu m ratings relat ed to
soldering conditions are also marked on the inner box label.
Table 20. Order ing information scheme
Example: M25P80 V MW 6 T P
Device type
M25P = Serial Flas h memory for Code Storage
Device function
80 = 8 Mbit (1 Mbit × 8)
Operatin g voltage
V = VCC = 2.7 V to 3.6 V
Package
MW = SO8W (208 mils width)
MN = SO8N (150 mils width)(1)
1. Package only available for products in the T9HX process.
MP = VDFPN8 (MLP8)
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3(2) = Automotive temperature range, –40 to 125 °C.
Device tested with High Reliability Certified Flow.
2. Grade 3 is available only in devices delivered in SO8N packages.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating technology
P or G = ECOPA CK® (RoHs compliant)
Revision history M25P80
50/52
13 Revision history
Table 21. Document revision history
Date Revision Changes
24-Apr-2002 1.0
Document released as a Product Preview data sheet
Clarification of descriptions of entering Standby Power mode from Deep
P ower-do wn mode, and of terminating an instruction sequence or data-out
sequence.
27-Sep-2002 1.1 VFQFPN8 package (MLP8) added. Order code (MW) corrected on page 1
for SO8 package. Document promoted to Preliminary Data.
13-Dec-2002 1.2
Typical Page Program time improved. Write Protect setup and ho ld times
specified, for applications that sw itch Write Protect to ex it the Hardware
Protec ti on mod e imme d iately before a WRSR, and to enter the Har dware
Protection mode again immedi ately after.
24-Oct-2003 2.0
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added.
40MHz AC Characteristics table included as well as 25MHz. Change of
naming for VDFPN8 pac kage. Document promoted to full datasheet
24-Nov-2003 2.1 Improvement to description of reading the 8-bit electroni c signature.
21-Apr-2004 3.0 SO16 package added. SO8W package removed. Soldering temperature
inf ormation clarified for RoHS compliant devices. Device Grade clarified
07-May-2004 4.0 Automotive range added
18-May-2004 5.0 SO8W package re-instated, but under limited availability
05-Aug-2004 6.0 Data-retention measurement temperature corrected. Details of how to find
the date of markin g added.
01-Aug-2005 7.0 Updated Page Program (PP) instructions in Page Programming, Page
Program (PP), Instruction times and Instruction Times (Device Grade 3).
20-Oct-2005 8.0
SO16 package removed. All packages are ECOPACK®. MLP8 package
renamed as VFQFPN8. Plating technology clarified in Table 20: Ordering
inf ormation scheme. VFQFPN silhouette modified (see silhouette on page
1). tSHQZ timing modified in Figure 25: Output timing.
13-Apr-2006 9
Device g r ade 3 specifications removed from datasheet. Data retention
conditions changed in Table 11: Data retention and endurance.
Figure 3: Bus Master and memory devices on the SPI bus modified and
Note 2 added.
Note 2 added below Figure 26 and Note 2 added below Figure 27.
Note on SO8 package removed below Table 20: Ordering information
scheme.
20-Jul-2006 10 SO8N package added (see Figure 28 and Table 19).
M25P80 Revision history
51/52
22-Sep-2006 11
Endurance and data retention information added to Features.
50 MHz frequency added, Read Identification (RDID) instruction added,
Instruction times table removed, data appended to Table 15: AC
characteristics (40 MHz operation, Grade 6) and Table 16. AC
characteristics (25MHz operation). Typical tW, tSE and tPP values modified
in Table 15: AC characteristics (40 MHz operation, Grade 6) and Note 2
added.
VFQFPN8 package specifications updated (see Table 17). Small text
changes. Process Technology information added to part numbering (see
Table 20).
12-Oct-2006 12 VIO max changed in Table 9: Absolute maximum ratings.
Data in Table 15: AC characteristics (75 MHz operation, Grade 6) are
preliminary data. tBE typ and fR modified in Table 15.
15-Dec-2006 13
Small text changes. Hardware Write protection added to Features.
VCC supply voltage and VSS ground added. Figure 3: Bus Master and
memory devices on the SPI bus updated, Note 2 removed and replaced
by an explanator y paragraph.
Behavior of WIP bit specified at Power-up in Section 7: Power-up and
Power-down.
TLEAD added to Table 9: Absolute maximum ratings.
SO8W and VFQFPN8 pac kage specifications updated (see Section 11:
Package mechanical). Note 1 added to Table 20: Ordering informati on
scheme.
09-Jan-2007 14 Temperature grade 3 added (available in products delivered in the SO8N
pac ka ge on l y ).
15-Jun-2007 15
Read Identification instruction modified in Section 6.3: Read Identification
(RDID).
Inserted UID and CFI content columns in Table 5: Read Identification
(RDID) data-out sequence.
Modified Data bytes for RDID instruction in Table 4: Instruction set.
Modified Q signal in Figure 9: Read Identification (RDID) instructio n
sequence and data-out sequence.
Modified Test condition and maximum value for ICC3 in Table 14: DC
characteristics.
Table 15: AC characteristics (40 MHz operation, Grade 6) removed.
Modified the maximum v a lue for fC in Table 15: AC characteristics
(75 MHz operation, Grade 6).
Table 21. Document revision history
Date Revision Changes
M25P80
52/52
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