CDC 3207G-C
Automotive Controller
Specification
Edition April 15, 2003
6251-589-3AI
ADVANCE INFORMATION
MICRONAS
CDC 3207G-C ADVANCE INFORMATION
2April 15, 2003; 6251-589-3AI Micronas
Contents
Page Section Title
3 1. Introduction
3 1.1. Features
5 1.2. Abbreviations
6 1.3. Block Diagram
7 2. Packages and Pins
7 2.1. Package Outline Dimensions
8 2.2. Pin Assignment
8 2.3. Pin Function Description (differing from CDC32xxG-C User Manual)
9 2.4. External Components
11 3. Electrical Characteristics
11 3.1. Absolute Maximum Ratings
12 3.2. Recommended Operating Conditions
13 3.3. Characteristics
15 3.4. Recommended Quartz Crystal Characteristics
17 4. CPU and Clock System
19 5. Memory and Special Function ROM (SFR) System
21 6. Core Logic
21 6.1. Control Word (CW)
23 7. Hardware Options
23 7.1. Functional Description
25 8. Differences
26 9. Data Sheet History
ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 3
1. Introduction
Release Note: Revision bars indicate significant
changes to the previous edition.
The device is a microcontroller for use in automotive applica-
tions. The on-chip CPU is an ARM processor ARM7TDMI
with 32-bit data and address bus, which supports Thumb
format instructions.
The chip contains timer/counters, interrupt controller, multi
channel AD converter, stepper motor and LCD driver, CAN
interfaces and PWM outputs and a crystal clock multiplying
PLL.
This document provides MCM Flash hardware specific infor-
mation. General information on operating the IC can be
found in the document “CDC32xxG-C Hardware Manual and
CDC3205G-C Data Sheet (3AI)”.
1.1. Features
Table 1–1: CDC32xxG-C Family Feature List
This Device:
Item CDC3205G-C
EMU CDC3207G-C
MCM Flash CDC3272G-C
Mask ROM CDC3272G-C
Mask ROM
Core
CPU 32-bit ARM7TDMI
CPU-Active Operation Modes DEEP SLOW, SLOW, FAST and PLL
Power Saving Modes (CPU Inactive) IDLE, WAKE and STANDBY
CPU clock multiplication PLL delivering up to 50MHz
EMI Reduction Mode selectable in PLL mode
Oscillators 4 to 5MHz Quartz and 20 to 50kHz Internal RC
RAM, zero wait state, 32 bit wide 32kByte 16kByte 6kByte
ROM ROMless, ext.
up to
4M x 32/
8M x 16,
int. 8-KByte
Boot ROM
512-kByte Flash
(256K x 16) top
boot conf.,
int. 8-KByte
Boot ROM
384kByte
(96K x 32/
192K x 16)
128kByte
(32K x 32/
64K x 16)
Digital Watchdog ✔
Central Clock Divider ✔
Interrupt Controller expanding IRQ 40 inputs, 16 priority levels 26 inputs, 16
priority levels
Port Interrupts including Slope Selection 6 inputs 5 inputs
Port Wake-Up Inputs including Slope / Level
Selection 10 inputs
Patch Module 10 ROM locations
Boot System allows in-system downloading of
external code to Flash memory via
JTAG
-
Device Lock Module Inhibits Access to internal Firm-
ware, Lock settable by Customer -
CDC 3207G-C ADVANCE INFORMATION
4April 15, 2003; 6251-589-3AI Micronas
Analog
Reset/Alarm Combined Input for Regulator Input Supervision
Clock and Supply Supervision ✔
10-bit ADC, charge balance type 16 channels (each selectable as digital input)
ADC Reference VREF Pin, P1.0 Pin, P1.1 Pin or VREFINT Internal Bandgap selectable
Comparators P06COMP with 1/2 AVDD reference,
WAITCOMP with Internal Bandgap reference
LCD Internal processing of all analog voltages for the LCD driver
Communication
DMA 3 DMA Channels, one each for serving the Graphics
Bus interface, SPI0 and SPI1 -
UART 2: UART0 and UART1 UART0
Synchronous Serial Peripheral Interfaces 2: SPI0 and SPI1
Full CAN modules V2.0B
with 512-byte object RAM each
(LCAN000E)
4: CAN0, CAN1, CAN2 and CAN3 2: CAN0 and
CAN1 1: CAN0
DIGITbus 1 master module -
I2C 2 master modules: I2C0 and I2C1 I2C0
Input & Output
Universal Ports selectable as 4:1 mux LCD
Segment/Backplane lines or Digital I/O Ports up to 52 I/O or 48 LCD segment lines (=192 segments),
individually configurable as I/O or LCD up to 50 I/O or
46LCD seg-
ment lines
(=184 seg-
ments)
Universal Port Slew Rate SW selectable
Stepper Motor Control Modules with High-
Current Ports 7 Modules,
32 dI/dt controlled ports 4 Modules
23 dI/dt con-
trolled ports
PWM Modules, each configurable as two 8-
bit PWMs or one 16-bit PWM 6 Modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7,
PWM8/9 and PWM10/11 5 Modules:
PWM0/1,
PWM2/3,
PWM4/5,
PWM6/7,
PWM8/9
Phase-Frequency Modulator 2: PFM0 and PFM1 -
Audio Module with auto-decay ✔
SW selectable Clock outputs 2
Polling / Flash Timer Output 1 High-Current Port output operable in Power Saving Modes
Table 1–1: CDC32xxG-C Family Feature List, continued
This Device:
Item CDC3205G-C
EMU CDC3207G-C
MCM Flash CDC3272G-C
Mask ROM CDC3272G-C
Mask ROM
ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 5
ARM and Thumb are the registered trademarks of ARM Limited.
ARM7TDMI is the trademark of ARM Limited.
1.2. Abbreviations
ADC Analog-to-Digital Converter
AM Audio Module
CAN Controller Area Network Module
CAPCOM Capture/Compare Module
CCC Capture/Compare Counter
CPU Central Processing Unit
DMA Direct Memory Access Module
ERM EMI Reduction Mode
ETM Embedded Trace Module
I2C I2C Interface Module
LCD Liquid Crystal Display Module
P06COMP P0.6 Alarm Comparator
PWM Pulse Width Modulator Module
SM Stepper Motor Control Module
SPI Serial Synchronous Peripheral Interface
TTimer
UART Universal Asynchronous Receiver Transmitter
WAITCOMP Wait Comparator
Timers & Counters
16-bit free running counters with Capture/
Compare modules CCC0 with 4 CAPCOM
CCC1 with 2 CAPCOM CCC0 with 4
CAPCOM
16-bit timers 1: T0
8-bit timers 4: T1, T2, T3 and T4
Real Time Clock, Delivering Hours, Minutes
and Seconds
✔
Miscellaneous
Scalable layout in CAN, RAM and ROM - ✔
Various randomly selectable HW options Set by copy from user program storage during system start-up
JTAG test interface ✔allows Flash
programming
✔
On Chip Debug Aids Embedded
Trace Module,
JTAG
JTAG
Core Bond-Out ✔-
Supply Voltage 3.5 to 5.5V (limited I/O performance below 4.5V)
Case Temperature Range -40 to +105C
Package
Type Ceramic
257PGA Plastic 128QFP
0.5mm pitch
Bonded Pins 256 128 126 111
Table 1–1: CDC32xxG-C Family Feature List, continued
This Device:
Item CDC3205G-C
EMU CDC3207G-C
MCM Flash CDC3272G-C
Mask ROM CDC3272G-C
Mask ROM
CDC 3207G-C ADVANCE INFORMATION
6April 15, 2003; 6251-589-3AI Micronas
1.3. Block Diagram
Fig. 1–1: CDC3207G-C block diagram
4
4
8
8
7
8
4
4
3
4
4
4
XTAL1
XTAL2
TEST
RESETQ
VREF
AVDD
AVSS
HVDD3
HVSS3
HVDD0
HVSS0
5
Bridge
Bridge
8Bit Timer 4
8Bit Timer 3
8Bit Timer 2
8Bit Timer 1
16Bit Timer 0
8Bit PWM 0
8/16B PWM 1
8
4
HVDD1
HVSS1
HVDD2
HVSS2
WAIT
WAITH
TEST2
32 16
8
UVDD1
UVSS1
4
8
6
8Bit PWM 2
8/16B PWM 3
8Bit PWM 4
8/16B PWM 5
8Bit PWM 6
8/16B PWM 7
8Bit PWM 8
8/16B PWM 9
8Bit PWM 10
8/16B PWM 11
3.3V Reg. 2.5V Reg.
FVDD UVDD VDD
FVSS UVSS VSS
BVDD
2.5V Reg.
HPort0HPort1HPort2HPort3HPort4HPort5HPort6HPort7
4
4
PPort0PPort1PPort2
2
Memory
Controller
VREFINT
PLL/ERM
RC Oscillator
RTC
Test
Reset/Alarm
Watchdog
Clock
Power
Saving
JTAG Test
and Debug
Interface
CAPCOM 0
CAPCOM 1
CAPCOM 2
CAPCOM 3
CAPCOM 4
CAPCOM 5
16Bit CCC 0
16Bit CCC 1
UPort8 UPort0UPort1UPort2UPort3UPort4UPort5UPort6UPort7
UART 0
UART 1
SPI 0
SPI 1
CAN 0
CAN 1
CAN 2
DIGITbus
I2C 0
I2C 1
LCD Control
Audio Module
Clock Out 0
Clock Out 1
Phase-Freq.-
Modulator 0
Phase-Freq.-
Modulator 1
Wait Comp.
P06 Comp.
Bandgap Ref.
10Bit ADC
DMA Logic
ARM7TDMI
CPU
40 Input
Interrupt
Controller
32K SRAM
Stepper Motor
Control
Special
Function
Device Lock
Module
Patch
CAN 3
ROM
4k x 16
Flash
256k x 16
ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 7
2. Packages and Pins
2.1. Package Outline Dimensions
Fig. 2–1: PQFP128 Plastic Quad Flat Pack 128-Pin (Weight approx. 1.61g. Dimensions in mm)
23.2 0.15±
17.2 0.15±
65102
381
103
128
64
39
0.5
0.5
SPGS705000-3(P128)/1E
0.1
3±0.2
0.17 0.04±
0.22 0.05±
1.3 0.05±
2.7 0.1±
25 x 0.5 = 12.5 0.1±
20 0.1±
14 0.1±
37 x 0.5 = 18.5 0.1±
CDC 3207G-C ADVANCE INFORMATION
8April 15, 2003; 6251-589-3AI Micronas
2.2. Pin Assignment
Fig. 2–2: Pin Assignment for PQFP128 Package
Note 1 denotes pins that are not available in future 88 pin versions.
Note 2 denotes pins that are not available in future 104 pin versions.
2.3. Pin Function Description (differing from CDC32xxG-C User Manual)
TEST2
For normal operation with internal code connect TEST2 to
System Ground (no internal pull-down).
Pin Functions Not
e
Pin
No.
LCD
Mode
Port
Special Out
Port
Special In
Basic
Function
SEG3.1 CC1-OUT CC1-IN / TMS U3.1 116
SEG3.0 CC2-OUT CC2-IN / TDI U3.0 117
TEST2 118
UVDD 119
UVSS 120
SEG2.6 DIGIT-OUT DIGIT-IN U2.6 121
SEG2.5 CC1-OUT UART0-RX U2.5 122
SEG2.4 UART0-TX DIGIT-IN/CC1-IN U2.4 123
SEG2.3 CC2-OUT UART1-RX U2.3 124
SEG2.2 UART1-TX CC2-IN U2.2 125
SEG7.7 CO0 U7.7/GD7 1,2 126
SEG7.6 CO1 U7.6/GD6 1,2 127
SEG7.5 LCK/PFM1 U7.5/GD5 1,2 128
SEG7.4 CC5-OUT CC5-IN U7.4/GD4 1,2 1
FVDD 1,2 2
FVSS 1,2 3
SEG5.3 CC4-OUT CC4-IN U5.3/GD3 1 4
SEG5.2 SDA1 SDA1 U5.2/GD2 1 5
SEG5.1 SCL1 SCL1 U5.1/GD1 1 6
SEG5.0 PFM0 U5.0/GD0 1 7
SEG2.1 SDA0 WP6/SDA0/CAN0-RX U2.1 8
SEG2.0 SCL0/CAN0-TX SCL0 U2.0 9
SEG1.7 PFM0 WP0/PINT0 U1.7 10
SEG1.6 INTRES/CO0 PINT1 U1.6 11
SEG1.5 CO1/CO0Q PINT2 U1.5 12
TEST 13
RESETQ/ALARMQ 14
XTAL2 15
XTAL1 16
VSS 17
VDD 18
SEG1.4 ITSTOUT/AM-OUT U1.4 19
SEG1.3 MTO/AM-PWM WP3 U1.3 20
SEG1.2 INTRES/T0-OUT MTI/ITSTIN U1.2 21
SEG1.1 T1-OUT U1.1 22
SEG1.0 T2-OUT U1.0 23
SEG0.7 T3-OUT WP4 U0.7 24
SEG0.6 CC3-OUT/T4-OUT CC3-IN U0.6 25
SEG0.5 CC3-OUT PINT4 U0.5 26
SEG0.4 CO1 PINT5 U0.4 27
SEG0.3 PWM0 U0.3 28
SEG0.2 PWM1 U0.2 29
SEG0.1 PWM2 U0.1 30
SEG0.0 PWM3 U0.0 31
SME1+/PWM4 SME-COMP3 H7.3 1 32
SME1-/PWM6 SME-COMP2 H7.2 1 33
SME2+/PWM8 SME-COMP1 H7.1 1 34
SME2-/PWM9 SME-COMP0 H7.0 1 35
HVDD2 1,2 36
HVSS2 1,2 37
PWM8 H6.3 1,2 38
PWM9 H6.2 1,2 39
PWM10 H6.1 1,2 40
PWM11 H6.0 1,2 41
SMD1+ SMD-COMP3 H5.3 42
SMD1- SMD-COMP2 H5.2 43
HVDD0 44
HVSS0 45
SMD2+ SMD-COMP1 H5.1 46
SMD2- SMD-COMP0 H5.0 47
SMA1+ SMA-COMP3 H4.3 48
SMA1- SMA-COMP2 H4.2 49
SMA2+ SMA-COMP1 H4.1 50
SMA2- SMA-COMP0 H4.0 51
Pin
No.
Not
e
Pin Functions
Basic
Function
Port
Special In
Port
Special Out
LCD
Mode
115 U3.2 CC0-IN / TCK CC0-OUT SEG3.2
114 U3.3 CO0/TDO SEG3.3
113 U3.4 SPI0-CLK-IN SPI0-CLK-OUT SEG3.4
112 U3.5 SPI0-D-IN TO3 SEG3.5
111 U3.6 SPI0-D-OUT SEG3.6
110 U3.7 SPI1-CLK-IN SPI1-CLK-OUT SEG3.7
109 U4.0 SPI1-D-IN CC0-OUT BP0
108 U4.1 CC0-IN SPI1-D-OUT BP1
107 U4.2 CAN0-TX BP2
106 U4.3 CAN0-RX/WP5 TO2 BP3
105 1,2 U8.0 CC4-OUT SEG8.0
104 1,2 U8.1 CC3-OUT SEG8.1
103 1,2 U8.2 LCD-CLK-IN CAN3-TX SEG8.2
102 1,2 U8.3 CAN3-RX/WP9 LCD-CLK-OUT SEG8.3
101 1,2 U8.4 LCD-SYNC-IN CAN2-TX SEG8.4
100 1,2 U8.5 CAN2-RX/PINT3/WP8 LCD-SYNC-OUT SEG8.5
99 1 U6.0 CAN1-TX SEG6.0
98 1 U6.1 CAN1-RX/WP7 GOEQ SEG6.1
97 1 U6.2 GWEQ SEG6.2
96 1 P2.0
95 P2.1
94 P0.0 CC4-IN
93 P0.1
92 P0.2
91 P0.3
90 P0.4
89 P0.5
88 P0.6 P0.6 Comp.
87 P0.7
86 WAITH
85 WAIT
84 BVDD
83 AVSS
82 AVDD
81 VREFINT
80 VREF
79 P1.0 VREF0/WP1
78 P1.1 VREF1/WP2
77 P1.2 PINT0
76 P1.3 PINT1
75 P1.4 PINT2
74 P1.5 PINT3
73 P1.6 PINT4
72 P1.7 PINT5
71 1 H0.0 SMG-COMP0 SMG2-/PWM7
70 1 H0.1 SMG-COMP1 SMG2+/PWM5
69 1 H0.2 SMG-COMP2 SMG1-/PWM3/POL
68 1 H0.3 SMG-COMP3 SMG1+/PWM1
67 1,2 HVSS3
66 1,2 HVDD3
65 1,2 H1.0 SMF-COMP0 SMF2-
64 1,2 H1.1 SMF-COMP1 SMF2+
63 1,2 H1.2 SMF-COMP2 SMF1-
62 1,2 H1.3 SMF-COMP3 SMF1+
61 H2.0 SMC-COMP0 SMC2-
60 H2.1 SMC-COMP1 SMC2+
59 HVSS1
58 HVDD1
57 H2.2 SMC-COMP2 SMC1-
56 H2.3 SMC-COMP3 SMC1+
55 H3.0 SMB-COMP0 SMB2-
54 H3.1 SMB-COMP1 SMB2+
53 H3.2 SMB-COMP2 SMB1-
52 H3.3 SMB-COMP3 SMB1+
1
38
102
65
39 64
103128 116 115
5251
NC = not connected,
leave vacant
(...) = future usage
ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 9
2.4. External Components
Fig. 2–3: CDC3207G-C: Recommended external supply and quartz connection.
To provide effective decoupling and to improve EMC behav-
iour, the small decoupling capacitors must be located as
close to the supply pins as possible. The self-inductance of
these capacitors and the parasitic inductance and capaci-
tance of the interconnecting traces determine the self-reso-
nant frequency of the decoupling network. Too low a fre-
quency will reduce decoupling effectiveness, will increase
RF emissions and may adversely affect device operation.
XTAL1 and XTAL2 quartz connections are especially sensi-
tive to capacitive coupling from other pc board signals. It is
strongly recommended to place quartz and oscillation capac-
itors as close to the pins as possible and to shield the XTAL1
and XTAL2 traces from other signals by embedding them in a
VSS trace.
The RESETQ pin adjacent to XTAL2 should be supplied with
a 47nF capacitor, to prevent fast RESETQ transients from
being coupled into XTAL2, to prevent XTAL2 from coupling
into RESETQ, and to guarantee a time constant of ≥200µs
sufficient for proper Wake Reset functionality.
HVDD0 to 3
System
Ground
+5V
Supply
4 x 100n to 150n
HVSS0 to 3
5V
2.5V
5V
2.5V
VREFINT
AVSS
AVDD
BVDD
Analog
Ground
Analog
Supply
150n
Ceramic, X7R
10n, Ceramic
VDD
VSS
XTAL1
XTAL2
UVSS
UVDD
System
Ground
+5V
Supply
220n
Ceramic
10µ
18p
18p
100n to 150n
5V
3.3V
FVDD
FVSS
470n
Ceramic
3.3µ
Tantal
100n to 150n
ESR < 14ΩX7R
X7R
Tantal
Low ESR
RESETQ
Resetq
47n
4.7k
+5V Supply
Flash
CDC 3207G-C ADVANCE INFORMATION
10 April 15, 2003; 6251-589-3AI Micronas
ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 11
3. Electrical Characteristics
3.1. Absolute Maximum Ratings
1) This condition represents the worst case load with regard to the intended application
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended
Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
Table 3–1: UVSS=HVSSn=FVSS=AVSS=0V
Symbol Parameter Pin Name Min. Max. Unit
VSUP Main Supply Voltage
Analog Supply Voltage
SM Supply Voltage
UVDD
AVDD
HVDD0 .. HVDD3
-0.3 6.0 V
VREG Flash Supply Voltage FVDD -0.3 4.0 V
Core Supply Voltage
PLL Supply Voltage VDD
BVDD -0.3 3.0 V
ISUP Core Supply Current
Main Supply Current VDD, VSS,
UVDD, UVSS -100 100 mA
Analog Supply Current AVDD, AVSS -20 20 mA
SM Supply Current
@TCASE=105C, Duty Factor=0.71 1)HVDD0 .. HVDD3
HVSS0 .. HVSS3 -250 250 mA
Flash Supply Current FVDD, FVSS -50 50 mA
PLL Supply Current BVDD -20 20 mA
Vin Input Voltage U-Ports,
XTAL,RESETQ,
TEST, TEST2
UVSS-0.5 UVDD+0.7 V
P-Ports
VREF UVSS-0.5 AVDD+0.7 V
H-Ports HVSS-0.5 HVDD+0.7 V
Iin Input Current all Inputs 0 2 mA
IoOutput Current U-Ports,
RESETQ, WAITH -5 5 mA
H-Ports -60 60 mA
toshsl Duration of Short Circuit to UVSS or
UVDD, Port SLOW Mode enabled U-Ports, except in
DP Mode indefinite s
TjJunction Temperature under Bias -45 115 °C
TsStorage Temperature -45 125 °C
Pmax Maximum Power Dissipation 0.8 W
CDC 3207G-C ADVANCE INFORMATION
12 April 15, 2003; 6251-589-3AI Micronas
3.2. Recommended Operating Conditions
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.
Keep UVDD=AVDD during all power-up and power-down sequences.
Failure to comply with the above recommendations will result in unpredictable behavior of the device and may result in device
destruction.
Table 3–2: UVSS=HVSSn=FVSS=AVSS=0V
Symbol Parameter Pin Name Min. Typ Max. Unit
VSUP Main Supply Voltage
Analog Supply Voltage UVDD=AVDD 3.5 5 5.5 V
HVSUP SM Supply Voltage HVDDn 4.75 5 5.25 V
dVDD Ripple, Peak to Peak UVDD
AVDD
BVDD
FVDD
VDD
200 mV
dVDD/dt Supply Voltage Up/Down Ramping
Rate UVDD
AVDD 20 V/µs
fXTAL XTAL Clock Frequency XTAL1 4 4 5 MHz
VSUP Main Supply Voltage
Analog Supply Voltage UVDD=AVDD 3.5 5 5.5 V
HVSUP SM Supply Voltage HVDDn 4.75 5 5.25 V
fSYS CPU Clock Frequency, PLL on For a list of available settings see Tables 4–1
and 4–2.
fBUS Program Storage Clock Fre-
quency, PLL on
Vil
(see Table 2-2
for a list of input
types and their
supply volt-
ages)
Automotive Low Input Voltage U-Ports
H-Ports
P-Ports
0.5*xVDD V
CMOS Low Input Voltage U-Ports, TEST,
TEST2
H-Ports
P-Ports
0.3*xVDD V
Vih
(see Table 2-2
for a list of input
types and their
supply volt-
ages)
Automotive High Input Voltage U-Ports
H-Ports
P-Ports
0.86*xVDD V
CMOS High Input Voltage U-Ports,TEST,
TEST2
H-Ports
P-Ports
0.7*xVDD V
RVil Reset Active Input Voltage RESETQ 0.75 V
WRVil Reset Active Input Voltage during
Power Saving Modes and Wake
Reset
RESETQ 0.4 V
RVim Reset Inactive and Alarm Active
Input Voltage RESETQ 1.5 2.3 V
RVih Reset Inactive and Alarm Inactive
Input Voltage RESETQ 3.2 V
ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 13
3.3. Characteristics
Listed are only those characteristics that are differing from Chapter 3.3 of Document “CDC32xxG-C, Automotive Controller Family
User Manual, CDC3205G-C Automotive Controller” (3AI). All not differing characteristics, that are not listed here, apply, but in a
TCASE temperature range extended to -40 to +105C
WRVih Reset Inactive Input Voltage dur-
ing Power Saving Modes and
Wake Reset
RESETQ UVDD-0.4V V
VREFi Ext. ADC Reference Input Voltage VREF 2.56 AVDD V
PViADC Port Input Voltage referenced
to int. VREF Reference
ADC Port Input Voltage referenced
to ext. VREFINT Reference
P-Ports 0
0
VREFi
VREFINT
V
Table 3–3: UVSS=FVSS=HVSSn=AVSS=0V, 3.5V<AVDD=UVDD<5.5V, 4.75V<HVDDn<5.25V, TCASE=-40 to +105C, fXTAL=5MHz,
external components according to Fig. 2–3 (unless otherwise noted)
Symbol Parameter Pin Na. Min. Typ 1) Max. Unit Test Conditions
Package
Rthjc Thermal Resistance from
Junction to Case 25 C/W
Rthja Thermal Resistance from
Junction to Ambient 60 C/W
Supply Currents (CMOS levels on all inputs, i.e. Vil=xVSS±0.3V and Vih=xVDD±0.3V, no loads on outputs)
UIDDp UVDD PLL Mode Supply
Current UVDD 50 mA Flash Read,
fSYS=24MHz
UIDDprog VDD Flash Program Supply
Current UVDD 45 mA Flash Write/Erase,
all Modules OFF, 2)
UIDDf UVDD FAST Mode Supply
Current UVDD 22 mA all Modules OFF, 2)
UIDDs UVDD SLOW Mode Supply
Current UVDD see
Fig. 3–
1
1.4 mA all Modules OFF 2) 3)
UIDDd UVDD DEEP SLOW Mode
Supply Current UVDD see
Fig. 3–
1
0.9 mA all Modules OFF 3)
UIDDw UVDD WAKE Mode Supply
Current UVDD 0 20 50 µA RC and XTAL oscillators
OFF
UIDDst UVDD STANDBY Mode
Supply Current UVDD 35 75 µA RC oscillator ON, XTAL
OFF
UVDD 60 100 µA XTAL oscillator ON, RC
OFF 3)
1) Typical values describe typical behaviour at room temperature (25C, unless otherwise noted), with typical
Recommended Operating Conditions applied, and are not 100% tested.
Table 3–2: UVSS=HVSSn=FVSS=AVSS=0V
Symbol Parameter Pin Name Min. Typ Max. Unit
CDC 3207G-C ADVANCE INFORMATION
14 April 15, 2003; 6251-589-3AI Micronas
2) Value may be exceeded with unusual Hardware Option setting
3) Measured with external clock. Add 120µA for operation on typical quartz with SR0.XTAL=0 (Oscillator RUN mode).
Fig. 3–1: Typical UIDD characteristics over temperature @ fXTAL=4MHz, 5V
UIDDi UVDD IDLE Mode Supply
Current UVDD 50 TBD µA RC oscillator ON, XTAL
OFF
75 TBD µA XTAL oscillator ON, RC
OFF 3)
AIDDa AVDD Active Supply Cur-
rent AVDD 0.35 0.6 mA ADC ON, PLL OFF
12mAADC and PLL ON,
fSYS=24MHz
AIDDq Quiescent Supply Current AVDD 1 10 µA SLOW, DEEP SLOW
and power saving
modes, ADC and PLL
OFF
HIDDq Sum of
all
HVDDn
140µA no Output Activity,
SM Module OFF
Inputs
IiInput Leakage Current TEST2 -1 1 µA0<V
i<UVDD
Table 3–3: UVSS=FVSS=HVSSn=AVSS=0V, 3.5V<AVDD=UVDD<5.5V, 4.75V<HVDDn<5.25V, TCASE=-40 to +105C, fXTAL=5MHz,
external components according to Fig. 2–3 (unless otherwise noted)
Symbol Parameter Pin Na. Min. Typ 1) Max. Unit Test Conditions
1) Typical values describe typical behaviour at room temperature (25C, unless otherwise noted), with typical
Recommended Operating Conditions applied, and are not 100% tested.
0
100
200
300
400
500
600
700
800
900
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 °C
µA
TCASE
UIDD
UIDDs (SLOW mode)
UIDDd (DEEP SLOW mode)
UIDDi (IDLE mode)
ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 15
3.4. Recommended Quartz Crystal Characteristics
See Chapter 3.4 of document “CDC32xxG-C, Automotive Controller Hardware Manual, CDC3205G-C EMU Data Sheet (3AI)”.
CDC 3207G-C ADVANCE INFORMATION
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ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 17
4. CPU and Clock System
4.1. Recommended Register Settings
Other settings for PMF, IOP and WSR than those given in
Tables 4–1 and 4–2 shall not be used and may result in
undefined behaviour. It is required not to operate I/O faster
than Flash.
Suppression Strength (SUP) and Clock Tolerance (TOL) may
be varied between zero and the values for strong settings
according to the rules in Section 4.4.2 of the CDC32xxG-C
Hardware Manual. The given limits must not be exceeded
Table 4–1: PLL and ERM Modes: Recommended Settings and Resulting Operating Frequencies (MHz)
fXTAL CPU Flash I/O ERMC.EOM = 1 ERMC.EOM = 2 or 3
Weak Normal Strong Weak Normal Strong
fSYS PLLC.
PMF fBUS WSR fIO=
f0
IOC.
IOP
SUP
TOL
SUP
TOL
SUP
TOL
SUP
TOL
SUP
TOL
SUP
TOL
4 8 1 8 0x00 8 0 0407011 427411 6
16 3 8 0x11 8 1 08014015 8414 722 11
24 5 8 0x22 8 2 012 0 15 015 12 6211131 12
12 0x11 010 0 10 010 12 221 233 2
32 7 8 0x33 8 3 012 0 12 012 16 8281231 12
10.67 0x22 012 0 12 012 16 819
23
28
9
7
6
19
23
37
9
7
6
40 9 10 0x33 8 4 06060 6 21 635 637 6
48 11 12 0x33 8 5 01010 1 25 142 142 1
5 10 1 10 0x00 10 0 0508014 538414 7
20 3 10 0x11 10 1 010 0 15 015 10 517 828 8
30 5 10 0x22 10 2 014 0 14 014 15 824
26 12
11 28
30
35
10
9
8
40 7 10 0x33 10 3 06060 6 21 635 637 6
50 9 12.5 0x33 10 4 set ERMC.EOM=0 set ERMC.EOM=0
Table 4–2: PLL2 and ERM Modes: Settings Sacrificing Unlimited Operation of Peripheral Modules and Resulting Operating
Frequencies (MHz)
fXTAL CPU Flash I/O ERMC.EOM = 1 ERMC.EOM = 2 or 3
Weak Normal Strong Weak Normal Strong
fSYS PLLC.
PMF fBUS WSR fIO=
f0
IOC.
IOP
SUP
TOL
SUP
TOL
SUP
TOL
SUP
TOL
SUP
TOL
SUP
TOL
4122 60x1142 06010015 6310 516 8
12 0x00 0505056210 216 2
20 4 10 0x11 4 4 010 0 15 015 10 517 828 8
5152 7.50x1152 07013015 7413 721 11
CDC 3207G-C ADVANCE INFORMATION
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ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 19
5. Memory and Special Function ROM (SFR) System
Fig. 5–1: Address Map. Most Common Settings
A0.0000
20.0000
0
F0.0000
.5M
2M
8M
address range
I/O I/O
SFR
Flash
SFR
00FF.FFFF
(16M)
I/O
SFR
C0.0000
RAM
.5M
2M
F8.0000
E0.0000
rsvd
SFR
RESETQ = 1
debug
CR.MAP = 00 CR.MAP = 01 CR.MAP = 1x
RESETQ = 0
TEST2-Pin = 0
SFR
TEST2-Pin = 1
8000
4.0000
512KB Flash
512KB
Flash
512KB
Flash
512KB
24.0000
C0.8000
The device contains a 512-KByte Flash
EEPROM of the AMD Am29LV400BT type
(top boot configuration). This device exhib-
its electrical byte program and sector
erase functions. Refer to the AMD data
sheet for details.
32KB RAM
32KB RAM
32KB
RAM
32KB
CDC 3207G-C ADVANCE INFORMATION
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ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 21
6. Core Logic
6.1. Control Word (CW)
A number of important system configuration properties are
selectable during device start-up by means of a unique Con-
trol Word (CW).
6.1.1. Reset Active
At the end of the reset period, the device fetches this CW
from address locations 0x20 to 0x23 of a source that is
determined by the state of pins TEST and TEST2 and flag
MFPLR.MFPL, see Table 6–1 for MCM parts, Table 6–2 for
ROM parts.
As can be seen from Table 6–1, the device disables external
access (through the Multi Function port) to internal code, as
long as MFPLR.MFPL is 1 (= state after UVDD power-up).
Setting it to 0 requires internal SW. By this means, an effec-
tive device lock mechanism is implemented, that prevents
unauthorized access to internal SW.
In ROM parts, flag MFPLR.MFPL is available, but does not
lock the Multi Function port. Thus Table 6–1 reduces to Table
6–2.
6.1.2. Reset Inactive
When exiting Reset, the CW is read and stored in the Control
Register (CR) and the system will start up according to the
configuration defined therein.
Normally the CW is fetched from the same memory that the
system will start executing code from. Table 6–3 gives fix
CWs for a list of the most commonly used configurations.
Table 6–1: CW fetch in MCM parts (QFP128)
Control Word Fetch
desired from Necessary Reset con-
figuration
TEST2 TEST MFPL
Int. Flash 0 0 x
Int. Flash 0 1 1
Ext. via Multi Function port 0 1)
Int. Special Function ROM 1 x x
1) Only available after a non-Power-On RESET with
MFPL = 0 set before
Table 6–2: CW fetch in ROM parts (QFP128)
Control Word Fetch desired from Necessary Reset
config. of pins
TEST2 TEST
Internal ROM 0 0
External via Multi Function port 0 1
Int. Special Function ROM 1 x
Table 6–3: Some common system configurations and the corresponding CW setting
Part
Type Program Start desired from Additional desired properties Necessary CW
31:16 15:0
MCM int. 16-Bit Flash (Am29LV400BT) - Don’t care 0x7F5F
ROM int. 16-Bit ROM - Don’t care 0x7F5F
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ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 23
7. Hardware Options
7.1. Functional Description
Hardware Options are available in several areas to adapt the
IC function to the host system requirements. For details see
the CDC32xxG-C Hardware Manual.
Hardware Option setting requires two steps:
1. selection is done by programming dedicated address loca-
tions in the HW Options field with the desired options’ code.
2. activation is done by copying the HW Options field to the
corresponding HW Options registers at least once after each
reset.
In EMU and MCM devices all HW Options are SW progam-
mable.
In mask ROM derivatives the clock options and the Watch-
dog, Clock and Supply Monitors are hard wired according to
the HW Options field of the ROM code hex file. Those
options can only be altered by changing a production mask.
To ensure compatible option settings in this IC and mask
ROM derivatives when run with the same ROM code, it is
mandatory to always write the HW Options field to the HW
option registers directly after reset.
CDC 3207G-C ADVANCE INFORMATION
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ADVANCE INFORMATION CDC 3207G-C
Micronas April 15, 2003; 6251-589-3AI 25
8. Differences
This chapter describes differences of this document to pre-
decessor document “CDC3207G-C V2.0 CDC3205G-C
Automotive Controller Specification“ (6251-589-2AI)
#Section Description
1 1. Introduction Some edtitorial corrections.
22. Pins and Packages TEST2 pin w/o internal pull-down.
Fig. 2-3: corrected.
33. Electrical Characteristics Some edtitorial corrections.
Abs. Max. Ratings: Some edtitorial corrections.
Rec. Op. Conditions: Some edtitorial corrections.
Characteristics: General remarks changed. Tab. 3-3 table title changed.
UIDDs, UIDDd, UIDDw, UIDDst, UIDDi, values and conditions changed.
AIDDa, AIDDq, conditions changed.
Ii added.
Fig. 3-1: UIDDi added.
48. Differences Added.
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
CDC 3207G-C ADVANCE INFORMATION
26 April 15, 2003; 6251-589-3AI Micronas
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com
Printed in Germany
Order No. 6251-589-3AI
9. Data Sheet History
1. Advance Information: “CDC3207G-C V1.0 Automo-
tive Controller Specification”, 21 FEB 02,
6251-589-1AI. First release of the advance informa-
tion.
Originally created for HW version CDC3207G-C1.
2. Advance Information: “CDC3207G-C V2.0 Automo-
tive Controller Specification”, June 6, 2003,
6251-589-2AI.
Second release of the advance information.
Originally created for HW version CDC3207G-C2.
3. Advance Information: “CDC3207G-C V2.0 Automo-
tive Controller Specification”, April 15, 2003,
6251-589-3AI.
Third release of the advance information.
Originally created for HW version CDC3207G-C3.
