KSZ8895MQ/RQ/FMQ
Integrated 5 -Port 10/100 Managed Ethernet
Switch with MII/RMII Interface
Revision 1.7
General Description
The KSZ8895MQ/RQ/FMQ is a highly-integrated,
Layer 2 managed, five-port switch with numerous
features designe d to reduc e s ystem cos t. Intended f or
cost-sensitive 10/100Mbps five-port switch systems
with low power consumption, on-chip termination, and
internal core power controllers, it supports
high-performance memory bandwidth and shared
memory-based switch fabric with non-blocking
configuration. Its extensive feature set includes power
management, programmable rate limit and priority
ratio, tag/port-based VLAN, packets filtering,
four-queue QoS prioritization, management interfaces,
and MIB counters. The KSZ8895 family provides
multiple CPU data interfaces to effectively address
both current and emerging fast Ethernet applications
when port 5 is configured to separate MAC5 with
SW5-MII/RMII and PHY5 with P5-MII/RMII interfaces.
The KSZ8895 family offers three configurations,
providing the flexibility to meet different requirements:
• KSZ8895MQ: Five 10/100Base-T/TX transceivers,
one SW5-MII and one P5-MII interface,
• KSZ8895RQ: Five 10/100Base-T /TX tr ansceivers,
one SW5-RMII and one P5-RMII interface
• KSZ8895FMQ: Three 10/100Base-T/TX
transceivers on Ports 1, 2, 5 and two 100Base-FX
transceivers on Ports 3, 4, one SW5-MII and one
P5-MII interface
All registers of MACs and PHYs units can be
managed by the SPI or the SMI interface. MIIM
registers can be accessed through the MDC/MDIO
interface. EEPRO M c an s et al l con tr ol r egis t ers f or the
unmanaged m ode. K SZ8895MQ /RQ/F MQ ar e 12 8-pin
PQFP packages.
Functional Diagram
Note:
SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 19, 2014 Revision 1.7
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Features
Advanced Switch Features
• IEEE 802.1 q VLAN supp ort for up t o 128 active VLAN groups
(full-range 4096 of VLAN ID s).
• Static MAC table supports up to 32 entries.
• VLAN ID t ag/untag options, per port basis
• IEEE 802.1p/q tag insertion or removal on a per port basis
based on ingress port (egress).
• Program mabl e r ate l i miti ng at t he i ngres s and egr ess on a per
port basis.
• Jitter-free per packet based rate limiting support.
• Broadcast storm protection with percentage control (global
and per port basis).
• IEEE 802.1d rapid spanni ng tree protocol RSTP support.
• Tail t ag mode (1 b yte add ed before FCS ) suppor t at Port 5 to
infor m the proc essor which ingress port receives the pack et.
• 1.4Gbps high-performanc e m emory ban dw idth and shared
memory-based switch fabric with fully
non-blocking configuration.
• Dual MII with MAC5 and PHY5 on port 5, SW5-MII/RMII for
MAC 5 and P5-MII/RMII for PHY 5.
• Enable/Disable option for huge frame size up to 2000 Bytes
per frame.
• IGMP v1/v2 snooping (Ipv4) support for multicast packet
filtering.
• IPv4/IPv6 QoS support.
• Support unk nown uni cas t /m ult icas t addres s and unk nown VI D
packet filtering.
• Self-address filtering.
Comprehensive Configuration Register Access
• Serial management interface (MDC/MDIO) to all PHYs
registers and SMI inter face (M DC/ M D IO) to all regis ters.
• High spee d SPI (up t o 25MHz) and I 2C master Interf ace to all
inter nal registers.
• I/0 pins strapping and EEPROM to program selective
registers i n unm anaged swi tch mode.
• Control registers configurable on the fly (port-priority,
802.1p/d/q, AN).
QoS/CoS Packet Prioritization Support
• Per port , 802.1p and DiffSer v-based.
• 1/2/4-queue QoS prioritization selecti on.
• Program m able weighted fair queuing f or rati o control.
• Re-mapping of 802.1p priority field per por t basis.
Integrated Five-Port 10/100 Ethernet Switch
• New generation switch with five MACs and five PHYs with
full y compliant with IEEE 802.3u standard.
• PHYs designed with patented enhanced mixed-signal
technology.
• Non-blocking switch fabric assures fast packet delivery by
utilizing a 1K MAC address lookup table and a store-and-
forward architect ure.
• On-chip 64Kb yte memory f or frame buf fering ( not shar ed with
1K unicast address table).
• Full duplex IEEE 802.3x flow control (PAUSE) with force
mode opt ion.
• Half-duplex back pressure flow control.
• HP Auto MDI/MDI-X and IEEE Aut o crossover support.
• SW-MII interface supports both MAC mode and PHY mode.
• 7-wire serial network interface (SNI) suppor t for legacy MAC.
• Per port LED Indicators for link, activity, and 10/100 speed.
• Register port status support for link, activity, full/half duplex
and 10/100 speed.
• On-chip terminations and internal biasing technology for cost
down and lowest pow er consum ption.
Switch Monitoring Featur e s
• Port m irroring/ monitori ng/snif fing: ingr ess and/or egr ess traff ic
to any port or MII .
• MIB counters for fully compliant statistics gathering 34 MIB
counters per port.
• Loop-back support for MAC, PHY and remote diagnostic of
failure.
• Interrupt for the link change on any ports.
Low Power Dissipation
• Full-chip hardware power -down.
• Full-chip software power-down and per port software power
down.
• Energy-detect mode support < 100mW full chip-power
consum ption when all ports have no activity.
• Very low full chip power consumption (<0.5W), without extra
power c onsumption on transformers.
• Dynamic clock tree shutdown feature.
• Voltages: Single 3.3V supply with 3.3V VDDIO and Internal
1.2V LDO controller enabled, or external 1.2V LDO soluti on.
– Analog VD D AT 3.3V only.
– VDDIO support 3. 3V , 2.5V and 1.8V.
– Low 1.2V c ore power .
• 0.13µm CMOS technology.
• Commerc ial temperature range: 0°C t o +70°C.
• Industrial Tem perature Range: -40°C to +8 5°C.
• Available in 128-pin PQFP lead-free package.
Applications
• VoIP phone
• Set-top/game bo x
• Automotive
• Industrial control
• IPTV POF
• SOHO residenti al gateway
• Broadband gatew ay/firewall/VPN
• Integrated DSL/cable modem
• Wireless LAN access point + gateway
• Standal one 10/10 0 switch
March 19, 2014 2 Revision 1.7
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Ordering Information
Part Number Temperature Range Package Lead Finish/Grade
KSZ8895MQ 0°C to 70°C 128-Pin PQFP Pb-Free/Commercial
KSZ8895MQI −40°C to +85°C 128-Pin PQFP Pb-Free/Industrial
KSZ8895RQ 0°C to 70°C 128-Pin PQFP Pb-Free/Commercial
KSZ8895RQI −40°C to +85°C 128-Pin PQFP Pb-Free/Industrial
KSZ8895FMQ 0°C to 70°C 128-Pin PQFP Pb-Free/Commercial
KSZ8895FMQI −40°C to +85°C 128-Pin PQFP Pb-Free/Industrial
KSZ8895MQ-EVAL Evaluation Board for KSZ8895MQ
KSZ8895RQ-EVAL Evaluation Board for KSZ8895RQ
KSZ8895FMQ-Eval Evaluation Board for KSZ8895FMQ
Note:
1. Please consult sales for the availability
Revision History
Revision
Date
Description
1.0 09/13/10 Initial document created
1.1 11/16/10 Remove TMQ part
1.2 01/20/11 Update the order ing infor mation and some data.
1.3 03/18/11 Update the register number, descriptions and correct typo error.
1.4 08/30/11 Correct typo error for packag e information and upda t e some
descriptions for SMI mode and IGMP and update register default
values, pins type and some parameters.
1.5 02/24/12
Update descriptions for Pin, register 1 chip ID, port register,
VLAN table and I2C master. Update the equation in the
broadcast stor m prot ect ion se ctio n. Update table of strap-in pins.
Update the ordering information for RQ parts.
1.6 11/28/12
Update the ordering information for FMQ parts available. Correct
typos. Update the operat io n rating to ±5% and TTL min/max I/O
voltage in different VDDIO. Add register 165 for FMQ part with
fiber mode. Update a note for pin 125 descriptions.
1.7 03/12/14
Change I/O from TTL to CMOS. Update SPI description from
127 to 255 for access registers. Update Register 6 offset. Update
register offset mapping index. Correct typos. Updat es tim ing data
for MII PHY mode. Update the table of tail tag rules. Update
description for Register 1 bits [7:4]. Update Table 8 from bit
[57:55] to bit [58:56]. Update the port register control 2 bit [6]
description (bits [20:16] change to bits [11:7]). Up date T ab le 33.
Add evaluation Board in ordering information table. Update a
note for pin 126 descriptions.
March 12, 2014 3 Revision 1.7
Micrel, Inc.
Contents
System Level Applications ........................................................................................................................................... 13
Pin Configuration .......................................................................................................................................................... 15
Pin Description .............................................................................................................................................................. 16
Pin for Strap-In Options ................................................................................................................................................ 23
Introduction ................................................................................................................................................................... 26
Functional Overview: Physical Layer Transceiver .................................................................................................... 26
100BASE-TX Transmit ............................................................................................................................................... 26
100BASE-TX Receive ................................................................................................................................................ 26
PLL Clock Synthesizer ................................................................................................................................................ 27
Scrambler/Descrambler (100BASE-TX only) ............................................................................................................. 27
100BASE-FX Operation .............................................................................................................................................. 27
100BASE-FX Signal Detection ................................................................................................................................... 27
100BASE-FX Far End Fault ........................................................................................................................................ 27
10BASE-T Transmit .................................................................................................................................................... 27
10BASE-T Receive ..................................................................................................................................................... 27
MDI/MDI-X Auto Crossover ........................................................................................................................................ 27
Straight Cab le ......................................................................................................................................................... 28
Crossover Cable ..................................................................................................................................................... 29
Auto-Negotiation ......................................................................................................................................................... 29
On-Chip Termination Resistors .................................................................................................................................. 31
Internal 1.2V LDO Controller ...................................................................................................................................... 31
Functional Overview: Power Management ................................................................................................................. 31
Normal Operation Mode ............................................................................................................................................. 31
Energy Detect Mode ................................................................................................................................................... 32
Soft Power Down Mode .............................................................................................................................................. 32
Power Saving Mod e .................................................................................................................................................... 32
Port-based Power Down M ode ................................................................................................................................... 32
Functional Overview: Switch Core .............................................................................................................................. 33
Address Look-Up ........................................................................................................................................................ 33
Learning ...................................................................................................................................................................... 33
Migration ..................................................................................................................................................................... 33
Aging ........................................................................................................................................................................... 33
Forwarding .................................................................................................................................................................. 33
Switching Engine ........................................................................................................................................................ 33
Media Access Controller (MAC) Operation ................................................................................................................ 33
Inter-Packet Gap (IPG) ........................................................................................................................................... 34
Backoff Algor it hm .................................................................................................................................................... 34
Late Collis ion .......................................................................................................................................................... 34
Illegal Frames ......................................................................................................................................................... 34
Flow Control ............................................................................................................................................................ 34
Half-Duplex Back Pressure .................................................................................................................................... 37
Broadcast Storm Protection .................................................................................................................................... 37
MII Interface Operation ............................................................................................................................................... 38
March 12, 2014 4 Revision 1.7
Micrel, Inc.
Port 5 PHY 5 P5-MII/RMII Interface ............................................................................................................................ 38
Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ ...................................................................................... 39
Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ ................................................................................. 40
SNI Interface Operation .............................................................................................................................................. 41
Advanced Functionality ................................................................................................................................................ 42
QoS Priorit y Support ................................................................................................................................................... 42
Port-Bas ed Prior ity .................................................................................................................................................. 42
802.1p-Bas ed Prior it y ............................................................................................................................................. 42
DiffServ-Based Priority ........................................................................................................................................... 43
Spanning Tree Support ............................................................................................................................................... 43
Rapid Spanning Tree Support .................................................................................................................................... 44
Tail Tagging Mode ...................................................................................................................................................... 45
IGMP Support ............................................................................................................................................................. 46
Port Mirroring Support ................................................................................................................................................ 46
VLAN Support ............................................................................................................................................................. 46
Rate Lim iting Suppor t ................................................................................................................................................. 47
Ingress Rate Limit ................................................................................................................................................... 47
Egress Rate Limit ................................................................................................................................................... 48
Transmit Queue Ratio Programming ...................................................................................................................... 48
Filtering for Self-Address, Unk nown Unicast/Multicast Address and Unknown VID Packet/IP Multicast .................. 48
Configuration Interface ............................................................................................................................................... 48
I2C Master Serial Bus Configuration ....................................................................................................................... 48
SPI Slave Serial Bus Configuration ........................................................................................................................ 49
MII Managem ent Inter f ace ( MII M) .......................................................................................................................... 52
Serial Management Interface (SMI) ........................................................................................................................ 52
Register Description ..................................................................................................................................................... 54
Global Registers ......................................................................................................................................................... 56
Register 0 (0x00): Chip ID0 .................................................................................................................................... 56
Register 1 (0x01): Chip ID1 / Start Switch .............................................................................................................. 56
Register 2 (0x02): Global Control 0 ........................................................................................................................ 56
Register 3 (0x03): Global Control 1 ........................................................................................................................ 57
Register 4 (0x04): Global Control 2 ........................................................................................................................ 58
Register 5 (0x05): Global Control 3 ........................................................................................................................ 59
Register 6 (0x06): Global Control 4 ........................................................................................................................ 60
Register 7 (0x07): Global Control 5 ........................................................................................................................ 61
Register 8 (0x08): Global Control 6 ........................................................................................................................ 61
Register 9 (0x09): Global Control 7 ........................................................................................................................ 61
Register 10 (0x0A): Global Control 8 ...................................................................................................................... 62
Register 11 (0x0B): Global Control 9 ...................................................................................................................... 62
Register 12 (0x0C): Global Control 10 ................................................................................................................... 63
Register 13 (0x0D): Global Control 11 ................................................................................................................... 63
Register 14 (0x0E): Power Down Management Control 1 ..................................................................................... 63
Register 15 (0x0F): Power Down Management Control 2...................................................................................... 64
March 12, 2014 5 Revision 1.7
Micrel, Inc.
Port Registers ............................................................................................................................................................. 65
Register 16 (0x10): Port 1 Control 0 ....................................................................................................................... 65
Register 32 (0x20): Port 2 Control 0 ....................................................................................................................... 65
Register 48 (0x30): Port 3 Control 0 ....................................................................................................................... 65
Register 64 (0x40): Port 4 Control 0 ....................................................................................................................... 65
Register 80 (0x50): Port 5 Control 0 ....................................................................................................................... 65
Register 17 (0x11): Port 1 Control 1 ....................................................................................................................... 66
Register 33 (0x21): Port 2 Control 1 ....................................................................................................................... 66
Register 49 (0x31): Port 3 Control 1 ....................................................................................................................... 66
Register 65 (0x41): Port 4 Control 1 ....................................................................................................................... 66
Register 81 (0x51): Port 5 Control 1 ....................................................................................................................... 66
Register 18 (0x12): Port 1 Control 2 ....................................................................................................................... 67
Register 34 (0x22): Port 2 Control 2 ....................................................................................................................... 67
Register 50 (0x32): Port 3 Control 2 ....................................................................................................................... 67
Register 66 (0x42): Port 4 Control 2 ....................................................................................................................... 67
Register 82 (0x52): Port 5 Control 2 ....................................................................................................................... 67
Register 19 (0x13): Port 1 Control 3 ....................................................................................................................... 68
Register 35 (0x23): Port 2 Control 3 ....................................................................................................................... 68
Register 51 (0x33): Port 3 Control 3 ....................................................................................................................... 68
Register 67 (0x43): Port 4 Control 3 ....................................................................................................................... 68
Register 83 (0x53): Port 5 Control 3 ....................................................................................................................... 68
Register 20 (0x14): Port 1 Control 4 ....................................................................................................................... 68
Register 36 (0x24): Port 2 Control 4 ....................................................................................................................... 68
Register 52 (0x34): Port 3 Control 4 ....................................................................................................................... 68
Register 68 (0x44): Port 4 Control 4 ....................................................................................................................... 68
Register 84 (0x54): Port 5 Control 4 ....................................................................................................................... 68
Register 87 (0x57): RMII Management Control Register ....................................................................................... 68
Register 25 (0x19): Port 1 Status 0 ........................................................................................................................ 69
Register 41 (0x29): Port 2 Status 0 ........................................................................................................................ 69
Register 57 (0x39): Port 3 Status 0 ........................................................................................................................ 69
Register 73 (0x49): Port 4 Status 0 ........................................................................................................................ 69
Register 89 (0x59): Port 5 Status 0 ........................................................................................................................ 69
Register 26 (0x1A): Port 1 PHY Special Control/Status ......................................................................................... 69
Register 42 (0x2A): Port 2 PHY Special Control/Status ......................................................................................... 69
Register 58 (0x3A): Port 3 PHY Special Control/Status ......................................................................................... 69
Register 74 (0x4A): Port 4 PHY Special Control/Status ......................................................................................... 69
Register 90 (0x5A): Port 5 PHY Special Control/Status ......................................................................................... 69
Register 27 (0x1B): Reserved ................................................................................................................................ 70
Register 43 (0x2B): Reserved ................................................................................................................................ 70
Register 59 (0x3B): Reserved ................................................................................................................................ 70
Register 75 (0x4B): Reserved ................................................................................................................................ 70
Register 91 (0x5B): Reserved ................................................................................................................................ 70
Register 28 (0x1C): Port 1 Control 5 ...................................................................................................................... 70
Register 44 (0x2C): Port 2 Control 5 ...................................................................................................................... 70
March 12, 2014 6 Revision 1.7
Micrel, Inc.
Register 60 (0x3C): Port 3 Control 5 ...................................................................................................................... 70
Register 76 (0x4C): Port 4 Control 5 ...................................................................................................................... 70
Register 92 (0x5C): Port 5 Control 5 ...................................................................................................................... 70
Register 29 (0x1D): Port 1 Control 6 ...................................................................................................................... 71
Register 45 (0x2D): Port 2 Control 6 ...................................................................................................................... 71
Register 61 (0x3D): Port 3 Control 6 ...................................................................................................................... 71
Register 77 (0x4D): Port 4 Control 6 ...................................................................................................................... 71
Register 93 (0x5D): Port 5 Control 6 ...................................................................................................................... 71
Register 30 (0x1E): Port 1 Status 1 ........................................................................................................................ 72
Register 46 (0x2E): Port 2 Status 1 ........................................................................................................................ 72
Register 62 (0x3E): Port 3 Status 1 ........................................................................................................................ 72
Register 78 (0x4E): Port 4 Status 1 ........................................................................................................................ 72
Register 94 (0x5E): Port 5 Status 1 ........................................................................................................................ 72
Register 31 (0x1F): Port 1 C ontrol 7 and Status 2 ................................................................................................. 72
Register 47 (0x2F): Port 2 Control 7 and Status 2 ................................................................................................. 72
Register 63 (0x3F): Port 3 C ontrol 7 and Status 2 ................................................................................................. 72
Register 79 (0x4F): Port 4 Control 7 and Status 2 ................................................................................................. 72
Register 95 (0x5F): Port 5 C ontrol 7 and Status 2 ................................................................................................. 72
Advanced Control Registers ....................................................................................................................................... 73
Register 104 (0x68): MAC Address Register 0 ...................................................................................................... 73
Register 105 (0x69): MAC Address Register 1 ...................................................................................................... 73
Register 106 (0x6A): MAC Address Register 2 ...................................................................................................... 73
Register 107 (0x6B): MAC Address Register 3 ...................................................................................................... 73
Register 108 (0x6C): MAC Address Regis ter 4 ...................................................................................................... 73
Register 109 (0X6D): MAC Address Register 5 ..................................................................................................... 73
Register 110 (0x6E): Indirect Access Control 0 ..................................................................................................... 74
Register 111 (0x6F): Indirect Access Control 1 ...................................................................................................... 74
Register 112 (0x70): Indirect Data Register 8 ........................................................................................................ 75
Register 113 (0x71): Indirect Data Register 7 ........................................................................................................ 75
Register 114 (0x72): Indirect Data Register 6 ........................................................................................................ 75
Register 115 (0x73): Indirect Data Register 5 ........................................................................................................ 75
Register 116 (0x74): Indirect Data Register 4 ........................................................................................................ 75
Register 117 (0x75): Indirect Data Register 3 ........................................................................................................ 75
Register 118 (0x76): Indirect Data Register 2 ........................................................................................................ 75
Register 119 (0x77): Indirect Data Register 1 ........................................................................................................ 75
Register 120 (0x78): Indirect Data Register 0 ........................................................................................................ 75
Register 124 (0x7C): Interrupt Status Register ...................................................................................................... 75
Register 125 (0x7D): Interrupt Mask Register ........................................................................................................ 76
Register 128 (0x80): Global Control 12 .................................................................................................................. 76
Register 129 (0x81): Global Control 13 .................................................................................................................. 76
Register 130 (0x82): Global Control 14 .................................................................................................................. 77
Register 131 (0x83): Global Control 15 .................................................................................................................. 77
Register 132 (0x84): Global Control 16 .................................................................................................................. 78
Register 133(0x85): Global Control 17 ................................................................................................................... 78
March 12, 2014 7 Revision 1.7
Micrel, Inc.
Register 134 (0x86): Global Control 18 .................................................................................................................. 78
Register 135 (0x87): Global Control 19 .................................................................................................................. 79
Register 144 (0x90): TOS Priority Control Register 0 ............................................................................................ 79
Register 145 (0x91): TOS Priority Control Register 1 ............................................................................................ 80
Register 146 (0x92): TOS Priority Control Register 2 ............................................................................................ 80
Register 147 (0x93): TOS Priority Control Register 3 ............................................................................................ 80
Register 148 (0x94): TOS Priority Control Register 4 ............................................................................................ 80
Register 149 (0x95): TOS Priority Control Register 5 ............................................................................................ 81
Register 150 (0x96): TOS Priority Control Register 6 ............................................................................................ 81
Register 151 (0x97): TOS Priority Control Register 7 ............................................................................................ 81
Register 152 (0x98): TOS Priority Control Register 8 ............................................................................................ 81
Register 153 (0x99): TOS Priority Control Register 9 ............................................................................................ 81
Register 154 (0x9A): TOS Priority Control Register 10 .......................................................................................... 81
Register 155 (0x9B): TOS Priority Control Register 11 .......................................................................................... 81
Register 156 (0x9C): TOS Priority Control Register 12 .......................................................................................... 82
Register 157 (0x9D): TOS Priority Control Register 13 .......................................................................................... 82
Register 158 (0x9E): TOS Priority Control Register 14 .......................................................................................... 82
Register 159 (0x9F): TOS Priority Control Register 15 .......................................................................................... 82
Register 165 (0xA5): Fiber Control Register .......................................................................................................... 82
Register 176 (0xB0): Port 1 Control 8 .................................................................................................................... 83
Register 192 (0xC0): Port 2 Control 8 .................................................................................................................... 83
Register 208 (0xD0): Port 3 Control 8 .................................................................................................................... 83
Register 224 (0xE0): Port 4 Control 8 .................................................................................................................... 83
Register 240 (0xF0): Port 5 Control 8 ..................................................................................................................... 83
Register 177 (0xB1): Port 1 Control 9 .................................................................................................................... 84
Register 193 (0xC1): Port 2 Control 9 .................................................................................................................... 84
Register 209 (0xD1): Port 3 Control 9 .................................................................................................................... 84
Register 225 (0xE1): Port 4 Control 9 .................................................................................................................... 84
Register 241 (0xF1): Port 5 Control 9 ..................................................................................................................... 84
Register 178 (0xB2): Port 1 Control 10 .................................................................................................................. 85
Register 194 (0xC2): Port 2 Control 10 .................................................................................................................. 85
Register 210 (0xD2): Port 3 Control 10 .................................................................................................................. 85
Register 226 (0xE2): Port 4 Control 10 .................................................................................................................. 85
Register 242 (0xF2): Port 5 Control 10................................................................................................................... 85
Register 179 (0xB3): Port 1 Control 11 .................................................................................................................. 85
Register 195 (0xC3): Port 2 Control 11 .................................................................................................................. 85
Register 211 (0xD3): Port 3 Control 11 .................................................................................................................. 85
Register 227 (0xE3): Port 4 Control 11 .................................................................................................................. 85
Register 243 (0xF3): Port 5 Control 11................................................................................................................... 85
Register 180 (0xB4): Port 1 Control 12 .................................................................................................................. 85
Register 196 (0xC4): Port 2 Control 12 .................................................................................................................. 85
Register 212 (0xD4): Port 3 Control 12 .................................................................................................................. 85
Register 228 (0xE4): Port 4 Control 12 .................................................................................................................. 85
Register 244 (0xF4): Port 5 Control 12................................................................................................................... 85
March 12, 2014 8 Revision 1.7
Micrel, Inc.
Register 181 (0xB5): Port 1 Control 13 .................................................................................................................. 86
Register 197 (0xC5): Port 2 Control 13 .................................................................................................................. 86
Register 213 (0xD5): Port 3 Control 13 .................................................................................................................. 86
Register 229 (0xE5): Port 4 Control 13 .................................................................................................................. 86
Register 245 (0xF5): Port 5 Control 13................................................................................................................... 86
Register 182 (0xB6): Por t 1 Rate Limit Control ...................................................................................................... 86
Register 198 (0xC6): Port 2 Rate Limit Control ...................................................................................................... 86
Register 214 (0xD6): Port 3 Rate Limit Control ...................................................................................................... 86
Register 230 (0xE6): Por t 4 Rate Limit Control ...................................................................................................... 86
Register 246 (0xF6): Port 5 Rate Limit Control ...................................................................................................... 86
Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1................................................................................ 87
Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1 ............................................................................... 87
Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1 ............................................................................... 87
Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1................................................................................ 87
Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1 ................................................................................ 87
Register 184 (0xB8) : Po rt 1 Priority 1 Ingress Limit Control 2................................................................................ 87
Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2 ............................................................................... 87
Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2 ............................................................................... 87
Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2................................................................................ 87
Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2 ................................................................................ 87
Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3................................................................................ 87
Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3 ............................................................................... 87
Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3 ............................................................................... 87
Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3................................................................................ 87
Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3 ................................................................................ 87
Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4 ............................................................................... 87
Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4 ............................................................................... 87
Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4 ............................................................................... 87
Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4 ............................................................................... 87
Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4 ............................................................................... 87
Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1 ................................................................................ 88
Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1 ................................................................................ 88
Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1 ................................................................................ 88
Register 235 (0xEB): Port 4 Queue 0 Egress Limit Control 1 ................................................................................ 88
Register 251 (0xFB): Port 5 Queue 0 Egress Limit Control 1 ................................................................................ 88
Register 188 (0xBC) : Port 1 Queue 1 Egress Limit Control 2 ............................................................................... 88
Register 204 (0xCC) : Port 2 Queue 1 Egress Limit Control 2 ............................................................................... 88
Register 220 (0xDC) : Port 3 Queue 1 Egress Limit Control 2 ............................................................................... 88
Register 236 (0xEC) : Port 4 Queue 1 Egress Limit Control 2 ............................................................................... 88
Register 252 (0xFC) : Port 5 Queue 1 Egress Limit Control 2 ............................................................................... 88
Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3 ................................................................................ 88
Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3 ................................................................................ 88
Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3 ................................................................................ 88
Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3 ................................................................................ 88
March 12, 2014 9 Revision 1.7
Micrel, Inc.
Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3 ................................................................................ 88
Register 190 (0xBE) : Port 1 Queue 3 Egress Limit Control 4 ............................................................................... 89
Register 206 (0xCE) : Port 2 Queue 3 Egress Limit Control 4 ............................................................................... 89
Register 222 (0xDE) : Port 3 Queue 3 Egress Limit Control 4 ............................................................................... 89
Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4 ................................................................................ 89
Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4 ................................................................................ 89
Data Rate Selection Table in 100BT .......................................................................................................................... 90
Data Rate Selection Table in 10BT ............................................................................................................................ 90
Register 191(0xBF): Testing Register .................................................................................................................... 91
Register 207(0xCF): Reserved Control Register ................................................................................................... 91
Register 223(0xDF): Test R egis ter 2 ...................................................................................................................... 91
Register 239(0xEF): Test R egister 3 ...................................................................................................................... 91
Register 255(0xFF): Testing Register4 .................................................................................................................. 91
Static MAC Address Table ........................................................................................................................................... 92
VLAN Table .................................................................................................................................................................... 94
Dynamic MAC Address Table ...................................................................................................................................... 96
MIB (Mana g ement Inform ation Base) Counters ......................................................................................................... 97
MIIM Registers ............................................................................................................................................................. 100
Register 0h: MII Contro l ............................................................................................................................................ 100
Register 1h: MII Status ............................................................................................................................................. 101
Register 2h: PHYID HIGH ........................................................................................................................................ 101
Register 3h: PHYID LOW ......................................................................................................................................... 101
Register 4h: Advertisement Ability ............................................................................................................................ 101
Register 5h: Link Partner Ability ............................................................................................................................... 102
Register 1dh: Reserved ........................................................................................................................................... 102
Register 1fh: PHY Special Control/Status ................................................................................................................ 102
Absolute Maximum Ratings ....................................................................................................................................... 104
Operating Ratings ....................................................................................................................................................... 104
Electrical Characteristics ........................................................................................................................................... 104
Timing Diagrams ......................................................................................................................................................... 106
EEPROM Timing ....................................................................................................................................................... 106
SNI Timing ................................................................................................................................................................ 107
MII Timing ................................................................................................................................................................. 108
RMII Timing ............................................................................................................................................................... 110
SPI Timing ................................................................................................................................................................ 111
Auto-Negotiation Timing ........................................................................................................................................... 113
MDC/MDIO Timing.................................................................................................................................................... 114
Reset Timing ............................................................................................................................................................. 115
Reset Circuit Diagram ............................................................................................................................................... 116
Selection of Isolati on Transformer ............................................................................................................................ 117
Selection of Reference Crystal .................................................................................................................................. 117
Package Information(1) ................................................................................................................................................ 118
March 12, 2014 10 Revision 1.7
Micrel, Inc.
List of Figures
Figure 1. Broadband Gateway ..................................................................................................................................... 13
Figure 2. Integrated Broadband Router ....................................................................................................................... 13
Figure 3. Standalon e S witc h ........................................................................................................................................ 14
Figure 4. Using KSZ8895FMQ for Dual Media Converter ........................................................................................... 14
Figure 5. KSZ8895MQ/RQ/FMQ 128-Pin PQFP Pins Configurat io n ........................................................................... 15
Figure 6. Typical Straight Cable Connection ............................................................................................................... 28
Figure 7. Typical Crossover Cable Connection ........................................................................................................... 29
Figure 8. Auto-Negotiation ........................................................................................................................................... 30
Figure 9. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 35
Figure 10. Destination Address Resolution Flow Chart, Stage 2 .................................................................................. 36
Figure 11. 802.1p Pr ior ity Field Form at......................................................................................................................... 42
Figure 12. Tail Tag Frame Format ............................................................................................................................... 45
Figure 13. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram .............................................................. 49
Figure 14. SPI W rite Data C ycle .................................................................................................................................. 50
Figure 15. SPI Read Data C ycle .................................................................................................................................. 50
Figure 16. SPI Multiple Write ....................................................................................................................................... 51
Figure 17. SPI Multiple Read ....................................................................................................................................... 51
Figure 18. EEPROM Interface Input Receive Timing Diagram .................................................................................. 106
Figure 19. EEPROM Interface Output Transmit Timing Diagram .............................................................................. 106
Figure 20. SNI Input Timing ....................................................................................................................................... 107
Figure 21. SNI Output Timing .................................................................................................................................... 107
Figure 22. MAC Mode MII T im ing – Data Received from MII .................................................................................... 108
Figure 23. MAC Mode MII T im ing – Data Transmitted from MII ................................................................................ 108
Figure 24. PHY Mode MII Timing – Data Received from MII ..................................................................................... 109
Figure 25. PHY Mode MII Timing – Data Transmitted from MII ................................................................................. 109
Figure 26. RMII Timing – Data Received from RMII .................................................................................................. 110
Figure 27. RMII Timing – Data Transmitted to RMII .................................................................................................. 110
Figure 28. SPI Input Timing ....................................................................................................................................... 111
Figure 29. SPI Output Timing ..................................................................................................................................... 112
Figure 30. Auto-Negotiation Timing ........................................................................................................................... 113
Figure 31. MDC/MDIO Timing .................................................................................................................................... 114
Figure 32. Reset Timing ............................................................................................................................................. 115
Figure 33. Recommended Reset C irc uit .................................................................................................................... 116
Figure 34. Recommended Circuit for Interfacing with CPU/FPGA Reset .................................................................. 116
March 12, 2014 11 Revision 1.7
Micrel, Inc.
List of Tables
Table 1. MDI/MDI-X Pin Definitions ............................................................................................................................. 28
Table 2. Internal Function Block Status ....................................................................................................................... 31
Table 3. Port 5 PH Y P5-MII /RMII Signa ls ..................................................................................................................... 38
Table 4. Switch MAC5 MII Si gnals ................................................................................................................................ 39
Table 5. Port 5 MAC5 SW 5-RMII Connection ............................................................................................................... 41
Table 6. SNI Signals..................................................................................................................................................... 41
Table 7. Tail Tag Rules ................................................................................................................................................ 45
Table 8. F ID+DA Look-Up in the VLAN Mode ............................................................................................................. 47
Table 9. FID+SA Look-Up in the VLAN Mode .............................................................................................................. 47
Table 10. SPI Connections .......................................................................................................................................... 50
Table 11. MII Management Interface Frame Format ................................................................................................... 52
Table 12. Serial Management Interface (SMI) Frame Format ..................................................................................... 52
Table 13. 100BT Rate Selection for the Rate limit ........................................................................................................ 90
Table 14. 10BT Rate Selection for the Rate Limit ......................................................................................................... 90
Table 15. Static MAC Address Table ............................................................................................................................ 92
Table 16. VLAN Table ................................................................................................................................................... 94
Table 17. VLAN ID and Indirect Registers .................................................................................................................... 95
Table 18. Dynamic MAC Address Table ....................................................................................................................... 96
Table 19. Port1 MIB Counter Indirect Memory Offerts .................................................................................................. 97
Table 20. Format of “Per Port” MIB Counter ................................................................................................................. 98
Table 21. All Port Dropped Pac ket MIB Counters ......................................................................................................... 98
Table 22. Format of “All Dropped Packet” MIB Counter ............................................................................................... 98
Table 23. EEPROM Timing Parameters ..................................................................................................................... 106
Table 24. SNI Timing Parameters ............................................................................................................................... 107
Table 25. MAC Mode MII Timing Parameters ............................................................................................................. 108
Table 26. PHY Mode MII Timing Parameters ............................................................................................................. 109
Table 27. RMII Timing Parameters ............................................................................................................................. 110
Table 28. SPI Input Timing Parameters ...................................................................................................................... 111
Table 29. SPI Output Timing Parameters ................................................................................................................... 112
Table 30. Auto-Negotiation Timing Parameters .......................................................................................................... 113
Table 31. MDC/MDIO Typical Timing Parameters ...................................................................................................... 114
Table 32. Reset Timing Parameters ........................................................................................................................... 115
Table 33. Transformer Selection Criteria .................................................................................................................... 117
Table 34. Qualified Magnetic Vendors ........................................................................................................................ 117
Table 35. Typical Reference Crystal Characteristics .................................................................................................. 117
March 12, 2014 12 Revision 1.7
Micrel, Inc.
System Level Applications
Ethernet
MAC
CPU
Switch Controller
On-Chip Frame Buffers
MII-SW
10/100
PHY 5
4-port
LAN
MII-P5
1-port
WAN I/F
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
10/100
PHY 1
10/100
PHY 2
10/100
PHY 3
10/100
PHY 4
SPI/GPIO
SPI
Ethernet
MAC
External WAN port PHY not required.
Figure 1. Broadband Gateway
Ethernet
MAC
CPU
Switch Controller
On-Chip Frame Buffers
MII-SW
10/100
PHY 5
4-port
LAN
MII-P5
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
10/100
PHY 1
10/100
PHY 2
10/100
PHY 3
10/100
PHY 4
WAN PHY & AFE
(xDSL, CM...)
SPISPI/GPIO
Figure 2. Integrated Broadband Router
March 12, 2014 13 Revision 1.7
Micrel, Inc.
Switch Controller
On-Chip Frame Buffers
10/100
PHY 5
5-port
LAN
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
10/100
PHY 1
10/100
PHY 2
10/100
PHY 3
10/100
PHY 4
Figure 3. Standalone Switch
Figure 4. Using KSZ8895FMQ for Dual Media Converter
March 12, 2014 14 Revision 1.7
Micrel, Inc.
Pin Configuration
TXM5
VDDAT
FXSD3
TXP5
33
34
35
36
37
38
KSZ8895MQ/RQ/FMQ
(Top View)
NC
PMRXDV/PMCRSDV
NC
NC
NC
NC
NC
NC
PWRDN_N
INTR_N
GNDD
VDDC
PMTXEN
PMTXD3
PMTXD2
PMTXD1
PMTXD0
PMTXER
PMTXC/PMREFCLK
GNDD
PMRXD1
VDDIO
PMRXC
PMRXD3
PMRXD2
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
64
FXSD4
LED3-1
LED4-0
LED3-2
SCONF1
SCOL
SMRXD2
VDDIO
SMTXC/SMREFCLK
SMTXD0
SMTXD2
SMTXEN
PCOL
PCRS
PMRXER
LED4-1
LED4-2
LED5-1
LED5-2
VDDC
GNDD
SCONF0
SCRS
SMRXD0
SMRXD1
SMRXD3
SMRXDV/SMCRSDV
SMRXC
GNDD
SMTXER
SMTXD1
SMTXD3
PMRXD0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LED2-1
LED2-2
VDDIO
GNDD
LED3-0
101
100
99
98
97
LED2-0
102
103
GNDA
LED1-0
MDIXDIS
TEST2
GNDA
IN_PWR_SEL
LDO_O
NC
X2
X1
NC
SCANEN
TESTEN
VDDC
GNDD
RST_N
PS0
PS1
SPIS_N
SPID/SDA
SPIC/SCL
SPIQ
MDIO
MDC
LED1-1
LED1-2104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VDDAR
RXP1
RXM1
GNDA
TXP1
TXM1
VDDAT
RXP2
RXM2
RXM3
TXP3
RXP4
TXM4
VDDAR
RXM5
GNDA
GNDA
TXP2
TXM2
VDDAR
GNDA
ISET
VDDAT
RXP3
GNDA
TXM3
VDDAT
RXM4
GNDA
TXP4
GNDA
RXP5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
LED5-0
Figure 5. KSZ8895MQ/RQ/FMQ 128-Pin PQFP Pins Configuration
March 12, 2014 15 Revision 1.7
Micrel, Inc.
Pin Description
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
1 MDI-XDIS IPD 1 − 5 Disable auto MDI/MDI-X.
PD (default) = normal operation.
PU = disable auto MDI/MDI-X on all ports.
2 GNDA GND Analog ground.
3 VDDAR P 1.2V analog VDD.
4 RXP1 I 1 Physical receive signal + ( differential).
5 RXM1 I 1 Physical receiv e sig nal - (differential).
6 GNDA GND Analog ground.
7 TXP1 O 1 Physical tr ansmit signal + (differential).
8 TXM1 O 1 Physical transmit signal - (differential).
9 VDDAT P 3.3V analog VDD.
10 RXP2 I 2 Physical receive s ignal + (di fferential).
11 RXM2 I 2 Physical receive signal - (differential).
12 GNDA GND Analog ground.
13 TXP2 O 2 Physical transmit signal + (differential).
14 TXM2 O 2 Physical transmit signal - (differential).
15 VDDAR P 1.2V analog VDD.
16 GNDA GND Analog ground.
17 ISET
Set physical transmit output current. Pull-down with a
12.4kΩ1% resistor.
18 VDDAT P 3.3V analog VDD.
19 RXP3 I 3 Physical receive s ignal + (di fferential).
20 RXM3 I 3 Physical receive signal - (differential).
21 GNDA GND Analog ground.
22 TXP3 O 3 Physical transmit signal + (differential).
23 TXM3 O 3 Physical transmit signal – (differential).
24 VDDAT P 3.3V analog VDD.
25 RXP4 I 4 Physical receive s ignal + (di fferential).
26 RXM4 I 4 Physical receive signal - (differential).
27 GNDA GND Analog ground.
28 TXP4 O 4 Physical transmit sig nal + (differential).
29 TXM4 O 4 Physical transmit signal - (differential).
30 GNDA GND Analog ground.
31 VDDAR P 1.2V analog VDD.
32 RXP5 I 5 Physical receive s ignal + (di fferential).
33 RXM5 I 5 Physical receive signal - (differential).
34 GNDA GND Analog ground.
35 TXP5 O 5 Physical transmit signal + (differential).
36 TXM5 O 5 Physical transmit signal - (differential).
37 VDDAT P 3.3V analog VDD.
38 FXSD3 IPD 3
FMQ: Fiber signal detect pin for Port 3.
MQ/RQ: no connection.
March 12, 2014 16 Revision 1.7
Micrel, Inc.
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
39 FXSD4 IPD 4
FMQ: Fiber signal detect pin for Port 4.
MQ/RQ: no connection.
40 NC NC No connect.
41 NC NC No connect.
42 NC NC No connect.
43 NC NC No connect.
44 NC NC No connect.
45 NC NC No connect.
46 NC NC No connect.
47 PWRDN_N IPU Full-chip power down. Active low.
48 INTR_N OPU Interrupt. This pin is Open-D ra in out put pin .
49 GNDD GND Digital ground.
50 VDDC P 1.2V digital core VDD.
51 PMTXEN IPD
5 PHY[5] MII/RMII transmit enable.
52 PMTXD3 IPD 5
MQ/FMQ: PHY[5] MII transmit bit 3.
RQ: no connection for RMII.
53 PMTXD2 IPD 5
MQ/FMQ: PHY[5] MII transmit bit 2.
RQ: no connection for RMII.
54 PMTXD1 IPD
5 PHY[5] MII/RMII transmit bit 1.
55 PMTXD0 IPD
5 PHY[5] MII/RMII transmit bit 0.
56 PMTXER IPD
5 MQ/FMQ: PHY[5] MII transmit error. RQ: no connection for RMII.
57 PMTXC/PMREFCLK I/O 5
MQ/FMQ: Output PHY[5] MII transmit clock
RQ: Input PHY[5] RMII reference clock, 50M H z ±50ppm, the
50MHz clock comes from PMRXC Pin 60.
58 GNDD GND Digital ground.
59 VDDIO P 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
60 PMRXC I/O 5
MQ/FMQ: Output PH Y [5] MII receive clock.
RQ: Output PHY[5] RMII reference clock, this clock is used when
opposite doesn’t provide RMII 50MHz clock or the system doesn’t
provide an external 50MHz clock for the P5-RMII interface.
61 PMRXDV/PMCRSDV IPD/O 5 MQ/FMQ: PMRXDV is for PHY[5] MII receive data valid.
RQ: PMCRSDV is for PHY[5] RMII Carrier Sense/Receive Data
Valid Output.
62 PMRXD3 IPD/O 5
MQ/FMQ: PHY[5] MII receive bit 3.
RQ: no connection for RMII.
Strap option:
PD (default) = enable flow control.
PU = disable flow control.
63 PMRXD2 IPD/O 5
MQ/FMQ: PHY[5] MII receive bit 2.
RQ: no connection for RMII.
Strap option:
PD (default) = disable back pressure.
PU = enable back pressure.
March 12, 2014 17 Revision 1.7
Micrel, Inc.
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
64 PMRXD1 IPD/O 5
PHY[5] MII/RMII receive bit 1.
Strap option:
PD (default) = drop excessive coll is ion pa cket s.
PU = does not drop excess iv e coll is ion pa cket s.
65 PMRXD0 IPD/O 5
PHY[5] MII/RMII receive bit 0.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex
mode.
PU = enable for performance enhancement.
66 PMRXER IPD/O 5
MQ/FMQ:PHY[5] MII receive error
RQ: no connection for RMII
Strap option:
PD (default) = packet size 1518/1522 bytes.
PU = 1536 bytes.
67 PCRS IPD/O 5
MQ/FMQ: PHY[5] MII carrier sense.
RQ: no connection for RMII.
Strap option for port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or
fails.
PU = force full-duplex if auto negotiation is disabled or fails. Refer
to Register 76.
68 PCOL IPD/O 5
MQ/FMQ: PHY[5] MII collision detect.
RQ: no connection.
Strap option for port 4 only .
PD (default) = no force flow control, normal operation.
PU = force flow control. Refer to Register 66.
69 SMTXEN IPD Port 5 Switch MII/RMII transmit enable.
70 SMTXD3 IPD
MQ/FMQ: Port 5 Switch MII transmit bit 3.
RQ: no connection for RMII.
71 SMTXD2 IPD
MQ/FMQ: Port 5 Switch MII transmit bit 2.
RQ: no connection for RMII.
72 SMTXD1 IPD Port 5 Switch MII/RMII transmit bit 1.
73 SMTXD0 IPD Port 5 Switch MII/RMII transmit bit 0.
74 SMTXER IPD
MQ/FMQ: Port 5 Switch MII transmit error.
RQ: no connection for RMII.
75 SMTXC/SMREFCLK
I/O
MQ/FMQ: Port 5 Switch MII transmit clock,
Input: SW5-MII MAC mode, Output: SW5-MII PHY modes.
RQ: Input SW5-RMII 50MHz +/-50ppm refer en ce cl oc k. The
50MHz clock comes from SMRXC Pin 78 when the device is the
clock mode which the device’s clock comes from 25MHz
crystal/oscillator from pins X1/X2. Or the 50MHz clock comes
from external 50MHz clock source when the device is the normal
mode which the device’s clock source comes from SMTXC pin
not from X1/X2 pins.
76 GNDD GND Digital ground.
77 VDDIO P 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
March 12, 2014 18 Revision 1.7
Micrel, Inc.
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
78 SMRXC I/O
MQ/FMQ: Port 5 Switch MII receive clock,
Input: SW5-MII MAC mode, Output: SW5-MII PHY mode.
RQ: Output SW5-RMII 50MHz clock, this clock is used when
opposite doesn’t provide RMII reference clock or the system
doesn’t provide an external 50MHz clock for the RMII interface.
79 SMRXDV/SMCRSDV IPD/O
MQ/FMQ: SMR XDV is fo r Switch MA C 5 MII receive data valid.
RQ: SMCRSDV is for MAC5 RMII Carrier Sense/Receive Data
Valid Output.
80 SMRXD3 IPD/O
MQ/FMQ: Port 5 Switch MII receive bit 3.
RQ: no connection for RMII
Strap option:
PD (default) = Disable Switch SW5-MII full-duplex flow control
PU = Enable Switch SW5-MII full-duplex flow control.
81 SMRXD2 IPD/O
MQ/FMQ: Port 5 Switch MII receive bit 2.
RQ: no connection for RMII
Strap option:
PD (default) = Switch SW5-MII in full-duplex mode;
PU = Switch SW5-MII in half-duplex mode.
82 SMRXD1 IPD/O
Port 5 Switch MII/RMII receive bit 1.
Strap option:
PD (default) = Port 5 Switch SW5-MII in 100Mbps mode.
PU = Switch SW5-MII in 10Mbps mode.
83 SMRXD0 IPD/O
Port 5 Switch MII/RMII receive bit 0.
Strap option:
LED mode
PD (default) = mode 0; PU = mode 1. See “Register 11.”
Mode 0, link at:
100/Full LEDx[2,1,0] = 0, 0, 0
100/Half LEDx[2,1,0] = 0, 1, 0
10/Full LEDx[2,1,0] = 0, 0, 1
10/Half LEDx[2,1,0] = 0, 1, 1
Mode 1, link at:
100/Full LEDx[2,1,0] = 0, 1, 0
100/Half LEDx[2,1,0] = 0, 1, 1
10/Full LEDx[2,1,0] = 1, 0, 0
10/Half LEDx[2,1,0] = 1, 0, 1
Mode 0
Mode 1
LEDX_2
Lnk/Act
100Lnk/Act
LEDX_1
Fulld/Col
10Lnk/Act
LEDX_0
Speed
Full duplex
84 SCOL IPD/O
MQ/FMQ: Port 5 Switch MII collision detect,
Input: SW5-MII MAC modes, Output: SW5-MII PHY modes.
RQ: no connection for RMII
85 SCRS IPD/O
MQ/FMQ: Port 5 Switch MII modes carrier sen se,
Input: SW5-MII MAC modes, Output: SW5-MII PHY modes.
RQ: no connection for RMII
March 12, 2014 19 Revision 1.7
Micrel, Inc.
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
86 SCONF1 IPD
Pins 91, 86, and 87 are dual MII/RMII configuration pins for the
Port 5 MAC5 MII/RMII and PHY[5] MII/RMII. SW5-MII supports
both MAC mode and PHY modes. P5-MII supports PHY mode
only. See pin s conf igur atio n below.
Pin# (91, 86, 87) Port 5 Switch
MAC5 SW5-
MII/RMII
Port5 PHY5
P5- MII/RMII
000 Disable , Otri Disable, O tri
001
PHY Mode MII, or
RMII
Disable, Ot ri
010
MAC Mode MII, or
RMII
Disable, Otri
011 PHY Mode SNI Disable, Otri
100 Disable (default) Disable (default)
101
PHY Mode MII or
RMII
P5-MII/RMII
110
MAC Mode MII or
RMII
P5-MII/RMII
111 PHY Mode SNI P5-MII/RMII
87 SCONF0 IPD Dual MII/RMII configuration pi n. See pin 86 des crip tio ns.
88 GNDD GND Digital ground.
89 VDDC P 1.2V digital core VDD.
90 LED5-2 IPU/O 5
LED indicator 2.
Strap option:
Aging setup. See “Aging” se cti on.
PU (default) = aging enable
PD = aging disable.
91 LED5-1 IPU/O 5
LED indicator 1.
Strap option:
PU (default): enable PHY[5] MII I/F.
PD: tristate all PHY[5] MII output. See “Pin 86 SCONF1.”
92 LED5-0 IPU/O 5
LED indicator 0.
Strap option for port 4 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negatiation. Strap to register76 bit[7].
93 LED4-2 IPU/O 4 LED indicator 2.
94 LED4-1 IPU/O 4 LED indicator 1.
95 LED4-0 IPU/O 4
LED indicator 0.
Strap option:
PU (default) = Normal mode.
PD = Energy Detection mode (EDPD mode)
Strap to register 14 bits[4:3]
96 LED3-2 IPU/O 3 LED indicator 2.
97 LED3-1 IPU/O 3 LED indicator 1.
98 LED3-0 IPU/O 3
LED indicator 0.
Strap option:
PU (default) = Select I/O drive strength (8mA);
PD = Select I/O drive strength (12mA).
Strap to register 132 bit[7-6].
99 GNDD GND Digital ground.
March 12, 2014 20 Revision 1.7
Micrel, Inc.
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
100 VDDIO P 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
101 LED2-2 IPU/O 2
LED indicator 2.
Strap option for RQ only:
PU (default) = Select the device as clock mode in SW5- RMII,
25MHz crystal/oscillator to X1/X2 pins of the device and pins of
SMRXC and PMRXC output 50MHz clock.
PD = Select the device as normal mode in SW5-RMII. Switch
MAC5 used only. The input clock from X1/X2 pins is not used, the
device’s clock source comes from SMTXC/SMREFCLK pin which
the 50MHz reference clock comes from external 50MHz clock
source, PMRXC can output 50MHz clock for P5-RMII interface in
the normal mode.
102 LED2-1 IPU/O 2
LED indicator 1.
Strap option: for Port 3 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negatiation. Strap to register60 bit[7].
103 LED2-0 IPU/O 2 LED indicator 0.
104 LED1-2 IPU/O 1 LED indicator 2.
105 LED1-1 IPU/O 1
LED indicator 1.
Strap option: for port 3 only.
PU (default) = no force flow control, normal operation.
PD = force flow control. Strap to register60 bit[4].
106 LED1-0 IPU/O 1
LED indicator 0.
Strap option for port 3 only.
PU (default) = force half-duplex if auto-negotiation is disabled or
fails.
PD = force full-duplex if auto negotiation is disabled or fails.
Strap to register60 bit[5].
107 MDC IPU All
Switch or PHY[5] MII management (MIIM registers) data clock. Or
SMI interface clock
108 MDIO IPU/O All
Switch or PHY[5] MII management (MIIM registers) data I/O. Or
SMI interface data I/O.
Features internal pull down to define pin state when not driven.
Note: Need an external pull-up when driven.
109 SPIQ IPU/O All SPI serial data output in SPI slav e mode.
Note: Need an external pull-up when driven.
110 SPIC/SCL IPU/O All (1) Input clock up to 25MHz in SPI slave mode,
(2) output clock at 61kHz in I2C master mode. See “Pin 113.”
Note: Need an external pull-up when driven.
111 SSPID/SDA IPU/O All (1) Serial data input in SPI slave mode;
(2) serial data input/output in I2C master mode. See “Pin 113.”
Note: Need an external pull-up when driven.
112 SPIS_N IPU All
Active low.
(1) SPI data transfer start in SPI slave mode. When SPIS_N is
high, the KSZ8895MQ/RQ/FMQ is deselected and SPIQ is held in
high impedanc e state, a high-to-low transition to initiate the SPI
data transfer.
(2) not used in I2C master mod e.
March 12, 2014 21 Revision 1.7
Micrel, Inc.
Pin Description (Continued)
Pin Number Pin Name Type
(1)
Port Pin Function
(2)
113 PS1 IPD
Serial bus confi gurat ion pin .
For this case, if the EEPROM is not present, the
KSZ8895MQ/RQ/FMQ will start itself with the PS[1.0] = 00 default
register values.
Pin Configuration Serial Bus Configuration
PS[1.0] = 00 I
2
C Master Mode for EEPROM
PS[1.0] = 01 SMI Interface Mode
PS[1.0] = 10 SPI Slave Mode for CPU Interface
PS[1.0] = 11 Factory Test Mode (BIST)
114 PS0 IPD Serial bus configuration pin. See “Pin 113.”
115 RST_N IPU Reset the KSZ8895MQ/RQ/FMQ device. Active low.
116 GNDD GND Digital ground.
117 VDDC P 1.2V digital core VDD.
118 TESTEN IPD NC for normal operation. Factory test pin.
119 SCANEN IPD NC for normal operation. Factory test pin.
120 NC NC No connect.
121 X1 I
25MHz crystal clo ck con ne ctio n/or 3. 3V Oscillator input.
Crystal/Oscillator should be ±50ppm tolerance.
122 X2 O 25MHz cryst al cl o ck conne cti o n.
123 NC NC No connect.
124 NC NC No connect.
125 LDO_O P
When pin126 is pull-up, the I nt ernal 1.2V LDO controller is
enabled and creat es a 1.2V output when using an external FET.
When pin126 is pull-down, the pin 125 is tristat ed .
Note: Use a 200Ω (approximately) resistor between t he source
and drain pins on the FE T if 3.3V power rail ex hibits a slow ramp
(>5ms) when using this internal 1.2V LDO controller. You can also
use an external 1.2V LDO when 3.3V power ramp time is slow.
126 IN_PWR_SEL I
Pull-up to enable LDO_O of pin 125. Pull-down to disable LDO_0.
Note: A 4.3K pull-up and a 1K pull-down resistor divider is
recommended if using the internal 1.2V LDO controller plus an
external MOSFET for 1.2V power.
127 GNDA GND Analog ground.
128 TEST2 NC NC for normal operation. Factory test pin.
Notes:
1. P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
GND = Ground.
IPU = Input w/internal pull-up.
IPD = Input w/internal pul l -down.
IPD/O = Input w/internal pull -down during reset, output
pin otherwise.
IPU/O = Input w/internal pull -up during reset, out put pin
otherwise.
NC = No connect.
2. PU = Strap pin pull-up.
PD = Strap pull-down.
OTRI = Output tristated.
March 12, 2014 22 Revision 1.7
Micrel, Inc.
Pin for Strap-In Options
The KSZ8895MQ/RQ/FMQ can function as a managed switch or an unmanaged switch. If no EEPROM or micro-
controller exists, then the KSZ8895MQ/RQ/FMQ will oper ate from its default s etting. The strap-in o ption pins c an be
configured by external pull-up/down resistors and take effect after power down reset or warm reset. The functions are
described in the following table.
Pin # Pin Name PU/PD
(1)
Description
(1)
1 MDI-XDIS IPD
Disable auto MDI/MDI-X.
Strap option:
PD = (default) = normal operation.
PU = disable auto MDI/MDI-X on all ports.
62 PMRXD3 IPD/O
PHY[5] MII receive bit 3.
Strap option:
PD (default) = enable flow control;
PU = disable flow control.
63 PMRXD2 IPD/O
PHY[5] MII receive bit 2.
Strap option:
PD (default) = disable back pressure;
PU = enable back pressure.
64 PMRXD1 IPD/O
PHY[5] MII receive bit 1.
Strap option:
PD (default) = drop ex cessiv e collis ion pa cket s;
PU = does not drop excess iv e coll is ion pa cket s.
65 PMRXD0 IPD/O
PHY[5] MII receive bit 0.
Strap option:
PD (default) = disable aggressive back-off algorit hm in half-duplex mode;
PU = enable for performance enhancement.
66 PMRXER IPD/O
PHY[5] MII receive error.
Strap option:
PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
67 PCRS IPD/O
PHY[5] MII carrier sense
Strap option for Port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or fails.
PU = force full-duplex if auto-negotiation is disabled or fails. Refer to register 76.
68 PCOL IPD/O
PHY[5] MII collision detect
Strap option for Port 4 only.
PD (default) = no force flow control.
PU = force flow control. Refer to register 66.
80 SMRXD3 IPD/O
Switch MII receive bit 3.
Strap option:
PD (default) = disable switch SW5-MII full-duplex flow control;
PU = enable switch SW5-MII full-duplex flow control.
81 SMRXD2 IPD/O
Switch MII receive bit 2.
Strap option:
PD (default) = switch SW5-MII in full-duplex mode;
PU = switch SW5-MII in half-duplex mode.
82 SMRXD1 IPD/O
Switch MII receive bit 1.
Strap option:
PD (default) = switch SW5-MII in 100Mbps mode.
PU = switch MII in 10Mbps mode.
March 12, 2014 23 Revision 1.7
Micrel, Inc.
Pin for Strap-In Options (Continued)
Pin # Pin Name PU/PD
(1)
Description
(1)
83 SMRXD0 IPD/O
Switch MII receive bit 0.
Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register
11.”
Mode 0 Mode 1
LEDX_2 Lnk/Act 100Lnk/Act
LEDX_1 Fulld/Col 10Lnk/Act
LEDX_0 Speed Fulld
86 SCONF1 IPD
Pin 91,86,87 are dual MII/RMII configuration pins for the Port 5 MAC 5 MII/RMII
and PHY[5] MII/RMII. SW5-MII supports both MAC mode and PHY modes. P5-
MII supports PHY mode only. See pins configuration below.
Pins [91, 86, 87]
Port 5 MAC 5 Switch
SW5-MII
Port 5 PHY [5]
MII/RMII P5-MII/RMII
000 Disable, Otri Disable, Otri
001 PHY Mode MII or RMII Disable, Otri
010 MAC Mode MII or RMII Disable, Otri
011 PHY Mode SNI Disable, Otri
100 Disable Disable
101 PHY Mode MII or RMII P5- MII/RMII
110 MAC Mode MII or RMII P5- MII/RMII
111 PHY Mode SNI P5- MII/RMII
87 SCONF0 IPD Dual MII/RMII configuration pin. See pin 86 description.
90 LED5-2 IPU/O
LED5 indicator 2.
Strap option: Aging setup. See “Aging” section
PU (default) = aging enable;
PD = aging disable.
91 LED5-1 IPU/O
LED5 indicator 1.
Strap option:
PU (default): enable PHY[5] MII I/F.
PD: tristate all PHY[5] MII output. See “Pin 86 SCONF1.”
92 LED5-0 IPU/O
LED5 indicator 0.
Strap option for Port 4 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negatiation. Strap to register76 bit[7].
95 LED4-0 IPU/O
LED indicator 0.
Strap option:
PU (default) = Normal mode.
PD = Energy Detection mode (EDPD mode).
Strap to register 14 bits[4: 3] .
98 LED3-0 IPU/O
LED3 indicator 0.
Strap option:
PU (default) = Select I/O current drive stren gth (8mA);
PD = Select I/O current drive strength (12mA).
Strap to register 132 bit[7:6].
March 12, 2014 24 Revision 1.7
Micrel, Inc.
Pin for Strap-In Options (Continued)
Pin # Pin Name PU/PD
(1)
Description
(1)
101 LED2-2 IPU/O
LED2 indicator 2.
Strap option for KSZ8895RQ only:
PU (default) = Select the device as clock mode in RQ SW5- RMII, 25MHz
crystal to X1/X 2 pins of the device and REFCLK output 50MHz clock.
PD = Select the device as normal mode in SW5-RMII. Switch MAC5 used only.
The input clock is useless from X1/X2 pin, the device’s clock comes from
SMTXC/SMREFCLK pin, 50MHz reference clock from external 50MHz clock
source.
102 LED2-1 IPU/O
LED2 indicator 1.
Strap option for Port 3 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negatiation.
Strap to register60 bit[7].
105 LED1-1 IPU/O
LED1 indicator 1.
Strap option for Por t 3 only.
PU (default) = no force flow control, normal operation.
PD = force flow control. Strap to register50 bit[4].
106 LED1-0 IPU/O
LED1 indicator 0.
Strap option for Port 3 only.
PU (default) = force half-duplex if auto-negotiation is disabled or fails.
PD = force full-duplex if auto negotiation is disabled or fails.
Strap to register60 bit[5].
113 PS1 IPD
Serial bus configuration pin. For this case, if the EEPROM is not present, the
KSZ8895MQ/RQ/FMQ will start itself with the PS[1:0] = 00 default register
values .
Pin Configuration Serial Bus Configuration
PS[1:0] = 00 I
2
C Master Mode for EEPROM
PS[1:0] = 01 SMI Interface Mode
PS[1:0] = 10 SPI Slave Mode for CPU Interface
PS[1:0] = 11 Factory Test Mode (BIST)
114 PS0 IPD Serial bus configuration pin. See “Pin 113.”
128 TEST2 NC NC for normal operation. Factory test pin.
Note:
1. NC = No connect.
IPD = Input w/internal pul l -down.
IPD/O = Input w/internal pull -down during reset, output pin otherwise.
IPU/O = Input w/internal pull-up during reset, output pin otherwise.
March 12, 2014 25 Revision 1.7
Micrel, Inc.
Introduction
The KSZ8895MQ/RQ/FMQ contains five 10/100 physical layer transceivers and five media access control (MAC)
units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-port
integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this
mode, access to the fifth MAC is provided through a media independent interface (MII/RMII). This is useful for
implementing an integrated broadband router. The third mode uses the dual MII/RMII feature to recover the use of
the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed
through the P5-MII/RMII po r t.
The KSZ8895MQ/RQ/FMQ has the f lexibilit y to reside in a managed or unmanag ed design. In a m anaged design, a
host processor has complete control of the KSZ8895MQ/RQ/FMQ via the SPI bus, or the MDC/MDIO interface. An
unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time.
On the media side, the KSZ8895MQ/RQ/FMQ supports IEEE 802.3 10BASE-T, 100BASE-TX on all copper ports
with Auto MDI/MDIX. The KSZ8895FMQ supports 100BASE-FX on port 3 and port 4. The KSZ8895MQ/RQ/FMQ can
be used as a f ully manage d five-port s witch or hook ed up to a mic roprocessor by i ts SW -MII/RMII interf aces for an y
application solutions.
Physical sig na l tr a ns mission and rec e pti on ar e en hanced thr oug h t he us e of pat e nted anal og c ir cuitry that mak es the
design more efficient and allows for reduced power consumption and smaller chip die size.
Major enhancements from the KS8895MA/FQ to the KSZ8895MQ/RQ/FMQ include more host interface options, a
dual-switch MAC5 MII and PHY5 MII interfaces with other options, RMII from part of the KSZ8895RQ, tag and port-
based V LAN, r apid spanni ng tr ee s upport, IGM P sn oopin g suppor t, por t m irr oring s upport , m ore f lex ible r at e lim iting,
and new filtering functionality.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts
the MII dat a f r om the MAC into a 12 5MH z s eri al b it s tr eam. The data a nd c on tr ol str eam is then c onvert ed i n to 4B /5B
coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then
transmitted in MLT3 current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1
transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding
amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the
100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The
receiving side starts with the equalization filter to compensate for intersymbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to
adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial
estimation based on comparisons of incom ing signal strength against som e known cable characteristics, then tunes
itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as
temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is
used to compensate for the effect of baseline wander and improve the dynamic range. The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The c lock rec overy circuit e xtr acts the 125M H z clock from the edges of the NRZI s ignal. T his rec overed c loc k is then
used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by
the 4B/5B decoder. Finally, the NRZ serial data is con verted to the MII form at and provided as the input data to the
MAC.
March 12, 2014 26 Revision 1.7
Micrel, Inc.
PLL Clock Synthesizer
The KSZ8895MQ/RQ/FMQ generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing.
Internal clocks are generated from an external 25MHz crystal or oscillator.
Scrambler/Descrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline
wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can
generate a 2047-bit non-repetitive sequence. The receiver will then descramble the incoming data stream with the
same sequence at the transmitter.
100BASE-FX Operation
100BASE-FX operation is very similar to 100BASE-TX operation except that the scrambler/descrambler and MLT3
encoder/ decoder are b ypas s ed on tr ansmiss ion and re c eptio n. In th is mode, the auto-negotiat ion f eature is bypassed
since there is no standard that supports fiber auto-negotiation.
100BASE-FX Signal Detection
The physical port runs in 100BASE-FX fiber mode for the Port 3 and Port 4 of the KSZ8895FMQ. This signal is
internally referenced to 1.2V. The fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is
above this 1.2V reference, indicating signa l detect, and FXSDx ‘L’ is below the 1.2V reference to indicate no signal.
There is no aut o-negoti atio n for 100BAS E-FX m ode, t he ports m ust be f orced t o eith er full or half -dup lex for the fiber
ports. Note that strap-in options support Port 3 and Port 4 to disable auto-negotiation, force 100Base-FX speed, force
duplex mode, and force flow control for KSZ8895FMQ with unmanaged mode.
100BASE-FX Far End Fault
Far end fault occ urs when the sign al detection is log ically false fr om the r eceive fiber module. W hen this occurs, t he
transmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between
frames.
10BASE-T Transmit
The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same
magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The
harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encode d s igna l.
10BASE-T Receive
On the recei ve side, in put buf f er and level detect ing s quelch circ uits ar e em ployed. A diff erentia l input rec eiver circuit
and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and
NRZ data. A s quelch circ uit rejects s ignals with levels less than 400m V or with short pul sewidths in ord er to prevent
noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the
PLL locks onto the incoming signal and the KSZ8895MQ/RQ/FMQ decodes a data frame. The receiver clock is
maintained active during idle periods in between data reception.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8895MQ/RQ/FMQ supports HP Auto MDI/MDI-X
and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the
KSZ8895MQ/RQ/FMQ device. This feature is extremely useful when end users are unaw are of cable types, and also, saves on
an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers, or
MIIM PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are:
March 12, 2014 27 Revision 1.7
Micrel, Inc.
MDI MDI-X
RJ-45 Pins Signals RJ-45 Pins Signals
1 TD+ 1 RD+
2 TD- 2 RD-
3 RD+ 3 TD+
6 RD- 6 TD-
Table 1. MDI/MDI-X Pin Definitions
Straight Cable
A straight c able connects an MDI device t o an MDI-X device, or an M DI-X devic e to an MDI dev ice. Figure 6 depicts
a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
Figure 6. Typical Straight Cable Connection
March 12, 2014 28 Revision 1.7
Micrel, Inc.
Crossover C able
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 7 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 7. Typical Crossover Cable Connection
Auto-Negotiation
The KSZ8895MQ/RQ/FMQ conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-
negotiation allows unshield ed twisted pair (UT P) link par tners to select th e highest com mon mode of oper ation. Link
partners advertise their capabilities to each other, and then compare their own capabilities with those they received
from their link partner s. The highes t speed and duplex setting that is comm on to the two link partner s is selected as
the mode of operation. Auto-negotiation is supported for the copper ports only.
The following list shows the speed and duplex operation mode from highest to lowest.
• Highest: 100Base-TX, full-duplex
• High: 100Base-TX, half-duplex
• Low: 10Base-T, full-duplex
• Lowest: 10Bas e-T, half-duplex
If auto-negotiation is not supported or the KSZ8895MQ/RQ/FMQ link partner is forced to bypass auto-negotiation, the
KSZ8895MQ/RQ/FMQ sets its operating mode by observing the signal at its receiver. This is known as parallel
detection, and allows the KSZ8895MQ/RQ/FMQ to establish link by listening for a fixed signal protocol in the
absence of auto-negotiation advertisement protocol. The auto-negotiation link up process is shown in F igur e 8.
March 12, 2014 29 Revision 1.7
Micrel, Inc.
Figure 8. Auto-Negotiation
March 12, 2014 30 Revision 1.7
Micrel, Inc.
On-Chip Termination Resistors
The KSZ8895MQ/RQ/FMQ reduces the board cost and simplifies the board layout by using on-chip termination
resistors for all ports and RX/TX differential pairs without the external termination resistors. The combination of the
on-chip term ination an d inter nal biasing wi ll save about 50 0 to 1000m w in po wer consum ption as compared to using
external b iasing and termination resistors, and the transformer will not consume power any more. The center tap of
the trans former does not need to be t ied to the ana log power and d oes not tie the center taps togeth er between RX
and TX pairs for its application.
Internal 1.2V LDO Controller
The KSZ8895MQ/RQ/FMQ reduces board cost and simplifies board layout by integrating an internal 1.2V LDO
controller to drive a low cost MOSFET to supply the 1.2V core power voltage for a single 3.3V power supply solution.
The internal 1.2V LDO controller can be disabled by pin 126 IN_PWR_SEL pull-down in order to use an external
1.2V LDO.
Functional Overview: Power Management
The KSZ8895MQ/RQ/FMQ supports a full chip hardware power down m ode. When the PWRDN pin 47 is internally
activated low (pin PWRDN = 0), the entire chip is powered down. If this pin is de-asserted, the chip will be reset
internally.
The KSZ8895MQ/RQ/FMQ can also use multiple power levels of 3.3V, 2.5V or 1.8V for VDDIO to support different
I/O voltage.
The KSZ8895MQ/RQ/FMQ supports enhanced power management in a low power state, with energy detection to
ensure low power dissipation during device idle periods. There are five operation modes under the power
management function which are controlled by the Register 14 bit[4:3] and the Port Register Control 13 bit 3 as shown
below:
Register 14 bit [4:3] = 00 Normal Operation Mode
Register 14 bit [4:3] = 01 Energy Detect Mode
Register 14 bit [4:3] = 10 Soft Power Down Mode
Register 14 bit [4:3] = 11 Power Saving Mode
The Port R e gister 29, 45, 61, 77, 93 Control 13 bit 3 = 1 are for the Port Based Power-Down Mode.
Table 2 indicates all internal function blocks’ status under four different power management operation modes.
KSZ8895MQ/RQ/FMQ
Function Blocks Power Management Operation Modes
Normal M ode Power Saving Mode Energy Detect Mode Soft Power Down Mode
Internal PLL Clock Enabled Enabled Disabled Disabled
Tx/Rx PHY Enabled Rx unused block disabled Energy detect at Rx Disabled
MAC Enabled Enabled Disabled Disabled
Host Interface Enabled Enabled Disabled Disabled
Table 2. Internal Function Block Status
Normal Operation Mode
This is the default setting bit [4:3] = 00 in register 14 after chip power-up or hardware reset. When
KSZ8895MQ/RQ/FMQ is in normal oper ation mode, a ll PLL cloc ks are runn ing, PH Y and M AC are on, and t he host
interface wil l be ready for CPU read or write.
During normal operation mode, the host CPU can set the bit [4:3] in register 14 to change the current normal
operation mode to any one of the other three power management operation modes.
March 12, 2014 31 Revision 1.7
Micrel, Inc.
Energy De tect Mode
Energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8895MQ/RQ/FMQ port is not connected to an active link partner. In th is mode, the de vice will sav e more power
when the cables are unplugged. If the ca bl e is not plugged in, the d ev ice c an autom aticall y enter a lo w po w er s tate—
the energy detect mode. In this mode, the device will keep transmitting 120ns width pulses at 1 pulse/s rate. Once
activit y resumes due to plugging a c ab le in or att empting b y the f ar en d to es ta bl i sh li nk, the dev ice c an aut o maticall y
power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
device reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The
energy detect mode is entered by setting bit [4:3] = 01 in register 14. When the KSZ8895MQ/RQ/FMQ is in this
mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than the pre-configured
value at bit [7:0] Go-Sleep time in register 15, KSZ8895MQ/RQ/FMQ will go into low power state. When
KSZ8895MQ/RQ/FMQ is in low power state, it will keep monitoring the cable energy. Once the energy is detected
from the cable, the device will enter normal power state. When the device is at normal power state, it is able to
transmit or receive packet from the cable.
Soft Power Down Mode
The sof t power down m ode is entered by setting bit [4:3] = 10 in register 14. W hen KSZ8895MQ/RQ/FMQ is in this
mode, all PLL clock s are disabled, als o all of PH Ys and the MACs are off . Any du mm y host access will wake-up this
device from current soft power down mode to normal operation mode and internal reset will be issued to make all
internal registers go to the default values.
Power Saving Mode
The po wer saving m ode is enter e d when a uto-n egotiat ion mode is ena ble d, the cable is d is conn ec ted, and by sett ing
bit[4:3] = 11 in register 14. W hen KSZ8895MQ/RQ/FMQ is in this mode, all PLL clocks are enabled, MAC is on, all
internal register values will not change, a nd the host interface is r eady for CPU r ead or writ e. In this m ode, it mainl y
controls the PHY tr anscei ver on or off , based on line status to ach ieve po wer sav ing. T he PHY co ntinues to t rans m it,
only turning off the unused receiver block. Once activity resumes, due to plugging a cable or attempting by the far
end to establish link, the KSZ8895MQ/RQ/FMQ c a n a utomaticall y enab le the PHY to power up to normal power state
from power saving mode.
During po wer sa ving m ode, the hos t CPU can s et bi t [ 4:3] in register 14 to change the curr ent po wer sav ing m ode to
any one of the other three power management operation modes.
Port-based Power Down Mode
In addition, t he KSZ8895MQ/RQ/FMQ f eatures a per-port pow er down mode. T o save power, a PH Y port that is not
in use can be powered down via the port registers control 13 bit 3, or MIIM PHY registers 0 bit 11.
March 12, 2014 32 Revision 1.7
Micrel, Inc.
Functional Overview: Switch Core
Address Look-Up
The internal look -up table stores MAC addresses and their associated information. It contains a 1K unicast address
table plus switching information. The KSZ8895MQ/RQ/FMQ is guaranteed to learn 1K addresses and distinguishes
itself from a hash-based look-up table, which, depending on the operating environment and probabilities, may not
guarantee the absolute number of addresses it can learn.
Learning
The internal look-up engine updates its table with a new entry if the following conditions are met:
• The received packet’s source address (SA) does not exist in the look-up table.
• The received packet is good; the packet has no receiving errors and is of legal length.
The look -up engine inser ts the qua lified S A into the ta ble, along with t he port nu mber and tim e stamp. If the table is
full, the last entry of the table is deleted first to make room for the new entry.
Migration
The int ernal look-up engine also m onitor s whether a st ation is m oved. If t his occur s, it up dates the table acc ording l y.
Migration happens when the following conditions are met:
• The received packet’s SA is in the table but the associated source port information is different.
• The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine will update the existing record in the table with the new source port information.
Aging
The look -up e ngine will u pdate the t im e stam p inf ormatio n of a recor d whenever t he corres pond ing SA ap pears . T he
time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will
remove the record from the table. The look-up engine constantly performs the aging process and will continuously
remove aging records. The aging period is 300 +/- 75 seconds. This feature can be enabled or disabled through
Register 3 or by external pull-up or pull-down resistors on LED[5][2]. See “Register 3” section.
Forwarding
The KSZ8895MQ/RQ/FMQ will f orwar d pac kets usin g an al gor it hm that is depicte d i n the follo wing flowchart s . Fig ur e
6 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and
dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further
modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to
forward 2” (PTF2), as shown in Figure 7. This is where the packet will be sent.
KSZ8895MQ/RQ/FMQ will not forward the following packets:
• Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors.
• 802.3x pause frames. The KSZ8895MQ/RQ/FMQ will intercept these packets and perform the appropriate
actions.
• “Local” packets. Based on destination address (DA) look-up. If the destination port from the look-up table
matches the port where the packet was from, the packet is defined as “local.”
Switching Engine
The KSZ8895MQ/RQ/FMQ features a high-performance switching engine to move data to and from the MAC’s
packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall
latenc y. The KSZ8895MQ/RQ/FMQ has a 64kB int ernal f rame buf fer. T his resour ce is sh ared be tween al l five p orts.
There are a total of 512 buffers available. Each buffer is sized at 128B.
Media Access Controller (MAC) Operation
The KSZ8895MQ/RQ/FMQ strictly abides by IEEE 802.3 standards to maximize compatibility.
March 12, 2014 33 Revision 1.7
Micrel, Inc.
Inter-Packet Gap (IPG)
If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the
current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN.
Backoff Algorithm
The KSZ8895MQ/RQ/FMQ implements the I EEE Standard 802.3 binary exponential backoff algorithm, and optional
“aggressive mode” backoff. After 16 collisions, the packet will be optionally dropped, depending on the chip
configuration in Register 3. See “Register 3.”
Late Collision
If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped.
Illegal Frames
The KSZ8895MQ/RQ/FMQ discards f rames les s than 64 bytes an d can be progr a m m ed to ac c ept f r ames up to 1 536
bytes in Register 4. For special applications, the KSZ8895MQ/RQ/FMQ can also be programmed to accept frames
up to 1916 bytes in Register 4. Since the KSZ8895MQ/RQ/FMQ supports VLAN tags, the maximum sizing is
adjusted when these tags are present.
Flow Control
The KSZ8895MQ/RQ/FMQ supports standard 802.3x flow control frames on both transmit and receive sides.
On the r eceive si de, if th e KSZ8895MQ/RQ/FMQ r eceives a p ause co ntrol fr ame, the KSZ8895MQ/RQ/FMQ will not
transmit the nex t normal fr ame until the timer, spec if ied in the pause control frame, expir es. I f another paus e f r ame is
received before the current timer expires, the timer will be updated with the new value in the second pause frame.
During this period (being flow controlled), only flow control packets from the KSZ8895MQ/RQ/FMQ will be
transmitted.
On the transmit side, the KSZ8895MQ/RQ/FMQ has intelligent and efficient ways to determine when to invoke flow
control. The flow control is based on availability of the system resources, including available buffers, available
transmit queues and available receive queues.
The KSZ8895MQ/RQ/FMQ flow controls a port that has just received a packet if the destination port resource is
busy. T he KSZ8895MQ/RQ/FMQ issues a f lo w co ntr ol frame ( X OFF) , c ontain in g t he maxim um paus e t ime defined in
IEEE standard 802.3x. Once the resource is freed up, the KSZ8895MQ/RQ/FMQ sends out the other flow control
frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis f eature is
also provided to prevent over-activation and deactivation of the flow control mechanism.
The KSZ8895MQ/RQ/FMQ flow controls all ports if the receive queue becomes full.
March 12, 2014 34 Revision 1.7
Micrel, Inc.
Figure 9. Destination Address Lookup Flow Chart, Stage 1
March 12, 2014 35 Revision 1.7
Micrel, Inc.
Figure 10. Destination Address Resolution Flow Chart, Stage 2
March 12, 2014 36 Revision 1.7
Micrel, Inc.
The KSZ8895MQ/RQ/FMQ will not forward the following packets:
1. Error packets
These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet
errors.
2. IEEE802.3x PAUSE frames
KSZ8895MQ/RQ/FMQ intercepts these packets and performs full duplex flow control accordingly.
3. "Local" packets
Based on destination address (DA) lookup, if the destination port from the lookup table matches the port from
which the packet originated, the packet is defined as "local."
Half-Duplex Back Pressure
The KSZ8895MQ/RQ/FMQ also provides a half-duplex back pressure option (note: this is not in IEEE 802.3
standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back
pressure is required, the KSZ8895MQ/RQ/FMQ sends preambles to defer the other station's transmission (carrier
sense deference). To avoid jabber and excessive deference as defined in IEEE 802.3 standards, after a certain
period of time, the KSZ8895MQ/RQ/FMQ discontinues carrier sense but raises it quickly after it drops packets to
inhibit other transmissions. This short silent time (no carrier sense) is to prevent other stations from sending out
packets and keeps other stations in a carrier sense-deferred state. If the port has packets to send during a back
pressure situation, the carrier sense-type back pressure is interrupted and those packets are transmitted instead. If
there are no more packets to send, carrier sense-type back pressure becomes active again until switch resources
are free. If a collision occurs, the binary exponential backoff algorithm is skipped and carrier sense is generated
immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets.
To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following:
• Aggressive backoff (Register 3, bit 0)
• No excessive collision drop (Register 4, bit 3)
• Back pressure (Register 4, bit 5)
These bits are not set as the default because this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8895MQ/RQ/FMQ has an int elligent opt ion t o protect the switch s ystem from receivin g too man y broadc ast
pack ets. Broadcast packets are norm ally forwarded t o all ports except the s ource por t and thus use t oo m any switch
resourc es (bandwidth an d available spac e in transm it queues). T he KSZ8895MQ/RQ/FMQ has the op tion to include
“multicast packets” for storm control. The broadcast storm rate parameters are programmed globally and can be
enabled or disabl ed on a per port basis. The rate is bas ed on a 5 0ms (0.05s) interval for 100BT an d a 500 ms (0.5s)
interval f or 10BT . At the be ginnin g of eac h inter val, th e counter is c leared to zero and the rate lim it m echanism starts
to count the number of bytes during the interval. The rate definition is described in Registers 6 and 7. The default
setting for Registers 6 and 7 is 0x4A (74 decimal). This is equal to a rate of 1%, calculated as follows:
148,80 frames/sec X 50ms (0.05s)/interval X 1% = 74 frames/interval (approx.) = 0x4A
March 12, 2014 37 Revision 1.7
Micrel, Inc.
MII Interface Operation
The media-independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface
between p hys ica l la yer and MAC la yer devic es . T he KSZ8895MQ/RQ/FMQ provides t wo suc h int erf ac es . The P5-MII
interfac e is us ed to c o nn ec t to t he fifth PH Y, wher e as the SW-MII interfac e is used to connect to th e f if th M A C. E ac h
of these MII interfaces contains two distin c t gr oups of signals, one for transmission and the other for receiving.
Port 5 PHY 5 P5-MII/RMII Interface
The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface
between the physical layer and MAC layer devices. The Reduced Media Independent Interface (RMII) specifies a low
pin count MII. The KSZ8895MQ/RQ/FMQ provides two such interfaces for MAC5 and PHY5. The Port 5 PHY5 P5-
MII/RMII interface is used to connect to the fifth PH Y, where as the SW -MII/RMII interface is used to connect to the
fifth MAC. The KSZ8895MQ/FMQ support P5-MII, the KSZ8895RQ supports P5-RMII. Each of these MII/RMII
interfac es contains t wo distinct grou ps of s ignals, one f or transm ission and the ot her for receiving. T able 3 describes
the signa ls used in the PH Y[5] P5-MII/R MI I interf ac e. The P5-MII interface operates in PHY mode only.
MII
Signal Description KSZ8895MQ/FMQ
P5-MII KSZ8895MQ/FMQ
MII Signal Type KSZ8895RQ
P5-RMII
KSZ8895RQ
RMII Signal
Type
MTXEN Transmit enable PMTXEN I PMTXEN I
MTXER Transmit error PMTXER I
MTXD3 Transmit data bit 3 PMTXD[3] I
MTXD2 Transmit data bit 2 PMTXD[2] I
MTXD1 Transmit data bit 1 PMTXD[1] I PMTXD[1] I
MTXD0 Transmit data bit 0 PMTXD[0] I PMTXD[0] I
MTXC Transmit clock PMTXC O PMREFCLK/PMTXC I
MCOL Collision detection PCOL O
MCRS Carrier sense PCRS O
MRXDV Receive data valid PMRXDV O PMRXDV O
MRXER Receive error PMRXER O PMRXER O
MRXD3 Receive data bit 3 PMRXD[3] O
MRXD2 Receive data bit 2 PMRXD[2] O
MRXD1 Receive data bit 1 PMRXD[1] O PMRXD[1] O
MRXD0 Receive data bit 0 PMRXD[0] O PMRXD[0] O
MRXC Receive clock PMRXC O PMRXC O
Table 3. Port 5 PHY P5-MII/RMII Signals
March 12, 2014 38 Revision 1.7
Micrel, Inc.
Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ
Table 4 shows two connection manners:
1. The first is an external MAC connects to SW5-MII PHY mode.
2. The second is an external PHY connects to SW5-MII MAC mode.
Please see the pin [91, 86, 87] descriptions for configuration details for the MAC mode and PHY mode. SW5-MII
works with 25MHz clock for 100Base-TX, SW5-MII works with 2.5MHz clock for 10Base-T.
KSZ8895MQ/RQ/FMQ PHY Mode Connection KSZ8895MQ/RQ/FMQ MAC Mode Connection
External MA C KSZ8895MQ/RQ/FMQ
SW5-MII Signals Type Description External
PHY KSZ8895MQ/RQ/FMQ
SW5-MII Signals Type
MTXEN SMTXEN Input Transmit enable MTXEN SMRXDV Output
MTXER SMTXER Input
Transmit error MTXER Not used Not used
MTXD3 SMTXD[3] Input
Transmit data bit 3 MTXD3 SMRXD[3] Output
MTXD2 SMTXD[2] Input
Transmit data bit 2 MTXD2 SMRXD[2] Output
MTXD1 SMTXD[1] Input
Transmit data bit 1 MTXD1 SMRXD[1] Output
MTXD0 SMTXD[0] Input
Transmit data bit 0 MTXD0 SMRXD[0] Output
MTXC SMTXC Output T ransmit cl oc k MTXC SMRXC Input
MCOL SCOL Output
Collision detection MCOL SCOL Input
MCRS SCRS Output
Carrier sense MCRS SCRS Input
MRXDV SMRXDV Output
Receive data valid MRXDV SMTXEN Input
MRXER Not used Output
Receive error MRXER SMTXER Input
MRXD3 SMRXD[3] Output
Receive data bit 3 MRXD3 SMTXD[3] Input
MRXD2 SMRXD[2] Output
Receive data bit 2 MRXD2 SMTXD[2] Input
MRXD1 SMRXD[1] Output
Receive data bit 1 MRXD1 SMTXD[1] Input
MRXD0 SMRXD[0] Output
Receive data bit 0 MRXD0 SMTXD[0] Input
MRXC SMRXC Output
Receive clock MRXC SMTXC Input
Table 4. Swit ch MA C 5 MII Signals
The switch MII interface op er ates in ei ther M AC mode or PH Y mode f or KSZ8895MQ/RQ/FMQ. These in ter f aces ar e
nibble-wide data interfaces, so they run at one-quarter the network bit rate (not encoded). Additional signals on the
transm it side indicate when data is valid or when an error occurs during transm ission. Lik ewise, the rec eive side h as
indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a
signal that indicates a collision has occurred during transmission.
Note that the sig nal MRX E R is not provide d on th e MI I-SW interf ace f or PHY m ode oper ation and t he signa l MT X ER
is not provided on the SW-MII interface for MAC mode operation. Normally MRXER would indicate a receive error
coming from the physical layer device. MTXER would indicate a transm it error from the MAC device. These signals
are not appropriate for this configuration. For PHY mode operation with an external MAC, if the device interfacing
with the KSZ8895MQ/RQ/FMQ has an M RXER pin, it should be ti ed low. For M AC mode oper ation with an external
PHY, if the device interfacing with the KSZ8895MQ/RQ/FMQ has an MTXER pin, it should be tied low.
March 12, 2014 39 Revision 1.7
Micrel, Inc.
Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The
KSZ8895RQ supports RMII interface at Port 5 switch side and provides a common interface at MAC5 layer in the
device, and has the following key characteristics:
• Supports 10Mbps and 100Mbps data rates.
• Uses a single 50 MH z clock r eferenc e (provi ded inter nall y or exter nall y): in internal m ode, the c hip pro vides a
refer ence c lock from the SMRX C pin t o the SMT XC pin and provides the cloc k to the oppos it e cloc k input pin
for RMII interface. In external mode, the chip receives 50MHz reference clock from an external oscillator or
opposite RMII interface.
• Provides independent 2-bit wide (bi-bit) transmit and receive data paths.
KSZ8895RQ supports MAC5 RMII interfaces at the switch side:
• For the detail of SW5-RMII (Port 5 MAC5 RMII) signals connection see the table below:
• The KSZ8895RQ c an provide a 50MHz refer ence clock for both MAC to MAC an d MAC to PH Y RMII interf aces
when SW5-RMII is used in the clock mode of the device (default with strap pin LED2_2 internal pull-up for the
clock mode).
• The KSZ8895RQ can also receive a 50MHz reference clock from an external 50MHz clock source or opposite
RMII to SW5-RMII SMTXC pin when the device is set to normal mode (the strap pin LED2_2 is pulled down).
When the device is strapped to normal mode by pin LED2_2 pull-down, the reference clock comes from SMTXC
which will be used as the device’s clock source. The external 25MHz crystal clock from pins X1/X2 will be ignored.
Note: In normal mode, the 50MHz clock from SMTXC will be used as the clock source for whole device. The PHY5
PMTXC/PMREFCLK pin cannot be used as the clock source for whole device. The pin of PMTXC/PMREFCLK can
receive the 50MHz clock from PMRXC when the device is strapped to normal mode and an external 50MHz
reference clock comes in from pin SMTXC. In normal mode, the 50MHz clock on pin SMRXC can be disabled by
register, and the PMRXC 50MHz clock can be used when P5-RMII interface is used.
There is a register 12 bit 6 to monitor the status of the device for the clock mode or normal mode.
When using an external 50MHz clock source as RMII reference clock, the KSZ8895RQ should be set to normal
mode by pulling down its LED2_2 strap-in pin first before power up reset or warm reset. The normal mode of the
KSZ8895 RQ device will st art to work when it gets the 50MHz ref erence clock from pin SMTX C/SMREFCLK from an
external 50MHz clock source. For the RMII connection examples, please refer to app note in the design kit.
March 12, 2014 40 Revision 1.7
Micrel, Inc.
SW5-RMII MAC to MAC Connection
(‘PHY mode’)
SW5-RMII MAC to PHY Connection
(‘MAC mode’)
External
MAC KSZ8895RQ
SW5-RMII
KSZ8895RQ
SW Signal
Type
Description External
PHY KSZ8895RQ
SW5-RMII KSZ8895RQ SW
Signal Type
REF_CLK SMRXC
Output (clock
mode with
50MHz)
(Normal mode
without
connection)
Reference Clock -------- SMTXC/SM
REFCLK
Input (clock comes
from SMRXC in
clock mod e or
external clock in
normal mode)
CRS_DV
SMRXDV
/SMCRSDV
Output
Carier sense/Receive
data valid
CRS_DV SMTXEN Input
RXD[1:0] SMRXD[1:0] Output Receive data bit [1:0] RXD[1:0] SMTXD[1:0] Input
TX_EN SMTXEN Input Transmit data enable TX_EN
SMRXDV
/SMCRSDV
Output
TXD[1:0] SMTXD[1:0] Input
Transmit dat a bit
[1:0]
TXD[1:0] SMRXD[1:0] Output
(not used) (not used) Receive error (not used) (not used)
--- SMTXC/SM
REFCLK
Input (clock
comes from
SMRXC in clock
mode or external
clock in normal
mode)
Reference Clock REF_CLK SMRXC
Output (clock mod e
with 50MHz)
(Normal mode
without connection)
Note:
1. MAC/PHY mode in RMII is difference with MAC/PHY mode in MII, there is no strap pin and register configuration request in RMII, just follow
the signals connect i on in the table.
Table 5. Port 5 MAC5 SW5-RMII Connection
SNI Interface Operatio n
The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing.
This interface can be directly connected to these t ypes of devices. The signals are divided into two groups, one for
transmission and the other for reception. The signals involved are described in Table below.
SNI Signal Description KSZ8895MQ/RQ/FMQ Signal
TXEN Transmit Enable SMTXEN
TXD Serial Transmit Data SMTXD[0]
TXC Transmit Clock SMTXC
COL Co llision Detection SCOL
CRS Carrier Sense SMRXDV
RXD Serial Receive Data SMRXD[0]
RXC Receive Clock SMRXC
Table 6. SNI Signals
This inter face is a bit-wid e data interf ace, s o it runs at the network bit rate (not encoded) . An additio nal signa l on the
transmit side indicates when data is valid. Likewise, the receive side has an indicator that shows when the data is
valid.
For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
March 12, 2014 41 Revision 1.7
Micrel, Inc.
Advanced Functionality
QoS Priority Support
The KSZ8895MQ/RQ/FMQ provides Quality of Serv ice (QoS) for applicat ions such as VoIP and video conf erencing.
The KSZ8895MQ/RQ/FMQ offers one, two, or four pr iority q ueues per port b y setting th e port re gisters xxx control 9
bit 1 and the port registers xxx control 0 bit 0, the 1/2/4 queues split as follows,
[Port registers xxx control 9 bit 1, control 0 bit 0] = 00 single output queue as default.
[Port registers xxx control 9 bit 1, control 0 bit 0] = 01 egress port can be split into two priority transmit queues.
[Port registers xxx control 9 bit 1, control 0 bit 0] = 10 egress port can be split into four priority transmit queues.
The four priority transmit queue is a new feature in the KSZ8895MQ/RQ/FMQ. The queue 3 is the highest priority
queue and queue 0 is the lowest priority queue. The port registers xxx control 9 bit 1 and the port registers xxx
control 0 bit 0 are used to enable split transmit queues for ports 1, 2, 3, 4 and 5, respectively. If a port's transmit
queue is not split, high priority and low priority packets have equal priority in the transmit queue.
There is an additiona l option to either al wa ys deliver high priorit y packets first or to use progr ammable weighted f air
queuing f or the f our priorit y queue scale b y the port r e gis ters c ontro l 10, 11, 12 a nd 13 ( def ault value are 8, 4, 2, 1 by
their bit[6:0] .
Register 130 bit[7: 6] Pr io_2Q[1:0] is used when the 2 Queue configuration is selected, these bits are used to map the
2-bit result of IEEE 802.1p from the registers 128, 129 or TOS/DiffServ mapping from registers 144-159 (for 4
Queues) into two-queue mode with priority high or low.
Please see the descriptions of the register 130 bits [7:6] for detail.
Port-Based Priority
With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets
received at the priorit y 3 re ceiving port are m arked as high pr iority and ar e sent to the high-priorit y transm it queue if
the corres ponding tra nsm it queue is sp lit. The Port Regis ters Cont rol 0 Bits[4: 3] is us ed to enable port-bas ed prior ity
for ports 1, 2, 3, 4 and 5, respectively.
802.1p-Based Priority
For 802.1p-b ased prior it y, the KSZ8895MQ/RQ/FMQ ex am ines the ingres s (inc om ing) pac k ets to determ ine whether
they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority
mapping” value, as specified by the registers 128 and 129, both register 128/129 can map 3-bit priority field of 0-7
value to 2-bit result of 0-3 priority levels. The “priority mapping” value is programmable.
Figure 11 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Figure 11. 802.1p Priority Field Format
802.1p-based priority is enabled by bit[5] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively.
March 12, 2014 42 Revision 1.7
Micrel, Inc.
The KSZ8895MQ/RQ/FMQ provides the option to insert or remove the priority tagged frame's header at each
individual egr ess por t. This header , c onsis ti ng of the two-byte VLAN Protoc o l ID ( VPID ) an d the two-b yte Tag C ontro l
Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enable d by bit[2] of the port re gisters c ontrol 0 and the p ort regis ter control 8 t o selec t which sourc e
port (ingress port) P VID ca n be inserte d on the egr ess por t for ports 1, 2, 3, 4 and 5, res pectivel y. At the e gres s port,
untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in the port
registers control 3 and contr ol 4 for ports 1, 2, 3, 4 and 5, res pectively. T he KSZ8895MQ/RQ/FMQ will not add tags
to already tagged packets.
Tag Removal is enabled by b it[ 1] of the port registers control 0 f or ports 1, 2, 3, 4 and 5, respect ively. At th e egress
port, tagged packets will have their 802.1Q VLAN tags removed. The KSZ8895MQ/RQ/FMQ will not modify untagged
packets.
The CRC is recalculated for both tag insertion and tag r emoval.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8895MQ/RQ/FMQ to set the “User Priority
Ceiling” at any ingress por t b y the p or t r e gister contro l 2 b it 7. I f the i ngres s p ac k et’s priorit y field h as a h igh er pri ority
value than t he def ault tag ’s prior ity fiel d of the i ngress port, th e pack et’s priorit y fi eld is r eplaced with the default t ag ’s
priority field.
DiffServ-Based Priority
DiffServ-based priorit y uses the T oS registers (regis ters 144 to 159) in th e Advanc ed Control Registers section. T he
ToS priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register
to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS
field are fully decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP
register to determine priority.
Spanning Tree Support
Port 5 is the designated port for spanning tree support.
The other ports (Port 1−Port 4) can be configured in one of the five spanning tree states via “transmit enable,”
“receive enable,” and “learning disable” register settings in Registers 18, 34, 50, and 66 for Ports 1, 2, 3, and 4,
respectively. The following description shows the port setting and software actions taken for each of the five
spanning tree states:
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software ac tio n: the pr oces sor s hould not send a ny pa cket s to the por t. T he sw itch m a y still sen d specif ic p ack ets to
the process or (packets that match s ome entries in the static tab le with “overridi ng bit” set) an d the processor should
discard those packets. Note: the processor is connected to Port 5 via MII interface. Address learning is disabled on
the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1"
Software action: the processor should not send any packets to the port(s) in this state. The processor should
program the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit
should also be set so that the switch will forward those specific packets to the processor. Address learning is
disabled on the port in this stat e.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1.
"Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send pack ets to the port(s) in this state, see “T ail Tagging Mode” section for details.
Address learning is disabled on the port in this state.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
March 12, 2014 43 Revision 1.7
Micrel, Inc.
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.,
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send pack ets to the port(s) in this state, see “T ail Tagging Mode” section for details.
Address learning is enabled on the port in this state.
Forwarding state: packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.,
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send pack ets to the port(s) in this state, see “T ail Tagging Mode” section for details.
Address learning is enabled on the port in this state.
Rapid Spanning Tree Support
There are three operational states of Discarding, Learning, and Forwarding assigned to each port for RSTP:
Discarding ports do not participate in the active topology and do not learn MAC addresses.
Discarding state: the state includes three states of the disable, blocking and listening of STP.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software ac tio n: the pr oces sor s hould not send a ny pa cket s to the por t. T he sw itch m a y still sen d specif ic p ack ets to
the process or (packets that match s ome entries in the static tab le with “overridi ng bit” set) an d the processor should
discard those packets. When disabling the port’s learning capability (learning disable = ’1’), set the register 1 bit 5
and bit 4 will flush rapidly with the port related entries in the dynamic MAC table and static MAC table.
Note: the processor is connected to Port 5 via MII interface. Address learning is disabled on the port in this state.
Ports in Learning states learn MAC addresses, but do not forward user traffic.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.,
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send pack ets to the port(s) in this state, see “Tail Tagging Mode” section for details.
Address learning is enabled on the port in this state.
Ports in Forwarding states fully participate in both data forwarding and MAC learning.
Forwarding state: packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.,
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send pack ets to the port(s) in this state, see “T ail Tagging Mode” section for details.
Address learning is enabled on the port in this state.
RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP Configuration BPDUs with the
exception of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carrying additional
information.
March 12, 2014 44 Revision 1.7
Micrel, Inc.
Tail Tagging Mode
The Tail Tag is only seen and used by the Port 5 interface, which should be connected to a processor by SW5-
MII/RMII interface. The one byte tail tagging is used to indicate the source/destination port in Port 5. Only bit [3−0]
are used for the destination in the tail tagging byte. Other bits are not used. The Tail Tag feature is enabled by setting
register 12 bit 1.
Figure 12. Tail Tag Frame Format
Ingress to Port 5 (Host --> KSZ8895MQ/RQ/FMQ)
Bit [3:0] Destination
0,0,0,0 Reserved
0,0,0,1 Port 1 (direct forward to Port1)
0,0,1,0 Port 2 (direct forward to Port2)
0,1,0,0 Port 3 (direct forward to Port3)
1,0,0,0 Port 4 (direct forward to Port4)
1,1,1,1 Port 1, 2,3 and 4 (direct forward to Port 1,2,3,4,)
Bit[7:4]
0,0,0,0 Queue 0 is used at destination port
0,0,0,1 Queue 1 is used at destination port
0,0,1,0 Queue 2 is used at destination port
0,0,1,1 Queue 3 is used at destination port
x, 1,x,x Anyhow send packets to specified port in bits [3:0]
1, x,x,x Bit[6:0] will be ignored as normal (Adress look-up)
Egress from Port 5 (KSZ8895MQ/RQ/FMQ --> Host)
Bit [1:0] Source
0,0 Port 1 (packets from Port 1)
0,1 Port 2 (packets from Port 2)
1,0 Port 3 (packets from Port 3)
1,1 Port 4 (packets from Port 4)
Table 7. Tail Tag Rules
March 12, 2014 45 Revision 1.7
Micrel, Inc.
IGMP Support
There ar e two parts involve d to support the Int ernet Gr oup Managem ent Pr otocol ( IGMP) in L aye r 2. The fir st pa rt is
IGMP snooping, the second part is this IGMP packet to be sent back to the subscribed port. Describe them as
follows.
• IGMP Snooping
The KSZ8895MQ/RQ/FMQ traps IGMP packets and forwards them only to the processor (Port 5 SW5-MII/RMII).
The IG MP pack ets are ide ntified as I P pack ets (either Ethernet IP pac kets , or IEEE 80 2.3 SNAP IP pack ets) with
IP version = 0x4 and protocol version number = 0x2. Set register 5 bit [6] to ‘1’ to enable IGMP snoo pin g.
• IGMP Send Bac k to the Subscribed Port
Once the hos t r es pon ds th e r ecei ve d IG M P p acket, th e host should know the original IGMP ingr ess por t a nd send
back the IGMP packet to this port only, otherwise this IGMP packet will be broadcasted to all port to downgrade
the performance.
Enable the tail tag mode, the host will know the IGMP packet received port from tail tag bits [1:0] and can send
back the response IGMP packet to this subscribed port by setting the bits [3:0] in the tail tag. Enable “Tail tag
mode” by setting Register 12 bit 1.
Port Mirror ing Support
The KSZ8895MQ/RQ/FMQ supports “port mirror” comprehensively as:
• “Recei ve Only” mirror on a por t
All the packets received on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be
“rx sniff,” and Port 5 is programmed to be the “sniffer port.” A packet, received on Port 1, is destined to Port 4
after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to both Port 4 and Port 5.
KSZ8895MQ/RQ/FMQ can optionally forward even “bad” received packets to Port 5.
• “Transmit Only” mirror on a port
All the packets transmitted on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to
be “tx sniff,” and Port 5 is programmed to be the “sniffer port.” A packet, received on any of the ports, is destined
to Port 1 after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to both Ports 1 and 5.
• “Recei ve and Transmit” mirr or on two ports.
All the packets received on port A AND transmitted on port B will be mirrored on the sniffer port. To turn on the
“AND” feature, set Register 5 bit 0 to 1. For example, Port 1 is programmed to be “rx sniff,” Port 2 is programmed
to be “transmit sniff,” and Port 5 is programmed to be the “sniffer port.” A packet, received on Port 1, is destined
to Port 4 after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to Port 4 only, since it does
not meet the “AND” condition. A packet, received on Port 1, is destined to Port 2 after the internal look-up. The
KSZ8895MQ/RQ/FMQ will forward the packet to both Port 2 and Port 5.
Multiple ports can be selected to be “rx sniffed” or “tx sniffed.” And any port can be selected to be the “sniffer port.”
All these per port features can be selected through Register 17.
VLAN Support
The KSZ8895MQ/RQ/FMQ supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q.
KSZ8895MQ/RQ/FMQ provides a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to
FID (7 bits) for address look-up max 128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then
the ingress port VID is us ed for look -up when 802.1q is enabled b y the glob al register 5 co ntrol 3 bit 7. In t he VLAN
mode, the look-up process starts from VLAN table look-up to determine whether the VID is valid. If the VID is not
valid, the packet will then be dropped and its address will not be learned. If the VID is valid, FID is retrieved for
further look -up by the stat ic MAC tab le or dynamic MA C tab le. F I D+D A is us ed to det ermine the d es tin ati on p or t. The
following table describes the different actions in different situations of DA and FID+DA in the static MAC table and
dynam ic MAC tab le af ter th e V LA N t abl e f in ish a look-up action. FID + SA is us ed f or le arni ng purposes. The foll o wing
table also describes learning in the dynamic MAC table when the VLAN table has done a look-up in the static MAC
table without a valid entry.
March 12, 2014 46 Revision 1.7
Micrel, Inc.
DA found in
Static MAC table
USE FID
Flag?
FID Match?
DA+FID found in
Dynamic MAC table
Action
No Do Not care Do Not care No
Broadcast to the mem bers hip port s def ined in
the VLAN table bit[11:7].
No Do Not care Do Not care Yes
Send to the destination port defined in the
dynamic MAC table bit[58:56].
Yes 0 Do Not care Do Not care
Send to the destination port(s) defined in the
static MAC table bit[52:48].
Yes 1 No No
Broadcast to the mem bers hip port s def ined in
the VLAN table bit[11:7].
Yes 1 No Yes
Send to the destination port defined in the
dynamic MAC table bit[58:56].
Yes 1 Yes Do Not care
Send to the destination port(s) defined in the
static MAC table bit[52:48].
Table 8. FID+DA Look-Up in the VLAN Mode
SA+FID found in
Dynamic MAC table
Action
No The SA+FID will be learned into the dynamic table.
Yes Time stamp will be updated.
Table 9. FID+SA Look-Up in the VLAN Mode
Advance d VLAN f eatures ar e also sup porte d in KSZ8895MQ/RQ/FMQ, s uch as “ VL AN ingres s f iltering” a nd “ discard
non PVID” defined in bits [6:5] of the port Register Control 2. These features can be controlled on a port basis.
Rate Limiting Support
The KSZ8895MQ/RQ/FMQ provides a fine resolution hardware rate limiting. The rate step is 64Kbps when the rate
limit is les s than 1Mb ps rat e for 100BT or 10BT . The rate s tep is 1Mbps when th e rate lim it is m ore than 1M bps rate
for 100BT or 10BT (refer to Data Rate Selection Table which follow the end of the Port Register Queue 0−3
Ingress/Egr ess Lim it Contr ol sect ion). T he rate limit is independent ly on the “rec eive side” a nd on th e “tran smit side”
on a per port basis . For 10 BASE-T, a r ate sett ing abo ve 10 Mbps m eans the rate is not lim ited. On th e recei ve side,
the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers. On the
transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate
Control R egisters . The si ze of eac h fram e has opti ons to include m inim um IFG ( Inter Fram e Gap) or Pream ble byte,
in addition to the data field (from packet DA to FCS).
Ingress Rate Limit
For ingress rate limiting, KSZ8895MQ/RQ/FMQ provides options to selectively choose frames from all types,
multicast, broadcast, and flooded unicast frames by bits [3−2] of the port rate limit control register. The
KSZ8895MQ/RQ/FMQ count s the data rate f rom those selec ted t ype of fr ames. Packets are dropp ed at th e ingress
port when the d ata rate ex ceeds t he spec ified rate limit or the f low contro l tak es eff ect without p acket dr opped when
the ingress rate limit flow control is enabled by the port rate limit control register bit 4. The ingress rate limiting
supports t he port-based, 802.1 p and Dif fServ-bas ed p riorit ies, the por t-base d prio rit y is fixed pr iority 0−3 selec tion b y
bits [4-3] of the port register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0−3 by
default of the r egister 128 and 129. In the ingres s rate lim it, set register 135 g lobal control 1 9 bit 3 to e nable queue-
based rate limit if using two-queue or four-queue mode. All related ingress ports and egress port should be split to
two-queue or f our -queue mode b y the por t registers control 9 and con tr ol 0. T he f our -queue m ode will us e Q0−Q3 f or
priority 0−3 by bit[6−0] of the port register ingress limit control 1−4. The two-queue mode will use Q0−Q1 for priority
0-1by bit[6-0] of the port register ingress limit control 1−2. The prio r ity leve ls in the packets of the 802.1p and DiffServ
can be programmed to priority 0−3 by the r eg ister 128 and 129 for a re-mapping.
March 12, 2014 47 Revision 1.7
Micrel, Inc.
Egress Rate Limit
For egres s r a te l imiting, th e Le aky Bucket algor ithm is app lie d to eac h ou tpu t priorit y q ueu e f or s hapi ng ou tput traf f ic.
Interfr am e gap is s tr etc hed on a per fram e bas e to gen er ate s mooth, non-bur st eg res s traf f ic. T he throughput of eac h
output priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate
limit control registers.
If an y egress queue r eceives mor e traffic than the sp ecified egress rate throughput, p ackets m ay be accum ulated in
the output q ueue and pack et mem ory. After the m emory of the queu e or the port i s used up, pack et dropping or flow
control will b e tr iggered . As a res ult of co ngest ion, t he actual e gres s rate m ay be dom inated b y flo w co ntrol/d roppi ng
at the ingress end, and may be therefore slightly less than the specified egress rate. The egress rate limiting
supports the port-based, 802.1 p and Dif fServ-bas ed p riorit ies, the por t-base d prio rit y is fixed pr iority 0−3 selec tion b y
bits[4−3] of the port register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0−3 by
default of the register 128 and 129. In the egress rate limit, set register 135 global control 19 bit 3 for queue-based
rate limit to be enabled if using two-queue or four-queue mode. All related ingress ports and egress port should be
split to two-queue or four-queue mode by the port registers control 9 and control 0. The four-queue mode will use
Q0-Q3 for pr iority 0−3 by b i t [6-0] of the port re gister eg r es s limit control 1−4. The two-queue mode w ill us e Q0-Q1 for
priority 0−1b y bi t [6−0] of the port regis ter egr ess lim it contr ol 1−2. The prior ity lev els in the pac k ets of the 802.1p and
DiffServ can be programmed to priorit y 0−3 by the regis ter 128 and 129 for a re-mapping.
When the egres s rat e is limited, just us e on e que ue pe r port f or th e egr ess por t ra te lim it . The prior it y pack ets will be
based upon the data rate selection table (see Tables 13 and 14). If the egress rate lim it uses more than one queue
per port f or the egr es s por t r ate lim it, then the h igh es t prior ity packets will be bas e d upon t he da ta r ate s e lecti on tab l e
for the rate limit exact number. Other lower priority packet rates will be limited based upon 8:4:2:1 (default) priority
ratio, which is based on the highest priority rate. The transmit queue priority ratio is programmable.
To reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Transmit Queue Ratio Programming
In transmit queues 0−3 of t he egr ess p or t, th e def au lt pr iority ratio is 8:4: 2:1. T he pr iority ratio ca n be pr ogra m m ed by
the port r egisters c ontrol 10, 11, 1 2 and 13. W hen the transm it rate ex ceeds t he ratio limit in the transm it queue , the
transm it rate w ill be lim ited b y the transmit que ue 0−3 ratio of the por t re gister co nt rol 10, 11, 12 and 13. T he hig hest
priorit y queue wil l not be limited. Other lower priority queues will be limited based on the transmit queue ratio.
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast
Enable Self-address fil terin g, the unkno wn un icast p ack et f iltering a nd for wardin g b y the Re gister 131 Global Control
15. Enable Unknown multicast packet filtering and forwarding by the Register 132 Global Control 16.
Enable Unknown VID pack et filter ing an d for war din g by the Register 133 Global C ontrol 17.
Enable Unknown IP multicast packet filtering and forwarding by the Register 134 Global Control 18.
This function is very useful in preventing packets that could degrade the quality of the port in applications such as
voice over Internet Protocol (VoIP) and the daisy chain connection.
Configuration Interface
I2C Master Serial Bus Configuration
If a 2-wire EEPROM exists, then the KSZ8895MQ/RQ/FMQ can perform more advanced features like broadcast
storm protection and rate control. The EEPROM should have the entire valid configuration data from Register 0 to
Register 255 defined in the “Memory Map,” except the chipID = 0 in the re gis ter1 and the status r egister s . Af ter r es et,
the KSZ8895MQ/RQ/FMQ will start to read all 255 registers sequentially from the EEPROM. The configuration
access time (tprgm) is less than 30ms, as shown in Figure 8.
March 12, 2014 48 Revision 1.7
Micrel, Inc.
Figure 13. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram
To configure the KSZ8895MQ/RQ/FMQ with a pre-configured EEPROM use the following steps:
1. At the b oard level, connect pin 110 on the KSZ8895MQ/RQ/FMQ to the SCL pin on the EEPROM. Connect pin
111 on the KSZ8895MQ/RQ/FMQ to the SDA pin on the EEPROM.
2. A[2-0] address pins of EEPROM should be tied to ground for address A[2-0] = ‘000’ to be identified by the
KSZ8895MQ/RQ/FMQ.
3. Set t he input si gnals P S[1:0] (pins 113 and 11 4, respec tively) to “ 00.” This puts the KSZ8895MQ/RQ/FMQ serial
bus configuration into I2C master mode.
4. Be sure the board-level reset signal is connected to the KSZ8895MQ/RQ/FMQ reset signal on pin 115 (RST_N).
5. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note
that the first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all
other data will be ignor ed.
6. Place EEPROM o n the boar d and power up the b oard. Asser t the active-l ow board le vel reset to RST_N o n the
KSZ8895MQ/RQ/FMQ. Af ter the res et is d e-ass erted, t he KSZ8895MQ/RQ/FMQ will begin readi ng co nfiguration
data from the EEPROM. The configuration access time (tprgm) is less than 30ms.
Note: For proper operation, make sure that pin 47 (PWRDN_N) is not asserted during the reset operation.
SPI Slave Serial Bus Configuration
The KSZ8895MQ/RQ/FMQ can also act as a SPI slave device. Through the SPI, the entire feature set can be
enabled, including “VLAN,” “IGMP snooping,” “MIB counters,” etc. The external master device can access any
register from Register 0 to Register 255 randomly. The system should configure all the desired settings before
enabling the switch in the KSZ8895MQ/RQ/FMQ. To enable the switch, write a "1" to Register 1 bit 0.
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To
speed configuration tim e, the KSZ8895MQ/RQ/FMQ also supports multiple reads or writes. After a byte is written to
or read from the KSZ8895MQ/RQ/FMQ, the internal address counter automatically increments if the SPI Slave
Select Signal ( SPIS_N) co ntinues to be dr iven low. If SPIS_N is k ept low after the first b yte is r ead, the next b yte at
the next address will be shifted out on SPIQ. If SPIS_N is kept low after the first byte is written, bits on the Master
Out Slave Input (SPID) line will be written to the next address. Asserting SPIS_N high terminates a read or write
operation. This means that the SPIS_N signal must be asserted high and then low again before issuing another
comm and and addr ess. T he address counter wraps b ack to zero once it r eaches the highes t addres s. Ther efor e the
entire register set can be written to or read from by issuing a single command and address.
The default SPI clock speed is 12.5MHz. The KSZ8895MQ/RQ/FMQ is able to s upport a SPI bus up to 25MHz (set
register 12 bit[5:4] = 0x10). A high perf ormance SPI master is recommended to prevent internal counter overflow.
March 12, 2014 49 Revision 1.7
Micrel, Inc.
To use the KSZ8895MQ/RQ/FMQ SPI:
1. At the board level, connect KSZ8895MQ/RQ/FMQ pins as follows:
KSZ8895MQ/RQ/FMQ
Pin Number
KSZ8895MQ/RQ/FMQ
Signal Name
Microprocessor Signal Description
112 SPIS_N SPI Slave Select
110 SPIC SPI Clock
111 SPID Master Out Slave Input
109 SPIQ Master In Slave Output
Table 10. SPI Connections
2. Set the input signals PS[1:0] (pins 113 and 114, respectivel y) to “10” to set the serial configuration t o SPI slave
mode.
3. Power up the boar d and as sert a reset s ignal. Af ter res et wait 100µs , the start s witch bit i n Register 1 will be set
to ‘0’. Configure the desired settings in the KSZ8895MQ/RQ/FMQ before setting the start register to ‘1.'
4. W rite conf iguration to register s using a typical SPI writ e data c ycle as s hown i n Figure 9 or SPI m ultiple write as
shown in Figure 11. Note that data input on SPID is registered on the rising edge of SPIC.
5. Regist ers can be r ead a nd c onfigurat ion c an be verifie d with a t ypical SP I rea d da ta c ycle as sh own in Fig ure 10
or a multiple read as shown in Figure 12. Note that read data is registered out of SPIQ on the falling edge of
SPIC.
6. After configuration is written and verified, write a ‘1’ to Register 1 bit 0 to begin KSZ8895MQ/RQ/FMQ switch
operation.
SPIQ
SPIC
SPID
SPIS_N
00000010X A7 A6 A5 A4 A3 A2 A1 A0
WRITE COMMAND WRITE ADDRESS WRITE DATA
D2 D0D1D3D4D5D6D7
Figure 14. SPI Write Data Cycle
SPIQ
SPIC
SPID
SPIS_N
00000011
XA7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
READ COMMAND READ ADDRESS READ DATA
Figure 15. SPI Read Data Cycle
March 12, 2014 50 Revision 1.7
Micrel, Inc.
SPIQ
SPIC
SPID
SPIS_N
00000010
XA7 A6 A5 A4 A3 A2 A1 A0
WRITE COMMAND WRITE ADDRESS Byte 1
D2 D0
D1
D3
D4
D5
D6
D7
SPIQ
SPIC
SPID
SPIS_N
D7 D6 D5 D4 D4 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Byte 2 Byte 3 ... Byte N
D2 D0D1
D3D4D5D6D7
Figure 16. SPI Multiple Write
SPIQ
SPIC
SPID
SPIS_N
0 0 00 0 0 1 1
XA7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
READ COMMAND READ ADDRESS Byte 1
X X X X XX X XXXXXXXXX
Byte 2 Byte 3 ... Byte N
XX X XXXXX
XXXX X X X X
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SPIQ
SPIC
SPID
SPIS_N
Figure 17. SPI Multiple Read
March 12, 2014 51 Revision 1.7
Micrel, Inc.
MII Management Interface (MIIM)
The KSZ8895MQ/RQ/FMQ supports the standard IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control
the states of the KSZ8895MQ/RQ/FMQ. An external device with MDC/MDIO capability is used to read the PHY
status or configure the PHY settings. Further details on the MIIM interface are found in Clause 22.2.4.5 of the IEEE
802.3u Spec if icatio n.
The MIIM interface consists of the following:
• A physical connection that incorporates the data line (pin 108 MDIO) and the clock line (pin 107 MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8895MQ/RQ/FMQ device.
• Access to a set of eight 16-bit registers, consisting of 8 standard MIIM registers [0:5h], 1d and 1f MIIM
registers per port.
The MIIM Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 11 depicts the MII Management Interface frame format.
Preamble Start of
Frame Read/Write
OP Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0] TA Data Bits[15:0] Idle
Read 32 1’s 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
Table 11. MII Man ag em ent In ter face Fr ame Format
The MIIM interface does not have access to all the configuration registers in the KSZ8895MQ/RQ/FMQ. It can only
access the standard MIIM registers. See “MIIM Registers”. The SPI interface and MDC/MDIO SMI mode, on the
other hand, can be used to access all registers with the entire KSZ8895MQ/RQ/FMQ feature set.
Serial Management Interface (SMI)
The SMI is the KSZ8895MQ/RQ/FMQ non-st a ndar d MI IM int erf ac e that pr ov id e s ac c es s to all KSZ8895MQ/RQ/FMQ
configurat ion registers. This interf ace allows an exter nal device with MDC/MDIO inter face to com pletely monitor and
control the states of the KSZ8895MQ/RQ/FMQ.
The SMI interface consists of the following:
• A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8895MQ/RQ/FMQ device.
• Access to all KSZ8895MQ/RQ/FMQ configuration registers. Register access includes the Global, Port and
Advanced Control Registers 0-255 (0x00 – 0xFF), and indirect access to the standard MIIM registers [0:5] and
custom MIIM registers [29, 31].
The SMI Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 12 depicts the SMI frame format.
Preamble Start of
Frame Read/Write
OP Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0] TA Data Bits[15:0] Idle
Read 32 1’s 01 10 RR11R RRRRR Z0 0000_0000_DDDD_DDDD Z
Write 32 1’s 01 01 RR11R RRRRR 10 xxxx_xxxx_DDDD_DDDD Z
Table 12. Serial Management Interface (SMI) Frame Format
March 12, 2014 52 Revision 1.7
Micrel, Inc.
SMI register Read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’.
The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit
[4:0]}. TA is turn-around bits. TA bits [1:0] are ’Z0’ means the processor MDIO pin is changed to input Hi-Z from
output mode and the followed ‘0’ is the read response from device, as the switch configuration registers are 8-bit
wide, only the lower 8 bits of data bits [15:0] are used
SMI register Write access is selected when OP Code is set to “01” and bits [2:1] of the PHY address is set to ‘11’.
The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit
[4:0]}. TA bits [1:0] are set to ’10’, as the switch configuration registers are 8-bit wide, on l y the lower 8 bits of data bits
[15:0] are used.
To access the KSZ8895MQ/RQ/FMQ registers 0-255 (0x00 - 0xFF), the following applies:
PHYAD [4, 3, 0] and REGAD [4:0] are concatenated to form the 8-bit address; that is, {PHYAD [4, 3, 0], REGAD
[4:0]} = bits [7:0] of the 8-bit address.
Register s are 8 data b its wi de. For read op erat ion, dat a bits [15: 8] are rea d back as zeroes. For write operat ion, dat a
bits [15:8] are not d ef ine d, and hence can be set to either zeroes or ones.
SMI reg ister ac cess is t he s ame as t he MIIM r egister acces s, except f or the regis ter acces s requirem ents p resented
in this section.
March 12, 2014 53 Revision 1.7
Micrel, Inc.
Register Description
Offset
Decimal Hex Description
0−1 0x00-0x01 Chip ID Registers.
2−13 0x02-0x0D Global Control Registers.
14−15 0x0E-0x0F Power Down Management Control Registers.
16−20 0x10-0x14 Port 1 Control Registers.
21−24 0x15-0x18 Port 1 Reserved (Factory Test Registers).
25−31 0x19-0x1F Port 1 Control/Status Registers.
32−36 0x20-0x24 Port 2 Control Registers.
37−40 0x25-0x28 Port 2 Reserved (Factory Test Registers).
41−47 0x29-0x2F Port 2 Control/Status Registers.
48−52 0x30-0x34 Port 3 Control Registers.
53−56 0x35-0x38 Port 3 Reserved (Factory Test Registers).
57−63 0x39-0x3F Port 3 Control/Status Registers.
64−68 0x40-0x44 Port 4 Control Registers.
69−72 0x45-0x48 Port 4 Reserved (Factory Test Registers).
73−79 0x49-0x4F Port 4 Control/Status Registers.
80−84 0x50-0x54 Port 5 Control Registers.
85−88 0x55-0x58 Port 5 Reserved (Factory Test Registers).
89−95 0x59-0x5F Port 5 Control/Status Registers.
96−103 0x60-0x67 Reserved (Factory Testing Registers).
104−109 0x68-0x6D MAC Address Registers.
110−111 0x6E-0x6F Indirect Access Control Registers.
112−120 0x70-0x78 Indirect Data Registers.
121−123 0x79-0x7B Reserved (Factory Testing Registers).
124−125 0x7C-0x7D Port Interrupt Registers.
126−127 0x7E-0x7F Reserved (Factory Testing Registers).
128−135 0x80-0x87 Global Control Registers.
136 0x88 Reserved for Factory Testing.
137−143 0x89-0x8F Reserved for Factory.
144−145 0x90-0x91 TOS Priority Control Registers.
146−159 0x92-0x9F TOS Priority Control Registers.
160−175 0xA0-0xAF Reserved (Factory Testing Registers).
176−190 0xB0-0xBE Port 1 Control Registers.
191 0xBF Reserved (Factory Testing Register): Transmit Queue Remap Base Register.
March 12, 2014 54 Revision 1.7
Micrel, Inc.
Register Description (Continued)
Offset
Decimal Hex Description
192−206 0xC0-0xCE Port 2 Control Registers.
207 0xCF Reserved (Factory Testing Register).
208−222 0xD0-0xDE Port 3 Control Registers.
223 0xDF Reserved (Factory Testing Register).
224−238 0xE0-0xEE Port 4 Control Registers.
239 0xEF Reserved (Factory Testing Register).
240−254 0xF0-0xFE Port 5 Control Registers.
255 0xFF Reserved (Factory Testing Register).
March 12, 2014 55 Revision 1.7
Micrel, Inc.
Global Registers
Address Name Description Mode Default
Register 0 (0x00): Chip ID0
7−0 Famil y ID Chip family. RO 0x95
Register 1 (0x01): Chip ID1 / Start Switch
7−4 Chip ID 0100 = KSZ8895MQ/FMQ
0110 = KSZ8995RQ RO
0x4 is for
MQ/FMQ
0x6 is RQ
3−1 Revision ID Revisio n ID RO 0x0
0 Start Switch
1, start the chip when external pins (PS1, PS0) = (1,0)
Note: in (PS1,PS0) = (0,0) mode, the chip will
start automatically, after trying to read the external
EEPROM. If EEPROM does not exist, the chip will use
default values for all internal registers. If EEPROM is
present, the contents in the EEPROM will be checked.
The switch will check:
7 Register 0 = 0x95,
(2) Register 1 [7:4] = Ava ili b le chip ID.
If this check is OK, the contents in the EEPROM will
override chip reg ist er default values =0, chip will not
start when external pins
(PS1, PS0) = (1,0) or (0,1).
Note: (PS1, PS0) = (1,1) for Factory test only.
0, stop the switch function of the chip.
R/W
0
Register 2 (0x02): Global Control 0
7 New Back-off Enable
New Back-off algorithm designed for UNH
1 = Enable
0 = Disable
R/W 0
6 Reserved Reserved. RO 0
5 Flush dynamic MAC table
Flush the entire dynamic MAC table for RSTP
1 = Trigger the flush dynamic MAC table operation.
This bit is self clear
0 = normal operation
Note: All the entries associated with a port that has its
learning capability being turned off (Learning Disable)
will be flushed. If you want to flush the entire Table, all
ports learnin g capab il ity must be turned of f.
R/W
(SC) 0
4 Flush static MAC table
Flush the matched entries in static MAC table for RSTP
1 = Trigger the flush static MAC table operation. This
bit is self clear
0 = normal operation
Note: The matc hed entry is defined as the entry whose
Forwarding Ports field contains a single port and MAC
address with unicast. This port, in turn, has its learning
capability being turned off (Learning Disable). Per port,
multiple entries can be qualified as matched entries.
R/W
(SC) 0
March 12, 2014 56 Revision 1.7
Micrel, Inc.
Global Registers (Continued)
Address Name Description Mode Default
3 Enable PHY MII/RMII 1, enable PHY P5-MII/RMII interface (default).
Note: if not enabled, the switch will tri-state all outputs. R/W
1
Pin LED[5][1]
strap option.
PD(0): isolate.
PU(1): Enable.
Note: LED[5][1]
has internal pull -
up (PU).
2 Reserved N/A Do not change. RO 1
1 UNH Mode
1, the switch will drop packets with 0x8808 in T/L filed,
or DA = 01-80-C2-00-00-01.
0, the switch will drop packets qualified as “flow control”
packets.
R/W 0
0 Link Change Age
1, link change from “link” to “no link” will cause fast
aging (<800µs) to age address table faster. After an
age cycle is complete, t he age logic will retur n to
normal (300 +/- 75 se cond s ). Note: If any port is
unplugged, all addresses will be automatically aged
out.
R/W 0
Registe r 3 (0x03): Global Control 1
7 Pass All Frames
1, switch all packets including bad ones. Used solely
for debugging purpose. Works in conjunction with
sniffer mode.
R/W 0
6 2K Byte packet support
1 = enable support 2K Byte packet
0 = disable support 2K Byte packet
R/W 0
5 IEEE 802.3x Transmit
Flow Control Disable
0, will enable transmit flow control based on AN result.
1, will not enable transmit flow control regardless of
AN result. R/W
0
Pin PMRXD3
strap option.
PD(0): Enable Tx
flow control
(default).
PU(1) : Disabl e
Tx/Rx flow
control.
Note: PMRXD3
has internal pull -
down.
4 IEEE 802.3x Receive
Flow Control Disable
0, will enable receive flow control based on AN result.
1, will not enable receive flow control regardless of
AN result.
Note: Bit 5 and bit 4 default values are controlled by
the same pin, but they can be programmed
independently.
R/W
0
Pin PMRXD3
strap option.
PD (0): Enable
Rx flow control
(default).
PU(1 ): Disable
Tx/Rx flow
control.
Note: PMRXD3
has internal pull -
down.
March 12, 2014 57 Revision 1.7
Micrel, Inc.
Global Registers (Continued)
Address Name Description Mode Default
3 Frame Length Fiel d
Check
1, will check frame length field in the IEEE packets
If the actual length does not match, the packet will be
dropped (for L/T <1500) . R/W 0
2 Aging Enable 1, Enable age function in the chip.
0, Disable aging function. R/W
1
Pin LED[5][2]
strap option.
PD(0): Aging
disable.
PU(1): Aging
enable (default).
Note: LED[5][2]
has internal pull
up.
1 Fast age Enable 1 = Turn on fast age (800µs). R/W 0
0 Aggressive Back Off
Enable
1 = Enable more aggressive back-off algorithm in half
duplex mode to enhance performance. This is not an
IEEE standard. R/W
0
Pin PMRXD0
strap option.
PD(0): D isable
aggressive back
off (default).
PU(1):
Aggressive back
off.
Note: PMRXD0
has internal pull
down.
Registe r 4 (0x04): Global Control 2
7 Unicast Port-VLAN
Mismatch Discard
This feature is used for port VLAN (described in
Register 17, Register 33...).
1, all packets can not cross VLAN boundary.
0, unicast packets (excluding unknown/
multicast/ br oad ca st) can cro ss VLAN boundary .
R/W 1
6 Multicast Storm
Protection Disable
1, “Broadcast Storm Protection” does not include
multicast packets. Only DA = FFFFFFFF FFFF pac kets
will be regulated.
0, “Broadcast Storm Protection” includes
DA = FFFFFFFFFFFF and DA[40] = 1 packet.
R/W 1
5 Back Pressure Mode 1, carrier sen se based bac kpressure is sele cte d.
0, collision based backpre ssur e is select ed. R/W 1
March 12, 2014 58 Revision 1.7
Micrel, Inc.
Global Registers (Continued)
Address Name Description Mode Default
4 Flow Control and Back
Pressure fair Mode
1, fair mode is selected. In this mode, if a flow control
port and a non-flow control port talk to the same
destination por t, then packets from the non-flow control
port may be dropped. This is to prevent the flow control
port from being flow controlled for an extended period
of time.
0, in this mode, if a flow control port and a non-flow
control port talk to the same destination port, the flow
control port will be flow controlled. This may not be
“fair” to the flow control port.
R/W 1
3 No Excessive
Collision Drop
1, the switch will not drop packets when 16 or more
co llisions occur .
0, the switch will drop pac ket s when 16 or more
co llisions occur .
R/W
0
Pin PMRXD1
strap option.
PD(0): (default )
Drop excessive
collision pa cket s.
PU(1): Do Not
drop excessive
collision pa cket s.
Note: PMRXD1
has internal pull
down.
2 Huge Packet Support
1, will accept packet sizes up to 1916 bytes (inclusive).
This bit setting will override setting from bit 1 of the
same register.
0, the max packet size will be determined by bit 1 of
this register.
R/W 0
1 Legal Maximum Packet
Size Check Disable
1, will accept packet sizes up to 1536 bytes (inclusive).
0, 1522 bytes for tagged packets (not including packets
with STPID from CPU to ports 1-4), 1518 bytes for
untagged packets. Any packets larger than the
specified value will be dropped.
R/W
0
Pin PMRXER
strap option.
PD(0): (default)
1518/1522 byte
packets.
PU(1): 1536 byte
packets.
Note: PMRXER
has internal pull -
down.
0 Reserved N/A RO 0
Registe r 5 (0x05): Global Control 3
7 802.1q VLAN Enable 1, 802.1q VLAN mode is turned on. VLAN table needs
to set up before the operation.
0, 802.1q VLAN is disabled. R/W 0
6 IGMP Snoop Enable on
Switch SW5-MII/RMII
Interface
1, IGMP snoop enabled. All the IGMP packets will be
forwarded to Switch MII/RMII port.
0, IGMP snoop disabled. R/W 0
5 Enable Direct Mode on
Switch SW5-MII/RMII
Interface
1, direct mode on Port 5. This is a special mode for th e
Switch MII/RMII interface. Using preamble before
MRXDV to direct switch to forward packets, bypassing
internal loo k-up.
0, normal operation.
R/W 0
March 12, 2014 59 Revision 1.7
Micrel, Inc.
Global Registers (Continued)
Address Name Description Mode Default
4 Enable Pre-Tag on
Switch SW5-MII/RMII
Interface
1, packets forwarded to Switch MII/RMII interface will
be pre-tagged with the source port number (preamble
before MRXDV).
0, normal operation.
R/W 0
3−2 Reserved N/A RO 00
1 Enable “Tag” Mask
1, the last 5 digits in the VID field are used as a mask to
determine which port(s) the packet should be forwarded
to.
0, no tag masks.
Note: you need to turn off the 802.1q VLAN mode
(reg0x5, bit 7 = 0) for this bit to work
R/W 0
0 Sniff Mode Select
1, will do Rx AND Tx sniff (both source port and
destination por t nee d to match ) .
0, will do Rx OR Tx sniff (Either source port or
destination por t nee ds to matc h).
This is the mode used to implement Rx only sniff.
R/W 0
Register 6 (0x06): Global Control 4
7 Switch SW5-MII/RMII
Back Pressure Enable
1, enable half-duplex back pressure on switch MII/RMII
interface.
0, disable back pressure on switch MII interface. R/W 0
6 Switch SW5-MII/RMII
Half-Duplex Mode 1, enable MII/RMII interface half-duplex mode.
0, enable MII/RMII interface full-duplex mode. R/W
0
Pin SMRXD2
strap option.
PD(0): (default)
Full-duplex
mode.
PU(1): Half-
duplex mode.
Note: SMRXD2
has internal pull -
down.
5 Switch SW5-MII/RMII
Flow Control Enable
1, enable full-duplex flow control on switch MII/RMII
interface.
0, disable full-duplex flow control on switch MII/RMII
interface.
R/W
0
Pin SMRXD3
strap option.
PD(0): (default)
Disable flow
control.
PU(1): enable
flow control.
Note: SMRXD3
has internal pull -
down.
March 12, 2014 60 Revision 1.7
Micrel, Inc.
Global Registers (Continued)
Address Name Description Mode Default
4 Switch SW5-MII/RMII
Speed 1, the switch SW5-MII/RMII is in 10Mbps mode.
0, the switch SW5-MII/RMII is in 100Mbps mode. R/W
0
Pin SMRXD1
strap option.
PD(0): (default)
Enable 100Mbps.
PU(1): Enable
10Mbps.
Note: SMRXD1
has internal pull -
down.
3 Null VID Replacement 1, will replace null VID with port VID (12 bits).
0, no replacement for null VID. R/W 0
2−0 Broadcast Storm
Protection Rate Bit[10:8]
This along with the next register determines how many
“64 byte blocks” of packet data allowed on an input port
in a preset period. The period is 50ms for 100BT or
500ms for 10BT. The default is 1%.
R/W 000
Registe r 7 (0x07): Global Control 5
7−0 Broadcast Storm
Protection Rate Bit[7:0]
This along with the previous register determines how
many “64-byte blocks” of packet data are allowed on an
input port in a preset period. The period is 50 ms for
100BT or 500ms for 10BT. The default is 1%.
R/W 0x4A(1)
Registe r 8 (0x08): Global Control 6
7−0 Factory Testing N/A Do not change. RO 0x00
Registe r 9 (0x09): Global Control 7
7−0 Factory Testing N/A Do not change. RO 0x4C
Note:
148,800 frames/sec × 50ms/interval × 1% = 74 frames/interval (approx.) = 0x4A.
March 12, 2014 61 Revision 1.7
Micrel, Inc.
Global Registers (Continued)
Address Name Description Mode Default
Registe r 1 0 (0x0A): Global Control 8
7−0 Factory Testing N/A Do not change. RO 0x00
Registe r 1 1 (0x0B): Global Control 9
7 Reversed N/A Do not change. RO 0
6 Port 5 SW5- RMII
reference clo ck edge
select
RQ: Select the data sampling edge of Switch MAC5
SW5- RMII reference clock:
1 = data sampling on negative edge of refclk
0 = data sampling on positive edge of refclk (default)
Note: MQ/FMQ is reserved with read only for this bit.
R/W 0
5 Reserved N/A Do not change. RO 0
4 Reserved N/A Do not change. RO 0
3 PHY Power
Save 1 = disable PHY power save mode.
0 = enable PHY power save mode. R/W 0
2 Reserved N/A Do not change. RO 0
1 LED Mode
0 = led mode 0.
1 = led mode 1.
Mode 0, link at
100/Full LEDx[2,1,0] = 0,0,0
100/Half LEDx[2,1,0] = 0,1,0
10/Full LEDx[2,1,0] = 0,0,1
10/Half LEDx[2,1,0] = 0,1,1
Mode 1, link at
100/Full LEDx[2,1,0] = 0,1,0
100/Half LEDx[2,1,0] = 0,1,1
10/Full LEDx[2,1,0] = 1,0,0
10/Half LEDx[2,1,0] = 1,0,1
(0 = LED on, 1 = LED off)
R/W
0
Pin SMRXD0 –
strap option. Pull-
down(0): Enabled
led mode 0. Pull-
up(1): Enabled
led mode 1.
Note: SMRXD0
has internal pull -
down 0.
Mode 0 Mode 1
LEDX_2 Lnk/Act 100Lnk/Act
LEDX_1 Fulld/Col 10Lnk/Act
LEDX_0 Speed Fulld
0 SPI/SMI read sampling
clock edge sele ct
Select the SPI/SMI clock edge for sampling SPI/SMI
read data.
1 = trigger by rising edge of SPI/SMI clock (for high
speed SPI about 25MHz and SMI about 10MHz)
0 = trigger by falling edge of SPI/SMI clock.
R/W 0
March 12, 2014 62 Revision 1.7
Micrel, Inc.
Global Registers (Continued)
Address Name Description Mode Default
Register 12 (0x0C): Global Control 10
7 Reserved
Reserved
RO 0
6
Satus of device with RMII
interface at clock mode or
normal mode, default is
clock mode with 25MHz
Crystal clock from pins
X1/X2
(used for RMII of the
KSZ8895RQ only)
1 = The device is in clock mode when use RMII
interface, 25 MHz Crystal clock input as clock so ur ce
for internal PLL. This internal PLL will provide the 50
MHz output on the pin SM RX C for RMII reference
cl ock (Default).
0 = The device is in normal mode when use SW4-RMII
interface and 50 MHz clock input from external clock
through pin SM4TXC as device’s clock source and
internal PLL clock source from this pin not from the
25MHz crystal.
Note: This bit is set by strap option only. Write to this
bit has no effect on mode selection.
Note: The normal mode is used in SW5-RMII interface
reference clock from external.
RO
1
Pin LED[2][2]
strap option.
PD(0): Select
SW5-RMII at
normal mode to
receive ex ter nal
50MHz RMII
reference clo ck
PU(1): (default)
Select SW5-
RMII at clock
mode, RMII
output 50MHz
Note: LED[2][2]
has internal pull -
up.
5–4 CPU interface clock select
Select the internal clock speed for SPI, MDI interface:
00 = 41.67MHz (SPI up to 6.25MHz, MDC up to
6MHz)
01 = 83.33MHz Default (SPI SCL up to 12.5MHz,
MDC up to 12MHz)
10 = 125MHz (for hign speed SPI about 25MHz)
11 = Reserved
R/W 01
3 Reserved N/A Do not change. RO 0
2 Enable restore preamble
This bit is to enable PHY5, when in 10BT mode, to
restore preamble before sending data on P5-MII
interface.
1 = Enable PHY5 to restore preamble.
0 = Disable PHY5 to restore preamble.
R/W 1
1 Tail Tag Enable Tail Tag feature is applied for Port 5 only.
1 = Insert 1 Byte of dat a rig ht before FCS.
0 = Do not insert. R/W 0
0 Pass Flow Control Packet 1 = Switch will not filter 802.1x “flow control” packets.
0 = Switch will filter 802.1x “flow control” packets. R/W 0
Register 13 (0x0D): Global Control 11
7–0 Factory Testing N/A Do not change. RO 00000000
Registe r 1 4 (0x0E): Power Down Management Control 1
7 Reserved N/A Do not change. RO 0
6 Reserved N/A Do not change. RO 0
March 12, 2014 63 Revision 1.7
Micrel, Inc.
Global Registers (Continued)
Address Name Description Mode Default
5 PLL Power Down Pll power down enable:
1 = Enable
0 = Disable R/W 0
4–3 Power Management Mode
Power manageme nt mode :
00 = Normal mode (D0)
01 = Energy Detection mode (D2)
10 = soft Power Down mode (D3)
11 = Power Saving mode (D1)
R/W
00
Pin LED[4][0]
strap option.
PD(0): Select
Energy detection
mode
PU(1): (default)
Normal mode
Note: LED[4][0]
has internal pull -
up.
2−0 Reserved N/A Do not change. RO 000
Registe r 1 5 (0x0F): Power Down Management Control 2
7–0 Go_sleep_time[7:0]
When the Energy Detect mode is on, this value is
used to control the minimu m period t hat the no energy
event has to be detected consecutively before the
device enters the low power state. The unit is 20 ms.
The default of go_sleep time is 1.6 seconds (80Dec x
20ms).
R/W 01010000
March 12, 2014 64 Revision 1.7
Micrel, Inc.
Port Re gisters
The following registers are used to enable features that are assigned on a per port basis. The register bit
assignments are the same for all ports, but the address for each port is different, as indicated.
Registe r 1 6 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Registe r 4 8 (0x30): Port 3 Control 0
Registe r 6 4 (0x40): Port 4 Control 0
Registe r 8 0 (0x50): Port 5 Control 0
Address Name Description Mode Default
7 Broadcast Storm
Protection Enable
1, enable broadcast storm protection for ingress
packets on the port.
0, disable broadcast storm protection. R/W 0
6 DiffServ Priority
Classification Enable
1, enable DiffServ priority classification for ingress
packets on port.
0, disable DiffServ function. R/W 0
5 802.1p Priority
Classification Enable
1, enable 802.1p priority classification for ingress
packets on port.
0, disable 802.1p. R/W 0
4–3 Port-Based Priority
Classification Enable
= 00, ingress packets on port will be
classified as priority 0 queue if “Diffserv” or “802.1p”
classif ication is not enabled or fails to classify .
= 01, ingress packets on port will be
classified as priority 1 queue if “Diffserv” or “802.1p”
cl assification is not enabl ed or f ail s to classify .
= 10, ingress packets on port will be
cl assified as priority 2 queue if “Diffserv” or “802.1p”
cl assification is not enabl ed or f ail s to classify .
= 11, ingress packets on port will be
classified as priority 3 queue if “Diffserv” or “802.1p”
cl assification is not enabl ed or f ail s to classify .
Note: “DiffServ”, “802 .1p” and port priority can be
enabled at the same time. The OR’ed result of 802.1p
and DSCP overwrites the port priority.
R/W 00
2 Tag insertion
1, when packets are output on the port, the switch will
add 802.1q tags to packets without 802.1q tags when
received. The switch will not add tags to packets
already tagged. The tag inserted is the ingress port’s
“port VID.”
0, disable tag insertion.
R/W 0
1 Tag Removal
1, when packets are output on the port, the switch will
remove 802.1q tags from packets with 802.1q tags
when received. The switch will not modify packets
received without tags.
0, disable tag removal.
R/W 0
March 12, 2014 65 Revision 1.7
Micrel, Inc.
Port Re gisters (Continued)
Address Name Description Mode Default
0 Two Queues Split Enable
This bit 0 in the register16/32/48/64/80 sho uld be in
combination with Register177/193/209/225/241 bit 1
for Port 1-5 will select the split of ½/4 queues:
For Port 1, [Register 177 bit 1, Register 16 bit 0] =
[11], Reserved
[10], the port output queue is split into four prior ity
queues or if map 802.1p to priority 0-3 mode.
[01], the port output queue is split into two priority
queues or if map 802.1p to priority 0-3 mode.
[00], single output queue on the port. There is no
priority differentiation even though packets are
cl assified into high or low priority.
R/W 0
Registe r 1 7 (0x11): Port 1 Control 1
Registe r 3 3 (0x21): Port 2 Control 1
Registe r 4 9 (0x31): Port 3 Control 1
Registe r 6 5 (0x41): Port 4 Control 1
Registe r 8 1 (0x51): Port 5 Control 1
Address Name Description Mode Default
7 Sniffer Port 1, port is designated as sniffer port and will transmit
packets that are monitored.
0, port is a normal port. R/W 0
6 Receive Sniff
1, all the packets received on the port will be marked
as “monitored packets” and forwarded to the
designated “sniffer port.”
0, no receive monitoring.
R/W 0
5 Transmit Sniff
1, all the packets transmitted on the port will be marked
as “monitored packets” and forwarded to the
designated “sniffer port.”
0, no transmit monitoring.
R/W 0
4−0 Port VLAN Membership
Define the port’s Port VLAN membership. Bit 4 stands
for Port 5, bit 3 for Port 4...bit 0 for Port 1. The port can
only communicate within the membership. A ‘1’
includes a port in the member ship , a ‘0’ excludes a port
from membershi p.
R/W 0x1f
March 12, 2014 66 Revision 1.7
Micrel, Inc.
Port Re gisters (Continued)
Registe r 1 8 (0x12): Port 1 Control 2
Registe r 3 4 (0x22): Port 2 Control 2
Registe r 5 0 (0x32): Port 3 Control 2
Registe r 6 6 (0x42): Port 4 Control 2
Registe r 8 2 (0x52): Port 5 Control 2
Address Name Description Mode Default
7 User Priority Ceiling
1, If packet ‘s “user priority field” is greater than the
“user priority field” in the port default tag register,
replace the packet’s “user priority field” with the “user
priority field” in the port default tag register control 3.
0, no replace packet’s priority filed with port default tag
priority filed of the port register control 3 bit[7:5].
R/W 0
6 Ingress VLAN Filt erin g.
1, the switch will dis car d pack ets whose VID port
membership in VLAN table bit[11:7] does not include
the ingress port.
0, no ingress VLAN filtering.
R/W 0
5 Discard Non-PVID
packets
1, the switch will discard packets whose VID does not
match ingress port def a ult VID .
0, no packets will be discarded. R/W 0
4 Force Flow Contro l
1, will always enable Rx and Tx flow control on the
port, regardless of AN result.
0, the flow control is enabled based on AN result
(Default)
R/W
0
Strap-in option
LED1_1/PCOL For
port 3/port 4 LED1_1
default Pull up (1):
Not force flow
control; PCOL default
Pull-down (0): Not
force flow control.
LED1_1 Pull dow n
(0): Force flow
control; PCOL Pull-
up (1): Force flow
control. Note:
LED1_1 has internal
pull-up; PCOL have
internal pul l-down.
3 Back Pressure Enable 1, enable port half-duplex back pressure.
0, disable port half-duplex back pressure. R/W
Pin PMRXD2 strap
option. Pull-down (0):
disable back
pressure. Pull-up(1):
enable back
pressure. Note:
PMRXD2 has internal
pull-down.
2 Transmit Enable 1, enable packet transmission on the port.
0, disable packet transmission on the port. R/W 1
1 Receive Enable 1, enable packet reception on the port.
0, disable packet reception on the port. R/W 1
0 Learning Disable 1, disab le sw itch addre ss lear ning cap abi lit y .
0, enable switch address learning. R/W 0
Note:
Bits 2-0 are used for spanning tree support. See “Spanning Tree Support” secti on.
March 12, 2014 67 Revision 1.7
Micrel, Inc.
Port Re gisters (Continued)
Registe r 1 9 (0x13): Port 1 Control 3
Registe r 3 5 (0x23): Port 2 Control 3
Registe r 5 1 (0x33): Port 3 Control 3
Registe r 6 7 (0x43): Port 4 Control 3
Registe r 8 3 (0x53): Port 5 Control 3
Address Name Description Mode Default
7−0 Default Tag [15:8]
Port’s default tag, co nt ai nin g:
7-5: user priority bits
4: CFI bit
3-0 : VID[11:8]
R/W 0x00
Registe r 2 0 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Registe r 5 2 (0x34): Port 3 Control 4
Registe r 6 8 (0x44): Port 4 Control 4
Registe r 8 4 (0x54): Port 5 Control 4
Address Name Description Mode Default
7−0 Default Tag [7:0] Default port 1’s tag, containing:
7-0: VID[7:0] R/W 0x01
Note:
Registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) Associat ed with the ingress untagged packets , and used for
egress tagging; (2) Default VID for the i ngress untagged or null-VID-tagged packets, and used for address look up.
Register 87 (0x57): RMII Management Control Register
Address Name Description Mode Default
7−4 Reserved N/A Do not change. RO 0000
3
Port 5 SW5-RMII 50MHz
clock output disable
(used for KSZ8895RQ
only)
Disable the output of port 5 SW5-RMII 50 MHz output
clock on RXC pin when 50MHz clock is not being used
by the device and the 50MHz clock from external
oscillator or opposite device in RMII mode
1 = Disable clock output when RXC pin is not used in
RMII mode
0 = Enable clock output in RMII mode
Note:MQ/FMQ is reserved with read only for this bit.
R/W 0
2
P5-RMII 50MHz clock
output disable
(used for KSZ8895RQ
only)
Disable the output of port 5 P5-RMII 50 MHz output
clock on RXC pin when 50MHz clock is not being used
by the device and the 50MHz clock from ex ternal
oscillator or opposite device in RMII mode
1 = Disable clock output when RXC pin is not used in
RMII mode
0 = Enable clock output in RMII mode
Note:MQ/FMQ is reserved with read only for this bit.
R/W 0
1−0 Reserved N/A Do not change. RO 00
March 12, 2014 68 Revision 1.7
Micrel, Inc.
Port Re gisters (Continued)
Register 25 (0x19): Port 1 Status 0
Register 41 (0x29): Port 2 Status 0
Register 57 (0x39): Port 3 Status 0
Register 73 (0x49): Port 4 Status 0
Register 89 (0x59): Port 5 Status 0
Address Name Description Mode Default
7 Hp_mdix
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
R/W 1
6 Factory Testing N/A Do not change. RO 0
5 Polrvs
1 = Polarity is reversed
0 = Polarity is not reversed
RO 0
4
Transmit Flow Contro l
Enable
1 = Transmit flow control feature is activ e
0 = Transmit flow control feature is inactive
RO 0
3
Receive Flow Control
Enable
1 = Receive flow control feature is active
0 = Receive flow control feature is inactive
RO 0
2 Operation Speed
1 = Link speed is 100Mbps
0 = Link speed is 10Mbps
RO 0
1 Operation Duplex
1 = Link duplex is full
0 = Link duplex is half
RO 0
0 Reserved N/A Do not change. RO 0
Register 26 (0x1A): Port 1 PHY Special Control/Status
Register 42 (0x2A): Port 2 PHY Special Control/Status
Register 58 (0x3A): Port 3 PHY Special Control/Status
Register 74 (0x4A): Port 4 PHY Special Control/Status
Register 90 (0x5A): Port 5 PHY Special Control/Status
Address Name Description Mode Default
7-4 Reserved N/A Do not change. RO 0000
3 Force_lnk
1 = Force link pass
0 = Normal Operation
R/W 0
2 Pwrsave
1 = Enable power saving
0 = Disable power saving
R/W 0
1 Remote Loopback
1 = Perform Remote loopback, loopback on port 1 as
follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start : RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Setting reg. 42, 58, 74, 90, bit 1 = ‘1’ will perform
remote loopback on port 2, 3, 4, 5.
0 = Normal Operation.
R/W 0
0 Reserved N/A Do not change. RO 0
March 12, 2014 69 Revision 1.7
Micrel, Inc.
Port Re gisters (Continued)
Register 27 (0x1B): Reserved
Register 43 (0x2B): Reserved
Register 59 (0x3B): Reserved
Register 75 (0x4B): Reserved
Register 91 (0x5B): Reserved
Address Name Description Mode Default
7−0 Reserved N/A Do not change. RO 0
Register 28 (0x1C): Port 1 Control 5
Registe r 4 4 (0x2C): Port 2 Control 5
Registe r 6 0 (0x3C): Port 3 Control 5
Registe r 7 6 (0x4C): Port 4 Control 5
Registe r 9 2 (0x5C): Port 5 Control 5
Address Name Description Mode Default
7 Disabl e Auto-Negotiation
1, disable auto-negotiation, speed and duplex are
decided by bit 6 and 5 of the same register.
0, auto-negotiation is on.
Note: The register bit value is the INVERT of the strap
value at the pin.
R/W
0
For Port 3/Port 4
only. INVERT of
pins
LED[2][1]/LED[5][0]
strap option.
PD(0): Disable
Auto-Negotiation.
PU(1): Enable
Auto-Negotiation.
Note:
LED[2][1]/LED[5][0]
have internal pull
up.
6 Forced Speed
1, forced 100BT if AN is disabled (bit 7).
0, forced 10BT if AN is disabled (bit 7).
R/W 1
5 Forced Duplex
1, forced full-duplex if (1) AN is disabled or (2) AN is
enabled but fail ed.
0, forced half-duplex if (1) AN is disabled or (2) AN is
enabled but failed (Default).
R/W
0
For Port 3/Port 4
only. Pins
LED1_0/PCRS
strap option:
1). Force half-
duplex mode:
LED1_0 pin Pull-
up(1) (default) for
Port 3
PCRS pin Pull-
down (0) (default)
for Port 4
2). Force full-
Duplex mode:
LED1_0 pin Pull-
down(0) for Port 3
PCRS Pull-up (1)
for Port 4.
Note: LED1_0 has
internal pul l-up;
PCRS have
internal pul l down.
March 12, 2014 70 Revision 1.7
Micrel, Inc.
Port Re gisters (Continued)
Address Name Description Mode Default
4 Advertised Flow Control
Capability
1, advertise flow contr ol capability.
0, suppress flow control capability from transmission to
link partner. R/W 1
3 Advertised 100BT Full-
Duplex Capability
1, advertise 100BT full-duplex capability.
0, suppress 100BT full-duplex capability from
transmission to link partner.
R/W 1
2 Advertised 100BT Half-
Duplex Capability
1, advertise 100BT half-duplex capability.
0, suppress 100BT half-duplex capability from
transmission to link partner.
R/W 1
1 Advertised 10BT Full-
Duplex Capability
1, advertise 10BT full-duplex capability.
0, suppress 10BT full-duplex capability from
transmission to link partner.
R/W 1
0 Advertised 10BT Half-
Duplex Capability
1, advertise 10BT half-duplex capability.
0, suppress 10BT half-duplex capability from
transmission to link partner.
R/W 1
Registe r 2 9 (0x1D): Port 1 Control 6
Registe r 4 5 (0x2D): Port 2 Control 6
Registe r 6 1 (0x3D): Port 3 Control 6
Registe r 7 7 (0x4D): Port 4 Control 6
Registe r 9 3 (0x5D): Port 5 Control 6
Address Name Description Mode Default
7 LED Off
1, turn off all port’s LEDs (LEDx_2, LEDx_1, LEDx_0,
where “x” is the port number). These pins will be driven
high if this bit is set to one.
0, normal operation.
R/W 0
6 Txids 1, disable port’s transmitter.
0, normal operation. R/W 0
5 Restar t AN 1, restart auto-negotiation.
0, normal operation. R/W
(SC) 0
4 FX reserved N/A RO 0
3 Power Down 1, power down.
0, normal operation.
R/W 0
2 Disable A uto MDI/MDI-X 1, disable auto MDI/MDI-X function.
0, enable auto MDI/MDI-X function. R/W 0
1 Forced MDI
1, if auto MDI/MDI-X is disabled, force PHY into MDI
mode (transmit on RX pair).
0, MDI-X mode (transmit on TX pair).
R/W 0
0 MAC Loopback
1, Perform MAC loopback, loop back path as follows:
E.g. set port 1 MAC Loopback (reg. 29, bit 0 = ‘1’), use
port 2 as monitor port. The pa ckets w ill trans fer
Start: Port 2 receivin g (also can start to receive
packets from port 3, 4, 5).
Loop-back: Port 1’s MAC.
End: Port 2 transmitting (also can e nd at Port 3, 4,
5 respectively).
Setting reg. 45, 61, 77, 93, bit 0 = ‘1’ will perform MAC
loopback on port 2, 3, 4, 5 respectively.
0, Normal Operation.
R/W 0
March 12, 2014 71 Revision 1.7
Micrel, Inc.
Port Re gisters (Continued)
Register 30 (0x1E): Port 1 Status 1
Register 46 (0x2E): Port 2 Status 1
Register 62 (0x3E): Port 3 Status 1
Register 78 (0x4E): Port 4 Status 1
Register 94 (0x5E): Port 5 Status 1
Address Name Description Mode Default
7 MDIX Status
1, MDI.
0, MDI-X.
RO 0
6 AN Done
1, AN done.
0, AN not done.
RO 0
5 Link Good
1, link good.
0, link not good.
RO 0
4
Partner Flow Control
Capability
1, link partner flow control capable.
0, link partner not flow control capa ble.
RO 0
3
Partner 100BT Full-
Duplex Capability
1, link partner 100BT full-duplex capable.
0, link partner not 100BT full-duplex capable.
RO 0
2
Partner 100BT Half-
Duplex Capability
1, link partner 100BT half-duplex capable.
0, link partner not 100BT half-duplex capable.
RO 0
1
Partner 10BT Full-Duplex
Capability
1, link partner 10BT full-duplex capable.
0, link partner not 10BT full-duplex capable.
RO 0
0
Partner 10BT Half-Duplex
Capability
1, link partner 10BT half-duplex capable.
0, link partner not 10BT half-duplex capable.
RO 0
Register 31 (0x1F): Port 1 Control 7 and Status 2
Register 47 (0x2F): Port 2 Control 7 and Status 2
Register 63 (0x3F): Port 3 Control 7 and Status 2
Register 79 (0x4F): Port 4 Control 7 and Status 2
Register 95 (0x5F): Port 5 Control 7 and Status 2
Address Name Description Mode Default
7 PHY Loopback
1, Perform PHY loopback, loop back path as follows:
E.g. set port 1 PHY Loopback (reg. 31, bit 7 = ‘1’)
Use the port 2 as monitor port. The packets will
transfer.
Start: Port 2 receiving (also can start from port
3, 4, 5).
Loopback: PMD/PMA of Port 1’s PHY
End: Por t 2 transmittin g (also can end at Port 3,
4, 5 respect ively).
Setting reg. 47, 63, 79, 95, bit 7 = ‘1’ will perform
PHY loopback on port 2, 3, 4, 5 respectively.
0, Normal Operation.
R/W 0
6 Reserved RO 0
5 PHY Isolate 1, electrical isolation of PHY from MII/RMII and
TX+/TX-.
0, normal operation. R/W 0
4 Soft Reset 1, PHY soft reset. This bit is self clear.
0, normal operation. R/W
(SC) 0
3 Force Link 1, force link in the PHY.
0, normal operation R/W 0
March 12, 2014 72 Revision 1.7
Micrel, Inc.
Port Re gisters (Continued)
Address Name Description Mode Default
2−0 Port Operation Mode
Indication
Indicate the curr ent state of port operation mode:
[000] = Reseved
[001] = still in auto-negotiation
[010] = 10BASE-T half duplex
[011] = 100BASE-TX half duplex
[100] = Reserved
[101] = 10BASE-T full duplex
[110] = 100BASE-TX full duplex
[111] = Reserved
RO 001
Note:
Port Control 12 and 13, 14 and Port Status 1,2 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM regist er definiti on.
Advanced Control Registers
Register s 104 to 109 d efine the s witching en gine’s MAC ad dress. T his 48-bit ad dress is us ed as the sourc e address
in MAC pause control frames.
Address Name Description Mode Default
Register 104 (0x68): MAC Address Register 0
7−0 MACA[47:40] R/W 0x00
Register 105 (0x69): MAC Address Register 1
7−0 MACA[39:32] R/W 0x10
Register 106 (0x6A): MAC Address Register 2
7−0 MACA[31:24] R/W 0xA1
Register 107 (0x6B): MAC Address Register 3
7−0 MACA[23:16] R/W 0xff
Register 108 (0x6C): MAC Address Register 4
7−0 MACA[15:8] R/W 0xff
Register 109 (0X6D): MAC Address Register 5
7−0 MACA[7:0] R/W 0xff
March 12, 2014 73 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Use reg ister s 11 0 and 11 1 to r ea d or writ e data to th e s tatic M AC ad dr ess tab le, VL AN table, dynamic addr e ss tabl e,
or the MIB counters.
Address Name Description Mode Default
Register 110 (0x6E): Indirect Access Control 0
7−5 Reserved Reserved. R/W 000
4 Read High Write Low 1, read cycle.
0, write cycle. R/W 0
3−2 Table Select
00 = static mac address table sele cte d.
01 = VLAN table selected.
10 = dynamic address table selected.
11 = MIB counter selected.
R/W 0
1−0 Indirect Address High Bit 9-8 of indirect addr es s. R/W 00
Register 111 (0x6F): Indirect Access Control 1
7−0 Indire ct Addr e ss Low Bit 7-0 of indirect addr es s. R/W 00000000
Note:
Write to Register 111 will actually trigger a c ommand. Read or write access will be decided by bit 4 of Register 110.
March 12, 2014 74 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
Register 112 (0x70): Indirect Data Register 8
68−64 Indirect Data Bit 68-64 of indirect data. R/W 00000
Register 113 (0x71): Indirect Data Register 7
63−56 Indirect Data Bit 63-56 of indirect data. R/W 00000000
Register 114 (0x72): Indirect Data Register 6
55−48 Indirect Data Bit 55-48 of indirect data. R/W 00000000
Register 115 (0x73): Indirect Data Register 5
47−40 Indirect Data Bit 47-40 of indirect data. R/W 00000000
Register 116 (0x74): Indirect Data Register 4
39−32 Indirect Data Bit 39-32 of indirect data. R/W 00000000
Register 117 (0x75): Indirect Data Register 3
31−24 Indirect D ata Bit of 31-24 of indirect data R/W 00000000
Register 118 (0x76): Indirect Data Register 2
23−16 Indirect Data Bit 23-16 of indirect data. R/W 00000000
Register 119 (0x77): Indirect Data Register 1
15−8 Indirect Data Bit 15-8 of indirect data. R/W 00000000
Register 120 (0x78): Indirect Data Register 0
7−0 Indirect Data Bit 7-0 of indirect data . R/W 00000000
Registe r 1 24 (0x7C): Interrupt Status Register
7–5 Reserved Reserved. RO 000
4 Port 5 Interrupt Status
1, Port 5 interrupt request
0, normal
Note: This bit is set by Port 5 link change. Write a
“1” to clear this bit
RO 0
3 Port 4 Interrupt Status
1, Port 4 interrupt request
0, normal
Note: This bit is set by Port 4 link change. Write a
“1” to clear this bit
RO 0
2 Port 3 Interrupt Status
1, Port 3 interrupt request
0, normal
Note: This bit is set by Port 3 link change. Write a
“1” to clear this bit
RO 0
1 Port 2 Interrupt Status
1, Port 2 interrupt request
0, normal
Note: This bit is set by Port 2 link change. Write a
“1” to clear this bit
RO 0
March 12, 2014 75 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
0 Port 1 Interrupt Status
1, Port 1 interrupt request
0, normal
Note: This bit is set by Port 1 link change. Write a
“1” to clear this bit
RO 0
Register 125 (0x7D): Interrupt Mask Register
7–5 Reserved Reserved. RO 000
4 Port 5 Interrupt Mask
1, Enable P ort 5 interrupt .
0, normal
R/W 0
3 Port 4 Interrupt Mask
1, Enable Port 4 interrupt.
0, normal
R/W 0
2 Port 3 Interrupt Mask
1, Enable Port 3 interrupt.
0, normal
R/W 0
1 Port 2 Interrupt Mask
1, Enable Port 2 interrupt.
0, normal
R/W 0
0 Port 1 Interrupt Mask
1, Enable Port 1 interrupt.
0, normal
R/W 0
The registers 128, 129 can be used to map from 802.1p priority field 0-7 to switch’s four priority queues 0-3, 0x3 is
highest priority queues as priority 3, 0x0 is lowest priority queues as priority 0.
Address Name Description Mode Default
Registe r 1 28 (0x80): Global Control 12
7–6 Tag_0x3
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x3.
R/W 0x1
5–4 Tag_0x2
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x2.
R/W 0x1
3–2 Tag_0x1
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x1.
R/W 0x0
1–0 Tag_0x0
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x0.
R/W 0x0
Register 129 (0x81): Global Control 13
7–6 Tag_0x7
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x7.
R/W 0x3
5–4 Tag_0x6
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x6.
R/W 0x3
3–2 Tag_0x5
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x5.
R/W 0x2
1–0 Tag_0x4
IEEE 802.1p mapping. The value in this field is
used as the frame’s priority when its IEEE 802.1p
tag has a value of 0x4.
R/W 0x2
March 12, 2014 76 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address
Name
Description
Mode
Default
Registe r 1 30 (0x82): Global Control 14
7–6
Pri_2Q[1:0]
(Note that program
Prio_2Q[1: 0] = 01 is not
supported and should be
avoided)
When the 2 Queues configuration is selected, these
Pri_2Q[1:0] bits are used to map the 2-bit result of
IEEE 802.1p from regi ster 128/129 or TOS/DiffServ
from register 144- 159 mapping (for 4 Queues) into
two queues low/high priorities.
2-bit result of IEEE 802.1p or TOS/DiffServ
00 (0) = map to Low priority queue
01 (1) = Prio_2Q[0] map to Low/High priority queue
10 (2) = Prio_2Q[1] map to Low/High priority queue
11 (3) = map to High priority queue
Pri_2Q[1:0] =
00: Result 0,1,2 are low priority. 3 is high priority.
10: Result 0,1 are low priority. 2,3 are high priority
(default).
11: Result 0 is low priority. 1,2,3 are high priority.
R/W 10
5 Reserved N/A Do not change. RO 0
4 Reserved N/A Do not change. RO 0
3–2 Reserved N/A Do not change. RO 01
1 Reserved N/A Do not change. RO 0
0 Reserved N/A Do not change. RO 0.
Registe r 1 31 (0x83): Global Control 15
7 Reserved N/A RO 1
6 Reserved N/A RO 0
5 Unknown unicast packet
forward
1 = enable supporting unknown unicast packet
forward
0 = disable
R/W 0
4–0 Unknown unicast packet
forwar d port map
00000 = filter unknown unicast packet
00001 = forward unknown unicast packet to port 1.
00010 = forward unknown unicast packet to port 2.
00011 = forward unknown unicast packet to port 1,
port 2
……
11111 = broadcast unknown unica st pac ket to all
ports
R/W 00000
March 12, 2014 77 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
Registe r 1 32 (0x84): Global Control 16
7–6 Chip I/O output drive strengt h
select[1:0]
Output drive strength select[1:0] =
00 = 4mA drive strength
01 = 8mA drive strength (default)
10 = 12mA drive strength
11 = 16 mA drive strength
Note:
bit[1] value is the INVERT of the strap value at the
pin.
Bit[0] value is the SAME of the strap value at the
pin
R/W
01
Pin LED[3][0]
strap option.
Pull-down (0):
Select 12mA
drive strength.
Pull-up (1):
Select 8mA
drive strength.
Note: LED[3][0]
has internal
pull-up.
5
Unknown multicast packet
forward (not including IP
multicast packet)
1 = enable supporting unknown multicast packet
forward
0 = disable
R/W 0
4–0 Unknown multicast packet
forwar d port map
00000 = filter unknown multiicast packet
00001 = forward unknown multicast packet to port
1.
00010 = forward unknown multicast packet to port
2.
00011 = forward unknown multicast packet to port
1, port 2
……
11111 = broadcast unknown mult ica st pac ket to all
ports
R/W 00000
Register 133(0x85): Global Control 17
7–6 Reserved RO 00
5 Unknown VID packet forward
1 = enable supporting unknown VID packet forward
0 = disable
R/W 0
4–0 Unknown VID packet forward
port map
00000 = filter uknown VID packet
00001 = forward unknown VID packet to port 1.
00010 = forward unknown VID packet to port 2.
00011 = forward unknown VID packet to port 1, port
2
……
11111 = broadcast unknown VID packet to all ports
R/W 00000
Registe r 1 34 (0x86): Global Control 18
7 Reserved N/A RO 0
6 Self Address Filter Enable
1 = Enable filtering of self-address unicast and
multicast packet
0 = Do not filter self-address packet
Note: The self-address filtering will filter packets on
the egress port , self MAC address is assigned in
the register 104-109.
R/W 0
5 Unknown IP multicast packet
forward
1 = enable supporting unknown IP multicast packet
forward
0 = disable
R/W 0
March 12, 2014 78 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
4–0 Unknown IP multicast packet
forwar d port map
00000 = filter unknown IP multiicast packet
00001 = forward unkn own IP multicast pac ket to
port 1.
00010 = forward unknow n IP multicast pac ket to
port 2.
00011 = forward unkn own IP multicast pac ket to
port 1, port 2
……
11111 = broadcast unknown IP multicast packet to
all ports
R/W 00000
Registe r 1 35 (0x87): Global Control 19
7 Reserved N/A Do not change. RO 0
6 Reserved N/A Do not change. RO 0
5–4 Ingress Rate Limit Period
The unit period for calculating Ingress Rate Limit
00 = 16 ms
01 = 64 ms
1x = 256 ms
R/W 01
3 Queue-based Egress Rate
Limit Enabled
Enable Queue-based Egress Rate Limit
0 = port-base Egress Rate Limit (default)
1 = queue-based Egress Rate Limit
R/W 0
2 Insertion Source Port PVID
Tag Selection Enable
1 = enable source port PVID tag insertion or non-
insertion option on the egress port f or each sour ce
port PVID based on the ports registers control 8.
0 = disable, all pack ets fr om a ny ingress port will be
inserted PVID based on port register control 0 bit 2.
R/W 0
1–0 Reserved N/A Do not change RO 00
Registe r 1 44 (0x90): TOS Priori ty Control Register 0
The Ipv4/ Ipv 6 TOS pr iori ty cont rol r egis ters implem ent a ful ly de coded 64 bi t diff erent iated s ervic es c ode point ( DSCP) r egi ster used to
determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64
possibili ties, and t he singular code that r esults is mapped to the value in the corresponding bit in t he D SC P register.
7–6 DSCP[7:6]
Ipv4 and Ipv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x03
R/W 00
5–4 DSCP[5:4]
Ipv4 and Ipv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x02
R/W 00
3–2 DSCP[3:2]
Ipv4 and Ipv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x01
R/W 00
March 12, 2014 79 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
1–0 DSCP[1:0]
Ipv4 and Ipv6 mapping
The value in this field is used as the frame’s priority
when bits[7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x00
R/W 00
Registe r 1 45 (0x91): TOS Priori ty Control Register 1
7–6 DSCP[15:14] Ipv4 and Ipv6 mapping _ for value 0x07 R/W 00
5–4 DSCP[13:12] Ipv4 and Ipv6 mapping _ for value 0x06 R/W 00
3–2 DSCP[11:10] Ipv4 and Ipv6 mapping _ for value 0x05 R/W 00
1–0 DSCP[9:8] Ipv4 and Ipv6 mapping _ for value 0x04 R/W 00
Registe r 1 46 (0x92): TOS Priori ty Control Register 2
7–6 DSCP[23:22] Ipv4 and Ipv6 mapping _ for v alue 0x0B R/W 00
5–4 DSCP[21:20] Ipv4 and Ipv6 mapping _ for value 0x0A R/W 00
3–2 DSCP[19:18] Ipv4 and Ipv6 mapping _ for value 0x09 R/W 00
1–0 DSCP[17:16] Ipv4 and Ipv6 mapping _ for value 0x08 R/W 00
Registe r 1 47 (0x93): TOS Priori ty Control Register 3
7–6 DSCP[31:30] Ipv4 and Ipv6 mapping _ for value 0x0F R/W 00
5–4 DSCP[29:28] Ipv4 and Ipv6 mapping _ for value 0x0E R/W 00
3–2 DSCP[27:26] Ipv4 and Ipv6 mapping _ for value 0x0D R/W 00
1–0 DSCP[25:24] Ipv4 and Ipv6 mapping _ for value 0x0C R/W 00
Registe r 1 48 (0x94): TOS Priori ty Control Register 4
7–6 DSCP[39:38] Ipv4 and Ipv6 mapping _ for value 0x13 R/W 00
5–4 DSCP[37:36] Ipv4 and Ipv6 mapping _ for value 0x12 R/W 00
3–2 DSCP[35:34] Ipv4 and Ipv6 mapping _ for value 0x11 R/W 00
1–0 DSCP[33:32] Ipv4 and Ipv6 mapping _ for value 0x10 R/W 00
March 12, 2014 80 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Registe r 1 49 (0x95): TOS Priori ty Control Register 5
7–6 DSCP[47:46] Ipv4 and Ipv6 mapping _ for value 0x17 R/W 00
5–4 DSCP[45:44] Ipv4 and Ipv6 mapping _ for value 0x16 R/W 00
3–2 DSCP[43:42] Ipv4 and Ipv6 mapping _ for value 0x15 R/W 00
1–0 DSCP[41:40] Ipv4 and Ipv6 mapping _ for value 0x14 R/W 00
Registe r 1 50 (0x96): TOS Priori ty Control Register 6
7–6 DSCP[55:54] Ipv4 and Ipv6 mapping _ for v alue 0x1B R/W 00
5–4 DSCP[53:52] Ipv4 and Ipv6 mapping _ for value 0x1A R/W 00
3–2 DSCP[51:50] Ipv4 and Ipv6 mapping _ for value 0x19 R/W 00
1–0 DSCP[49:48] Ipv4 and Ipv6 mapping _ for value 0x18 R/W 00
Registe r 1 51 (0x97): TOS Priori ty Control Register 7
7–6 DSCP[63:62] Ipv4 and Ipv6 mapping _ for value 0x1F R/W 00
5–4 DSCP[61:60] Ipv4 and Ipv6 mapping _ for value 0x1E R/W 00
3–2 DSCP[59:58] Ipv4 and Ipv6 mapping _ for value 0x1D R/W 00
1–0 DSCP[57:56] Ipv4 and Ipv6 mapping _ for value 0x1C R/W 00
Registe r 1 52 (0x98): TOS Priori ty Control Register 8
7–6 DSCP[71:70] Ipv4 and Ipv6 mapping _ for value 0x23 R/W 00
5–4 DSCP[69:68] Ipv4 and Ipv6 mapping _ for value 0x22 R/W 00
3–2 DSCP[67:66] Ipv4 and Ipv6 mapping _ for value 0x21 R/W 00
1–0 DSCP[65:64]
Ipv4 and Ipv6 mapping _ for value 0x20
R/W 00
Registe r 1 53 (0x99): TOS Priori ty Control Register 9
7–6 DSCP[79:78] Ipv4 and Ipv6 mapping _ for value 0x27 R/W 00
5–4 DSCP[77:76] Ipv4 and Ipv6 mapping _ for value 0x26 R/W 00
3–2 DSCP[75:74] Ipv4 and Ipv6 mapping _ for value 0x25 R/W 00
1–0 DSCP[73:72] Ipv4 and Ipv6 mapping _ for value 0x24 R/W 00
Registe r 1 54 (0x9A): TOS Priority Control Register 10
7–6 DSCP[87:86] Ipv4 and Ipv6 mapping _ for value 0x2B R/W 00
5–4 DSCP[85:84] Ipv4 and Ipv6 mapping _ for value 0x2A R/W 00
3–2 DSCP[83:82] Ipv4 and Ipv6 mapping _ for value 0x29 R/W 00
1–0 DSCP[81:80] Ipv4 and Ipv6 mapping _ for value 0x28 R/W 00
Registe r 1 55 (0x9B): TOS Priority Control Register 11
7–6 DSCP[95:94] Ipv4 and Ipv6 mapping _ for value 0x2F R/W 00
5–4 DSCP[93:92] Ipv4 and Ipv6 mapping _ for value 0x2E R/W 00
3–2 DSCP[91:90] Ipv4 and Ipv6 mapping _ for value 0x2D R/W 00
1–0 DSCP[89:88] Ipv4 and Ipv6 mapping _ for value 0x2C R/W 00
March 12, 2014 81 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
Registe r 1 56 (0x9C): TOS Priority Control Register 12
7–6 DSCP[103:102] Ipv4 and Ipv6 mapping _ for value 0x33 R/W 00
5–4 DSCP[101:100] Ipv4 and Ipv6 mapping _ for value 0x32 R/W 00
3–2 DSCP[99:98] Ipv4 and Ipv6 mapping _ for value 0x31 R/W 00
1–0 DSCP[97:96] Ipv4 and Ipv6 mapping _ for value 0x30 R/W 00
Registe r 1 57 (0x9D): TOS Priority Control Register 13
7–6 DSCP[111:110] Ipv4 and Ipv6 mapping _ for value 0x37 R/W 00
5–4 DSCP[109:108] Ipv4 a nd Ipv6 mapping _ for value 0x36 R/W 00
3–2 DSCP[107:106] Ipv4 and Ipv6 mapping _ for value 0x35 R/W 00
1–0 DSCP[105:104] Ipv4 and Ipv6 mapping _ for value 0x34 R/W 00
Registe r 1 58 (0x9E): TOS Priority Control Register 14
7–6 DSCP[119:118] Ipv4 and Ipv6 mapping _ for value 0x3B R/W 00
5–4 DSCP[117:116] Ipv4 and Ipv6 mapping _ for value 0x3A R/W 00
3–2 DSCP[115:114] Ipv4 and Ipv6 mapping _ for value 0x39 R/W 00
1–0 DSCP[113:112] Ipv4 and Ipv6 mapping _ for value 0x38 R/W 00
Register 159 (0x9F): TOS Priority Control Register 15
7−6 DSCP[127:126] Ipv4 and Ipv6 mapping _ for value 0x3F R/W 00
5−4 DSCP[125:124] Ipv4 and Ipv6 mapping _ for value 0x3E R/W 00
3−2 DSCP[123:122] Ipv4 and Ipv6 mapping _ for value 0x3D R/W 00
1−0 DSCP[121:120] Ipv4 and Ipv6 mapping _ for value 0x3C R/W 00
Register 165 (0xA5): Fiber Control Regis ter
7−6 Reserved N/A Do not change RO 000
5 FMQ Fiber Mode Enable
1= MQ/RQ device (Default)
0= FMQ device (Fiber mode)
R/W 1
4−0 Reserved N/A Do not change RO 10000
March 12, 2014 82 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
Registe r 1 76 (0xB0): Port 1 Control 8
Registe r 1 92 (0xC0): Port 2 Control 8
Registe r 2 08 (0xD0): Port 3 Control 8
Registe r 2 24 (0xE0): Port 4 Control 8
Register 240 (0xF0): Port 5 Control 8
7−4 Reserved RO 0000
3
Insert Source Port PVID for
Untagged Packet Destination
to Highest Egress Port
Note: Enabled by the register
135 bit 2
Register 176: insert source Port 1 PVID for
untagged fram e at egress Port 5
Register 192: insert source Port 2 PVID for
untagged fram e at egress Port 5
Register 208: insert source Port 3 PVID for
untagged fram e at egress Port 5
Register 224: insert source Port 4 PVID for
untagged fram e at egress Port 5
Register 240: insert source Port 5 PVID for
untagged fram e at egress Port 4
R/W 0
2
Insert Source Port PVID for
Untagged Packet Destination
to Second Highest Egress Port
Note: Enabled by the register
135 bit 2
Register 176: insert source Port 1 PVID for
untagged fram e at egress pPort 4
Register 192: insert source Port 2 PVID for
untagged fram e at egress Port 4
Register 208: insert source Port 3 PVID for
untagged fram e at egress Port 4
Register 224: insert source Port 4 PVID for
untagged fram e at egress Port 3
Register 240: insert source Port 5 PVID for
untagged fram e at egress Port 3
R/W 0
1
Insert Source Port PVID for
Untagged Packet Destination
to Second Lowest Egress Port
Note: Enabled by the register
135 bit 2
Register 176: insert source Port 1 PVID for
untagged fram e at egress Port 3
Register 192: insert source Port 2 PVID for
untagged fram e at egress Port 3
Register 208: insert source Port 3 PVID for
untagged fram e at egress Port 2
Register 224: insert source Port 4 PVID for
untagged fram e at egress Port 2
Register 240: insert source Port 5 PVID for
untagged fram e at egress Port 2
R/W 0
0
Insert Source Port PVID for
Untagged Packet Destination
to Lowest Egress Port
Note: Enabled by the register
135 bit 2
Register 176: insert source Port 1 PVID for
untagged fram e at egress Port 2
Register 192: insert source Port 2 PVID for
untagged fram e at egress Port 1
Register 208: insert source Port 3 PVID for
untagged fram e at egress Port 1
Register 224: insert source Port 4 PVID for
untagged fram e at egress Port 1
Register 240: insert source Port 5 PVID for
untagged fram e at egress Port 1
R/W 0
March 12, 2014 83 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
Registe r 1 77 (0xB1): Port 1 Control 9
Registe r 1 93 (0xC1): Port 2 Control 9
Registe r 2 09 (0xD1): Port 3 Control 9
Register 225 (0xE1): Port 4 Control 9
Registe r 2 41 (0xF1): Port 5 Contro l 9
7−2 Reserved RO 0000000
1 4 Queue Split Enable
This bit in combination with Register16/32/48/64/80
bit 0 will select the split of ½/4 queues:
{Register177 bit 1, Register16 bit 0} =
11, reserved.
10, the port output queue is split into four priority
queues or if map 802.1p to priority 0-3 mode.
01, the port output queue is split into two priority
queues or if map 802.1p to priority 0-3 mode.
00, single output queue on the port. There is no
priority differentiation even though packets are
classified into high and low priority.
R/W 0
0 Enable Dropping Tag
0 = Normal
1 = enable the drop receiv ed t agged pack ets
R/W 0
March 12, 2014 84 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
Registe r 1 78 (0xB2): Port 1 Control 10
Registe r 1 94 (0xC2): Port 2 Control 10
Registe r 2 10 (0xD2): Port 3 Control 10
Registe r 2 26 (0xE2): Port 4 Control 10
Registe r 2 42 (0xF2): Port 5 Contro l 10
7 Enable Port Transmit Queue 3
Ratio
0, strict priority, will trans mit all the packets from
this priority queue 3 before transmit lower priority
queue.
1, bit[6:0] reflect the packet number allow to
transmit from this priority queue 3 within a certain
time.
R/W 1
6−0
Port Transmit Queue 3
Ratio[6:0]
Packet number for Transmit Queue 3 for highest
priority packets in four queues mode.
R/W 0001000
Registe r 1 79 (0xB3): Port 1 Control 11
Registe r 1 95 (0xC3): Port 2 Control 11
Registe r 2 11 (0xD3): Port 3 Control 11
Registe r 2 27 (0xE3): Port 4 Control 11
Register 243 (0xF3): Port 5 Control 11
7 Enable Port Transmit Queue 2
Ratio
0, strict priority, will transmit all the packets from
this priority queue 2 before transmit lower priority
queue.
1, bit[6:0] reflect the packet number allow to
transmit from this priority queue 1 w ithin a cer tai n
time.
R/W 1
6−0 Port Transmit Queue 2
Ratio[6:0]
Packet number for Transmit Queue 2 for hig h/low
priority packets in high/low priority packets in four
queues mode.
R/W 0000100
Registe r 1 80 (0xB4): Port 1 Control 12
Register 196 (0xC4): Port 2 Control 12
Registe r 2 12 (0xD4): Port 3 Control 12
Registe r 2 28 (0xE4): Port 4 Control 12
Registe r 2 44 (0xF4): Port 5 Contro l 12
7 Enable Port Transmit Queue 1
Rate
0, strict priority, wil l transmit all the packe ts from
this priority queue 1 before transmit lower priority
queue.
1, bit[6:0] reflect the packet number allow to
transmit from this priority queue 1 within a certain
time.
R/W 1
6−0 Port Transmit Queue 1
Ratio[6:0]
Packet number for Transmit Queue 1 for low/high
priority packets in four queues mode and high
priority packets in two queues mode.
R/W 0000010
March 12, 2014 85 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
Registe r 1 81 (0xB5): Port 1 Control 13
Registe r 1 97 (0xC5): Port 2 Control 13
Register 213 (0xD5): Por t 3 Control 13
Registe r 2 29 (0xE5): Port 4 Control 13
Registe r 2 45 (0xF5): Port 5 Contro l 13
7 Enable Port Transmit Queue 0
Rate
0, strict priority, wil l transmit all the packe ts from
this priority queue 0 before transmit lower priority
queue.
1, bit[6:0] refl ect the pac ket number all ow to
transmit from this priority queue 0 within a certain
time.
R/W 1
6−0 Port Transmit Queue 0
Ratio[6:0]
packet number for Transmit Queue 0 for lowest
priority packets in four queues mode and low
priority packets in two queues mode.
R/W 0000001
Registe r 1 82 (0xB6): Port 1 Rate Limit Control
Registe r 1 98 (0xC6): Port 2 Rate Limit Control
Registe r 2 14 (0xD6): Port 3 Rate Limit Control
Registe r 2 30 (0xE6): Port 4 Rate Limit Control
Register 246 (0xF6): Port 5 Rate Limit Control
7−5 Reserved RO 000
4 Ingress Rate Lim it Flow
Control Enable
1 = Flow Control is asserted if the port’s receive
rate is exceeded.
0 = Flow Control is not asserted if the port’s receive
rate is exceeded.
R/W 0
3−2 Limit Mode
Ingress Limit Mode
These bits determine what kinds of frames are
limited and counted against ingress rate limiting.
= 00, limit and count all frames.
= 01, limit and count Broadca st, M ultica st, and
flooded unicast frames.
= 10, limit and count Broadcast and Multicast
frames only.
= 11, limit and count Broadcast frames only.
R/W 00
1 Count IFG
Count IFG bytes
= 1, each frame’s minimum inter frame gap.
(IFG) bytes (12 per frame) are included in Ingress
and Egress rate limiting calculations.
= 0, IFG bytes are not counted.
R/W 0
0 Count Pre
Count Preamble by tes
= 1, each frame’s preamble bytes (8 per
frame) are included in Ingress and Egress rate
limiting calculations.
= 0, preamble bytes are not counted.
R/W 0
March 12, 2014 86 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1
Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1
Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1
Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1
Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1
7 Reserved RO 0
6−0 Port Based Priorit y 0 Ingress
Limit
Ingress data rate limit for priority 0 frames
Ingress traffic from this port is shaped according to
the Data Rate Selected Table. See the table
following the end of Egress limit control registers.
R/W 0000000
Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2
Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2
Register 216 (0xD8): Port 3 Priority 1 Ingress Lim it Control 2
Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2
Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2
7 Reserved RO 0
6−0 Port Based Priority 1 Ingress
Limit
Ingress data rate limit for priority 1 frames
Ingress traffic from this port is shaped according to
the Data Rate Selected Table. See the table
following the end of Egress limit control registers.
R/W 0000000
Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3
Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3
Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3
Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3
Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3
7 Reserved RO 0
6−0 Port-Based Priority 2 Ingress
Limit
Ingress data rate limit for priority 2 frames
Ingress traffic from this port is shaped according to
the Data Rate Selected Table. See the table follow
the end of Egress limit contr ol regis ter s .
R/W 0000000
Register 186 (0xBA): Port 1 Priority 3 Ingress Limi t Control 4
Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4
Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4
Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4
Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4
7 Reserved RO 0
6−0 Port-Based Priority 3 Ingress
Limit
Ingress data rate limit for priority 3 frames
Ingress traffic from this port is shaped according to
the Data Rate Selected Table. See the table follow
the end of Egress lim it contr ol r egist ers .
R/W 0000000
March 12, 2014 87 Revision 1.7
Micrel, Inc.
Advanced Control Registers (Continued)
Address Name Description Mode Default
Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1
Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1
Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1
Registe r 2 35 (0xEB): Port 4 Queue 0 Egress Limit Control 1
Registe r 2 51 (0xFB): Port 5 Queue 0 Egre ss Limit Control 1
7 Reserved RO 0
6−0 Port Queue 0 Egress Limit
Egress data rate limit for priority 0 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
In four queues mode, it is lowest priority.
In two queues mode, it is low priority.
R/W 0000000
Register 188 (0xBC) : Port 1 Queue 1 Egress Limit Control 2
Register 204 (0xCC) : Port 2 Queue 1 Egress Limit Control 2
Register 220 (0xDC) : Port 3 Queue 1 Egress Limit Control 2
Register 236 (0xEC) : Port 4 Queue 1 Egress Limit Control 2
Register 252 (0xFC) : Port 5 Queue 1 Egress Lim it Control 2
7 Reserved RO 0
6−0 Port Queue 1 Egress Limit
Egress data rate limit for priority 1 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
In four queues mode, it is low/high priority.
In two queues mode, it is high priority.
R/W 0000000
Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3
Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3
Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3
Registe r 2 37 (0xED): Port 4 Queue 2 Egress Limit Control 3
Registe r 2 53 (0xFD): Port 5 Queue 2 Egre ss Limit Control 3
7 Reserved RO 0
6−0 Port Queue 2 Egress Limit
Egress data rate limit for priority 2 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
In four queues mode, it is high/low priority.
R/W 0000000
March 12, 2014 88 Revision 1.7
Micrel, Inc.
Advanced Co ntrol Registers (Continue d )
Address Name Description Mode Default
Register 190 (0xBE) : Port 1 Queue 3 Egress Limit Control 4
Register 206 (0xCE) : Port 2 Queue 3 Egress Limit Control 4
Register 222 (0xDE) : Port 3 Queue 3 Egress Limit Control 4
Register 238 (0xEE): Port 4 Queue 3 Egres s Limit Control 4
Registe r 2 54 (0xFE): Port 5 Queue 3 Egress Limit Control 4
7 Reserved RO 0
6−0 Port Queue 3 Egress Limit
Egress data rate limit for priority 3 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Selected Table. See the
table follow the end of Egress limit control registers.
In four queues mode, it is highest priority.
R/W 0000000
Notes:
1. In the port priority 0−3 ingress rate limit mode, will need to set all related ingress/egress ports to two queues or four queues mode.
2. In the port queue 0−3 egress rate limit mode, the highest priority get exact rate limit based on the rate select table, other prioriti es packets
rate are based upon the ratio of the port register control 10/11/12/13 when use more than one egress queue per port.
March 12, 2014 89 Revision 1.7
Micrel, Inc.
Data Rate Selection Table in 100BT
Rate for 100BT mode
Priority/Queue 0-3 Ingress/egress limit Control Register bit[6:0] = decimal
1 Mbps <= rate <= 99 Mbps
rate(decimal integer 1-99)
rate = 100 Mbps
0 or 100 (decimal), ‘0’ is default value
Less than 1Mbps see as below
Decimal
64 Kbps
7’d101
128 Kbps
7’d102
192 Kbps
7’d103
256 Kbps
7’d104
320 Kbps
7’d105
384 Kbps
7’d106
448 Kbps
7’d107
512 Kbps
7’d108
576 Kbps
7’d109
640 Kbps
7’d110
704 Kbps
7’d111
768 Kbps
7’d112
832 Kbps
7’d113
896 Kbps
7’d114
960 Kbps
7’d115
Table 13. 100BT Rate Selection for the Rate limit
Data Rate Selection Table in 10BT
Rate for 10BT mode
Priority/Queue 0-3 Ingress/egress limit Control Register bit[6:0] = de cimal
1 Mbps <= rate <= 9 Mbps
rate(decimal integer 1-9)
rate = 10 Mbps
0 or 10 (decimal), ‘0’ is default value
Less than 1Mbps see as below
Decimal
64 Kbps
7’d101
128 Kbps
7’d102
192 Kbps
7’d103
256 Kbps
7’d104
320 Kbps
7’d105
384 Kbps
7’d106
448 Kbps
7’d107
512 Kbps
7’d108
576 Kbps
7’d109
640 Kbps
7’d110
704 Kbps
7’d111
768 Kbps
7’d112
832 Kbps
7’d113
896 Kbps
7’d114
960 Kbps
7’d115
Table 14. 10BT Rate Selection for the Rate Limit
March 12, 2014 90 Revision 1.7
Micrel, Inc.
Address Name Description Mode Default
Register 191(0xBF): Testing Register
7−0 Reserved N/A RO 0x80
Register 207(0xCF): Reserved Control Register
7−0 Reserved N/A Do not change. RO 0x15
Register 223(0xDF): Test Register 2
7−0 Reserved R/W 0x0C
Register 239(0xEF): Test Register 3
7−0 Reserved N/A Do not change. RO 0x32
Register 255(0xFF): Testing Register4
7 Reserved N/A Do not change. RO 0
6 Invert phase of SMTXC clock
input for SW5-RMII
(Used for KSZ8895RQ only)
1 = Invert the phase of SMTXC clock input in RMII
mode, set this bit at normal mode device when
connect two devices with SW5-RMII back to back
connection case only. Please see stra p pin LED2_ 2
for normal mode.
0 = normal phase if SMTXC clock input
Note: MQ/FMQ are reserved with read only for this
bit.
R/W 0
5−0 Reserved N/A Do not change. RO 000000
March 12, 2014 91 Revision 1.7
Micrel, Inc.
Static MAC Address Table
KSZ8895MQ/RQ/FMQ has a static and a dynamic address table. When a DA look -up is requested, both tables will
be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is
searched for aging, migration, and learning purposes. The static DA look-up result will have precedence over the
dynamic DA look-up result. If there are DA matches in both tables, the result f rom the static table will be used. T he
static ta ble can onl y be access ed and control led by an ex ternal SPI m aster (usual ly a process or). The ent ries in the
static table will not be aged out by KSZ8895MQ/RQ/FMQ. An external device does all addition, modification and
deletion.
Note:
Register bit assignments are different for static MAC table reads and static MAC table write, as shown in Table 15.
Address Name Description Mode Default
Format of Static MAC Table for Reads (32 entries)
63−57 FID
Filter VLAN ID, representing one of the 128 active
VLANs.
RO 0000000
56 Use FID
1, use (FID+MAC) to look-up in static table.
0, use MAC only to look-up in static table.
RO 0
55 Reserved Reserved. RO N/A
54 Override
1, override spanning tree “transmit enable = 0” or
“receive enable = 0* setting. This bit is used for
spanning tree implementation.
0, no override.
RO 0
53 Valid
1, this entry is valid, the look-up result will be used.
0, this entry is not valid.
RO 0
52−48 Forwarding Ports
The 5 bits control the forward ports, example:
00001, forward to Port 1
00010, forward to Port 2
…..
10000, forward to Port 5
00110, forward to Port 2 and Port 3
11111, broadcasting (excluding the ingress port)
RO 00000
47−0 MAC Address (DA) 48 bit MAC address. RO 0x0
Format of Static MAC Table for Writes (32 entries)
62−56 FID
Filter VLAN ID, representing one of the 128 active
VLANs.
W 0000000
55 Use FID
1, use (FID+MAC) to look-up in static table.
0, use MAC only to look-up in static table.
W 0
54 Override
1, override spanning tree “transmit enable = 0” or
“receive ena ble = 0” setting. T his bit is used for
spanning tree implementation.
0, no override.
W 0
53 Valid
1, this entry is valid, the look-up result will be used.
0, this entry is not valid.
W 0
52−48 Forwarding Ports
The 5 bits control the forward ports, example:
00001, forward toPort 1
00010, forward to Port 2
.....
10000, forward to Port 5
00110, forward to Port 2 and Port 3
11111, broadcasting (excluding the ingress port)
W 00000
47−0 MAC Address (DA) 48-bit MAC address. W 0x0
Table 15. Stat ic MAC Address Table
March 12, 2014 92 Revision 1.7
Micrel, Inc.
Examples:
(1) Static Address Table Read (read the 2nd entry)
Write to Register 110 with 0x10 (read static table selected)
Write to Register 111 with 0x1 (trigger the read operation)
Then
Read Register 113 (63-56)
Read Register 114 (55-48)
Read Register 115 (47-40)
Read Register 116 (39-32)
Read Register 117 (31-24)
Read Register 118 (23-16)
Read Register 119 (15-8)
Read Register 120 (7-0)
(2) Static Address Table Write (write the 8th entry)
Write to Register 110 with 0x10 (read static table selected)
Write Register 113 (62-56)
Write Register 114 (55-48)
Write Register 115 (47-40)
Write Register 116 (39-32)
Write Register 117 (31-24)
Write Register 118 (23-16)
Write Register 119 (15-8)
Write Register 120 (7-0)
Write to Register 110 with 0x00 (write static table selected)
Write to Register 111 with 0x7 (trigger the write operation)
March 12, 2014 93 Revision 1.7
Micrel, Inc.
VLAN Table
The VLAN table is used f or VLAN tabl e look-up. If 802 .1q VLAN m ode is enabled (Register 5 b it 7 = 1), this table is
used to retri eve VLAN inf orm ation that is assoc iated with th e ingress packet. T here are three f ields for FID (filter ID),
Valid, and VL AN member ship in the VL AN t ab le . The three f ields must be initia li zed before the table is used. T her e is
no VID field because 4096 VIDs are used as a dedicated memory address index into a 1024x52-bit memory space.
Each entr y has four VLANs. Each VLAN has 13 bits. Four VLANs need 52 bits. There are a total of 1024 entries to
support a total of 4096 VLAN IDs by using dedicated memory address and data bits. Refer to Table 17 for details.
FID has 7-bits to support 128 active VLANs.
Address Name Description Mode
Initial Value
suggestion
Format of Static VLAN Table (Support Max 4096 VLAN ID entries and 128 Active VLANs)
12 Valid
1, the entry is valid.
0, entry is invalid.
R/W 0
11−7 Membership
Specifies which ports are mem bers of the VLAN.
If a DA look-up fails (no match in both static and
dynamic tables), the packet associated with this VLAN
will be forwarded to ports specified in this field.
E.g., 11001 means Ports 5, 4, and 1 are in this VLAN.
R/W 11111
6−0 FID
Filter ID. KSZ8895MQ/RQ/FMQ supports 128 act iv e
VLANs represented by these seven bit fields. FID is the
mapped ID. If 802.1q VLAN is enabled, the loo k-up will
be based on FID+DA and FID+SA.
R/W 0
Table 16. VLAN Table
If 802.1q VLAN mode is enabled, KSZ8895MQ/RQ/FMQ assigns a VID to every ingress packet when the packet is
untagge d or tagged with a nul l VID, the pack et is assi gned with t he default port VID of the ingres s port. I f the p acket
is tagged with non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up based
on VID number with its dedicated memory address and data bits. If the entry is not valid in the VLAN table, the
pack et is dr oppe d an d no a ddr es s lear n in g occ ur s. I f the en try is valid, th e F ID is ret rie ved. T he F ID +D A an d F ID+ SA
lookups in M AC tab les are perform ed. T he FID +DA look -up deter m ines the f orwarding ports. If FID+D A fails for look-
up in the MAC table, the packet is broadcast to all the members or specified members (excluding the ingress port)
based on the VLAN table. If FID+SA fails, the FID+SA is learned. To communicate between different active VLANs,
set the same FID; otherwise set a different FID.
The VLAN table configuration is organized as 1024 VLAN sets, each VLAN set consists o f four VLAN entries, to
support up to 4096 VLAN entries. Each VLAN set has 52 bits and should be read or written at the same time
specified by the indirect address.
The VLAN entries in the VLAN set are mapped to indirect data registers as follow:
• Entry0[12:0] maps to the VLAN set bits[12-0] {register119[4:0], register120[7:0]}
• Entry1[12:0] maps to the VLAN set bits[25-13]{register117[1:0], register118[7:0], register119[7:5]}
• Entry2[12:0] maps to the VLAN set bits[38-26]{register116[6:0], register117[7:2]}
• Entry3[12:0] maps to the VLAN set bits[51-39]{register114[3:0], register115[7:0], register116[7]}
In order to read one VLAN entry, the VLAN set is read first and the specific VLAN entry information can be extracted.
To update any VLAN entry, the VLAN set is read first then only the desired VLAN entry is updated and the whole
VLAN set is written back. The FID in the VLAN table is 7-bit, so the VLAN table supports unique 128 flow VLAN
groups. Each VLAN set address is 10 bits long (Maximum is 1024) in the indirect address register 110 and 111, the
bit[9-8] of VLAN set address is at bit[1-0] of register 110, and the bit[7-0] of VL AN s et address is at bit[7-0] of r egister
111. Each Write and Read can access up to four consecutive VLAN entries.
March 12, 2014 94 Revision 1.7
Micrel, Inc.
Examples:
(1) VLAN Table Read (read the VID = 2 entry)
Write the indirect control and address registers first
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x0 (trigger the read operation for VID = 0, 1, 2, 3 entries)
Then read the indirect data registers bits[38-26] for VID = 2 entry
Read Register 116 (0x74), (register116[6:0] are bits 12-6 of VLAN VID = 2 entry)
Read Register 117 (0x75), (register117[7:2] are bits 5-0 of VLAN VID = 2 entry)
(2) VLAN Table Write (write the VID = 10 entry)
Read the VLAN set that contains VID = 8, 9, 10, 11.
Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the read operation and VID = 8, 9, 10, 11 indirect address)
Read the VLAN set first by the indirect data registers 114, 115, 116, 117, 118, 119, 120.
Modify the indirect data registers bits[38-26] by the register 116 bit[6-0] and register 117 bit[7-2] as follows:
Write to Register 116 (0x74), (register116[6:0] are bits 12-6 of VLAN VID = 10 entry)
Write to Register 117 (0x75), (register117[7:2] are bits 5-0 of VLAN VID = 10 entry)
Then write the indirect control and address registers
Write to Register 110 (0x6E) with 0x04 (write VLAN table selected)
Write to Register 111 (0x6F) with 0x02 (trigger the write operation and VID = 8, 9, 10, 11 indirect
address)
Table 17 shows the relationship of the indirect address/data registers and VLAN ID.
Indirect Address
high/low bit[9-0]
for VLAN sets
Indirect Data Registers
Bits for each VLAN
entry
VID
Numbers VID bit[12-2] in V LAN
Tag VID bit[1-0] in V LAN Tag
0
Bits[12-0]
0
0
0
0
Bits[25-13]
1
0
1
0
Bits[38-26]
2
0
2
0
Bits[51-39]
3
0
3
1
Bits[12-0]
4
1
0
1
Bits[25-13]
5
1
1
1
Bits[38-26]
6
1
2
1
Bits[51-39]
7
1
3
2
Bits[12-0]
8
2
0
2
Bits[25-13]
9
2
1
2
Bits[38-26]
10
2
2
2
Bits[51-39]
11
2
3
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1023
Bits[12-0]
4092
1023
0
1023
Bits[25-13]
4093
1023
1
1023
Bits[38-26]
4094
1023
2
1023
Bits[51-39]
4095
1023
3
Table 17. VLAN ID and Indirect Registers
March 12, 2014 95 Revision 1.7
Micrel, Inc.
Dynamic MAC Address Table
This table is read only. The contents are maintained by the KSZ8895MQ/RQ/FMQ only.
Address Name Description Mode Default
Format of Dynamic MAC Address Table (1K entries)
71 MAC Empty
1, there is no valid entry in the table.
0, there are valid entries in the table.
RO 1
70−61 No of Valid Entries
Indicates how many valid entries in the table.
0x3ff means 1K entries
0x1 and bit 71 = 0: means 2 entries
0x0 and bit 71 = 0: means 1 entry
0x0 and bit 71 = 1: means 0 entry
RO 0
60-59 Time Stamp 2-bit counters for inte rnal aging RO
58-56 Source Port
The source port where FID+MAC is learned.
000 Port 1
001 Port 2
010 Port 3
011 Port 4
100 Port 5
RO 0x0
55 Data Ready
1, The entry is not ready, retry until this bit is set to 0.
0, The entry is ready.
RO
54−48 FID Filter ID. RO 0x0
47−0 MAC Address 48-bit MAC address. RO 0x0
Table 18. Dynamic MAC Address Table
Examples:
(1) Dynamic MAC Address Table Read (read the 1st entry), and retrieve the MAC table size
Write to Register 110 with 0x18 (read dynamic table selected)
Write to Register 111 with 0x0 (trigger the read operation) and then
Read Register 112 (71-64)
Read Register 113 (63-56); // the above two registers show # of entries
Read Register 114 (55-48) // if bit 55 is 1, restart (reread) from this register
Read Register 115 (47-40)
Read Register 116 (39-32)
Read Register 117 (31-24)
Read Register 118 (23-16)
Read Register 119 (15-8)
Read Register 120 (7-0)
(2) Dynamic MAC Address Table Read (read the 257th entry), without retrieving # of entries information
Write to Register 110 with 0x19 (read dynamic table selected)
Write to Register 111 with 0x1 (trigger the read operation) and then
Read Register 112 (71-64)
Read Register 113 (63-56)
Read Register 114 (55-48) // if bit 55 is 1, restart (reread) from this register
Read Register 115 (47-40)
Read Register 116 (39-32)
Read Register 117 (31-24)
Read Register 118 (23-16)
Read Register 119 (15-8)
Read Register 120 (7-0)
March 12, 2014 96 Revision 1.7
Micrel, Inc.
MIB (Management Information Base) Counters
The MIB counters are provided on per port basis. These counters are read using indirect memory access as below:
For Port 1
Offset Counter Nam e Description
0x0 RxLoPriorityByte Rx lo-priority (default) octet count including bad packets.
0x1 RxHiPriorityByte Rx hi-priority oct et count inc luding bad packets.
0x2 RxUndersizePkt Rx undersize packets w/good CR C .
0x3 RxFragments Rx fragment packets w /bad CRC, s ymbol err ors or ali gnment err ors.
0x4 RxOversize Rx oversize packets w/good CRC ( max: 1536 or 15 22 bytes).
0x5 RxJabbers
Rx pack ets longer than 1522B w/either CRC er rors, al ignment errors, or symbol errors (depends
on max packet si ze setti ng) or Rx pack ets longer than 1916B only.
0x6 RxSymbolError Rx packets w/ invali d data symb ol and legal preamble, packet size.
0x7 RxCRCerror
Rx pack ets within (64,1522) bytes w /an integr al number of bytes and a bad C RC (upper limit
depends on max packet si ze setting).
0x8 RxAlignmentError
Rx pack ets within (64,1522) bytes w /a non-integral number of bytes and a bad CRC (upper limit
depends on max packet si ze setting).
0x9 RxControl8808Pkts The number of MAC control frames r eceived by a port with 88-08h i n EtherType field.
0xA RxPausePkts
The number of PAUSE frames received by a port. PAUS E frame is qualified wi th EtherType (88-
08h), DA, control opcode (00-01), data length (64B min) , and a valid CRC.
0xB RxBroadcast Rx good broadcast packets (not including errored broadcast packets or valid mul ticast packets).
0xC RxMulticast
Rx good mul ticast packets (not inc luding MAC control frames , errored multic ast pack ets or vali d
broadcast packets).
0xD RxUnicast Rx good unicast packets.
0xE Rx64Octets Total Rx packets (bad pac kets incl uded) that were 64 octets in length.
0xF Rx65to127Octets Total Rx packets (bad packets included) that are between 65 and 127 octets in length.
0x10 Rx128to255Octets Total Rx packet s (bad packets included) that are between 128 and 255 octet s in lengt h.
0x11 Rx256to511Octets Total Rx packet s (bad packets included) that are betwe en 256 and 51 1 octets in lengt h.
0x12 Rx512to1023Octets Tot al Rx pack ets (bad packets included) that are between 512 a nd 1023 octets i n length.
0x13 Rx1024to1522Octets
Total Rx packets (bad packets included) that are betwe en 1024 and 1 522 octets in lengt h (upper
limit depends on max pack et size setting).
0x14 TxLoPriorityByte Tx lo-prior ity good octet count , includi ng P AU SE packets.
0x15 TxHiPriorityByte Tx hi-prior ity good octet count , includi ng PA U SE pack ets.
0x16 TxLateCollision The number of times a collision is detected later than 512 bit-times int o the Tx of a packet.
0x17 TxPausePkts The number of PAUSE frames transmitted by a port.
0x18 TxBroadcastPkts Tx good broadcast packets (not including er rored broadcast or valid multic ast packets).
0x19 TxMulticastPkts Tx good multicast packets (not including errored multicast packets or val id broadcast packets).
0x1A TxUnicastPkts Tx good unic ast packets.
0x1B TxDeferred Tx packets by a port for whic h the 1st Tx attempt is delayed due to the busy medium.
0x1C TxTotalCollision Tx total col lision, half-duplex only.
0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive coll isions.
0x1E TxSingleCollision Succes sfully Tx frames on a port for which Tx is inhi bited by exactly one coll ision.
0x1F TxMultipleCollision Successfully Tx fr am es on a port for which Tx is inhi bited by more than one collision.
Table 19. Port1 MIB Counter Indirect Memory Offerts
March 12, 2014 97 Revision 1.7
Micrel, Inc.
For port 2, the base is 0x20, same offset definition (0x20-0x3f)
For port 3, the base is 0x40, same offset definition (0x40-0x5f)
For port 4, the base is 0x60, same offset definition (0x60-0x7f)
For port 5, the base is 0x80, same offset definition (0x80-0x9f)
Address Name Description Mode Default
Format of Per Port MIB Counters (16 entries)
31 Overflow
1, Counter overflow.
0, No Counter overflow.
RO 0
30 Count Valid
1, Counter value is valid.
0, Counter value is not valid.
RO 0
29−0 Counter Values Counter value. RO 0
Table 20. Format of “Per Port” MIB Counter
Offset Counter Name Description
0x100 Port1 Tx Drop Packets Tx packets dropped due to lack of resources.
0x101 Port2 Tx Drop Packets Tx packets dropped due to lack of resources.
0x102 Port3 Tx Drop Packets Tx packets dropped due to lack of resources.
0x103 Port4 Tx Drop Packets Tx packets dropped due to lack of resources.
0x104 Port5 Tx Drop Packets Tx packets dropped due to lack of resources.
0x105 Port1 Rx Drop Packets Rx packets dropped due to lack of resources.
0x106 Port2 Rx Drop Packets Rx packets dropped due to lack of resources.
0x107 Port3 Rx Drop Packets Rx packets dropped due to lack of resources.
0x108 Port4 Rx Drop Packets Rx packets dropped due to lack of resources.
0x109 Port5 Rx Drop Packets Rx packets dropped due to lack of resources.
Table 21. All Port Dropped Packet MIB Counters
Address Name Description Mode Default
Format of All Port Dropped Packet MIB Counters
30−16 Reserved Reserved. N/A N/A
15−0 Counter Values Counter value. RO 0
Table 22. Format of “All Dropped Packet” MIB Counter
Note:
All port dropped packet MIB counters do not indicat e overflow or validity; theref ore t he application must keep track of overflow and valid
conditions.
March 12, 2014 98 Revision 1.7
Micrel, Inc.
The KSZ8895MQ/RQ/FMQ provides a total of 34 MIB counters per port. These counters are used to monitor the port
detail activity for network management and maintenance. These MIB counters are read using indirect memory
access, per the following examples.
Programming Examples:
(1) MIB counter read (read port 1 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counters selected)
Write to Register 111 with 0xe (trigger the read operation)
Then
Read Register 117 (counter value 31-24)
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23-16)
Read Register 119 (counter value 15-8)
Read Register 120 (counter value 7-0)
(2) MIB counter read (read port 2 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counter selected)
Write to Register 111 with 0x2e (trigger the read operation)
Then
Read Register 117 (counter value 31-24)
//If bit 31 = 1, there was a counter overflow
//If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23-16)
Read Register 119 (counter value 15-8)
Read Register 120 (counter value 7-0)
(3) MIB counter read (read port 1 tx drop packets)
Write to Register 110 with 0x1d
Write to Register 111 with 0x00
Then
Read Register 119 (counter value 15-8)
Read Register 120 (counter value 7-0)
Note:
To read out all the counters, the best performance over the SPI bus is (160+3) × 8 × 80 = 104us, where there are 160 registers , 3 overhead, 8
clocks per access, at 12.5MHz. In the heaviest conditi on, the byte counter will overflow in 2 minutes. It is recomm ended that the software read all
the counters at least every 30 seconds. The per port MIB counters are designed as “read clear.” A per port MIB counter will be cleared after it is
accessed. All port dropped packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid
conditi ons on these counters.
March 12, 2014 99 Revision 1.7
Micrel, Inc.
MIIM Registers
All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping
mechanisms are used f or MIIM and S PI. The “ PHYA D” def ined in IEEE is ass igned as “ 0x1” f or Port 1, “0x2” f or Port
2, “0x3” for Port 3, “0x4” for Port 4, and “0x5” for Port 5. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh)
and 0x1F (1fh).
Address Name Description Mode Default
Registe r 0 h : MII Control
15 Soft Reset
1, PHY soft reset.
0, Normal operation.
R/W
(SC)
0
14 Loop Back
1, Perform MAC loopback, loop back path as follows:
Assume the loop-back is at Port 1 MAC, Port 2 is the
monitor port.
Port 1 MAC Loopback (Port 1 reg. 0, bit 14 = ‘1’)
Start: RXP2/RXM2 (Port 2). Can also start from
port 3, 4, 5
Loopback: MAC/PHY interface of Port 1’s MAC
End: TXP2/TXM2 (Port 2). Can also end at
Ports 3, 4, 5 respectiv ely
Setting address ox3,4,5 reg. 0, bit 14 = ‘1’ will
perform MAC loopback on Ports 3, 4, 5 respectively.
0, Normal Operation.
R/W 0
13 Force 100
1, 100Mbps.
0, 10Mbps.
R/W 1
12 AN Enable
1, Auto-negotiation enabled.
0, Auto-negotiation disabled.
R/W 1
11 Power Down
1, Power down.
0, Normal operation.
R/W 0
10 PHY Isolate
1, Electrical PHY isolation of PHY from Tx+/Tx-.
0, Normal operation.
R/W 0
9 Restar t AN
1, Restart Auto-negotiation.
0, Normal operation.
R/W 0
8 Force Full Duplex
1, Full duplex.
0, Half duplex .
R/W 0
7 Collision Test Not supported. RO 0
6 Reserved RO 0
5 Hp_mdix
1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode
R/W 1
4 Force MDI
1, Force to MDI when dis abl e auto M D I/M DI -X.
0, Force to MDI-X when disable auto MDI/MDI-X.
R/W 0
3 Disable A uto MDI/MDI-X
1, Disable auto MDI/MDI-X.
0, Enable auto MD I/M D I-X.
R/W 0
2 Disable far End fault
1, Disable far end fault detection.
0, Normal operation.
R/W 0
1 Disable Transmit
1, Disable transmit.
0, Normal operation.
R/W 0
0 Disable LED
1, Disable LED.
0, Normal operation.
R/W 0
March 12, 2014 100 Revision 1.7
Micrel, Inc.
MIIM Registers (Continued)
Address Name Description Mode Default
Registe r 1 h : MII Status
15 T4 Capable 0, Not 100 BASET4 capable. RO 0
14 100 Full Capable
1, 100BASE-TX full-duplex capable.
0, Not capable of 100BASE-TX full-duplex.
RO 1
13 100 Half Capable
1, 100BASE-TX half-duplex capable.
0, Not 100BASE-TX half-duplex capable.
RO 1
12 10 Full Capable
1, 10BASE-T full-duplex capable.
0, Not 10BASE-T full-duplex capable.
RO 1
11 10 Half Capable
1, 10BASE-T half-duplex capable.
0, 10BASE-T half-duplex capable.
RO 1
10−7 Reserved RO 0
6 Preamble Suppressed Not supported. RO 0
5 AN Complete
1, Auto-negotiation complete.
0, Auto-negotiation not completed.
RO 0
4 far End fault
1, far end fault detected.
0, No far end fault detected.
RO 0
3 AN Capable
1, Auto-negotiation capable.
0, Not auto-negotiat ion cap abl e.
RO 1
2 Link Status
1, Link is up.
0, Link is dow n.
RO 0
1 Jabber Test Not supported. RO 0
0 Extended Capable 0, Not extended register capable. RO 0
Register 2h: PHYID HIGH
15−0 Phyid High High order PHYID bits. RO 0x0022
Registe r 3 h : PHYID LOW
15−0 Phyid Low Low order PHYID bits. RO 0x1450
Registe r 4 h : Advertisement Ability
15 Next Page Not supported. RO 0
14 Reserved RO 0
13 Remote fault Not supported. RO 0
12−11 Reserved RO 0
10 Pause
1, Advertise pause ability.
0, Do not advertise pause abi li ty .
R/W 1
9 Reserved R/W 0
8 Adv 100 Full
1, Advertise 100 full-duplex ability.
0, Do not advertise 100 full-duplex ability.
R/W 1
7 Adv 100 Half
1, Advertise 100 half-duplex ability.
0, Do not advertise 100 half-duplex ability.
R/W 1
6 Adv 10 Full
1, Advertise 10 full-duplex ability.
0, Do not advertise 10 full-duplex ability.
R/W 1
5 Adv 10 Half
1, Advertise 10 half-duplex ability.
0, Do not advertise 10 half-duplex ability.
R/W 1
4−0 Selector Field 802.3 RO 00001
March 12, 2014 101 Revision 1.7
Micrel, Inc.
MIIM Registers (Continued)
Address Name Description Mode Default
Registe r 5 h : Link Partner Ability
15 Next Page Not supported. RO 0
14 LP ACK Not supported. RO 0
13 Remote fault Not supported. RO 0
12−11 Reserved RO 0
10 Pause
1, link partner flow control capable.
0, link partner not flow control capa ble.
RO 0
9 Reserved RO 0
Address Name Description Mode Default
8 Adv 100 Full
1, link partner 100BT full-duplex capable.
0, link partner not 100BT full-duplex capable.
RO 0
7 Adv 100 Half
1, link partner 100BT half-duplex capable.
0, link partner not 100BT half-duplex capable.
RO 0
6 Adv 10 Full
1, link partner 10BT full-duplex capable.
0, link partner not 10BT full-duplex capable.
RO 0
5 Adv 10 Half
1, link partner 10BT half-duplex capable.
0, link partner not 10BT half-duplex capable.
RO 0
4-0 Reserved RO 00001
Registe r 1 d h: Reserved
15 Reserved RO 0
14-13 Reserved RO 00
12 Reserved RO 0
11-9 Reserved RO 0
8−0 Reserved RO 000000000
Registe r 1 fh : PHY Special Control/Status
15−11 Reserved RO 0000000000
10−8 Port Operation Mode
Indication
Indicate the curr ent state of port operatio n mode:
[000] = reserved
[001] = still in auto-negotiation
[010] = 10BASE-T half duplex
[011] = 100BASE-TX half duplex
[100] = reserved
[101] = 10BASE-T full duplex
[110] = 100BASE-TX full duplex
[111] = PHY/MII isolate
RO 000
7−6 Reserved N/A, Do Not change R/W xx
5 Polrvs
1 = Polarity is reversed
0 = Polarity is not reversed
RO 0
4 MDI-X status
1 = MD I
0 = MD I-X
RO 0
3 Force_lnk
1 = Force lin k pass
0 = Normal operation
R/W 0
2 Pwrsave
1 = Enable power save
0 = Disable power save
R/W 0
March 12, 2014 102 Revision 1.7
Micrel, Inc.
MIIM Registers (Continued)
Address Name Description Mode Default
1 Remote Loopback
1, Perform Remote loopback, loop back path as
follows:
Port 1 (PHY ID address 0x1 reg. 1f, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Setting PHY ID address 0x2,3,4,5 reg. 1f, bit 1 = ‘1’
will perform remote loopback on port 2, 3, 4, 5.
0, Normal Operation.
R/W 0
0 Reserved N/A RO 0
March 12, 2014 103 Revision 1.7
Micrel, Inc.
Absolute Maximum Ratings(1)
Suppl y Voltage
(VDDAR, VDDAP, V DDC) ....................... –0.5V to +2.4V
(VDDAT, VDDIO) ................................. –0.5V to +4.0V
Input Voltage ........................................ –0.5V to +4.0V
Output Volta ge ..................................... –0.5V to +4.0V
Lead Temperature (soldering, 10 sec.) .............. 260°C
Storage Temperature (TS) .................–55°C to +150°C
HBM ESD Rating ................................................... 4KV
Operating Ratings(2)
Suppl y Voltage
(VDDAR, VDDAP, V DDC) ................... +1.14V to +1.26V
(VDDAT) ....................................... +3.15V to +3.45V
(VDDIO) ........ 3.15 to 3.45V or 2.4 to 2.6V or 1.71 to
1.89V
Ambient Temperature (TA)
Commercial .................................... –0°C to +70 °C
Industrial ....................................... –40°C to +85°C
Max Junction Temperature (TJ) ......................... 125°C
Package Thermal Resistance(3)
Thermal Resistance (θJA) ..................... 41.54°C/W
Thermal Resistance (θJC) ..................... 19.78°C/W
Electrical Characteristics(4, 5)
VIN = 1.2V/3.3V (typ.); TA = 25°C
Symbol Parameter Condition Min. Typ. Max. Units
100BASE-TX Operation—All Ports 100% Utilization
IDX
100BASE-TX (Transmitt er) 3.3V Analog
VDDAT
129
mA
IDda 100BASE-TX 1.2V Analog VDDAR 40 mA
IDDc 100BASE-TX 1.2V Digital VDDC 45 mA
IDDIO 100BASE-TX (Digital IO) 3. 3V Digit a l VDDIO 2.5 mA
10BASE-T Operation —All Ports 100% Utilization
IDX
10BASE-T (Transmitter) 3.3V Analo g
VDDAT
124
mA
IDda 10BASE-T 1.2V Analog VDDAR 15 mA
IDDc 10BASE-T 1.2V Digital VDDC 56 mA
IDDIO 10BASE-T (Digita l IO) 3.3V Digital VDDIO 2 mA
Auto-Negotiation Mode
IDX
10BASE-T (Transmitter) 3.3V Analog
VDDAT
75
mA
IDda 10BASE-T 1.2V Analog VDDAR 39 mA
IEDM 10BASE-T 1.2V Digital VDDC 58 mA
IDDIO 10BASE-T (Digital IO) 3.3V Digital VDDIO 1.6 mA
Power Manageme nt Mode
IPSM1
Power Saving Mode 3.3V
VDDAT + VDDIO
38
mA
IPSM2 Power Saving Mode 1.2V VDDAR + VDDC 73 mA
ISPDM1 Soft Power Down Mode 3.3V VDDAT + VDDIO 1.6 mA
ISPDM2 Soft Power Down Mode 1.2V VDDAR + VDDC 0.8 mA
IEDM1 Energy Detect Mode 3.3V VDDAT + VDDIO 7.5 mA
IEDM2
Energy Detect Mode 1.2V
VDDAR + VDDC
46
mA
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to functi on outside its operat i ng rating. Unused inputs must al ways be tied to an appropriate logic voltage level
(ground or VDD).
3. No heat spreader in package. The thermal juncti on to ambient (θJA) and the thermal j unction t o case (θJC) are under air velocity 0m/s.
4. Specific at i on for pack aged product only. T here is no an additional transform er consumption due to use on chip termination technology with
internal biasing for 10B ese-T and 100Base-TX.
5. Measurem ents were taken with operating rati ngs.
March 12, 2014 104 Revision 1.7
Micrel, Inc.
Electrical Characteristics(4, 5) (Continued)
VIN = 1.2V/3.3V (typ.); TA = 25°C
Symbol Parameter Condition Min. Typ. Max. Units
CMOS Inputs
VIH Input High Voltage (VDDIO=3.3/2.5/1.8V)
2.0/1.8
/1.3
V
VIL Input Low Voltag e (VDDIO=3.3/2.5/1.8V)
0.8/0.7
/0.5
V
IIN Input Current (Excluding Pull-up/Pull-down) VIN = GND ~ VDDIO –10 10 µA
CMOS Outputs
VOH Output High Voltage (VDDIO=3.3/2.5/1.8V) IOH = –8mA
2.4/2.0
/1.5
V
VOL Output Low Voltage (VDDIO=3.3/2.5/1.8V) IOL = 8mA
0.4/0.4
/0.3
V
IOZ Output Tri-State Leakage VIN = GND ~ VDDIO 10 µA
100BASE-TX Transmit (measured differentially after 1:1 transformer)
VO Peak Differential Output Voltage
100Ω termination on the
differential output
0.95 1.05 V
VIMB Output Voltage Imbalance
100Ω termination on the
differential output
2 %
tr tt
Rise/fall Time
3
5
ns
Rise/fall Time Imbalance 0 0.5 ns
Duty Cycle Distortion ±0.5 ns
Overshoot 5 %
Output Jitters Peak-to-peak 0 0.75 1.4 ns
10BASE-T Receive
VSQ Squelch Threshold 5MHz square wave 300 400 585 mV
10BASE-T Transmit (measured differentially after 1:1 transformer) VDDAT = 3.3V
VP Peak Differential Output Voltage
100Ω termination on the
differential output
2.2 2.5 2.8 V
Output Jitters Peak-to-peak 1.4 3.5 ns
Rise/fall Times
28
30
ns
March 12, 2014 105 Revision 1.7
Micrel, Inc.
Timing Diagrams
EEPROM Timing
Figure 18. EEPROM Interface Input Receive Timing Diagram
Figure 19. EEPROM Interface Output Transmit Timing Diagram
Symbol Parameter Min. Typ. Max. Units
tCYC1 Clock Cyc le 16384 ns
tS1 Set-Up Time 20 ns
tH1 Hold Time 20 ns
tOV1 Output Valid 4096 4112 4128 ns
Table 23. EEPROM Timing Par ameter s
March 12, 2014 106 Revision 1.7
Micrel, Inc.
SNI Timing
Figure 20. SNI Input Timing
Figure 21. SNI Output Timing
Symbol Parameter Min. Typ. Max. Units
tCYC2 Clock Cycle 100 ns
tS2 Set-Up Time 10 ns
tH2 Hold Time 0 ns
tO2 Output Valid 0 3 6 ns
Table 24. SNI Timing Parameters
March 12, 2014 107 Revision 1.7
Micrel, Inc.
MII Timing
Figure 22. MAC Mode MII Timing – Data Received from MII
Figure 23. MAC Mode MII Timing – Data Transmitted from MII
10Base-T/100Base-TX
Symbol Parameter Min. Typ. Max. Units
tCYC3 Clock Cycle
400/40
ns
tS3 Set-Up Time 10
ns
tH3 Hold Time 5
ns
tOV3 Output Valid 3 9 25 ns
Table 25. MAC Mode MII Timing Parameters
March 12, 2014 108 Revision 1.7
Micrel, Inc.
MII Timing (Continued)
Figure 24. PHY Mode MII Timing – Data Received from MII
Figure 25. PHY Mode MII Timing – Data Transmitted from MII
10BaseT/100BaseT
Symbol Parameter Min. Typ. Max. Units
tCYC4 Clock Cycle
400/40
ns
tS4 Set-Up Time 10
ns
tH4 Hold Time 0
ns
tOV4 Output Valid 16 20 25 ns
Table 26. PHY Mode MII Timing Parameters
March 12, 2014 109 Revision 1.7
Micrel, Inc.
RMII Timing
Figure 26. RMII Timing – Data Received from RMII
Figure 27. RMII Timing – Data Transmitted to RMII
Timing Parameter Description Min. Typ. Max. Unit
tcyc Clock cycle 20 ns
t1 Setup time 4 ns
t2 Hold time 2 ns
tod Output delay 3 14 ns
Table 27. RMII Timing Parameters
March 12, 2014 110 Revision 1.7
Micrel, Inc.
SPI Timing
Figure 28. SPI Input Timing
Symbol Parameter Min. Typ. Max. Units
fC Clock Frequency 25 MHz
tCHSL SPIS_N Inactive Hold Time 10 ns
tSLCH SPIS_N Active Set-Up Time 10 ns
tCHSH SPIS_N Active Hold Time 10 ns
tSHCH SPIS_N Inactive Set-Up Time 10 ns
tSHSL SPIS_N Deselect Time 20 ns
tDVCH Data Input Set-Up Time 5 ns
tCHDX Data Input Hold Time 5 ns
tCLCH Clock Ri se Time 1 µs
tCHCL Clock fall Time 1 µs
tDLDH Data Input Rise Time 1 µs
tDHDL Data Input fall Time 1 µs
Table 28. SPI Input Timing Parameters
March 12, 2014 111 Revision 1.7
Micrel, Inc.
SPI Timing (Continued)
Figure 29. SPI Output Timing
Symbol Parameter Min. Typ. Max. Units
fC Clock Frequency 25 MHz
tCLQX SPIQ Hold Time 0 0 ns
tCLQV Clock Low to SPIQ Valid 15 ns
tCH Clock High Time 18 ns
tCL Clock Low Time 18 ns
tQLQH SPIQ Rise Time 50 ns
tQHQL SPIQ fall Time 50 ns
tSHQZ SPIQ Disable Time 15 ns
Table 29. SPI Output Tim in g Par ameter s
March 12, 2014 112 Revision 1.7
Micrel, Inc.
Auto-Negotiation Timing
Figure 30. Auto-Negotiation Timing
Symbols Parameters Min. Typ. Max. Units
t
BTB
FLP burst to FLP burst 8 16 24 ms
t
FLPW
FLP burst width 2 ms
t
PW
Clock/Data pul se w idth 100 ns
t
CTD
Clock pulse to Data pulse 55.5 64 69.5 µs
t
CTC
Clock pulse to Clock pulse 111 128 139 µs
Number of Clock/D ata pul se per
burst 17 33
Table 30. Auto-Negotiation Timing Parameters
March 12, 2014 113 Revision 1.7
Micrel, Inc.
MDC/MDIO Timing
Figure 31. MDC/MDIO Timing
Timing Parameter
Description
Min.
Typ.
Max
Unit
tP MDC period 400 ns
t1MD1 MDIO (PHY input) setup to rising edge of MDC 10 ns
tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns
tMD3 MDIO (PHY output) delay from rising edge of MDC 222 ns
Table 31. MDC/MDIO Typical Timing Parameters
March 12, 2014 114 Revision 1.7
Micrel, Inc.
Reset Timing
Figure 32. Reset Timing
Symbol Parameter Min. Typ. Max. Units
tSR Stable Supply Voltages to Reset High 10 ms
tCS Configuration Set-Up Time 50 ns
tCH Configuration Hold Time 50 ns
tRC Reset to Strap-In Pin Output 50 ns
tvr 3.3V rise time 100 us
Table 32. Reset Timing Parameters
March 12, 2014 115 Revision 1.7
Micrel, Inc.
Reset Circuit Diagram
Micrel recom mends the following d is c rete r es et cir cuit as s ho wn in Fi gur e 2 2 whe n po w erin g up t he KS 889 5 MQ de vice.
For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend
the reset circuit as shown in Figure 23.
Figure 33. Recommended Reset Circuit
Figure 34. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
March 12, 2014 116 Revision 1.7
Micrel, Inc.
Selection of Isolation Transformer(1)
One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-
mode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of
RX/TX at chip side. The following table gives recommended transformer characteristics.
Characteristics Name Value Test Condition
Turns Ratio 1 CT : 1 CT
Open-Circuit Inductance (min.) 350µH 100mV, 100kHz, 8mA
Insertion Loss (max.) 1.1dB 0.1MHz to 100MHz
HIPOT (min.) 1500Vrms
Table 33. Transformer Selection Criteria
Notes:
1. The IEEE 802.3u standard for 100BASE -TX ass umes a transformer loss of 0.5dB. For the transmit li ne transform er, insert i on loss of up to 1.3dB
can be compensated by increasing the line drive current by means of reduci ng the ISET resist or value.
2. The center taps of RX and TX should be isolated for the low power consumption.
The following transformer vendors provide compatible magnetic parts for Micrel’s device:
Vendors and Parts Auto
MDIX Number
of Ports Vendors and Parts Auto
MDIX Number of
Ports
Pulse H1664NL Yes 4 Pulse H1102 Yes 1
YCL PH406082 Yes 4 Bel Fuse S558-5999-U7 Yes 1
TDK TLA-6T718A Yes 1 YCL PT163020 Yes 1
LanKom LF-H41S Yes 1 Transpower HB726 Yes 1
Datatronic NT79075 Yes 1 Delta LF8505 Yes 1
Table 34. Qua lified Mag netic Vendors
Selection of Reference Crystal
Chacteristics Value Units
Frequency 25.00000 MHz
Frequency tolerance (max) <= ±50 ppm
Load capacitan ce (max) 27 pF
Series resistance (max ESR) 40 Ω
Table 35. Typical Reference Crystal Characteristics
March 12, 2014 117 Revision 1.7
Micrel, Inc.
Package Information(1)
128-Pin PQFP Package
Note:
1. Package i nformat i on is correct as of the publication date. For updat es and most current inform ation, go t o www.micrel.com.
March 12, 2014 118 Revision 1.7
Micrel, Inc.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representati ons or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
informat i on is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specificat i ons and descript i ons at any time without notice. No license, whether express , im plied, aris i ng by estoppel or otherwise, t o any intellectual
property rights is granted by this document.
Except as provided in Micrel’s terms and conditi ons of sale for such prod
ucts, Micrel assumes no liabil ity
whatsoever, and Micrel disclaims any express or impl i ed warranty relati ng to t he sale and/or use of Micrel products includi ng liabi l ity or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other int el l ect ual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where mal
function of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the
user. A Purchaser’s use or sale of Micrel Products for use in life support applianc es, devic es or systems is a Purchaser’s own risk and Purchas er
agrees to fully indemnif y Micrel for any damages resulting from such use or sale.
© 2010 Micrel, Incorporated.
March 12, 2014 119 Revision 1.7