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1. General description
The 74LVC1G32-Q100 provides one 2-input OR function.
Inputs ca n be driven from e ither 3.3 V or 5 V device s. This f eature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
time.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the outpu t, pr eve n tin g the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
24 mA output drive (VCC =3.0V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
74LVC1G32-Q100
Single 2-input OR gate
Rev. 2 — 9 December 2016 Product data sheet
74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 2 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lo wer left corner of the device, below the marking code.
5. Functional diagram
6. Pinning information
6.1 Pinning
Table 1. Ordering information
Type number Package
Temperature
range Name Description Version
74LVC1G32GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm SOT353-1
74LVC1G32GV-Q100 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753
Table 2. Marking
Type number Marking code [1]
74LVC1G32GW-Q100 VG
74LVC1G32GV-Q100 V32
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram
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74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 3 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
Table 3. Pin description
Symbol Pin Description
B 1 data input
A 2 data input
GND 3 ground (0 V)
Y 4 data output
VCC 5 supply voltage
Table 4. Function table[1]
Input Output
ABY
LLL
LHH
HLH
HHH
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA
VOoutput voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V
IOoutput current VO = 0 V to VCC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125 C[3] -250mW
Tstg storage temperature 65 +150 C
74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 4 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
9. Recommended operating conditions
10. Static characteristics
Table 6. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage Active mode 0 - VCC V
VCC = 0 V; Power-down mode 0 - 5.5 V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V
VCC = 2.7 V to 5.5 V - - 10 ns/V
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7 VCC --0.7VCC -V
VIL LOW-level
input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 VCC -0.3VCC V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto 5.5V VCC 0.1 - - VCC 0.1 - V
IO=4mA; V
CC = 1.65 V 1.2 - - 0.95 - V
IO=8mA; V
CC = 2.3 V 1.9 - - 1.7 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 1.9 - V
IO=24 mA; VCC = 3.0 V 2.3 - - 2.0 - V
IO=32 mA; VCC = 4.5 V 3.8 - - 3.4 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=100A;
VCC = 1.65 V to 5.5 V - - 0.10 - 0.10 V
IO=4mA; V
CC = 1.65 V - - 0.45 - 0.70 V
IO=8mA; V
CC = 2.3 V - - 0.30 - 0.45 V
IO=12mA; V
CC = 2.7 V - - 0.40 - 0.60 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.80 V
IO=32mA; V
CC = 4.5 V - - 0.55 - 0.80 V
74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 5 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
[1] All typical values are measured at VCC = 3.3 V and Tamb =25C.
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W).
PD=(C
PD VCC2fiN) + (CLVCC2fo) where:
VCC = supply voltage in V,
fi= input frequency in MHz,
N = number of inputs switching,
CL= output load capacitance in pF,
fo= output frequency in MHz.
IIinput leakage
current VI = 5.5 V or GND;
VCC =0Vto5.5V -0.1 1-1A
IOFF power-off
leakage
current
VCC = 0 V; VIor VO=5.5V - 0.1 2-2A
ICC supply current VI = 5.5 V or GND; IO = 0 A;
VCC = 1.65 V to 5.5 V -0.14 - 4A
ICC additional
supply current per pin; VCC = 2.3 V to 5.5 V;
VI=V
CC 0.6 V; IO=0 A - 5 500 - 500 A
CIinput
capacitance VCC =3.3V; V
I = GND to VCC -5---pF
Table 7. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay A, B to Y; see Figure 5 [2]
VCC = 1.65 V to 1.95 V 1.0 3.1 8.0 1.0 10.5 ns
VCC = 2.3 V to 2.7 V 0.5 2.1 5.5 0.5 7.0 ns
VCC = 2.7 V 0.5 2.5 5.5 0.5 7.0 ns
VCC = 3.0 V to 3.6 V 0.5 2.1 4.5 0.5 6 .0 ns
VCC = 4.5 V to 5.5 V 0.5 1.7 4.0 0.5 5 .5 ns
CPD power dissipation
capacitance VI = GND to VCC; VCC = 3.3 V [3] -16- - -pF
74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 6 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
12. AC waveforms
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. The input A, B to output Y propagation delays
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Supply voltage Input Output
VCC VMVM
1.65 V to 1.95 V 0.5 VCC 0.5 VCC
2.3 V to 2.7 V 0.5 VCC 0.5 VCC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5 V 0.5 VCC 0.5 VCC
74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 7 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance; should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 6. Test circuit for measuring switching times
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Supply voltage Input Load VEXT
VCC VItr=t
fCLRLtPLH, tPHL
1.65 V to 1.95 V VCC 2.0ns 30pF 1kopen
2.3 V to 2.7 V VCC 2.0ns 30pF 500open
2.7V 2.7V 2.5ns 50pF 500open
3.0V to 3.6V 2.7V 2.5ns 50pF 500open
4.5 V to 5.5 V VCC 2.5ns 50pF 500open
74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 8 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
13. Package outline
Fig 7. Package outline SOT353-1 (TSSOP5)
74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 9 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
Fig 8. Package outline SOT753 (SC-74A)
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74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 10 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LV C1G32_Q100 v.2 20161209 Product data sheet - 74LVC1G32 _Q100 v.1
Modifications: •Table 7: The maximum limits for leakage current and supply current have changed.
74LV C1G32_Q100 v.1 20120807 Product data sheet - -
74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 11 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
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representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
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contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed ,
authorized or warranted to be suitable for use in life support , life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and t her efo re su ch inclu si on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associate d with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessa ry
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development .
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
74LVC1G32_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 2 — 9 December 2016 12 of 13
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to se ll product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
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Translations — A non-English (translated) version of a document is for
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between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC1G32-Q100
Single 2-input OR gate
© NXP Semiconductors N.V. 2016. All rig hts reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 December 2016
Document identifier: 74LVC1G32_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 10
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
17 Contact information. . . . . . . . . . . . . . . . . . . . . 12
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13