TC74LCX573F/FK
2018-08-02
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© 2018
Toshiba Electronic Devices & Storage Corporation
TOS HIBA CMOS Digital Int e g r a ted Circuit Silicon Mon olithic
TC74LCX573F TC74LCX573FK
Low-Voltage Octal D-Type Latch with 5-V Tolerant Inputs and Outputs
The TC74LCX573 is a high-performance CMOS octal D-type latch.
Designed for use in 3.3-V systems, it achieves high-speed operation
while maintaining the CMOS low power dissipation.
The device is designed for low-voltage (3.3 V) VCC applications, but it
could be used to interface to 5-V supply environment for both inputs and
outputs.
This 8-bit D-type latch is controlled by a latch enable input (LE) and
an output enable input (
OE
).
When the
OE
input is high, the eight outputs are in a high-impedance
state.
All inputs are equipped with protection circuits against static
discharge.
Features
• Low-voltage operation: VCC = 1.65 to 3.6 V
• High-speed operation: tpd = 8.0 ns (max) (VCC = 3.0 to 3.6 V)
• Output current: |IOH|/IOL = 24 mA (min) (VCC = 3.0 V)
• Latch-up performance: > ±500 mA
• Available in JEITA SOP, VSSOP (US)
• Power-down protection provided on all inputs and outputs
• Pin and function compatible with the 74 series
(74AC/VHC/HC/F/ALS/LS etc.) 573 type
Note: The Electrical Characteristics of VCC = 1.8 ± 0.15 V is only applicable for products which manufactured
from January 2009 onward.
TC74L
CX573F
TC74LCX573FK
Weight
SOP20
-P-300-1.27A : 0.22 g ( typ.)
VSSOP20-P-0030-0.50 : 0.03 g ( typ.)
Start of commercial production
1994-10
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Toshiba Electronic Devices & Storage Corporation
Pin Assignment (top view) IEC Logic Symbol
Truth Table
Inputs Outputs
OE
LE D
H X X Z
L L X Qn
L H L L
L H H H
X: Don’t care
Z: High impeda nce
Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram
LE
Q1
1
11
2
19
Q2
3
18
Q3
4
17
Q4
5
16
Q5
6
15
Q6
7
14
Q7
8
13
L
D
L
D
L
D
L
D
L
D
L
D
L
D
D1
D2
D3
D4
D5
D6
D7
9
12
L
D
Q0
D0
VCC
20
Q0
Q1
Q2
19
18
17
16
15
14
1
2
3
4
5
6
7
D2
D3
D4
D5
D6
D7
Q3
8
9
10
Q6
Q7
GND
13
12
11
Q4
Q5
LE
D0
D1
(1)
(11)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(19)
(18)
(17)
(16)
(15)
(14)
(13)
(12)
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
EN
1D
C1
LE
D0
D1
D2
D3
D4
D5
D6
D7
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Absolute Maximum Ratings (Note 1 )
Characteristics Symbol Rating Unit
Power supply voltage VCC −0.5 to 7.0 V
DC input voltage VIN −0.5 to 7.0 V
DC output voltage VOUT
−0.5 to 7.0 (Note 2)
V
−0.5 to VCC + 0.5
(Note 3)
Input diode current IIK −50 mA
Output diode current IOK ±50 (Note 4)
mA
DC output current IOUT ±50 mA
Power dissipation PD 180 mW
DC VCC/ground current ICC/IGND ±100 mA
Storage temperature Tstg −65 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant
change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating
conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the
operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 2: Output in OFF state
Note 3: High or low state. IOUT absolute maximum rating must be observed.
Note 4: VOUT < GND, VOUT > VCC
Operating Ranges (Note 1)
Characteristics Symbol Rating Unit
Power supply voltage VCC 1.65 to 3.6 V
1.5 to 3.6 (Note 2)
Input voltage VIN 0 to 5.5 V
Output voltage VOUT 0 to 5.5 (Note 3)
V
0 to VCC (Note 4)
Output current IOH/IOL ±24 (Note 5)
mA
±12 (Note 6)
Operating temperature Topr −40 to 85 °C
Input rise and fall time dt/dv 0 to 10 (Note 7)
ns/V
Note 1: The operating ranges mus t be maintain ed to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Note 2: Data retention only
Note 3: Output in OFF state
Note 4: High or low state
Note 5: VCC = 3.0 to 3.6 V
Note 6: VCC = 2.7 to 3.0 V
Note 7: VIN = 0.8 to 2.0 V, VCC = 3.0 V
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Electrical Characteristics
DC Characteristics (Ta = −40 to 85°C)
Characteristics Symbol Test Condition Min Max Unit
VCC (V)
Input volt age
H-level VIH
1.65 to 2.3 VCC×0.9
V
2.3 to 2.7 1.7
2.7 to 3.6 2.0
L-level VIL
1.65 to 2.3 VCC×0.1
2.3 to 2.7 0.7
2.7 to 3.6 0.8
Output voltage
H-level VOH VIN = VIH or VIL
IOH = −100 µA 1. 65 to 3.6 VCC−0.2
V
IOH = −4 mA 1.65 1.05
IOH = −8 mA 2.3 1.7
IOH = −12 mA 2.7 2.2
IOH = −18 mA 3.0 2.4
IOH = −24 mA 3.0 2.2
L-level VOL VIN = VIH or VIL
IOL = 100 µA 1.65 to 3.6 0.2
IOL = 4 mA 1.65 0.45
IOL = 8 mA 2.3 0.7
IOL = 12 mA 2.7 0.4
IOL = 16 mA 3.0 0.4
IOL = 24 mA 3.0 0.55
Input leakage current IIN VIN = 0 to 5.5 V 1.65 to 3.6 ±5.0 µA
3-state output OFF state current IOZ VIN = VIH or V IL
VOUT = 0 to 5.5 V 1.65 to 3.6 ±5.0 µA
Power-off leakage current IOFF VIN/VOUT = 5.5 V 0 10.0 µA
Quiescent supply current ICC VIN = VCC or GND 1.65 to 3.6 10.0
µA
VIN/VOUT = 3.6 to 5.5 V 1.65 to 3.6 ±10.0
Increase in ICC per input ∆ICC VIH = VCC − 0.6 V (per 1 input) 2.7 to 3.6 500
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AC Characteristics (Ta = −40 to 85°C)
Characteristics Symbol Test Condition Min Max Unit
VCC (V)
Propagation delay time
(D-Q) tpLH
tpHL Figure 1, Figure 2
1.8 ± 0.15 30.0
ns
2.5 ± 0.2 10.0
2.7 9.0
3.3 ± 0.3 1.5 8.0
Propagation delay time
(LE-Q) tpLH
tpHL Figure 1, Figure 2
1.8 ± 0.15 30.0
ns
2.5 ± 0.2 10.5
2.7 9.5
3.3 ± 0.3 1.5 8.5
Output enable time tpZL
tpZH Figure 1, Figure 3
1.8 ± 0.15 34.0
ns
2.5 ± 0.2 17.0
2.7 9.5
3.3 ± 0.3 1.5 8.5
Output disable time tpLZ
tpHZ Figure 1, Figure 3
1.8±0.15 28.0
ns
2.5±0.2 14.0
2.7 7.0
3.3 ± 0.3 1.5 6.5
Minimum pulse width
(LE) tw (H) Figure 1, Figure 2
1.8 ± 0.15 10.0
ns
2.5 ± 0.2 5.0
2.7 3.3
3.3 ± 0.3 3.3
Minimum setup time ts Figure 1, Figure 2
1.8 ± 0.15 10.0
ns
2.5 ± 0.2 5.0
2.7 2.5
3.3 ± 0.3 2.5
Minimum hold time th Figure 1, Figure 2
1.8 ± 0.15 1.5
ns
2.5 ± 0.2 1.5
2.7 1.5
3.3 ± 0.3 1.5
Output to output skew tosLH
tosHL (Note)
2.7 ns
3.3 ± 0.3 1.0
Note: Parameter guaranteed by design.
(tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|)
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Dynamic Switching Characteristics (Ta = 25°C, input: tr = tf = 2.5 ns, CL = 50 pF, RL = 500 Ω)
Characteristics Symbol Test Condition Typ. Unit
VCC (V)
Quiet output maximum dynamic VOL VOLP VIH = 3.3 V, VIL = 0 V 3.3 0.8 V
Quiet output minimum dynamic VOL |VOLV| VIH = 3.3 V, VIL = 0 V 3.3 0.8 V
Capacitive Characteristics (Ta = 25°C)
Characteristics Symbol Test Condition Typ. Unit
VCC (V)
Input capacitance
CIN 3.3 7 pF
Output capacitance COUT 3.3 8 pF
Power dissipation capacitance CPD fIN = 10 MHz (Note)
3.3 25 pF
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption.
Average operating current can be obtained by the equation:
ICC (opr) = CPD･VCC･fIN + ICC/8 (per bit)
AC Test Circuit
Open
6.0 V or V
CC
×2
GND
Switch
Output Measure
Parameter Switch
tpLH, tpHL
Open
tpLZ, tpZL
6.0 V @ VCC =3.3±0.3V
@ VCC =2.7V
VCC×2 @ VCC =2.5±0.2V
@ VCC =1.8±0.15V
tpHZ, tpZH GND
RL
RL
CL
Figure 1
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AC Waveform
Symbol
VCC
3.3 ± 0.3 V
2.7 V 2.5 ± 0.2 V 1.8 ± 0.15 V
Input VIH 2.7 V VCC VCC
VIM 1.5 V VCC/2 VCC/2
tr,tf 2.5 ns 2.0 ns 2.0 ns
Output VOM 1.5 V VOH/2 VOH/2
VX VOL +0.3 V VOL +0.15 V VOL +0.15 V
VY VOH -0.3 V VOH -0.15 V VOH -0.15 V
Load CL 50 pF 30 pF 30 pF
RL 500 Ω 500 Ω 1 kΩ
th (L)
ts (L)
10%
tr
90%
VIM
VIH
GND
VIH
GND
VOH
VOL
tf
ts (H)
th (H)
tf
tr
90%
VIM
10%
VIM
VIM
tpHL
tpLH
VOM
tw (H)
tpLH
tpHL
VOM
Input
(LE)
Input
(D)
Output
(Q)
Figure 2 tpLH, tpHL, tw, ts, th
Figure 3 tpLZ, tpHZ, tpZL, tpZH
90%
10%
VOL
VOH
GND
VIH
VOM
t
pHZ
t
pZH
tr
tf
VIM
GND
VOH
Outputs
enabled
VOM
tpLZ
tpZL
V
X
VY
Outputs
disabled
Outputs
enabled
Output Enable
(
)
Output (Q)
Low to Off to Low
Output (Q)
High to Off to High
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Package Dimensions
Weight: 0.22 g (typ.)
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Package Dimensions
Weight : 0.03 g (typ.)
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Toshiba Electronic Devices & Storage Corporation
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